Storage circuit and data writing method

Abstract

The present invention relates to a storage circuit and a data writing method. In the data writing stage, a static random access memory cell to be written is selected by a word line signal of a first level and a first bit line signal. The first bit line signal of the first level turns on a bit line switch that controls the bit line potential, and latches a low-side voltage into a first storage node through the bit line. The second bit line signal of the second level turns off a bit line non-switch that controls the bit line non-potential, and latches a high-side voltage into a second storage node through the bit line non, so as to replace a current value with a pre-written value and write the static random access memory cell to be written. At the moment when the first bit line signal jumps from the first level to the second level and turns off the bit line switch, a preset voltage lower than the high-side voltage is instantaneously coupled to the bit line once to prevent the pre-written value from rebounding to the current value.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of data storage, and more specifically, to a storage circuit and a data writing method which can avoid data being unable to be written or being written incorrectly in data storage. Background Art

[0002] Static random access memory (SRAM), as a member of memory, has the advantages of high speed, low power consumption and compatibility with standard processes. It is widely used in PCs, personal communications, consumer electronics, smart cards, digital cameras, multimedia players and other fields. For example, many subsystems of industrial science and automotive electronics use SRAM. Many modern devices are embedded with thousands of bytes of SRAM. In fact, almost all modern devices that implement electronic user interfaces may use SRAM, such as toys, digital cameras, mobile phones, audio synthesizers, etc., which use several megabytes of SRAM. Real-time signal processing circuits often use dual-ported SRAM.

[0003] Compared with DRAM (Dynamic Random Access Memory), SRAM does not need a refresh circuit to save the data stored inside. DRAM needs to be refreshed and charged every once in a while, otherwise the internal data will disappear. Therefore, SRAM has higher performance, but SRAM also has its disadvantages, that is, its integration is low and its power consumption is higher than DRAM. DRAM memory of the same capacity can be designed to be smaller in size, but SRAM requires a large volume. DRAM can make a larger capacity memory on the same area of ​​silicon wafer and make SRAM more expensive. On the basis of realizing basic storage, SRAM should try to compress unnecessary circuits but must ensure that there are no functional defects.

[0004] The data writing stability of the SRAM in the prior art is poor, and it is easy to cause the stored data to jump or fail to write data during the data writing operation. Therefore, how to improve the stability of SRAM data writing has become a problem to be solved by those skilled in the art. The read and write function of the storage circuit still needs to be improved. Data writing is not completed instantly for the memory. When a single storage unit is selected through the word line and the bit line, there is a jump time for the potential change on the word line and the bit line, and there is also a lasting time for the potential maintenance on the word line and the bit line. During data operation, if the aforementioned time is set to be longer in order to ensure that the data can be written smoothly, the doubt that follows is that the mismatched single write operation time or single read operation time in a high-speed storage environment will cause an imbalance with the data communication protocol, resulting in data operation failure. For example, the excessive data read and write time of a single storage unit will not match the speed specified by the data protocol. Summary of the invention

[0005] The present application relates to a data writing method, which is characterized by comprising:

[0006] In the stage of writing data to the static random access memory cell, the static random access memory cell to be written is selected by a word line signal of the first level and a first bit line signal of the first level:

[0007] The first bit line signal of the first level turns on the bit line switch that controls the bit line potential, and latches the low side voltage into the first storage node through the bit line, and the second bit line signal of the second level turns off the bit line non-switch that controls the bit line non-potential, and latches the high side voltage into the second storage node complementary to the first storage node through the bit line non, thereby replacing the previously stored current value with the pre-written value and writing it into the static random access memory cell to be written;

[0008] At the moment when the first bit line signal jumps from the first level to the second level and turns off the bit line switch, a preset voltage lower than the high-side voltage is instantaneously coupled to the bit line once to prevent the pre-written value from rebounding to the current value, wherein the preset voltage is an independent reference voltage or the low-side voltage or a negative voltage.

[0009] In the above method, the first bit line signal is divided into two branches, one of which is coupled to an input end of the first NOR gate and the other is coupled to the other input end of the first NOR gate after passing through a delay unit and an inverter, and the output of the first NOR gate controls the turning off or on of the first switch, and at the transition time, for example, by turning on the first switch, the preset voltage is coupled to the bit line once;

[0010] A first switch and a first transistor with a source-drain short circuit are arranged between the preset voltage and the bit line, and two ends of the first transistor are respectively connected to the bit line and to the preset voltage through the first switch (e.g., one of the two ends of the first transistor is connected to the bit line and the other end is connected to the preset voltage through the first switch).

[0011] In the above method, the low-side voltage is the reference ground voltage, the high-side voltage is the power supply voltage for the static random access memory cell to work, and when the preset voltage is a negative voltage, it is limited to be lower than the reference ground voltage.

[0012] In the above method, the first level is a high level and the second level is a low level, or the first level is a low level and the second level is a high level.

[0013] In the above method, after the static random access memory cell completes data writing, the word line signal and the first bit line signal both jump from the first level to the second level to exit the data writing operation on the static random access memory cell to be written.

[0014] In the above method, the current value includes data 1 and the pre-written value includes data 0.

[0015] In the above method, the low-side voltage is a reference ground voltage, the high-side voltage is a power supply voltage of a static random access memory cell, and the preset voltage is an independent reference voltage or the low-side voltage or a negative voltage.

[0016] In the above method, the preset voltage is instantaneously coupled to the bit line at the jump moment, so that the first storage node tends to be close to the low-side voltage but has not yet reached the oscillation of the low-side voltage, and the second storage node tends to be close to the high-side voltage but has not yet reached the oscillation of the high-side voltage, developing towards the trend of establishing positive feedback between the first and second storage nodes.

[0017] The present application relates to a data writing method, which is characterized by comprising:

[0018] In the stage of writing data to the static random access memory cell, the static random access memory cell to be written is selected by a word line signal of the first level and a second bit line signal of the first level:

[0019] The second bit line signal of the first level turns on the bit line non-switch controlling the bit line non-potential, and latches the low-side voltage into the second storage node through the bit line non-potential; and the first bit line signal of the second level turns off the bit line switch controlling the bit line potential, and latches the high-side voltage into the first storage node complementary to the second storage node through the bit line, thereby replacing the previously stored current value with the pre-written value and writing it into the static random access memory cell to be written;

[0020] When the second bit line signal jumps from the first level to the second level and turns off the bit line non-switch, a preset voltage lower than the high-side voltage is instantaneously coupled to the bit line non-switch once to prevent the pre-written value from rebounding to the current value, wherein the preset voltage is an independent reference voltage or the low-side voltage or a negative voltage.

[0021] In the above method, the second bit line signal is divided into two branches, one of which is coupled to an input end of the second NOR gate and the other is coupled to the other input end of the second NOR gate after passing through a delay unit and an inverter, and the output of the second NOR gate controls the turning off or on of the second switch, and at the said transition time, for example, by turning on the second switch, the preset voltage is coupled to the bit line NOR once;

[0022] A second switch and a second transistor with a source-drain short circuit are arranged between the preset voltage and the bit line NAND, and two ends of the second transistor are respectively connected to the bit line NAND and to the preset voltage through the second switch (for example, one of the two ends of the second transistor is connected to the bit line NAND and the other end is connected to the preset voltage through the second switch).

[0023] The above method, at the said jump moment, instantaneously couples the preset voltage to the bit line, so that the second storage node tends to be close to the low-side voltage but has not yet reached the oscillation of the low-side voltage, and the first storage node tends to be close to the high-side voltage but has not yet reached the oscillation of the high-side voltage, and develops towards the trend of establishing positive feedback between the first and second storage nodes.

[0024] In the above method, the first level is a high level and the second level is a low level, or the first level is a low level and the second level is a high level.

[0025] In the above method, after the static random access memory cell completes data writing, the word line signal and the second bit line signal both jump from the first level to the second level to exit the data writing operation on the static random access memory cell to be written.

[0026] In the above method, the low-side voltage is a reference ground voltage, the high-side voltage is a power supply voltage of a static random access memory cell, and the preset voltage is an independent reference voltage or the low-side voltage or a negative voltage.

[0027] In the above method, the current value includes data 0 and the pre-written value includes data 1.

[0028] The present application relates to a storage circuit, characterized in that it includes:

[0029] A plurality of static random access memory cells sharing a bit line and a bit line non-signal, wherein the first bit line signal controls the turning off or on of a bit line switch to adjust the potential of the bit line, the second bit line signal controls the turning off or on of a bit line non-signal to adjust the potential of the bit line non-signal, and a word line signal matching any static random access memory cell is used to select the static random access memory cell;

[0030] The first bit line signal is divided into two branches, one of which is coupled to an input end of the first NOR gate, and the other is coupled to the other input end of the first NOR gate after passing through a delay unit and an inverter. The output of the first NOR gate controls the turning off or on of the first switch. When the first bit line signal jumps from the first level to the second level and the bit line switch is turned off, the preset voltage is coupled to the bit line once (the first switch is turned on and the preset voltage is coupled to the bit line once), so as to prevent the pre-written value written into the static random access memory cell from rebounding to the current value.

[0031] A first switch and a first transistor with a source and a drain short-circuited are arranged between the preset voltage and the bit line, and two ends of the first transistor are respectively connected to the bit line and to the preset voltage through the first switch; and / or

[0032] The second bit line signal is divided into two branches, one of which is coupled to an input end of the second NOR gate, and the other is coupled to the other input end of the second NOR gate after passing through a delay unit and an inverter. The output of the second NOR gate controls the turning off or on of the second switch, and couples the preset voltage to the bit line NOR once (turns on the second switch and couples the preset voltage to the bit line NOR once) at the moment when the second bit line signal jumps from the first level to the second level and the bit line NOR switch is turned off, so as to prevent the pre-written value written into the static random access memory cell from rebounding to the current value;

[0033] A second switch and a second transistor with a source and a drain short-circuited are arranged between the preset voltage and the bit line N / A, and two ends of the second transistor are respectively connected to the bit line N / A and to the preset voltage through the second switch.

[0034] The present application relates to a data writing method, which is characterized by comprising:

[0035] In the stage of writing data to the static random access memory cell, the static random access memory cell to be written is selected by a word line signal of a first level and a first bit line signal:

[0036] The first bit line signal of the first level turns on the bit line switch that controls the bit line potential, and latches the low side voltage into the first storage node through the bit line, and the second bit line signal of the second level turns off the bit line non-switch that controls the bit line non-potential, and latches the high side voltage into the second storage node complementary to the first storage node through the bit line non, thereby replacing the previously stored current value with the pre-written value and writing it into the static random access memory cell to be written;

[0037] At the moment when the first bit line signal jumps from the first level to the second level and turns off the bit line switch, a preset voltage lower than the high-side voltage is instantaneously coupled to the bit line once to prevent the pre-written value from rebounding to the current value;

[0038] A switch and a transistor with a source and a drain short-circuited are arranged between the preset voltage and the bit line, and two ends of the transistor are respectively connected to the bit line and to the preset voltage through the switch;

[0039] The first bit line signal is divided into two branches, one of which is coupled to an input end of an NOR gate, and the other is coupled to the other input end of the NOR gate after passing through a delay unit and an inverter. The output of the NOR gate controls the turning off or on of the switch, and couples the preset voltage to the bit line once by turning on the switch at the transition moment.

[0040] The present application relates to a data writing method, which is characterized by comprising:

[0041] In the stage of writing data to the static random access memory cell, the static random access memory cell to be written is selected by a word line signal of a first level and a second bit line signal:

[0042] The second bit line signal of the first level turns on the bit line non-switch controlling the bit line non-potential, and latches the low-side voltage into the second storage node through the bit line non-potential; and the first bit line signal of the second level turns off the bit line switch controlling the bit line potential, and latches the high-side voltage into the first storage node complementary to the second storage node through the bit line, thereby replacing the previously stored current value with the pre-written value and writing it into the static random access memory cell to be written;

[0043] At the moment when the second bit line signal jumps from the first level to the second level and turns off the bit line non-switch, a preset voltage lower than the high-side voltage is instantaneously coupled to the bit line non-switch to prevent the pre-written value from rebounding to the current value;

[0044] A switch and a transistor with a source and a drain short-circuited are arranged between the preset voltage and the bit line NAND, and two ends of the transistor are respectively connected to the bit line NAND and to the preset voltage through the switch;

[0045] The second bit line signal is divided into two branches, one of which is coupled to an input end of an NOR gate, and the other is coupled to the other input end of the NOR gate after passing through a delay unit and an inverter. The output of the NOR gate controls the turning off or on of the switch, and couples the preset voltage to the bit line NOR once by turning on the switch at the transition moment.

[0046] The technical solution of the present application solves the problems of poor stability of SRAM data writing, easy storage data jump or inability to write data during data writing operation. Considering the time required for each bit of data writing operation: when a single storage unit is selected through the word line and the bit line, there is a jump time for the potential change on the word line and the bit line, and there is also a continuation time for the potential maintenance on the word line and the bit line. During the data operation, the present application can smoothly write data without excessive jump time and continuation time. The potential change of the word line and the bit line meets the data operation time limit of high-speed communication, the success rate of the data operation is guaranteed, and the data writing operation can match the data operation speed specified by the communication protocol. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to make the above purposes, features and advantages more understandable, the following text will explain the specific implementation methods in detail in conjunction with the drawings. After reading the following description and referring to the following drawings, the features and advantages of the present application will become apparent.

[0048] Figure 1 This is a schematic diagram of the general circuit structure of the current common static random access memory.

[0049] Figure 2 This is a schematic diagram of the current common static random access memory storage array.

[0050] Figure 3 A single column of storage cells and a designed data errata solution are taken as an example.

[0051] Figure 4 It is to select a word line from a single column of memory cells and pull down one of the bit lines.

[0052] Figure 5 It is to select the word line from a single column of memory cells and jump from a one value to a zero value.

[0053] Figure 6 It is to select the word line from a single column of memory cells and pull down the other of the bit lines.

[0054] Figure 7 The word line is selected from a single column of memory cells and jumps from a zero value to a one value.

[0055] Figure 8 It is an example of writing zero or one to a memory cell in a static random access memory array. DETAILED DESCRIPTION

[0056] The technical solutions disclosed in the present application will be clearly and completely described below in conjunction with specific embodiments. However, the embodiments described are only embodiments used for narrative explanation in the present application and are not all embodiments. Based on these embodiments, technicians in this field should realize that any solution obtained without creative work falls within the scope of protection of the present application.

[0057] See also Figure 1 The static random access memory SRAM cell of the prior art is usually a 6T structure, where T in the static random access memory is the abbreviation of transistor. The common 6T structure SRAM cell usually includes a storage cell and some read-write cells, which are not fully shown in the figure. The storage cell includes T1 and T3 connected in series between the VCC power supply voltage and the reference voltage VSS, and T2 and T4 connected in series between VCC and VSS. The storage node N1 of the storage cell is coupled to the gates of both T2 and T4, the storage node N2 is coupled to the gates of both T1 and T3, and the storage nodes N1 and N2 are used to store 1 signals or 0 signals respectively.

[0058] See also Figure 1The gates of transistors T5 and T6 are coupled to the word line W. If the word line W is selected, the pair of transistors T5 and T6 can be turned on. Transistors T5 and T6 are also called switch transistors or transmission transistors or access transistors. After the access transistors are turned on, write operations can be performed on the storage nodes N1 and N2 according to the potential conditions of the word line B1 or B2. After the access transistors are turned on, read operations can be performed on the storage nodes according to the signal conditions of the storage nodes N1 and N2.

[0059] See also Figure 1 , the storage nodes N1 and N2 are complementary, ie, their logic states are opposite. The transistors T1 and T3 are both interconnected to the storage node N1, and the transistors T2 and T4 are both interconnected to the storage node N2.

[0060] See also Figure 1 One end of the transistor T5 is connected to the storage node N1 of the memory cell and the other end of the transistor T5 is connected to the bit line B1 for performing read and write operations on the memory cell.

[0061] See also Figure 1 One end of the transistor T6 is connected to the storage node N2 of the memory cell and the other end of the transistor T6 is connected to the bit line B2 for performing read and write operations on the memory cell.

[0062] See also Figure 1 Among them, T3, T4, T5, and T6 are NMOS, and T1 and T2 are PMOS.

[0063] See also Figure 1 , where T1 and T3, T2 and T4 form an inverter in pairs, which can invert the signal and then use it as input to another inverter. For example, the first inverter (T1 and T3) can invert the signal 1 or 0 and then use it as input to the second inverter (T2 and T4). These two inverters are connected through input and output to form a latch to store the required information. The reference voltage VSS can be called the reference ground voltage.

[0064] See also Figure 1 Regardless of the type of SRAM or the variation of the SRAM shown in the figure, the basic principle is to latch data through two inverters connected end to end, where the two inverters roughly form positive feedback, so that the storage unit circuit always tends to return to the desired stable state.

[0065] See also Figure 1 In terms of function, the aforementioned transistors T5 and T6 implement access, which is used to read or write data. For example, assuming that the access transistor is turned on by the word line (W), the storage data is transmitted from the bit lines (B1 and B2) to the peripheral reading circuit. The inverter and the access circuit form an SRAM cell.

[0066] See also Figure 1 The storage unit of the present application is different from the traditional storage unit. Figure 3 , but there are also common parts described above. The storage unit or storage circuit mentioned in this application can be called T-UNIT, which is used to characterize static random access memory circuits or static random access memory units, etc.

[0067] See also Figure 1 , the key technology nodes of semiconductors have been following a trend of gradual shrinking, such as from the early hundreds of nanometers to tens of nanometers, and now more than ten nanometers or even several nanometers. When the key technology nodes of transistors develop to the stage of more than ten nanometers or even several nanometers, the natural manufacturing process errors of transistors and the gradually reduced operating voltage with the process nodes make the data writing operation of the storage circuit T-UNIT extremely difficult. The difficulties of this data operation will be explained in detail below.

[0068] See also Figure 2 In a storage array formed by integrating many individual storage circuits, different storage circuits store different data or information. The word lines W0-WN and the bit lines B1-B6 are selected to perform data writing operations or data reading operations on the selected storage circuits.

[0069] See also Figure 2 Assuming that the word line WK and the bit lines B1-B2 are selected, the position of the storage circuit selected individually in the entire storage array is determined, and the logic data stored in it is 1, recorded as LOGIC_1. The following embodiment will explain how to change the logic data 1 to 0, and the change result is recorded as LOGIC_0.

[0070] See also Figure 2 , for example, if the word line WN and the bit lines B3-B4 are selected, the position of the storage circuit selected individually in the entire storage array is determined, and the logic data stored in it is 0, recorded as LOGIC_0. The following embodiment will explain how to change the logic data 0 to 1, and the change result is recorded as LOGIC_1.

[0071] See also Figure 1 , the explanation of the logic data being 1 (LOGIC_1): the voltage of the storage node N1 is high, for example, its voltage potential is equal to or close to the power supply voltage or the working voltage VCC, the voltage of the storage node N2 is low, for example, its voltage potential is equal to or close to the ground voltage or the reference voltage VSS, and the value or data stored in the static random access memory 6T unit at this time is logic 1. The state of the storage nodes N1-N2 is DATA[1:0].

[0072] See also Figure 1, the explanation of the logic data being 0 (LOGIC_0): the voltage of the storage node N2 is high, for example, its voltage potential is equal to or close to the power supply voltage or the working voltage VCC, the voltage of the storage node N1 is low, for example, its voltage potential is equal to or close to the ground voltage or the reference voltage VSS, and the value or data stored in the static random access memory 6T unit at this time is logic 0. The state of the storage nodes N1-N2 is DATA[0:1].

[0073] See also Figure 1 In the traditional scheme, if data 0 is written, the current value is 1, which means that the state of the storage node N1-N2 changes from DATA[1:0] to DATA[0:1] in this data writing phase.

[0074] See also Figure 1 , of the two bit lines B1 and B2, B1 is a bit line and B2 can be called a bit line inversion or bit line negation. If they are not pulled down to VSS, VCC can be added or loaded to both bit lines by default. However, if VSS is added or loaded to any bit line, then the VCC on that bit line is removed at the same time.

[0075] See also Figure 1 , the specific operation of changing from DATA[1:0] to DATA[0:1] is as follows: first, the word line W is charged to a high voltage, for example, usually equal to the power supply voltage or the operating voltage VCC, at which time transistors T5 and T6 are turned on.

[0076] See also Figure 1 , the specific operation of changing from DATA[1:0] to DATA[0:1]: Secondly, the voltage of the bit line B1 is pulled down from the power supply voltage VCC to the ground voltage VSS, while the voltage of the bit line B2 is maintained at the power supply voltage VCC. Note that at this time, since the transistor T5 is turned on, the storage node N1 tends to be pulled down to the ground voltage VSS by the bit line B1.

[0077] See also Figure 1 , the specific operation of changing from DATA[1:0] to DATA[0:1]: Furthermore, the storage node N1 will be pulled down to a lower voltage such as close to VSS by the bit line B1 connected to it. After the voltage of the storage node N1 is reduced, it will drive the voltage of the storage node N2 to rise. Note that the increase in the voltage of the storage node N2 will further promote the decrease in the voltage of the storage node N1, so a positive feedback will be established between the storage nodes N1-N2.

[0078] See also Figure 1, the specific operation of changing from DATA[1:0] to DATA[0:1]: Finally, the above positive feedback process will always pull down the voltage of the storage node N1 to the ground voltage VSS, and pull up the voltage of the storage node N2 to the power supply voltage VCC. In this way, the logic state stored in the 6T cell is changed from 1 to 0. The doubt is that as the process node is reduced, the driving capabilities of the PMOS transistors T1-T2 and the NMOS transistors T3-T6 do not change in the same proportion during the reduction of the key size. For example, when N1 is pulled down by B1, the low voltage of N2 may also turn on the PMOS transistor T1 with unstable driving capability, and the voltage of the storage node N1 will show various random results under the state of uncertainty. Because VCC can charge N1 through the PMOS transistor T1, although the access tube also tries to couple the bit line B1 voltage to the storage node N1 at this time. In an uncertain state, its random result may be that the storage circuit completes the change from DATA[1:0] to DATA[0:1]. In an uncertain state, the random result may be that the storage circuit completes the change from DATA[1:0] to DATA[1:0], for example, the voltage of the storage node N1 rebounds to the initial high voltage after being slightly lowered, and the storage node N2 rebounds to the initial low voltage.

[0079] See also Figure 1 If there is no accident, the change from DATA[1:0] to DATA[0:1] is written as 0. If an accident occurs, the change from DATA[1:0] to DATA[0:1] is uncertain, and whether to write 0 is uncertain, which is one of the reasons why the storage circuit cannot write correct data or writes wrong data.

[0080] See also Figure 1 In the traditional scheme, if data 1 is written, the current value is 0. In this data writing phase, it means that the state of the storage node N1-N2 changes from DATA[0:1] to DATA[1:0].

[0081] See also Figure 1 , the specific operation of changing from DATA[0:1] to DATA[1:0] is as follows: first, the word line W is charged to a high voltage, for example, usually equal to the power supply voltage or the operating voltage VCC, at which time transistors T5 and T6 are turned on.

[0082] See also Figure 1 , the specific operation of changing from DATA[0:1] to DATA[1:0]: Secondly, the voltage of the bit line B2 is pulled down from the power supply voltage VCC to the ground voltage VSS, while the voltage of the bit line B1 is maintained at the power supply voltage VCC. Note that at this time, since the transistor T6 is turned on, the storage node N2 tends to be pulled down to the ground voltage VSS by the bit line B2.

[0083] See also Figure 1 , the specific operation of changing from DATA[0:1] to DATA[1:0]: Furthermore, the storage node N2 will be pulled down to a lower voltage such as close to VSS by the bit line B2 connected to it. After the voltage of the storage node N2 is reduced, it will drive the voltage of the storage node N1 to rise. Note that the increase in the voltage of the storage node N1 will further promote the decrease in the voltage of the storage node N2, so a positive feedback will be established between the storage nodes N1-N2.

[0084] See also Figure 1 , the specific operation of changing from DATA[0:1] to DATA[1:0]: Finally, the above positive feedback process will always pull down the voltage of the storage node N2 to the ground voltage VSS, and pull up the voltage of the storage node N1 to the power supply voltage VCC. In this way, the logic state stored in the 6T cell is changed from 0 to 1. The doubt is that as the process node is reduced, the driving capabilities of the PMOS transistors T1-T2 and the NMOS transistors T3-T6 do not change in the same proportion during the reduction of the key size. For example, when N2 is pulled down by B2, the low voltage of N1 may also turn on the PMOS transistor T2 with unstable driving capability, and the voltage of the storage node N2 will show various random results under the state of uncertainty. Because VCC can charge N2 through the PMOS transistor T2, although the access tube also tries to couple the bit line B2 voltage to the storage node N2 at this time. In an uncertain state, its random result may be that the storage circuit completes the change from DATA[0:1] to DATA[1:0]. In an uncertain state, the random result may be that the storage circuit completes the change from DATA[0:1] to DATA[0:1], for example, the voltage of the storage node N2 rebounds to the initial high voltage after being slightly lowered, and the storage node N1 rebounds to the initial low voltage.

[0085] See also Figure 1 If there is no accident, the change from DATA[0:1] to DATA[1:0] is written as 1. If an accident occurs, the change from DATA[0:1] to DATA[1:0] is uncertain, and whether 1 is written is uncertain, which is one of the reasons why the storage circuit cannot write correct data or writes wrong data.

[0086] See also Figure 3As a solution to prevent the storage circuit from being unable to write correct data or writing erroneous data, a delay unit D1, an inverter I1 and a NOR gate NR1 are set for the bit line B1 as shown in the figure. Among them, the transistor TB1 is mainly used to control the potential of the bit line B1, and the transistor TA1 is coupled to the bit line B1 through the transistor TC1 with a source-drain short circuit. The bit line control signal CTL_B1 used to control the bit line B1 can control the turn-off or conduction of the transistor TB1.

[0087] See also Figure 3 , one of the two bifurcated signals of the control signal CTL_B1 is coupled to one input terminal of the NOR gate NR1 through the delay unit D1 and the inverter I1. At the same time, the other of the two bifurcated signals of the control signal CTL_B1 is coupled to the other input terminal of the NOR gate NR1. The output of the NOR gate NR1 controls the turning off or on of the transistor TA1.

[0088] See also Figure 3 When the transistor TA1 is turned on, it couples a reference potential VEE to the bit line B1 through the transistor TC1 shown in the figure, and instantly pulls down the bit line B1. The reference potential VEE can be VSS or a voltage slightly higher or lower than VSS, or a negative voltage. However, VEE should be at least lower than VCC.

[0089] See also Figure 3 As a solution to prevent the storage circuit from being unable to write correct data or writing erroneous data, a delay unit D2, an inverter I2, and a NOR gate NR2 are provided for the bit line B2 as shown in the figure. Among them, the transistor TB2 is mainly used to control the potential of the bit line B2, and the transistor TA2 is coupled to the bit line B2 through the transistor TC2 with a source-drain short circuit. The bit line control signal CTL_B2 used to control the bit line B2 can control the turn-off or conduction of the transistor TB2.

[0090] See also Figure 3 , one of the two bifurcated signals of the control signal CTL_B2 is coupled to one input end of the NOR gate NR2 through the delay unit D2 and the inverter I2. At the same time, the other of the two bifurcated signals of the control signal CTL_B2 is coupled to the other input end of the NOR gate NR2. The output of the NOR gate NR2 controls the turning off or on of the transistor TA2.

[0091] See also Figure 3 When the transistor TA2 is turned on, it couples a reference potential VEE to the bit line B2 through the transistor TC2 shown in the figure, and instantly pulls down the bit line B2. The reference potential VEE can be VSS or a voltage slightly higher or lower than VSS, or a negative voltage. However, VEE should be at least lower than VCC.

[0092] See also Figure 4, taking word line W0 as an example, word line W0 applies a high level to turn on transistors T5-T6. Note that other transistors T5-T6 not mounted on word line W0 are not turned on. For example, if word line WN does not apply a high level, other transistors T5-T6 mounted on word line WN are not turned on. Word line W0 can be charged to a high voltage, such as usually equal to the power supply voltage or the operating voltage VCC. At this time, an attempt is made to write logic data 0 (LOGIC_0).

[0093] See also Figure 4 , taking the bit line B1 as an example, the control signal CTL_B1 jumps from a low level to a high level so as to turn on the transistor TB1 and pull the voltage of the bit line B1 from the power supply voltage VCC to the ground voltage VSS. It should be noted that the control signal CTL_B2 is still at a low level at this time, so the voltage of the bit line B2 is maintained at the power supply voltage VCC. At this time, since the transistor T5 is turned on, the storage node N1 tends to be pulled down to the ground voltage VSS by the bit line B1 as shown in the dotted line. Normally, the high level of the word line W0 will be released as soon as possible and switched to a low level.

[0094] See also Figure 4 Taking the bit line B1 as an example, the transistor TB1 is turned on and the transistor TB2 is turned off, and the storage node N1 will be pulled down to a lower voltage such as close to VSS by the bit line B1 connected to it. After the voltage of the storage node N1 decreases, it will drive the voltage of the storage node N2 to rise. Note that the increase in the voltage of the storage node N2 will further promote the decrease in the voltage of the storage node N1, so a positive feedback will be established between the storage nodes N1-N2.

[0095] See also Figure 5 , taking the bit line B1 as an example, the control signal CTL_B1 jumps from a low level to a high level and slightly delays the high level until the bit line B1 is pulled down to a lower voltage such as close to VSS. The control signal CTL_B1 cannot maintain a high level for a long time, and the word line W0 cannot maintain a high level for a long time, otherwise it will be unbalanced with the data writing or reading speed required by the data communication protocol. Moreover, the driving capabilities of PMOS transistors and NMOS transistors are not the same, and they do not change in the same proportion during the reduction of key dimensions. So the problem is: after the voltage of the storage node N1 is slightly pulled down by the turned-on transistor TB1 and the bit line B1, the voltage of the storage node N1 rebounds to the initial high voltage when the control signal CTL_B1 jumps from a high level to a low level. For the same reason, the positive feedback between the storage nodes N1-N2 will cause the storage node N2 to rebound to the initial low voltage. Data writing fails.

[0096] See also Figure 5, using transistor TA1, the control signal CTL_B1 jumps from a low level to a high level and slightly delays the high level until the bit line B1 is pulled down to a lower voltage such as close to VSS. In this application, no matter how short the high level of the control signal CTL_B1 is required by the data communication protocol, the control signal CTL_B1 will instantly turn on the transistor TA1 once when it jumps from a high level to a low level. At this time, the transistor TB1 is off. The turned-on transistor TA1 will couple the reference voltage VEE shown in the figure to the bit line B1 to prevent the voltage of the storage node N1 from rebounding, and prevent the storage node N1 / N2 from self-oscillating back to the initial voltage due to the positive feedback between the storage nodes N1-N2 caused by this rebound. Thereby, the current value 1 is successfully replaced with the newly written data 0. Change from DATA[1:0] to DATA[0:1]. Instantaneously turning on the transistor once means that the transistor will immediately return to its normal state of being turned off after being turned on once.

[0097] See also Figure 6 , taking word line W0 as an example, word line W0 applies a high level to turn on transistors T5-T6. Note that other transistors T5-T6 not mounted on word line W0 are not turned on. For example, if word line WN does not apply a high level, other transistors T5-T6 mounted on word line WN are not turned on. Word line W0 can be charged to a high voltage, such as usually equal to the power supply voltage or the operating voltage VCC. At this time, an attempt is made to write logic data 1 (LOGIC_1).

[0098] See also Figure 6 , taking the bit line B2 as an example, the control signal CTL_B2 jumps from a low level to a high level so as to turn on the transistor TB2 and pull the voltage of the bit line B2 from the power supply voltage VCC to the ground voltage VSS. It should be noted that the control signal CTL_B1 is still at a low level at this time, so the voltage of the bit line B1 is maintained at the power supply voltage VCC. At this time, since the transistor T6 is turned on, the storage node N2 tends to be pulled down to the ground voltage VSS by the bit line B2 as shown in the dotted line. Normally, the high level of the word line W0 will be released as soon as possible and switched to a low level.

[0099] See also Figure 6 Taking the bit line B2 as an example, when the transistor TB2 is turned on and the transistor TB1 is turned off, the storage node N2 will be pulled down to a lower voltage such as close to VSS by the bit line B2 connected to it. After the voltage of the storage node N2 is reduced, it will drive the voltage of the storage node N1 to rise. Note that the rise in the voltage of the storage node N1 will further promote the decrease in the voltage of the storage node N2, so a positive feedback will be established between the storage nodes N1-N2.

[0100] See also Figure 7, taking the bit line B2 as an example, the control signal CTL_B2 jumps from a low level to a high level and slightly delays the high level until the bit line B2 is pulled down to a lower voltage such as close to VSS. The control signal CTL_B2 cannot maintain a high level for a long time, and the word line W0 cannot maintain a high level for a long time, otherwise it will be unbalanced with the data writing or reading speed required by the data communication protocol. Moreover, the driving capabilities of PMOS transistors and NMOS transistors are not the same, and they do not change in the same proportion during the reduction of key dimensions. So the problem is: after the voltage of the storage node N2 is slightly pulled down by the turned-on transistor TB2 and the bit line B2, the voltage of the storage node N2 rebounds to the initial high voltage when the control signal CTL_B2 jumps from a high level to a low level. For the same reason, the positive feedback between the storage nodes N1-N2 will cause the storage node N1 to rebound to the initial low voltage. Data writing fails.

[0101] See also Figure 7 , using transistor TA2, control signal CTL_B2 jumps from low level to high level and slightly delays the high level until bit line B2 is pulled down to a lower voltage such as close to VSS. In this application, no matter how short the high level of control signal CTL_B2 is required by the data communication protocol, when control signal CTL_B2 jumps from high level to low level, transistor TA2 will be instantly turned on once, at which time transistor TB2 is off, and the turned-on transistor TA2 will couple the illustrated reference voltage VEE to bit line B2, preventing the voltage of storage node N2 from rebounding, and preventing the storage node N1 / N2 from self-oscillating back to the initial voltage due to the positive feedback between storage nodes N1-N2 caused by this rebound. Thereby, the current value 0 is successfully replaced with the newly written data 1. Change from DATA[0:1] to DATA[1:0]. Instantaneously turning on a transistor once means that the transistor will immediately return to its normal state of being turned off after being turned on once.

[0102] See also Figure 8 In a storage array formed by integrating many storage circuits, different storage circuits store different data or information. The word lines W0-WN and bit lines B1-B2 are selected to write data to or read data from the selected storage circuit. Figure 2 .

[0103] See also Figure 8 , assuming that the word line WK and the bit lines B1-B2 are selected, the position of the storage circuit selected individually in the entire storage array is determined, and the logic data stored in it is 0, recorded as LOGIC_0. The previous embodiment has explained how to change the logic data 1 to 0, and the change result is recorded as LOGIC_0. Figure 2 .

[0104] See also Figure 8 , for example, if the word line WN and the bit lines B3-B4 are selected, the position of the storage circuit selected individually in the entire storage array is determined, and the logic data stored in it is 1, recorded as LOGIC_1. The previous embodiment has explained how to change the logic data 0 to 1, and the change result is recorded as LOGIC_1. Figure 2 .

[0105] See also Figure 5 In this application, if data 0 is written, the current value is 1, which means that the state of the storage node N1-N2 changes from DATA[1:0] to DATA[0:1] in this data writing phase.

[0106] See also Figure 5 , the specific operation of changing from DATA[1:0] to DATA[0:1] is as follows: first, the word line W0 is charged to a high voltage, for example, usually equal to the power supply voltage or the operating voltage VCC, at which time transistors T5 and T6 are turned on.

[0107] See also Figure 5 , the specific operation of changing from DATA[1:0] to DATA[0:1]: Secondly, the voltage of the bit line B1 is pulled down from the power supply voltage VCC to the ground voltage VSS, and the voltage of the bit line B2 is maintained at the power supply voltage VCC. Note that at this time, because the transistor T5 is turned on. The control signal CTL_B1 drives the transistor TB1 to turn on and the storage node N1 tends to be pulled down to the ground voltage VSS by the pulled-down bit line B1. The control signal CTL_B1 then jumps to a low potential.

[0108] See also Figure 5 , the specific operation of changing from DATA[1:0] to DATA[0:1]: Furthermore, the storage node N1 will be pulled down to a lower voltage such as close to VSS by the bit line B1 connected to it. After the voltage of the storage node N1 is reduced, it will drive the voltage of the storage node N2 to rise. Note that the increase in the voltage of the storage node N2 will further promote the decrease in the voltage of the storage node N1, so a positive feedback will be established between the storage nodes N1-N2.

[0109] See also Figure 5, the specific operation of changing from DATA[1:0] to DATA[0:1]: Finally, the above positive feedback process will always pull the voltage of the storage node N1 down to the ground voltage VSS, and pull the voltage of the storage node N2 up to the power supply voltage VCC. In this way, the logic state stored in the 6T unit is changed from 1 to 0. The doubt is that as the process node is reduced, the driving capabilities of the PMOS transistors T1-T2 and the NMOS transistors T3-T6 do not change in the same proportion during the reduction of the key size. For example, in the stage where N1 is pulled down by B1, the low voltage of N2 may also turn on the PMOS transistor T1 with unstable driving capability, and the voltage of the storage node N1 will show various random results under the uncertain state. After the control signal CTL_B1 jumps to a low potential to turn off TB1, it will instantly turn on the transistor TA1 when it jumps from a high level to a low level. At this time, the transistor TB1 is off, and the turned-on transistor TA1 will couple the reference voltage VEE shown in the figure to the bit line B1 to prevent the voltage of the storage node N1 from rebounding, and prevent the storage node N1 / N2 from self-oscillating back to the initial voltage due to the positive feedback between the storage nodes N1-N2 caused by the rebound. Thus, the current value 1 is successfully replaced with the newly written data 0.

[0110] See also Figure 7 In this application, if data 1 is written, the current value is 0, which means that the state of the storage node N1-N2 changes from DATA[0:1] to DATA[1:0] in this data writing phase.

[0111] See also Figure 7 , the specific operation of changing from DATA[0:1] to DATA[1:0] is as follows: first, the word line W is charged to a high voltage, for example, usually equal to the power supply voltage or the operating voltage VCC, at which time transistors T5 and T6 are turned on.

[0112] See also Figure 7 , the specific operation of changing from DATA[0:1] to DATA[1:0]: Secondly, the voltage of the bit line B2 is pulled down from the power supply voltage VCC to the ground voltage VSS, while the voltage of the bit line B1 is maintained at the power supply voltage VCC. Note that at this time, because the transistor T6 is turned on. The control signal CTL_B2 drives the transistor TB2 to turn on and the storage node N2 tends to be pulled down to the ground voltage VSS by the bit line B2. The control signal CTL_B2 then jumps to a low potential.

[0113] See also Figure 7, the specific operation of changing from DATA[0:1] to DATA[1:0]: Furthermore, the storage node N2 will be pulled down to a lower voltage such as close to VSS by the bit line B2 connected to it. After the voltage of the storage node N2 is reduced, it will drive the voltage of the storage node N1 to rise. Note that the increase in the voltage of the storage node N1 will further promote the decrease in the voltage of the storage node N2, so a positive feedback will be established between the storage nodes N1-N2.

[0114] See also Figure 7 , the specific operation of changing from DATA[0:1] to DATA[1:0]: Finally, the above positive feedback process will always pull the voltage of the storage node N2 down to the ground voltage VSS, and pull the voltage of the storage node N1 up to the power supply voltage VCC. In this way, the logic state stored in the 6T unit is changed from 0 to 1. The doubt is that as the process node is reduced, the driving capabilities of the PMOS transistors T1-T2 and the NMOS transistors T3-T6 do not change in the same proportion during the reduction of the key size. For example, in the stage where N2 is pulled down by B2, the low voltage of N1 may also turn on the PMOS transistor T2 with unstable driving capability, and the voltage of the storage node N2 will show various random results under the state of uncertainty. After the control signal CTL_B2 jumps to a low potential to turn off TB2, it will instantly turn on the transistor TA2 when it jumps from a high level to a low level. At this time, the transistor TB2 is off, and the turned-on transistor TA2 will couple the reference voltage VEE shown in the figure to the bit line B2 to prevent the voltage of the storage node N2 from rebounding, and prevent the storage node N1 / N2 from self-oscillating back to the initial voltage due to the positive feedback between the storage nodes N1-N2 caused by the rebound. Thus, the current value 0 is successfully replaced with the newly written data 1.

[0115] See also Figure 4 In an optional embodiment, after the control signal CTL_B1 has written the previous data or the previous bit through the logic level jump of the previous signal, it is necessary to write the next data or the next bit, that is, there must be a logic level jump event of the next signal. In the communication protocol for data storage, such as the cache structure field of SRAM applications, the data read and write rate specified by the bus protocol commonly used is extremely high. The time between the two level jump events of the control signal CTL_B1 becomes shorter as the speed of the communication protocol increases. Therefore, the primary design technique in this article is not to affect the normal level operation of the control signals CTL_B1 and CTL_B2. Figure 6The same is true. Based on the communication protocol restrictions, it also means that the timing of turning on and off the transistors TA1 and TB1 needs to be selected in a targeted manner. For example, their switching actions are not allowed to affect the normal changes in voltage and current of the bit line B1 and the bit line B2 during data reading and writing, but to assist in the smooth writing of normal data. This is also one of the most prominent advantages of this application compared to traditional technologies. Otherwise, it will have a negative impact on the normal data writing: the unexpected changes in the voltage and current of B1 and B2 are the main reason.

[0116] See also Figure 4 In an optional embodiment, a method for writing data is disclosed: in the stage of writing data to a static random memory cell, the static random memory cell to be written is selected by the word line signal of the first level such as a high level (such as word line W0) and the first bit line signal of the first level such as a high level (such as control signal CTL_B1), and the static random memory cell to be written is a storage circuit T-UNIT that matches the word line W0. In the stage of writing data to a static random memory cell, if the word line signal of the first level such as a high level (such as word line WN) and the first bit line signal of the first level such as a high level (such as control signal CTL_B1) select the static random memory cell to be written, the static random memory cell to be written is a storage circuit T-UNIT that matches the word line WN.

[0117] See also Figure 5 The first level, such as the high level, first bit line signal (such as control signal CTL_B1) can turn on the bit line switch (such as transistor TB1) that controls the potential of bit line B1, and latch the low side voltage such as VSS into the first storage node N1 through the bit line. The second level second bit line signal (such as control signal CTL_B2) can turn off the bit line switch (such as transistor TB2) that controls the potential of bit line B2, and latch the high side voltage such as VCC into the second storage node N2 complementary to the first storage node N1 through the bit line, thereby replacing the previously saved current value such as 1 with the pre-written value such as 0 and writing it into the static random access memory cell to be written. For example, write DATA[0:1]. At this time, the stored logical data is 0, recorded as LOGIC_0.

[0118] See also Figure 5 In an optional embodiment, at the moment when the first bit line signal (such as the control signal CTL_B1) jumps from the first level to the second level and turns off the bit line switch (such as the transistor TB1), a preset voltage such as VEE which is lower than the high-side voltage such as VCC is instantaneously coupled to the bit line B1 once, thereby preventing the logic state of the first bit line signal from jumping and causing the pre-written value written into the static random access memory cell to rebound to the current value.

[0119] See also Figure 5In an optional embodiment, the first level may be a high level and the second level may be a low level, or the first level may be a low level and the second level may be a high level.

[0120] See also Figure 5 In an optional embodiment, after the static random access memory unit T-UNIT completes data writing, the word line signal (such as word line W0) and the first bit line signal (such as control signal CTL_B1) are both changed from the first level to the second level to exit the data writing operation on the static random access memory unit T-UNIT to be written.

[0121] See also Figure 5 In an optional embodiment, the low-side voltage uses, for example, a reference ground voltage VSS, the high-side voltage uses, for example, an operating voltage or a power supply voltage VCC of a static random access memory cell, and the preset voltage such as VEE is an independent reference voltage or a low-side voltage VSS or a negative voltage value.

[0122] See also Figure 5 In an optional embodiment, the current values ​​stored in the first storage node N1 and the second storage node N2 include data 1 (such as DATA[1:0]), and the pre-written values ​​to be written include data 0 (such as DATA[0:1]).

[0123] See also Figure 5 In an optional embodiment, the first bit line signal (such as the control signal CTL_B1) is divided into two branches and one of the two branches is coupled to an input end of a NOR gate (Nor Gate) NR1, and the other is coupled to the other input end of the NOR gate NR1 after passing through the delay unit D1 and the inverter I1. The output of the NOR gate NR1 is used to control the turning off or on of a switch (such as a transistor TA1, which can be called the first switch). At the transition moment (the transition moment when the first bit line signal jumps from the first level to the second level and turns off the bit line switch TB1), the preset voltage can be coupled to the bit line B1 once. The preset voltage such as VEE is coupled to B1 once for each bit of data written. The preset voltage can be coupled to the bit line B1, for example, by turning on the switch (such as the transistor TA1) to couple VEE to B1.

[0124] See also Figure 5 A switch (such as transistor TA1) and a transistor TC1 with a source-drain short circuit are set between a preset voltage such as VEE and the bit line B1. The two ends of transistor TC1 are respectively connected to the bit line B1 and to the preset voltage such as VEE through the switch such as TA1. The two ends of transistor TC1 are respectively the gate end and the source-drain short circuit end. The two ends of transistor TC1 can be Figure 5One of the two ends of transistor TC1 is connected to the bit line B1 and the other end is connected to the preset voltage through the first switch TA1.

[0125] See also Figure 5 In an optional embodiment, at the transition moment (the moment when the first bit line signal jumps from the first level to the second level and turns off the bit line switch TB1), the instantaneous coupling of the preset voltage VEE to the bit line B1 causes the first storage node N1 to approach the low-side voltage VSS but not to the oscillation of the low-side voltage VSS, and the second storage node N2 to approach the high-side voltage VCC but not to the oscillation of the high-side voltage VCC, and develops toward the oscillation trend of establishing positive feedback between the first storage node and the second storage node. Instead of breaking the balance of positive feedback between N1 and N2 and causing the first storage node N1 to oscillate to the high-side voltage VCC or the second storage node N2 to oscillate to the low-side voltage VSS. The first storage node N1 is not allowed to oscillate repeatedly between the low-side voltage VSS and the high-side voltage VCC, and the second storage node N2 is not allowed to oscillate repeatedly between the low-side voltage VSS and the high-side voltage VCC.

[0126] See also Figure 4 In an optional embodiment, a method for writing data is disclosed: in the stage of writing data to a static random access memory cell, the static random access memory cell to be written is selected by the word line signal of the first level such as a high level (such as word line W0) and the second bit line signal of the first level such as a high level (such as control signal CTL_B2), and the static random access memory cell to be written is a storage circuit T-UNIT that matches the word line W0. In the stage of writing data to a static random access memory cell, the static random access memory cell to be written is selected by the word line signal of the first level such as a high level (such as word line WK) and the second bit line signal of the first level such as a high level (such as control signal CTL_B2), and the static random access memory cell to be written is a storage circuit T-UNIT that matches the word line WK.

[0127] See also Figure 7The first level, such as the high level, second bit line signal (such as control signal CTL_B2) can turn on the bit line non switch (such as transistor TB2) that controls the potential of bit line non B2, and latch the low side voltage VSS into the second storage node N2 through the bit line non. The second level first bit line signal (such as control signal CTL_B1) can turn off the bit line switch (such as transistor TB1) that controls the potential of bit line B1, and latch the high side voltage such as VCC into the first storage node N1 complementary to the second storage node N2 through the bit line, thereby replacing the previously saved current value such as 0 with the pre-written value such as 1 and writing it into the static random access memory cell to be written. For example, write DATA[1:0]. The logical data stored at this time is 1, recorded as LOGIC_1.

[0128] See also Figure 7 In an optional embodiment, at the moment when the second bit line signal (such as the control signal CTL_B2) flips from the first level to the second level and turns off the bit line non-switch (such as the transistor TB2), the preset voltage VEE lower than the high-side voltage such as VCC is instantaneously coupled to the bit line non-B2 once to prevent the pre-written value from rebounding to the current value.

[0129] See also Figure 7 In an optional embodiment, the first level may be a high level and the second level may be a low level, or the first level may be a low level and the second level may be a high level.

[0130] See also Figure 7 In an optional embodiment, after the static random access memory unit T-UNIT completes data writing, the word line signal (such as word line W0) and the second bit line signal (such as control signal CTL_B2) are both jumped from the first level to the second level to exit the data writing operation on the static random access memory unit T-UNIT to be written.

[0131] See also Figure 7 In an optional embodiment, the current values ​​stored in the first storage node N1 and the second storage node N2 include data 0 (such as DATA[0:1]), and the pre-written values ​​to be written include data 1 (such as DATA[1:0]).

[0132] See also Figure 7In an optional embodiment, the second bit line signal (such as the control signal CTL_B2) is divided into two branches and one of the two branches is coupled to an input end of a NOR gate (Nor Gate) NR2, and the other is coupled to the other input end of the NOR gate NR2 after passing through the delay unit D2 and the inverter I2. The output of the NOR gate NR2 is used to control the turning off or on of a switch (such as a transistor TA2, which can be called the second switch), and the preset voltage is coupled to the bit line non-switch TB2 once at the transition moment (the transition moment when the second bit line signal jumps from the first level to the second level and turns off the bit line non-switch TB2). The preset voltage VEE is coupled to B2 once for each bit of data written. The preset voltage is coupled to the bit line non-B2, for example, by turning on the switch (such as the transistor TA2) to couple VEE to B2.

[0133] See also Figure 7 A switch (such as transistor TA2) and a transistor TC2 with a source-drain short circuit are set between the preset voltage such as VEE and the bit line non-B2. The two ends of transistor TC2 are respectively connected to the bit line non-B2 and connected to the preset voltage such as VEE through the switch such as TA2. The two ends of transistor TC2 are respectively the gate end and the source-drain short circuit end. The two ends of transistor TC2 can be Figure 7 In the embodiment of the present invention, the gate terminal and the source-drain short circuit terminal are swapped. One of the two ends of the transistor TC2 is connected to the bit line non-B2 and the other end is connected to the preset voltage through the second switch TA2.

[0134] See also Figure 7 In an optional embodiment, at the transition moment (the moment when the second bit line signal turns from the first level to the second level and the bit line non-switch TB2 is turned off), the instantaneous coupling of the preset voltage VEE to the bit line non-switch TB2 causes the second storage node N2 to tend to approach the low-side voltage VSS but not to the oscillation of the low-side voltage VSS, and the first storage node N1 to tend to approach the high-side voltage VCC but not to the oscillation of the high-side voltage VCC, and develops toward the oscillation trend of establishing positive feedback between the first storage node and the second storage node. Instead of breaking the balance of positive feedback between N1 and N2 and causing the second storage node N2 to oscillate to the high-side voltage VCC or the first storage node N1 to oscillate to the low-side voltage VSS. The second storage node N2 is not allowed to oscillate repeatedly between the low-side voltage VSS and the high-side voltage VCC, and the first storage node N1 is not allowed to oscillate repeatedly between the low-side voltage VSS and the high-side voltage VCC.

[0135] See also Figure 7In an optional embodiment, the storage circuit includes: a plurality of static random access memory cells sharing a bit line B1 and a bit line non-B2, a first bit line signal (control signal CTL_B1) controls the turning off or on of a bit line switch such as TB1 to adjust the potential of the bit line B1, a second bit line signal (control signal CTL_B2) controls the turning off or on of a bit line non-switch such as TB2 to adjust the potential of the bit line non-B2, and a word line signal such as WK matching any static random access memory cell is used to select any static random access memory cell (such as T-UNIT matching WK). 0≤K≤N.

[0136] See also Figure 7 In an optional embodiment, the first bit line signal (control signal CTL_B1) is divided into two branches and one of the two branches is coupled to an input end of a first NOR gate such as NR1, and the other is coupled to the other input end of the first NOR gate such as NR1 after passing through a delay unit and an inverter. The output of the first NOR gate such as NR1 controls the turning off or on of a first switch such as TA1. When the first bit line signal (control signal CTL_B1) jumps from the first level to the second level and turns off the bit line switch such as TB1, the preset voltage VEE is coupled to the bit line B1 once to prevent the pre-written value written into the static random access memory cell from rebounding to the current value.

[0137] See also Figure 7 A first switch such as TA1 and a first transistor such as TC1 with a source and drain short-circuited are set between a preset voltage such as VEE and a bit line B1, and two ends of the first transistor such as TC1 are respectively connected to the bit line B1 and to the preset voltage such as VEE through the first switch such as TA1.

[0138] See also Figure 7 In an optional embodiment, the second bit line signal (control signal CTL_B2) is divided into two branches and one of the two branches is coupled to an input end of a second NOR gate such as NR2, and the other is coupled to the other input end of the second NOR gate such as NR2 after passing through a delay unit and an inverter. The output of the second NOR gate such as NR2 controls the turning off or on of a second switch such as TA2. When the second bit line signal (control signal CTL_B2) flips from the first level to the second level and turns off the bit line non-switch such as TB2, the preset voltage VEE is coupled to the bit line non-switch B2 once, thereby preventing the logic state of the second bit line signal from jumping and causing the pre-written value written into the static random memory cell to rebound to the current value.

[0139] See also Figure 7 A second switch such as TA2 and a second transistor such as TC2 with a source and drain short-circuited are set between the preset voltage such as VEE and the bit line non-B2, and the two ends of the second transistor such as TC2 are respectively connected to the bit line non-B2 and connected to the preset voltage such as VEE through the second switch such as TA2.

[0140] See also Figure 7 , the data writing method or the corresponding storage circuit function is as described below. In the stage of high-frequency data writing (for example, to cater to high-speed communication protocols), avoid the event of failure to write data and write erroneous data caused by the fact that the write state of the previous data writing action has not stabilized and the adjacent subsequent data writing action has come again, and prevent the subsequent data writing action from being constructed under the unstable data condition of the previous data writing action. Otherwise, starting from a wrong writing action, all subsequent written data have reason to be suspected of being wrong, because the previous unstable data is inaccurate, and the subsequent writing of data is established under inaccurate data conditions. Obviously, the present application can avoid the event of failure to accurately write data or write erroneous data caused by the too short time between the previous data writing action and the adjacent subsequent data writing action. In the industry, high-speed caches based on SRAM often require the use of high-speed communication protocols to perform data operations. The aforementioned negative events typically include: the state of the previous data writing has not stabilized, such as the data of the first storage node and the second storage node are still oscillating and not stable, and the high-frequency subsequent data writing comes next, so the subsequent written data are all wrong. For example, when the CPU executes a task and uses the cache and memory to interact, the related task will crash or run incorrectly during the execution process. When the first bit line signal flips from the first level to the second level and turns off the bit line switch, the preset voltage is instantaneously coupled to the bit line once; when the second bit line signal flips from the first level to the second level and turns off the bit line non-switch, the preset voltage is instantaneously coupled to the bit line non-once. When the next data is written, the self-oscillation of the first storage node and the second storage node caused by the previous data writing has stabilized. It can be guaranteed that the adjacent next data writing action is in the stable writing state period of the previous data writing action, and it can also be guaranteed that the next data writing action is constructed under the data stability condition of the previous data writing action. The time between the previous data writing action and the adjacent next data writing action decreases with the increase of the data writing speed. Usually, the next data writing action and the previous data writing action are absolutely not allowed to overlap in time. However, the coupling timing of the previous data writing action using the preset voltage to couple to the bit line or to the bit line non-is designed to overlap or partially overlap with the next data writing action in time. Especially under high writing speed conditions, the advantages of this solution are obvious, as it not only meets the requirements of high-speed writing, but also avoids the negative events of being unable to write data or writing erroneous data. Figure 5 The relevant embodiments of Figure 7 Various technical implementation schemes mentioned.

[0141] See also Figure 7, the data writing method or the corresponding storage circuit function is as described below. In the stage of high-frequency data writing (for example, to cater to high-speed communication protocols), based on the condition that the driving capabilities of both PMOS and NMOS in the static random access memory cell are similar, at the transition moment (the transition moment when the first bit line signal jumps from the first level to the second level and turns off the bit line switch), the instantaneous coupling of the preset voltage to the bit line causes the first storage node to tend to oscillate close to the low-side voltage but not to the low-side voltage, and the second storage node to tend to oscillate close to the high-side voltage but not to the high-side voltage, and oscillates toward the trend of establishing positive feedback between the first and second storage nodes, rather than breaking the balance of positive feedback and causing the first storage node to oscillate to the high-side voltage or the second storage node to oscillate to the low-side voltage. Figure 5 The relevant embodiments of Figure 7 The various technical implementation schemes mentioned above. The negative impact of the convergence of the driving capabilities of PMOS and NMOS in the static random access memory cell is manifested in that the first storage node may be pulled to the level of the high-side voltage by the second storage node during the oscillation phase when it approaches the low-side voltage, and the second storage node may be pulled to the level of the low-side voltage by the first storage node during the oscillation phase when it approaches the high-side voltage, and negative feedback is formed between the first storage node and the second storage node. The smaller the critical dimensions (CD) used by PMOS and NMOS, the more serious this consequence is.

[0142] See also Figure 7 , the data writing method or the corresponding storage circuit function is as described below. In the stage of high-frequency data writing (for example, to cater to high-speed communication protocols), based on the condition that the driving capabilities of both PMOS and NMOS in the static random memory cell are similar, at the said jump moment (the jump moment when the second bit line signal jumps from the first level to the second level and turns off the bit line non-switch), the instantaneous coupling of the preset voltage to the bit line non-switch causes the second storage node to tend to oscillate close to the low-side voltage but not to the low-side voltage, and the first storage node to tend to oscillate close to the high-side voltage but not to the high-side voltage, and oscillate towards the trend of establishing positive feedback between the first and second storage nodes, rather than breaking the balance of positive feedback and causing the second storage node to oscillate to the high-side voltage or the first storage node to oscillate to the low-side voltage. Figure 5 The relevant embodiments of Figure 7The various technical implementation schemes mentioned above. The negative impact of the convergence of the driving capabilities of PMOS and NMOS in the static random access memory cell is manifested in that the second storage node may be pulled to the level of the high-side voltage by the first storage node during the oscillation phase when it approaches the low-side voltage, and the first storage node may be pulled to the level of the low-side voltage by the second storage node during the oscillation phase when it approaches the high-side voltage, and negative feedback is formed between the first storage node and the second storage node. The smaller the critical dimensions (CD) used by PMOS and NMOS, the more serious this consequence is.

[0143] See also Figure 4 , the first bit line signal such as CTL_B1 is divided into two branches. It is worth noting that these two branches change unconditionally following the change of the first bit line signal such as CTL_B1. Therefore, there is no need to use any additional enable signal to control the enable or disable time of these two branches. The effect of TC1 isolating DC can also prevent the static current of these two branches from coupling to the bit line B1. That is, the circuit part where these two branches are located only plays a predetermined effect in the stage of writing data, and does not affect the operation of the entire SRAM at other times. This advantage is not available in traditional solutions or other solutions. For example, if the preset voltage VEE is a negative voltage lower than the reference ground voltage or is directly the reference ground voltage VSS, TC1 avoids the generation of static current between the bit line B1 and the circuit part where the two branches are located, so the bit line B1 will not be constrained by the circuit where the two branches are located.

[0144] See also Figure 6 , the second bit line signal such as CTL_B2 is divided into two branches. It is worth noting that these two branches change unconditionally following the change of the second bit line signal such as CTL_B2. Therefore, there is no need to use any additional enable signal to control the enable or disable time of these two branches. The effect of TC2 isolating DC can also prevent the static current of these two branches from coupling to the bit line B2. That is, the circuit part where these two branches are located only plays a predetermined effect in the stage of writing data, and does not affect the operation of the entire SRAM at other times. This advantage is not available in traditional solutions or other solutions. For example, if the preset voltage VEE is a negative voltage lower than the reference ground voltage or is directly the reference ground voltage VSS, TC2 avoids the generation of static current between the bit line B2 and the circuit part where the two branches are located, so the bit line B2 will not be constrained by the circuit where the two branches are located.

[0145] The above description and drawings provide typical embodiments of specific structures of specific embodiments, and the above invention provides existing preferred embodiments, but these contents are not intended to be limiting. For those skilled in the art, various changes and modifications will undoubtedly be obvious after reading the above description. Therefore, the attached claims should be regarded as covering all changes and modifications to the true intent and scope of the present invention. Any and all equivalent scopes and contents within the scope of the claims should be considered to still be within the intent and scope of the present invention.

Claims

1. A method for writing data, characterized in that: include: In the stage of writing data to the static random access memory cell, the static random access memory cell to be written is selected by a first level word line signal and a first bit line signal: The first bit line signal of the first level turns on the bit line switch that controls the bit line potential, and latches the low-side voltage into the first storage node through the bit line; as well as The bit line non-switch controlling the bit line non-potential is turned off by a second bit line signal of a second level, and the high side voltage is latched into a second storage node complementary to the first storage node through the bit line non-potential; Thereby, the pre-written value replaces the previously saved current value and is written into the static random access memory cell to be written; At the moment when the first bit line signal jumps from the first level to the second level and turns off the bit line switch, a preset voltage lower than the high side voltage is instantaneously coupled to the bit line once to prevent the pre-written value from rebounding to the current value, wherein the preset voltage is an independent reference voltage or the low side voltage or a negative voltage; A switch and a transistor with a source and a drain short-circuited are arranged between the preset voltage and the bit line, and two ends of the transistor are respectively connected to the bit line and to the preset voltage through the switch; The first bit line signal is divided into two branches, one of which is coupled to an input end of an NOR gate, and the other is coupled to the other input end of the NOR gate after passing through a delay unit and an inverter. The output of the NOR gate controls the turning off or on of the switch, and couples the preset voltage to the bit line once by turning on the switch at the transition moment.

2. The method according to claim 1, characterized in that: The low-side voltage is a reference ground voltage, the high-side voltage is a power supply voltage for the static random access memory cell to work, and when the preset voltage is a negative voltage, it is limited to be lower than the reference ground voltage.

3. The method according to claim 1, characterized in that: The first level is a high level and the second level is a low level, or the first level is a low level and the second level is a high level.

4. The method according to claim 1, characterized in that: After the static random access memory cell completes data writing, the word line signal and the first bit line signal both jump from the first level to the second level to exit the data writing operation on the static random access memory cell to be written.

5. The method according to claim 1, characterized in that: At the transition moment, the preset voltage instantaneously couples the bit line, causing the first storage node to approach the low-side voltage but not yet to oscillate at the low-side voltage, and the second storage node to approach the high-side voltage but not yet to oscillate at the high-side voltage, toward establishing a positive feedback trend between the voltage of the first storage node and the voltage of the second storage node.

6. A method for writing data, characterized in that: include: In the stage of writing data to the static random access memory cell, the static random access memory cell to be written is selected by a word line signal of a first level and a second bit line signal: The second bit line signal of the first level turns on the bit line non-switch controlling the bit line non-potential, and latches the low-side voltage into the second storage node through the bit line non-potential; as well as The bit line switch controlling the bit line potential is turned off by the first bit line signal of the second level, and the high side voltage is latched into the first storage node complementary to the second storage node through the bit line; Thereby, the pre-written value replaces the previously saved current value and is written into the static random access memory cell to be written; At the moment when the second bit line signal jumps from the first level to the second level and turns off the bit line non-switch, a preset voltage lower than the high-side voltage is instantaneously coupled to the bit line non-switch to prevent the pre-written value from rebounding to the current value, wherein the preset voltage is an independent reference voltage or the low-side voltage or a negative voltage; A switch and a transistor with a source and a drain short-circuited are arranged between the preset voltage and the bit line NAND, and two ends of the transistor are respectively connected to the bit line NAND and to the preset voltage through the switch; The second bit line signal is divided into two branches, one of which is coupled to an input end of an NOR gate, and the other is coupled to the other input end of the NOR gate after passing through a delay unit and an inverter. The output of the NOR gate controls the turning off or on of the switch, and couples the preset voltage to the bit line NOR once by turning on the switch at the transition moment.

7. The method according to claim 6, characterized in that: At the transition moment, the preset voltage instantaneously couples the bit line, causing the second storage node to approach the low-side voltage but not to oscillate at the low-side voltage, and the first storage node to approach the high-side voltage but not to oscillate at the high-side voltage, toward establishing a positive feedback trend between the voltage of the first storage node and the voltage of the second storage node.

8. The method according to claim 6, characterized in that: The first level is a high level and the second level is a low level, or the first level is a low level and the second level is a high level.

9. The method according to claim 6, characterized in that: The low-side voltage is a reference ground voltage, the high-side voltage is a power supply voltage for the static random access memory cell to work, and when the preset voltage is a negative voltage, it is limited to be lower than the reference ground voltage.

10. A storage circuit, characterized in that: include: A plurality of static random access memory cells sharing a bit line and a bit line non-signal, wherein the first bit line signal controls the turning off or on of a bit line switch to adjust the potential of the bit line, the second bit line signal controls the turning off or on of a bit line non-signal to adjust the potential of the bit line non-signal, and a word line signal matching any static random access memory cell is used to select the static random access memory cell; A first switch and a first transistor with a source and a drain short-circuited are arranged between the preset voltage and the bit line, and two ends of the first transistor are respectively connected to the bit line and to the preset voltage through the first switch; The first bit line signal is divided into two branches, one of which is coupled to an input end of the first NOR gate, and the other is coupled to the other input end of the first NOR gate after passing through a delay unit and an inverter. The output of the first NOR gate controls the turning off or on of the first switch. When the first bit line signal jumps from the first level to the second level and the bit line switch is turned off, the preset voltage is coupled to the bit line once, so as to prevent the pre-written value written into the static random access memory cell from rebounding to the current value. as well as A second switch and a second transistor with a source and a drain short-circuited are arranged between the preset voltage and the bit line N, and two ends of the second transistor are respectively connected to the bit line N and to the preset voltage through the second switch; The second bit line signal is divided into two branches, one of which is coupled to an input end of the second NOR gate, and the other is coupled to the other input end of the second NOR gate after passing through a delay unit and an inverter. The output of the second NOR gate controls the turning off or on of the second switch. When the second bit line signal jumps from the first level to the second level and the bit line NOR switch is turned off, the preset voltage is coupled to the bit line NOR once to prevent the pre-written value written into the static random access memory cell from rebounding to the current value.

Images