Semiconductor structure and method of forming the same
By setting horizontally arranged switching transistors and storage transistors within the storage cell, combined with a channel-all-around structure, the problem of low storage density in semiconductor structures is solved, thereby improving storage density and integration and expanding application areas.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-05-24
- Publication Date
- 2026-07-24
Smart Images
Figure CN117177556B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.
[0003] To increase the density of transistors and capacitors in semiconductor structures such as DRAM, capacitors are often arranged laterally. However, with the continuous development of semiconductor technology and the shrinking size of semiconductor structures, the increase in storage density of semiconductor structures with lateral capacitor structures is limited, thus restricting the further development of semiconductor structures.
[0004] Therefore, how to improve the storage density of semiconductor structures and expand their application areas is a pressing technical problem that needs to be solved. Summary of the Invention
[0005] This disclosure provides semiconductor structures and methods for forming the same in some embodiments, which are used to solve the problem of low storage density in semiconductor structures, thereby expanding the application areas of semiconductor structures.
[0006] According to some embodiments, this disclosure provides a semiconductor structure, including:
[0007] Substrate;
[0008] A switching transistor, located on the top surface of the substrate, includes a first gate, a first channel layer covering a portion of the first gate, and a first source / drain and a second source / drain both covering the surface of the first channel layer. The first source / drain and the second source / drain are distributed at opposite ends of the first channel layer along a first direction, which is a direction parallel to the top surface of the substrate.
[0009] A storage transistor, located on the top surface of the substrate, includes a second gate, a second channel layer covering a portion of the second gate, and a third source drain and a fourth source drain, both covering the surface of the second channel layer. The third source drain and the fourth source drain are distributed at opposite ends of the second channel layer along a first direction. A portion of the second gate extending out of the second channel layer along the first direction is electrically connected to the second source drain. The storage transistor is used to store charge.
[0010] In some embodiments, the material of the second channel layer is indium gallium zinc oxide.
[0011] In some embodiments, the switching transistor further includes a first gate dielectric layer, the first gate dielectric layer being located between the first channel layer and the first gate;
[0012] The storage transistor further includes a second gate dielectric layer, which is located between the second channel layer and the second gate.
[0013] In some embodiments, it also includes:
[0014] A write word line is located on the top surface of the substrate and is electrically connected to a portion of the first gate extending out of the first channel layer along the first direction.
[0015] Write bit lines, located on the top surface of the substrate, and electrically connected to the first source and drain;
[0016] The read word line is located on the top surface of the substrate and is electrically connected to the fourth source-drain electrode;
[0017] The read bit line is located on the top surface of the substrate and is electrically connected to the third source-drain electrode.
[0018] In some embodiments, the write word line and the read word line both extend along a second direction, and the write bit line and the read bit line both extend along a third direction. The second direction and the third direction both intersect with the first direction, and the second direction intersects with the third direction.
[0019] In some embodiments, a plurality of memory cells are stacked along the third direction, each memory cell including a switching transistor and a storage transistor arranged along the first direction, the second direction being a direction parallel to the top surface of the substrate, and the third direction being a direction perpendicular to the top surface of the substrate;
[0020] The multiple write word lines are spaced apart along the third direction, and among two adjacent write word lines along the third direction, the write word line closer to the substrate protrudes from the other write word line along the second direction.
[0021] The read word lines are arranged at intervals along the third direction, and among two adjacent read word lines along the third direction, the read word line closer to the substrate protrudes from the other read word line along the second direction.
[0022] In some embodiments, a plurality of memory cells are stacked along the second direction, each memory cell including a switching transistor and a storage transistor arranged along the first direction, the second direction being a direction perpendicular to the top surface of the substrate, and the third direction being a direction parallel to the top surface of the substrate;
[0023] The multiple write bit lines are arranged at intervals along the second direction, and among two adjacent write bit lines along the second direction, the write bit line closer to the substrate protrudes from the other write bit line along the third direction.
[0024] The read bit lines are arranged at intervals along the second direction, and among two adjacent read bit lines along the second direction, the read bit line closer to the substrate protrudes from the other read bit line along the third direction.
[0025] In some embodiments, the material of the write word line is polycrystalline silicon material including first doped ions, and the material of the read word line includes a metallic material.
[0026] According to other embodiments, this disclosure also provides a method for forming a semiconductor structure, including:
[0027] Provide substrate;
[0028] A switching transistor and a storage transistor are formed on the top surface of the substrate. The switching transistor includes a first gate, a first channel layer covering a portion of the first gate, and a first source drain and a second source drain, both covering the surface of the first channel layer. The first source drain and the second source drain are distributed at opposite ends of the first channel layer along a first direction. The storage transistor includes a second gate, a second channel layer covering a portion of the second gate, and a third source drain and a fourth source drain, both covering the surface of the second channel layer. The third source drain and the fourth source drain are distributed at opposite ends of the second channel layer along the first direction. A portion of the second gate extending out of the second channel layer along the first direction is electrically connected to the second source drain. The storage transistor is used to store charge. The first direction is a direction parallel to the top surface of the substrate.
[0029] In some embodiments, forming a switching transistor and a storage transistor on the top surface of the substrate includes:
[0030] A stacked layer is formed on the top surface of the substrate, the stacked layer comprising a plurality of semiconductor layers spaced apart along a direction perpendicular to the top surface of the substrate;
[0031] A support frame is formed to cover a portion of the semiconductor layer, the support frame dividing the stacked layer into a switching region and a storage region arranged along the first direction, wherein the semiconductor layer of the switching region serves as the first gate and the semiconductor layer of the storage region serves as the second gate;
[0032] A channel material is deposited on the first gate and the second gate to form a first channel layer covering the first gate and a second channel layer covering the second gate;
[0033] A second source / drain electrode is formed covering the surface of the first channel layer, and the second source / drain electrode is connected to the second gate electrode.
[0034] In some embodiments, forming a stacked layer on the top surface of the substrate includes:
[0035] The first sacrificial layer and the semiconductor layer are alternately deposited on the top surface of the substrate to form the stacked layer;
[0036] The stacked layer is etched to form a first portion, and a second portion and a third portion, both protruding from the sidewall of the first portion along a second direction, wherein the second direction is parallel to the top surface of the substrate and intersects with the first direction;
[0037] Multiple first trenches are formed that penetrate the first portion, and the multiple first trenches divide each of the semiconductor layers into multiple active strips spaced apart along a second direction.
[0038] In some embodiments, a support frame covering a portion of the semiconductor layer is formed, comprising:
[0039] A switching region and a storage region are defined in the stacked layer, such that the third part is located on the side of the switching region away from the storage region, and the second part is located on the side of the storage region closer to the switching region;
[0040] A second sacrificial layer is formed to fill the first trench and the gap between the second portion and the third portion;
[0041] Remove the second sacrificial layer at the end of the storage area adjacent to the switch area to expose a portion of the active strip;
[0042] The support frame is formed to cover the exposed surface of the active strip.
[0043] In some embodiments, forming a first channel layer covering the first gate and a second channel layer covering the second gate includes:
[0044] Remove the stacked layer and the second sacrificial layer at the end of the switching region adjacent to the support frame to form a second trench exposing the substrate;
[0045] A third sacrificial layer is formed to fill the second trench;
[0046] Remove the first sacrificial layer and the second sacrificial layer to expose a portion of the first gate and a portion of the second gate;
[0047] A first gate dielectric layer is formed to cover the exposed first gate, and a second gate dielectric layer is formed to cover the exposed second gate;
[0048] Remove the third sacrificial layer to expose the end of the second gate located in the support frame;
[0049] Implanting second doped ions into the exposed end of the second gate;
[0050] A channel material is deposited on the first gate and the second gate to form a first channel layer covering the first gate and a second channel layer covering the second gate, and the first channel layer is in contact with the end of the second gate after the second doped ions are implanted.
[0051] In some embodiments, before forming the second source / drain electrode covering the surface of the first channel layer, the method further includes:
[0052] A conductive material is deposited on a portion of the surface of the second channel layer and the surface of the second portion of the storage region to form a fourth source / drain electrode and read word lines extending along the second direction and continuously connecting a plurality of the fourth source / drain electrodes.
[0053] In some embodiments, after forming the second source / drain electrode covering the surface of the first channel layer, the method further includes:
[0054] The first source / drain, the third source / drain, the read bit line, and the write bit line are formed. The first source / drain and the second source / drain are distributed at opposite ends of the first channel layer along a first direction. The third source / drain and the fourth source / drain are distributed at two pairs of ends of the second channel layer along the first direction. The read bit line extends along a third direction and is continuously connected to a plurality of third source / drains spaced apart along the third direction. The write bit line extends along a third direction and is continuously connected to a plurality of first source / drains spaced apart along the third direction. The third direction is a direction perpendicular to the top surface of the substrate.
[0055] Write word lines are formed in the third portion and the first portion connected to the third portion along the second direction, and the write word lines are connected to the first gate.
[0056] The semiconductor structure and its formation method provided in some embodiments of this disclosure, by setting up switching transistors and storage transistors arranged horizontally in a storage cell, controlling the charging and discharging of the storage transistors through the switching transistors to write information to the storage transistors, and storing and retrieving information through the storage transistors, eliminates the need for capacitor structures in the storage cell, thereby reducing the size of the storage cell and increasing the storage density of the memory. Furthermore, in some embodiments of this disclosure, the first gate of the first channel layer-covered portion of the switching transistor and the second gate of the second channel layer-covered portion of the storage transistor, i.e., both the switching transistor and the storage transistor in the storage cell, have a channel-encircling structure, thereby further reducing the size of the storage cell and increasing the storage density of the semiconductor structure. Attached Figure Description
[0057] Appendix Figure 1 This is a schematic diagram of a semiconductor structure provided in some embodiments of this disclosure;
[0058] Appendix Figure 2 This is a schematic diagram of the structure of a transistor provided in some embodiments of this disclosure;
[0059] Appendix Figure 3 This is a top view schematic diagram of a semiconductor structure provided in some embodiments of this disclosure;
[0060] Appendix Figure 4 This is a schematic diagram of the circuit principle of a semiconductor structure provided in some embodiments of this disclosure;
[0061] Appendix Figure 5 This is a flowchart illustrating a method for forming a semiconductor structure according to some embodiments of this disclosure;
[0062] Appendix Figures 6A-6Q This is a schematic diagram of the main process structure provided in some embodiments of the present disclosure during the formation of a semiconductor structure. Detailed Implementation
[0063] The specific embodiments of the semiconductor structure and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0064] Embodiments of this disclosure provide a semiconductor structure, with appended... Figure 1 This is a schematic diagram of a semiconductor structure provided in some embodiments of this disclosure, with accompanying drawings. Figure 2 This is a schematic diagram of the structure of a transistor (taking a switching transistor as an example) provided in some embodiments of this disclosure, with attached... Figure 3 This is a top view schematic diagram of a semiconductor structure provided in some embodiments of this disclosure, with accompanying drawings. Figure 4 This is a schematic diagram of a semiconductor structure provided in some embodiments of this disclosure. The semiconductor structure provided in the embodiments of this disclosure can be used to form DRAM, but is not limited thereto. Figures 1-4 As shown, the semiconductor structure includes:
[0065] Substrate;
[0066] Switching transistor T1 is located on the substrate ( Figures 1-4 On the top surface of the substrate (not shown), there is a first gate 10, a first channel layer 12 covering a portion of the first gate 10, and a first source / drain 11 and a second source / drain 14 both covering the surface of the first channel layer 12. The first source / drain 11 and the second source / drain 14 are distributed at opposite ends of the first channel layer 12 along a first direction D1, which is parallel to the top surface of the substrate.
[0067] The storage transistor T2 is located on the top surface of the substrate and includes a second gate 16, a second channel layer 18 covering a portion of the second gate 16, and a third source drain 19 and a fourth source drain 17, both covering the surface of the second channel layer 18. The third source drain 19 and the fourth source drain 17 are distributed at opposite ends of the second channel layer 18 along a first direction D1. The portion of the second gate 16 extending out of the second channel layer 18 along the first direction D1 is electrically connected to the second source drain 14. The storage transistor is used to store charge.
[0068] For example, the substrate can be, but is not limited to, a silicon substrate. This disclosure uses a silicon substrate as an example for illustration. In other examples, the substrate can be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The top surface of the substrate refers to the surface on the substrate used to form the switching transistor T1 and the storage transistor T2. The semiconductor structure includes multiple memory cells arranged in an array, located within a region surrounded by a support frame 30. Each memory cell includes a storage region and a switching region separated by the support frame 30. The storage region contains a storage transistor T2, and the switching region contains a switching transistor T1, thus forming a 2TOC structure. This eliminates the need for a capacitor structure within the memory cell, reducing the size of the memory cell and increasing the memory density. The storage transistor T2 is used for storing charge and reading stored signals; the switching transistor T1 is connected to the storage transistor T2 and is used to control the charging and discharging of the storage transistor T2 to write stored signals to it. The portion of the second gate 16 extending out of the second channel layer 18 along the first direction D1 and being electrically connected to the second source / drain 14 means that the portion of the second gate 16 not covered by the second channel layer 18 is electrically connected to the second source / drain 14.
[0069] like Figure 2 As shown, the switching transistor T1 employs a channel-all-around structure, meaning that the first gate 10 is partially covered by the first channel layer 12 of the switching transistor T1, thereby further reducing the size of the memory cell and increasing the storage density of the semiconductor structure. The first source-drain 11 and the second source-drain 14 in the switching transistor T1 independently cover the surface of the first channel layer 12, and the first source-drain 11 and the second source-drain 14 are distributed along the first direction D1 at opposite ends of the first channel layer 12. A portion of the first gate 10 extends out of the first channel layer 12 along the first direction D1. Similarly, the storage transistor T2 also employs a channel-all-around structure, meaning that the second gate 16 is partially covered by the second channel layer 18 of the storage transistor T2, to further reduce the size of the memory cell and increase the storage density of the semiconductor structure. The third source-drain 19 and the fourth source-drain 17 in the storage transistor T2 independently cover opposite sides of the second channel layer 18 along the first direction D1. A portion of the second gate 16 extends out of the second channel layer 18 along the first direction D1. The second source-drain 14 and the second gate 16 of the switching transistor are partially electrically connected along the first direction D1 to extend the second channel layer 18, thereby controlling the opening and closing of the storage transistor T2 through the switching transistor T1.
[0070] In some embodiments, at least one of the first channel layer 12 and the second channel layer 18 is made of indium gallium zinc oxide.
[0071] For example, indium gallium zinc oxide (IGZO) material possesses excellent properties such as high on / off ratio and low leakage current, and its retention time can meet the charge storage requirements of the storage transistor T2. Therefore, in this embodiment, using IGZO material to form the second channel layer 18 helps to further improve the charge retention performance of the semiconductor structure. In one embodiment, the material of the first channel layer 12 is the same as that of the second channel layer 18, for example, both are IGZO, thereby allowing the first channel layer 12 and the second channel layer 18 to be formed simultaneously, thereby further simplifying the semiconductor structure fabrication process.
[0072] In some embodiments, the switching transistor T1 further includes a first gate dielectric layer 22, which is located between the first channel layer 12 and the first gate 10;
[0073] The storage transistor T2 also includes a second gate dielectric layer, which is located between the second channel layer 18 and the second gate 16.
[0074] In one embodiment, the material of the first gate dielectric layer 22 may be the same as that of the second gate dielectric layer, such as an oxide (e.g., silicon dioxide) material, but is not limited thereto. For example, the first gate dielectric layer 22 and the second gate dielectric layer may be formed using in-situ oxidation growth (e.g., in-situ water vapor generation) or atomic layer deposition processes.
[0075] In some embodiments, the semiconductor structure further includes:
[0076] Write word line 13 is located on the top surface of the substrate and is electrically connected to a portion of the first gate 10 extending out of the first channel layer 12 along the first direction.
[0077] Write bit line 15, located on the top surface of the substrate, and electrically connected to the first source / drain electrode 11;
[0078] The read word line 20 is located on the top surface of the substrate and is electrically connected to the fourth source / drain electrode 17;
[0079] Read bit line 21, located on the top surface of the substrate, and electrically connected to the third source / drain 19.
[0080] In some embodiments, both the write word line 13 and the read word line 15 extend along the second direction D2, and both the write bit line 15 and the read bit line 21 extend along the third direction D3. Both the second direction D2 and the third direction D3 intersect the first direction D1, and the second direction D2 intersects the third direction D3. The partial electrical connection between the write word line 13 and the first gate 10 extending along the first direction out of the first channel layer 12 refers to the partial electrical connection between the write word line 13 and the first gate 10 that is not covered by the first channel layer 12.
[0081] To further improve the storage density and integration of the semiconductor structure, in some embodiments, the semiconductor structure includes a plurality of memory cells stacked along a second direction D2, each memory cell including a switching transistor T1 and a storage transistor T2 arranged along a first direction D1, the second direction D2 being a direction perpendicular to the top surface of the substrate, and the third direction D3 being a direction parallel to the top surface of the substrate.
[0082] Multiple write bit lines 15 are arranged at intervals along the second direction D2, and among two adjacent write bit lines 15 along the second direction D2, the write bit line 15 closer to the substrate protrudes from the other write bit line 15 along the third direction D3.
[0083] Multiple read bit lines 21 are arranged at intervals along the second direction D2, and among two adjacent read bit lines 21 along the second direction D2, the read bit line 21 closer to the substrate protrudes from the other read bit line 21 along the third direction D3.
[0084] For example, the semiconductor structure includes multiple layers of memory cells stacked along a second direction D2, each layer including at least a plurality of memory cells spaced apart along a third direction D3, thereby forming a memory cell array with a three-dimensional structure. Write word line 13 extends along the second direction D2 and is continuously electrically connected to the first gate 10 of the plurality of memory cells spaced apart along the second direction D2, forming a vertical write word line structure. Write bit line 15 extends along the third direction D3 and is continuously electrically connected to the first source / drain 11 of the plurality of memory cells spaced apart along the third direction D3, forming a horizontal write bit line structure. Read word line 20 extends along the second direction D2 and is continuously electrically connected to the fourth source / drain 17 of the plurality of memory cells spaced apart along the second direction D2, forming a vertical read word line structure. Read bit line 21 extends along the third direction D3 and is continuously electrically connected to the third source / drain 19 of the plurality of memory cells spaced apart along the third direction D3, forming a horizontal read bit line structure.
[0085] Multiple write bit lines 15 are arranged at intervals along the second direction D2, and the ends of the multiple write bit lines 15 form a stepped structure (i.e., among two adjacent write bit lines 15 along the second direction D2, the write bit line 15 closer to the substrate protrudes beyond the other write bit line 15 along the third direction D3), thereby facilitating the introduction of write bit line signals from the same side of the semiconductor structure through the write bit line plug 34, thereby further improving the integration of the semiconductor structure. Multiple read bit lines 21 are arranged at intervals along the second direction D2, and the ends of the multiple read bit lines 21 also form a stepped structure (i.e., among two adjacent read bit lines 21 along the second direction D2, the read bit line 21 closer to the substrate protrudes beyond the other read bit line 21 along the third direction D3), thereby facilitating the extraction of read bit line signals from the same side of the semiconductor structure through the read bit line plug 33, thereby further improving the integration of the semiconductor structure. Write word line 13 introduces the write word line signal through write word line plug 32 located above it, and read word line 20 introduces the read word line signal through read word line plug 31 located above it.
[0086] In other embodiments, the semiconductor structure includes a plurality of memory cells stacked along a third direction D3, each memory cell including a switching transistor T1 and a storage transistor T2 arranged along a first direction D1, the second direction D2 being parallel to the top surface of the substrate, and the third direction D3 being perpendicular to the top surface of the substrate.
[0087] Multiple write word lines 13 are arranged at intervals along the third direction D3, and among two adjacent write word lines 13 along the third direction D3, the write word line 13 closer to the substrate protrudes from the other write word line 13 along the second direction D2.
[0088] Multiple read word lines 20 are arranged at intervals along the third direction D3, and among two adjacent read word lines 20 along the third direction D3, the read word line 20 closer to the substrate protrudes from the other read word line 20 along the second direction D2.
[0089] In this case, horizontal write word line structure, horizontal read word line structure, vertical write bit line structure, and vertical read bit line structure can be formed.
[0090] To simplify the manufacturing process of semiconductor structures, in some embodiments, the material of the write word line 13 is polycrystalline silicon material including first doped ions, and the material of the read word line 20 is a metal material.
[0091] In other embodiments, in order to reduce the resistance of the write word line 13, both the write word line 13 and the read word line 20 are made of metallic materials (e.g., tungsten).
[0092] It should be noted that, in the embodiments disclosed herein, the first source-drain can be one of the source and the drain, and the second source-drain can be the other of the source and the drain; similarly, the third source-drain can be one of the source and the drain, and the fourth source-drain can be the other of the source and the drain.
[0093] This disclosure also provides a method for forming a semiconductor structure, with appended... Figure 5 This is a flowchart illustrating a method for forming a semiconductor structure according to some embodiments of this disclosure, with attached... Figures 6A-6Q These are schematic diagrams illustrating the main process structures involved in forming a semiconductor structure, provided in some embodiments of this disclosure. The semiconductor structure formation method provided in these embodiments can also be used to form structures such as... Figures 1-4 The semiconductor structure shown. (As shown in the image) Figure 5 , Figures 6A-6Q As shown, the method for forming the semiconductor structure includes:
[0094] Step S51, provide substrate 60, such as Figure 6A As shown.
[0095] For example, substrate 60 may be, but is not limited to, a silicon substrate. This embodiment of the disclosure uses a silicon substrate as an example for illustration. In other examples, substrate 60 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
[0096] In step S52, a switching transistor and a storage transistor are formed on the top surface of the substrate 60. The switching transistor includes a first gate 10, a first channel layer 12 covering a portion of the first gate 10, and a first source drain 11 and a second source drain 14, both covering the surface of the first channel layer 12. The first source drain 11 and the second source drain 14 are distributed at opposite ends of the first channel layer 12 along a first direction D1. The storage transistor includes a second gate 16, a second channel layer 18 covering a portion of the second gate 16, and a third source drain 19 and a fourth source drain 17, both covering the surface of the second channel layer 18. The third source drain 19 and the fourth source drain 17 are distributed at opposite ends of the second channel layer 18 along the first direction D1. The portion of the second gate 16 extending out of the second channel layer 18 along the first direction D1 is electrically connected to the second source drain 14. The storage transistor is used to store charge. The first direction D1 is a direction parallel to the top surface of the substrate 60.
[0097] In some embodiments, a switching transistor and a storage transistor are formed on the top surface of the substrate 60, including:
[0098] A stacked layer is formed on the top surface of the substrate, the stacked layer comprising a plurality of semiconductor layers 83 spaced apart along a direction perpendicular to the top surface of the substrate, such as... Figure 6A As shown;
[0099] A support frame 66 is formed to cover a portion of the semiconductor layer 83. The support frame 66 divides the stacked layer into a switching region P1 and a storage region P2 arranged along a first direction D1. The semiconductor layer 83 of the switching region P1 serves as a first gate 10, and the semiconductor layer 83 of the storage region P2 serves as a second gate 16. Figure 6C As shown;
[0100] A channel material is deposited on the first gate 10 and the second gate 16 to form a first channel layer 12 covering the first gate 10 and a second channel layer 18 covering the second gate 16, as shown below. Figure 6J As shown;
[0101] A second source / drain 14 is formed covering the surface of the first channel layer 12, and the second source / drain 14 is connected to the second gate 16, as shown below. Figure 6N As shown.
[0102] In some embodiments, forming a stacked layer on the top surface of the substrate 60 includes:
[0103] Alternating deposition of a first sacrificial layer 81 and a semiconductor layer 83 on the top surface of the substrate 60 forms a stacked layer, such as... Figure 6A As shown;
[0104] The etched stacked layers form a first portion 61, and a second portion 62 and a third portion 63, both protruding along a second direction D2 from the sidewall of the first portion 61. The second direction D2 is parallel to the top surface of the substrate 60, and the second direction D2 intersects with the first direction D1. Figure 6B As shown;
[0105] Multiple first trenches 65 are formed penetrating the first portion 61, and the multiple first trenches 65 divide each semiconductor layer 83 into multiple active strips 64 spaced apart along the second direction D2, such as... Figure 6B As shown.
[0106] For example, chemical vapor deposition, physical vapor deposition, or atomic layer deposition can be used to alternately deposit the first sacrificial layer 81 and the semiconductor layer 83 on the top surface of the substrate 60 along a third direction to form a stacked layer, resulting in a layer as shown below. Figure 6A The structure is shown. The first sacrificial layer 81 can be made of an oxide material (e.g., silicon dioxide) or silicon germanide, and the semiconductor layer 83 can be made of polycrystalline silicon with a first doped ion. It should be noted that the surface of polycrystalline silicon is usually rough; in this case, a chemical mechanical polishing process or similar method can be used to planarize its surface. The first doped ion can be a P-type ion or an N-type ion. Next, a hard mask material such as silicon nitride can be deposited on the top surface of the stacked layers to form a hard mask layer 76. Then, other mask layers can be deposited on top of the hard mask layer 76, allowing the formation of the first portion 61, the second portion 62, the third portion 63, and multiple first trenches 65 penetrating the first portion 61 using SADP (Self-aligned Double Patterning) or SAQP (Self-aligned Quadruple Patterning). The first portion 61 is subsequently used to form a memory transistor and a switching transistor, the second portion 62 is subsequently used to form read word lines, and the third portion 63 is subsequently used to form write word lines. The hard mask layer 76 (e.g., silicon nitride layer) remaining after the formation of the first trench 65 can protect the topmost semiconductor layer in the stacked layers.
[0107] In some embodiments, a support frame 66 covering a portion of the semiconductor layer 83 is formed, comprising:
[0108] In the stacked layer, a switch region P1 and a storage region P2 are defined such that the third part 63 is located on the side of the switch region P1 away from the storage region P2, and the second part 62 is located on the side of the storage region P2 closer to the switch region P1.
[0109] A second sacrificial layer 80 is formed to fill the first trench 65 and the gap between the second portion 62 and the third portion 63;
[0110] Remove the second sacrificial layer 80 at the end of the storage area P2 adjacent to the switch area P1, exposing the active strip 64;
[0111] A support frame 66 is formed to cover the exposed surface of the active strip 64, such as... Figure 6C As shown.
[0112] In some embodiments, forming a first channel layer 12 covering the first gate 10 and a second channel layer 18 covering the second gate 16 includes:
[0113] Remove the stacked layer and the second sacrificial layer 80 at the end of the switch region P1 adjacent to the support frame 66 to form a second trench exposing the substrate 60;
[0114] A third sacrificial layer 67 is formed, filling the second trench, as shown. Figure 6D As shown;
[0115] Removing the first sacrificial layer 81 and the second sacrificial layer 80 exposes portions of the first gate 10 and portions of the second gate 16, as follows. Figure 6E As shown;
[0116] A first gate dielectric layer 22 is formed covering the exposed first gate 10, and a second gate dielectric layer 71 is formed covering the exposed second gate 16, as shown below. Figure 6F As shown;
[0117] Remove the third sacrificial layer 67 to expose the end of the second gate 16 located in the support frame 66, as shown. Figure 6H As shown;
[0118] Implanting second doped ions into the exposed end 681 of the second gate 16, as... Figure 6I As shown;
[0119] A channel material is deposited on the first gate 10 and the second gate 16 to form a first channel layer 12 covering the first gate 10 and a second channel layer 18 covering the second gate 16. The first channel layer 12 is in contact with the end of the second gate 16 after implantation of the second doped ions. Figure 6J As shown.
[0120] For example, SADP or SAQP etching can be used to etch the stacked layers and the second sacrificial layer 80 along the support frame 66, forming second trenches exposing the substrate 60 on both the side of the switching region P1 facing the memory region P2 and the side of the memory region P2 away from the switching region P1. Then, an epitaxial growth process can be used to form a third sacrificial layer 67 that fills the second trenches, such as... Figure 6DAs shown. The material of the support frame 66 can be the same as the material of the hard mask layer 76. In one embodiment, the material of the support frame 66 can be, but is not limited to, a nitride material (e.g., silicon nitride). The material of the second sacrificial layer 80 can be, but is not limited to, an oxide material (e.g., silicon dioxide). The material of the third sacrificial layer 67 should have a higher etching selectivity than the material of the support frame 66 to facilitate subsequent selective etching. In one embodiment, the material of the third sacrificial layer 67 can be silicon. Next, a wet etching process can be used to remove the first sacrificial layer 81 and the second sacrificial layer 80 in the stacked layers, forming as shown. Figure 6E The diagram shows a top view of the structure. The top surfaces of the third part 63 and the portion of the first part 61 connected to the third part 63 along the second direction D2 are covered by the support frame 66. Therefore, the first sacrificial layer 81 in the third part 63 and the portion of the first part 61 connected to the third part 63 along the second direction D2 is not removed. Then, an in-situ oxidation growth (e.g., in-situ water vapor growth) or atomic layer deposition process is used to form a first gate dielectric layer 22 on the exposed surface of the first gate 10, and simultaneously a second gate dielectric layer 71 is formed on the exposed surface of the second gate 16, forming a structure as shown... Figure 6F The diagram shows a top view of the structure. The first gate dielectric layer 22 and the second gate dielectric layer 16 can be made of silicon dioxide or other materials with a high dielectric constant (High-K, HK).
[0121] Next, a hard mask material is spin-coated onto the switching region P1 and the storage region P2 to form a first filling layer 73 that fills the gaps in the switching region P1 and the storage region P2, resulting in... Figure 6G The diagram shows a top view of the structure. Then, the third sacrificial layer 67 is removed, forming a third trench 74 that exposes the end of the second gate 16 located in the support frame 66, forming as shown... Figure 6H The diagram shows a top view of the structure. After removing the first filler layer 73, second doped ions are implanted to the end of the second gate 16 exposed in the third trench 74, as shown. Figure 6I As shown, this is done to enhance the conductivity of the end of the second gate 16 and reduce the contact resistance between the switching transistor and the storage transistor inside the semiconductor structure.
[0122] An IGZO channel material is deposited on the first gate dielectric layer 22 and the second gate dielectric layer 71 using a process such as atomic layer deposition (ALD) to form a first channel layer 12 located on the surface of the first gate dielectric layer 22 and covering a portion of the first gate 10, and a second channel layer 18 located on the surface of the second gate dielectric layer 71 and covering a portion of the second gate 16, resulting in the following: Figure 6JThe diagram shows a top view of the structure. The deposition of the channel material causes the formed first channel layer 12 to make contact with the end of the second gate 16 after the implantation of the second doped ions, thereby connecting the switching region P1 and the storage region P2. Backfilling with an insulating dielectric material such as oxide (e.g., silicon dioxide) forms a second filling layer 75, resulting in... Figure 6K The diagram shows a top view of the structure.
[0123] In some embodiments, before forming the second source / drain electrode 14 covering the surface of the first channel layer 12, the method further includes:
[0124] Conductive material is deposited on a portion of the surface of the second channel layer 18 and the surface of the second portion 62 located in the storage region P2 to form fourth source / drain electrodes, and read word lines 20 extending along the second direction D2 and continuously connecting multiple fourth source / drain electrodes, such as... Figure 6M As shown.
[0125] For example, a portion of the second filling layer 75 on the surface of the second channel layer 18 and the surface of the second portion 62 is removed using a photolithography process, exposing a portion of the second channel layer 18. Then, a conductive material such as tungsten or TiN is deposited on the exposed surface of the second channel layer 18 using an atomic layer deposition process, for example, to form the fourth source / drain of the storage transistor, and read word lines 20 extending along the second direction D2 and continuously connecting multiple fourth source / drains, as shown below. Figure 6M As shown. Next, a portion of the second filler layer 75 on the surface of the first channel layer 12 is removed, exposing a portion of the first channel layer 12. Then, a conductive material such as tungsten or TiN is deposited on the exposed surface of the first channel layer 12 to form the second source / drain electrode 14 of the switching transistor, as shown. Figure 6N As shown.
[0126] In some embodiments, after forming the second source / drain electrode 14 covering the surface of the first channel layer 12, the method further includes:
[0127] Forming the first source / drain 11, the third source / drain 19, the read bit line 21, and the write bit line 15, as follows: Figure 6O As shown, the first source drain 11 and the second source drain 14 are distributed at opposite ends of the first channel layer 12 along the first direction D1, and the third source drain 19 and the fourth source drain 17 are distributed at opposite ends of the second channel layer 18 along the first direction D1. The read bit line 21 extends along the third direction D3 and continuously connects multiple third source drains 19 spaced apart along the third direction D3. The write bit line 15 extends along the third direction D3 and continuously connects multiple first source drains 11 spaced apart along the third direction D3. The third direction D3 is a direction perpendicular to the top surface of the substrate 60.
[0128] Write word lines 13 are formed in the third portion 63 and the first portion 61 connected to the third portion 63 along the second direction D2. Write word lines 13 are connected to the first gate 10, as shown below. Figure 6P and Figure 6Q As shown, where, Figure 6Q This is a schematic diagram of the connection structure between the storage transistor and the switching transistor within the storage cell.
[0129] For example, after forming the second source / drain 14, an oxide material (e.g., silicon dioxide) is backfilled into the storage region P2 and the switching region P1. Next, a portion of the second filler layer is removed using, for example, a photolithography process, exposing a portion of the second channel layer 18 and a portion of the first channel layer 12. A conductive material such as tungsten or TiN is deposited on the exposed surfaces of the second channel layer 18 and the first channel layer 12 to form the first source / drain 11, the third source / drain 19, the read bit line 21, and the write bit line 15. Then, a support frame 66 covering the third portion 63 and connected to the third portion 61 along the second direction D2 is removed using, for example, a photolithography process, exposing the semiconductor layer 83. The exposed semiconductor layer 83 is etched to form multiple write word lines 13, and the ends of the multiple write word lines 13 arranged at intervals along the third direction D3 are stepped (that is, among two adjacent write word lines 13 on the third direction D3, the write word line closer to the substrate 60 protrudes from the other write word line along the second direction D2).
[0130] It should be noted that the semiconductor structures formed according to the above-described method include horizontal write word line structures, horizontal read word line structures, vertical write bit line structures, and vertical read bit line structures (such as...). Figure 6Q (As shown). It is understood that, referring to the above formation method and making appropriate adjustments, the formed semiconductor structure can include a vertical write word line structure, a vertical read word line structure, a horizontal write bit line structure, and a horizontal read bit line structure (as shown). Figure 1 (As shown).
[0131] The semiconductor structure and its formation method provided in this disclosure, by setting up a horizontally arranged switching transistor and a storage transistor in a storage cell, controls the charging and discharging of the storage transistor to write information to the storage transistor, and stores and reads information through the storage transistor, eliminating the need for a capacitor structure in the storage cell, thereby reducing the size of the storage cell and increasing the storage density of the memory. Furthermore, in some embodiments of this disclosure, the first gate of the first channel layer-covered portion of the switching transistor and the second gate of the second channel layer-covered portion of the storage transistor, i.e., both the switching transistor and the storage transistor in the storage cell, have a channel-encircling structure, which further reduces the size of the storage cell and thus increases the storage density of the semiconductor structure.
[0132] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A switching transistor and a storage transistor are formed on the top surface of the substrate. The switching transistor includes a first gate, a first channel layer covering a portion of the first gate, and a first source drain and a second source drain, both covering the surface of the first channel layer. The first source drain and the second source drain are distributed at opposite ends of the first channel layer along a first direction. The storage transistor includes a second gate, a second channel layer covering a portion of the second gate, and a third source drain and a fourth source drain, both covering the surface of the second channel layer. The third source drain and the fourth source drain are distributed at opposite ends of the second channel layer along the first direction. A portion of the second gate extending out of the second channel layer along the first direction is electrically connected to the second source drain. The storage transistor is used to store charge. The first direction is a direction parallel to the top surface of the substrate. The formation of switching transistors and storage transistors on the top surface of the substrate includes: A stacked layer is formed on the top surface of the substrate, the stacked layer comprising a plurality of semiconductor layers spaced apart along a direction perpendicular to the top surface of the substrate; A support frame is formed to cover a portion of the semiconductor layer, the support frame dividing the stacked layer into a switching region and a storage region arranged along the first direction, wherein the semiconductor layer of the switching region serves as the first gate and the semiconductor layer of the storage region serves as the second gate; A channel material is deposited on the first gate and the second gate to form a first channel layer covering the first gate and a second channel layer covering the second gate; A second source / drain electrode is formed covering the surface of the first channel layer, and the second source / drain electrode is connected to the second gate electrode.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, Forming a stacked layer on the top surface of the substrate includes: The first sacrificial layer and the semiconductor layer are alternately deposited on the top surface of the substrate to form the stacked layer; The stacked layer is etched to form a first portion, and a second portion and a third portion, both protruding from the sidewall of the first portion along a second direction, wherein the second direction is parallel to the top surface of the substrate and intersects with the first direction; Multiple first trenches are formed that penetrate the first portion, and the multiple first trenches divide each of the semiconductor layers into multiple active strips spaced apart along a second direction.
3. The method for forming a semiconductor structure according to claim 2, characterized in that, The support frame forming a portion of the semiconductor layer includes: A switching region and a storage region are defined in the stacked layer, such that the third part is located on the side of the switching region away from the storage region, and the second part is located on the side of the storage region closer to the switching region; A second sacrificial layer is formed to fill the first trench and the gap between the second portion and the third portion; Remove the second sacrificial layer at the end of the storage area adjacent to the switch area to expose a portion of the active strip; The support frame is formed to cover the exposed surface of the active strip.
4. The method for forming a semiconductor structure according to claim 3, characterized in that, Forming a first channel layer covering the first gate and a second channel layer covering the second gate includes: Remove the stacked layer and the second sacrificial layer at the end of the switching region adjacent to the support frame to form a second trench exposing the substrate; A third sacrificial layer is formed to fill the second trench; Remove the first sacrificial layer and the second sacrificial layer to expose a portion of the first gate and a portion of the second gate; A first gate dielectric layer is formed to cover the exposed first gate, and a second gate dielectric layer is formed to cover the exposed second gate; Remove the third sacrificial layer to expose the end of the second gate located in the support frame; Implanting a second doped ion into the exposed end of the second gate; A channel material is deposited on the first gate and the second gate to form a first channel layer covering the first gate and a second channel layer covering the second gate, and the first channel layer is in contact with the end of the second gate after the second doped ions are implanted.
5. The method for forming a semiconductor structure according to claim 4, characterized in that, Before forming the second source / drain electrode covering the surface of the first channel layer, the method further includes: A conductive material is deposited on a portion of the surface of the second channel layer and the surface of the second portion of the storage region to form a fourth source / drain electrode and read word lines extending along the second direction and continuously connecting a plurality of the fourth source / drain electrodes.
6. The method for forming a semiconductor structure according to claim 4, characterized in that, After forming the second source / drain electrode covering the surface of the first channel layer, the method further includes: The first source / drain, the third source / drain, the read bit line, and the write bit line are formed. The first source / drain and the second source / drain are distributed at opposite ends of the first channel layer along a first direction. The third source / drain and the fourth source / drain are distributed at two pairs of ends of the second channel layer along the first direction. The read bit line extends along a third direction and is continuously connected to a plurality of third source / drains spaced apart along the third direction. The write bit line extends along a third direction and is continuously connected to a plurality of first source / drains spaced apart along the third direction. The third direction is a direction perpendicular to the top surface of the substrate. Write word lines are formed in the third portion and the first portion connected to the third portion along the second direction, and the write word lines are connected to the first gate.
7. A semiconductor structure, characterized in that, Obtained by the forming method according to any one of claims 1-6, comprising: Substrate; A switching transistor, located on the top surface of the substrate, includes a first gate, a first channel layer covering a portion of the first gate, and a first source / drain and a second source / drain both covering the surface of the first channel layer. The first source / drain and the second source / drain are distributed at opposite ends of the first channel layer along a first direction, which is a direction parallel to the top surface of the substrate. A storage transistor, located on the top surface of the substrate, includes a second gate, a second channel layer covering a portion of the second gate, and a third source drain and a fourth source drain, both covering the surface of the second channel layer. The third source drain and the fourth source drain are distributed at opposite ends of the second channel layer along a first direction. A portion of the second gate extending out of the second channel layer along the first direction is electrically connected to the second source drain. The storage transistor is used to store charge.
8. The semiconductor structure according to claim 7, characterized in that, The material of at least one of the first channel layer and the second channel layer is indium gallium zinc oxide.
9. The semiconductor structure according to claim 7, characterized in that, The switching transistor further includes a first gate dielectric layer, which is located between the first channel layer and the first gate. The storage transistor further includes a second gate dielectric layer, which is located between the second channel layer and the second gate.
10. The semiconductor structure according to claim 7, characterized in that, Also includes: A write word line is located on the top surface of the substrate and is electrically connected to a portion of the first gate extending out of the first channel layer along the first direction. Write bit lines, located on the top surface of the substrate, and electrically connected to the first source and drain; The read word line is located on the top surface of the substrate and is electrically connected to the fourth source-drain electrode; The read bit line is located on the top surface of the substrate and is electrically connected to the third source-drain electrode.
11. The semiconductor structure according to claim 10, characterized in that, Both the write word line and the read word line extend along a second direction, and both the write bit line and the read bit line extend along a third direction. Both the second direction and the third direction intersect with the first direction, and the second direction intersects with the third direction.
12. The semiconductor structure according to claim 11, characterized in that, The device includes a plurality of memory cells stacked along the third direction, each memory cell including the switching transistor and the storage transistor arranged along the first direction, the second direction being parallel to the top surface of the substrate, and the third direction being perpendicular to the top surface of the substrate. The multiple write word lines are spaced apart along the third direction, and among two adjacent write word lines along the third direction, the write word line closer to the substrate protrudes from the other write word line along the second direction. The read word lines are arranged at intervals along the third direction, and among two adjacent read word lines along the third direction, the read word line closer to the substrate protrudes from the other read word line along the second direction.
13. The semiconductor structure according to claim 11, characterized in that, It includes a plurality of memory cells stacked along the second direction, each memory cell including the switching transistor and the storage transistor arranged along the first direction, the second direction being a direction perpendicular to the top surface of the substrate, and the third direction being a direction parallel to the top surface of the substrate; The multiple write bit lines are arranged at intervals along the second direction, and among two adjacent write bit lines along the second direction, the write bit line closer to the substrate protrudes from the other write bit line along the third direction. The read bit lines are arranged at intervals along the second direction, and among two adjacent read bit lines along the second direction, the read bit line closer to the substrate protrudes from the other read bit line along the third direction.
14. The semiconductor structure according to claim 10, characterized in that, The write word line is made of polycrystalline silicon material containing first doped ions, and the read word line is made of metal material.