Semiconductor memory device

Abstract

In the first chip of the semiconductor memory device of the present invention, a plurality of first semiconductor films extend along the stacking direction, penetrating a plurality of first conductive layers. In the first chip, a plurality of memory cells are formed at a plurality of intersection locations where the plurality of first conductive layers intersect with the plurality of first semiconductor films. In the second chip, a plurality of second semiconductor films extend along the stacking direction, penetrating a plurality of second conductive layers. In the second chip, a plurality of memory cells are formed at a plurality of intersection locations where the plurality of second conductive layers intersect with the plurality of second semiconductor films. The first connection configuration and the second connection configuration are insulated from each other. The first connection configuration extends from the first conductive layer reached by the leading edge of the first semiconductor film in the plurality of first conductive layers to the third chip. The second connection configuration extends from the second conductive layer reached by the leading edge of the second semiconductor film in the plurality of second conductive layers to the third chip.

Description

[0001] [Cross-reference to related applications]

[0002] This application claims priority based on the priority of the prior Japanese Patent Application No. 2022-090696, filed on June 3, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] In semiconductor memory devices with arrays of memory cells, data is sometimes erased from the array. Specific functions are implemented during the erasure process in semiconductor memory devices. Summary of the Invention

[0005] One embodiment provides a semiconductor memory device that can easily make the erase process multifunctional.

[0006] According to one embodiment, a semiconductor memory device having a first chip, a second chip, and a third chip is provided. The second chip is bonded to the first chip. The third chip is bonded to the second chip on the side opposite to the first chip. The first chip has a plurality of first conductive layers, a plurality of first semiconductor films, and a plurality of first insulating films. The plurality of first conductive layers are stacked with respect to a first insulating layer. The plurality of first semiconductor films extend through the plurality of first conductive layers in a stacking direction. The plurality of first insulating films are disposed between the plurality of first conductive layers and the first semiconductor films. In the first chip, a plurality of memory cells are formed at a plurality of intersection locations where the plurality of first conductive layers and the plurality of first semiconductor films intersect. The second chip has a plurality of second conductive layers, a plurality of second semiconductor films, and a plurality of second insulating films. The plurality of second conductive layers are stacked with respect to a second insulating layer. The plurality of second semiconductor films extend through the plurality of second conductive layers in a stacking direction. The plurality of second insulating films are disposed between the plurality of second conductive layers and the second semiconductor films. In the second chip, multiple memory cells are formed at multiple intersection locations where multiple second conductive layers intersect with multiple second semiconductor films. The first connection configuration and the second connection configuration are insulated from each other. The first connection configuration extends from the leading edge of the first semiconductor film in the multiple first conductive layers to the third chip. The second connection configuration extends from the leading edge of the second semiconductor film in the multiple second conductive layers to the third chip.

[0007] Based on the aforementioned configuration, a semiconductor memory device can be provided that can easily make the erase process multifunctional. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating the configuration of a semiconductor memory device according to an implementation method.

[0009] Figure 2 This is a circuit diagram showing the configuration of each memory cell array in the implementation method.

[0010] Figure 3 This is a diagram illustrating the interconnections between chips in an implementation method.

[0011] Figure 4 This is a cross-sectional view showing the stacking direction of the semiconductor memory device configuration according to an embodiment.

[0012] Figure 5 (a) and (b) are cross-sectional views in the stacking direction and top view direction, showing the configuration of the storage cells in the embodiment.

[0013] Figure 6 This is a top view showing the configuration of a semiconductor memory device according to an embodiment.

[0014] Figure 7 This is a top view showing the configuration of a semiconductor memory device according to an embodiment.

[0015] Figure 8 This is a cross-sectional view showing the stacking direction of the plug connection portion in the embodiment.

[0016] Figure 9 It is a cross-sectional view showing the stacking direction of the unit portion configuration of the embodiment. Detailed Implementation

[0017] Hereinafter, a semiconductor memory device according to an embodiment will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to this embodiment.

[0018] (Embodiment Embodiment) The semiconductor memory device of the embodiment has a memory cell array, and data is sometimes erased from the memory cell array, and efforts are made to make the erasure process multifunctional. For example, semiconductor memory device 1 uses... Figure 1 It is constructed in the manner shown. Figure 1 This is a block diagram showing the configuration of semiconductor memory device 1.

[0019] Semiconductor memory device 1 has multiple chips 10_1, 10_2, and 20. Among the multiple chips 10_1, 10_2, and 20, chips 10_1 and 10_2 respectively contain memory cell arrays 11_1 and 11_2, and are also referred to as array chips. Chip 20 contains circuitry for controlling the memory cell arrays 11_1 and 11_2, and is also referred to as a circuit chip.

[0020] Furthermore, chips 10_1 and 10_2 are simply referred to as chip 10 when there is no need to distinguish them from each other. Memory cell arrays 11_1 and 11_2 are simply referred to as memory cell array 11 when there is no need to distinguish them from each other.

[0021] Chip 10_1 includes a memory cell array 11_1. Multiple memory cell transistors (hereinafter referred to as memory cells) are arranged in a three-dimensional array within memory cell array 11_1. Chip 10_2 includes a memory cell array 11_2. Multiple memory cells are arranged in a three-dimensional array within memory cell array 11_2. The memory cell array group 12, including memory cell arrays 11_1 and 11_2, includes multiple blocks BK. A block BK is a collection of multiple memory cells commonly connected by word lines WL. Blocks BK are partitioned and configured across multiple chips 10_1 and 10_2. The unit that partitions block BK for each chip is called a sub-block SBK.

[0022] In the case where the storage cell array group 12 contains multiple blocks BK0 to BK2, the storage cell array 11_1 contains multiple sub-blocks SBK0_1 to SBK2_1, and the storage cell array 11_2 contains multiple sub-blocks SBK0_2 to SBK2_2. Multiple storage cells within a sub-block SBK are associated with rows and columns.

[0023] Each subblock SBK contains multiple string components SU. A string component SU is a collection of multiple memory strings MS that share a word line WL. Figure 1 In the example, the sub-block SBK is composed of four string components SU0 to SU3.

[0024] A string component SU contains multiple memory strings MS. A memory string MS contains a collection of multiple memory cells connected in series.

[0025] also, Figure 1 The example illustrates a semiconductor memory device 1 comprising two chips (array chips) 10_1 and 10_2, but the semiconductor memory device 1 may also comprise three or more array chips. Correspondingly, the memory cell array group 12 may also comprise three or more memory cell arrays 11. The number of blocks BK within the memory cell array group 12 and the number of sub-blocks SBK within the memory cell array 11 are arbitrary. The number of string components SU within a sub-block SBK is also arbitrary.

[0026] Chip 20 includes a sequencer 21, a voltage generation circuit 22, a row driver 23, a row decoder 24, and a sensing amplifier 25 as circuitry for controlling memory cell arrays 11_1 and 11_2.

[0027] The sequencer 21 controls all parts of the control chip 20. The sequencer 21 is connected to the voltage generation circuit 22, the line driver 23, the line decoder 24, and the sense amplifier 25, respectively. The sequencer 21 controls the operation of the semiconductor memory device 1 based on the instructions and data received from the external controller CTR.

[0028] For example, sequencer 21 controls write operations based on write commands. Under the control of write operations, sequencer 21 writes data from the memory cell at the specified address in memory cell array 11 and sends a write completion notification back to controller CTR. Sequencer 21 controls read operations based on read commands. Under the control of read operations, sequencer 21 reads data from the memory cell at the specified address in memory cell array 11 and sends a read data notification back to controller CTR. Sequencer 21 controls erase operations based on erase commands. Under the control of erase operations, sequencer 21 erases data from the region at the specified address in memory cell array 11 and sends an erase completion notification back to controller CTR.

[0029] The voltage generation circuit 22 generates the voltage used for write, read, and erase operations. The voltage generation circuit 22 is connected to the row driver 23 and the sense amplifier 25. The voltage generation circuit 22 supplies the generated voltage to the row driver 23 and / or the sense amplifier 25.

[0030] The row driver 23 is connected to the row decoder 24. The row driver 23 receives the row address (e.g., the page address) from the sequencer 21. Based on the row address, the row driver 23 transmits the voltage received from the voltage generation circuit 22 to the row decoder 24.

[0031] The row decoder 24 receives the row address (e.g., the block address) from the sequencer 21. The row decoder 24 decodes the row address. Based on the decoding result, the row decoder 24 selects the block BK in the memory cell array 11 whose address is specified.

[0032] The row decoder 24 is connected to the memory cell arrays 11_1 and 11_2 via multiple word lines WL. The word lines WL of memory cell array 11_1 and memory cell array 11_2 are shared by the row decoder 24. Thus, the row decoder 24 can drive the word lines WL of memory cell array 11_1 and memory cell array 11_2 in parallel.

[0033] The row decoder 24 is connected to the memory cell arrays 11_1 and 11_2 via multiple select gate lines SGD and SGS. The select gate lines SGD and SGS of memory cell array 11_1 and memory cell array 11_2 are all connected to the row decoder 24. Thus, the row decoder 24 can drive the select gate lines SGD and SGS of memory cell array 11_1 and memory cell array 11_2 in parallel.

[0034] The row decoder 24 is connected to the memory cell array 11_1 via multiple source lines SL_1 and to the memory cell array 11_2 via multiple source lines SL_2. The source lines SL_1 of memory cell array 11_1 and SL_2 of memory cell array 11_2 are respectively connected to the row decoder 24. Therefore, the row decoder 24 can drive the source lines SL_1 of memory cell array 11_1 and SL_2 of memory cell array 11_2 independently.

[0035] The line decoder 24 may, during an erase operation, supply an erase voltage to one of the source lines SL_1 and SL_2 but not to the other. Alternatively, the line decoder 24 may, during an erase operation, supply an erase voltage to the source line SL_1 and independently supply an erase voltage to the source line SL_2.

[0036] Bit lines BL_1 of memory cell array 11_1 and BL_2 of memory cell array 11_2 are individually connected to sensing amplifier 25. Thus, sensing amplifier 25 can drive or sense bit lines BL_1 of memory cell array 11_1 and BL_2 of memory cell array 11_2 independently.

[0037] The sensing amplifier 25 is connected to the BL selection circuit 26 via multiple bit lines BL. The BL selection circuit 26 is connected to the memory cell arrays 11_1 and 11_2 respectively. The BL selection circuit 26 is connected to the memory cell array 11_1 via multiple bit lines BL_1 and to the memory cell array 11_2 via multiple bit lines BL_2. The BL selection circuit 26 selects at least one of the multiple bit lines BL_1 and multiple bit lines BL_2 and connects them to the multiple bit lines BL.

[0038] When the BL selection circuit 26 selects multiple bit lines BL_1 and connects them to the multiple bit lines BL, the sense amplifier 25 supplies a voltage corresponding to the written data to the bit lines BL_1 of the memory cell array 11_1 during a write operation. During a read operation, the sense amplifier 25 supplies voltage to the bit lines BL_1 of the memory cell array 11_1 and senses the potential. The sense amplifier 25 can also supply an erase voltage to the bit lines BL_1 during an erase operation.

[0039] When the BL selection circuit 26 selects multiple bit lines BL_2 and connects them to multiple bit lines BL, the sense amplifier 25 supplies a voltage corresponding to the written data to the bit lines BL_2 of the memory cell array 11_2 during a write operation. During a read operation, the sense amplifier 25 supplies voltage to the bit lines BL_2 of the memory cell array 11_2 and senses the potential. The sense amplifier 25 can also supply an erase voltage to the bit lines BL_2 during an erase operation.

[0040] Next, use Figure 2 The circuit configuration of each memory cell array 11_1 and 11_2 is described. Figure 2 This is a circuit diagram showing the configuration of each memory cell array 11_1 and 11_2.

[0041] Each sub-block SBK of each memory cell array 11 has multiple memory strings MS. Each memory string MS has multiple memory cells MC and selection transistors ST1 and ST2. Within each memory string MS, multiple memory cells MC0 to MC5 are connected in series between selection transistors ST1 and ST2. The drain of selection transistor ST1 is connected to bit line BL. The source of selection transistor ST2 is connected to source line SL.

[0042] In each string component SU, multiple memory strings MS are commonly connected to the select gate line SGD, SGS, and word line WL. For example, the select gate line SGD is commonly connected to the gate of the select transistor ST1 of the multiple memory strings MS. The word line WL is commonly connected to the gate of the memory cell MC of the multiple memory strings MS. The select gate line SGS is commonly connected to the gate of the select transistor ST2 of the multiple memory strings MS.

[0043] Within a single string component SU, the set of multiple memory cells MC connected to a single word line WL is denoted as a cell component CU. For example, if a memory cell MC stores p bits of data (p being an integer greater than or equal to 1), the storage capacity of the cell component CU is defined as p pages of data.

[0044] Each memory string MS in memory cell array 11_1 and each memory string MS in memory cell array 11_2 are configured to drive word lines WL in parallel. Each word line WL is commonly connected to the gate of a memory cell MC in memory cell array 11_1 and the gate of a memory cell MC in memory cell array 11_2. Word line WL0 is commonly connected to the gate of a memory cell MC0 in memory cell array 11_1 and the gate of a memory cell MC0 in memory cell array 11_2. Word line WL5 is commonly connected to the gate of a memory cell MC5 in memory cell array 11_1 and the gate of a memory cell MC5 in memory cell array 11_2.

[0045] Each memory string MS in memory cell array 11_1 and each memory string MS in memory cell array 11_2 are configured to drive the select gate line SGD in parallel. Select gate line SGD0 is commonly connected to the gate of the select transistor ST2 of the string component SU0 in memory cell array 11_1 and the gate of the select transistor ST2 of the string component SU0 in memory cell array 11_2. Select gate line SGD2 is commonly connected to the gate of the select transistor ST2 of the string component SU2 in memory cell array 11_1 and the gate of the select transistor ST2 of the string component SU2 in memory cell array 11_2.

[0046] Each memory string MS in memory cell array 11_1 and each memory string MS in memory cell array 11_2 are configured to drive the select gate line SGS in parallel. The select gate line SGS is commonly connected to the gate of the select transistor ST2 in memory cell array 11_1 and the gate of the select transistor ST2 in memory cell array 11_2.

[0047] That is, the line decoder 24 can drive the word line WL in parallel using the memory cell array 11_1 and the memory cell array 11_2, and can drive the select gate line SGD and the select gate line SGS in parallel. As a result, the circuit area of ​​the parts of the line decoder 24 that drive the word line WL, the select gate line SGD, and the select gate line SGS can be reduced, thus miniaturizing the line decoder.

[0048] Each memory string MS in memory cell array 11_1 and each memory string MS in memory cell array 11_2 constitutes a source line SL that can be driven independently of each other. The source line SL is individually connected to memory cell array 11_1 and memory cell array 11_2. Source line SL_1 is connected to the source of the selection transistor ST2 of each memory string MS in memory cell array 11_1. Source line SL_2 is connected to the source of the selection transistor ST2 of each memory string MS in memory cell array 11_2.

[0049] Each memory string MS in memory cell array 11_1 and each memory string MS in memory cell array 11_2 are configured to drive bit lines BL independently. Bit lines BL are individually connected to memory cell array 11_1 and memory cell array 11_2. Bit line BL_1 is connected to the drain of the selection transistor ST2 of each memory string MS in memory cell array 11_1. Bit line BL_2 is connected to the drain of the selection transistor ST2 of each memory string MS in memory cell array 11_2.

[0050] A BL selection circuit 26 is connected between the memory cell arrays 11_1 and 11_2 and the sense amplifier 25. The BL selection circuit 26 has n selectors SEL. The n selectors SEL correspond to the n bit lines BL0 to BLn on the sense amplifier 25 side, and to the n bit lines BL0_1 to BLn_1 on the memory cell array 11_1 side, and to the n bit lines BL0_2 to BLn_2 on the memory cell array 11_2 side. Each selector SEL connects the bit line BL on the sense amplifier 25 side to at least one of the bit lines BL_1 on the memory cell array 11_1 side and BL_2 on the memory cell array 11_2 side according to the bit line selection signals BS1 and BS2.

[0051] That is, the line decoder 24 can independently drive source lines SL_1 and SL_2 using memory cell arrays 11_1 and 11_2, and can selectively drive at least one of memory cell arrays 11_1 and 11_2. The sensing amplifier 25 can independently drive bit lines BL_1 and BL_2 using memory cell arrays 11_1 and 11_2, and can selectively drive at least one of memory cell arrays 11_1 and 11_2. Therefore, memory cell arrays 11_1 and 11_2 can perform different erase operations independently of each other. That is, different functions can be achieved using memory cell arrays 11_1 and 11_2 with respect to erase operations, and memory cell arrays 11_1 and 11_2 can be used differently depending on the application.

[0052] For example, during an erasure operation, if the line decoder 24 and the BL selection circuit 26 select memory cell array 11_1 instead of memory cell array 11_2, data can be selectively erased using the sub-block SBK with the specified address in memory cell array 11_1. In this case, data is not erased in memory cell array 11_2. That is, the erasure unit can be reduced to the size of the sub-block SBK, which is divided into chip units within block BK. Furthermore, data can also be erased by selecting both memory cell array 11_1 and memory cell array 11_2 using the line decoder 24 and the BL selection circuit 26.

[0053] Alternatively, the wiring load of the source line SL_1 of memory cell array 11_1 may differ from that of the source line SL_2 of memory cell array 11_2. The wiring load may vary due to parasitic capacitance, parasitic resistance, etc. During the erase operation, the erasure time of data in memory cell array 11_1 can be made different from that of data in memory cell array 11_2 by utilizing the line decoder 24, BL selection circuit 26, and sense amplifier 25, based on the difference in wiring load. When the wiring load of the source line SL_1 of memory cell array 11_1 is higher than that of the source line SL_2 of memory cell array 11_2, the erasure time of data in memory cell array 11_1 can be controlled to be longer than that of data in memory cell array 11_2 during the erase operation.

[0054] Alternatively, during the erase operation, the erase voltage of the data in memory cell array 11_1 can be made different from the erase voltage of the data in memory cell array 11_2 based on the difference in wiring load, using the line decoder 24, BL selection circuit 26, and sensing amplifier 25. When the wiring load of the source line SL_1 of memory cell array 11_1 is higher than the wiring load of the source line SL_2 of memory cell array 11_2, the erase voltage of the data in memory cell array 11_1 can be controlled to be higher than the erase voltage of the data in memory cell array 11_2 during the erase operation.

[0055] Next, use Figure 3 This will illustrate the connection structure between chips. Figure 3 This is a diagram showing the connections between chips 20, 10_1, and 10_2.

[0056] Chip (array chip) 10_1 is disposed on the upper side of chip (circuit chip) 20. Chip 10_1 may also be bonded to the upper surface of chip 20. Chip (array chip) 10_2 is disposed on the upper side of chip 10_1. Chip 10_2 may also be bonded to the upper surface of chip 10_1. Chip 10_2 is bonded to chip 10_1 on the opposite side of chip 20. That is, a structure is formed in which chips 10_1 and 10_2 are sequentially stacked on chip 20. This structure is formed by stacking multiple memory cell arrays 11_1 and 11_2, and is also called a multi-stacked array.

[0057] In each of chips 10_1 and 10_2, the memory cell arrays 11_1 and 11_2 include a cell section, a plug connection section, and cell source sections CSL_1 and CSL_2. The cell section is a region where multiple memory cells MC are arranged. The plug connection section has select gate line SGS, word line WL, and select gate line SGD led out relative to the cell section in a top-view direction and connected to the contact plug area. The cell source sections CSL_1 and CSL_2 are adjacent to the cell section and the plug connection section in the stacking direction and are connected to each memory string MS (see reference). Figure 2 The source-side end of the cell. The source portions CSL_1 and CSL_2 function as part of the source lines SL_1 and SL_2.

[0058] Source connection line SCL_1 of chip 10_1 and source connection line SCL_2 of chip 10_2 are individually connected to the line decoder 24 of chip 20. Source connection line SCL_1 is connected to the cell source section CSL_1 of memory cell array 11_1. Source connection line SCL_1 and cell source section CSL_1 function as source line SL_1. Source connection line SCL_2, insulated from cell source section CSL_1, is connected to the cell source section CSL_2 of memory cell array 11_2 via cell source section CSL_1. Source connection line SCL_2 and cell source section CSL_2 function as source line SL_2. Source connection line SCL_1 and source connection line SCL_2 are electrically insulated from each other. That is, source line SL_1 and source line SL_2 are electrically insulated from each other.

[0059] The word line WL of chip 10_1 and the word line WL of chip 10_2 are connected to the line decoder 24 of chip 20. The word line WL is connected to the plug connection part of memory cell array 11_1 and the plug connection part of memory cell array 11_2.

[0060] The select gate line SGD of chip 10_1 and the select gate line SGD of chip 10_2 are commonly connected to the line decoder 24 of chip 20. The select gate line SGD is connected to the plug connection portion of memory cell array 11_1 and the plug connection portion of memory cell array 11_2.

[0061] The select gate line SGS of chip 10_1 and the select gate line SGS of chip 10_2 are commonly connected to the row decoder 24 of chip 20. The select gate line SGS is connected to the plug connection portion of memory cell array 11_1 and the plug connection portion of memory cell array 11_2.

[0062] The bit line BL of chip 10_1 and the bit line BL of chip 10_2 are commonly connected to the sense amplifier 25 of chip 20. The bit line BL is connected to the cell section of memory cell array 11_1 and the cell section of memory cell array 11_2.

[0063] Next, use Figure 4 This section describes the general configuration of the chips 20, 10_1, and 10_2 in the semiconductor memory device 1. Figure 4 This is a cross-sectional view showing the stacking direction of the semiconductor memory device 1.

[0064] In semiconductor memory device 1, multiple chips 20, 10_1, and 10_2 are stacked. Chip 10_1 is disposed on the +Z side of chip 20. Chip 10_2 is disposed on the +Z side of chip 10_1. That is, chips 10_1 and 10_2 are stacked sequentially on the +Z side of chip 20. In the configuration where chips 10_1 and 10_2 are sequentially bonded to the +Z side of chip 20, memory cell arrays 11_1 and 11_2 are stacked sequentially, which is referred to as a multi-stack array.

[0065] Furthermore, the number of stacked chips (array chips) 10 in the multi-stacked array is not limited to 2, but can also be 3 or more.

[0066] Chip 10_1 is bonded to the +Z side of chip 20. Chip 10_1 can also be bonded by direct bonding. Chip 20 has an insulating film (e.g., an oxide film) DL1 and an electrode PD1 on the +Z side. Chip 10_1 has an insulating film (e.g., an oxide film) DL2 and an electrode PD2 on the -Z side. At the bonding surface BF1 of chips 20 and 10_1, the insulating film DL1 of chip 20 is bonded to the insulating film DL2 of chip 10_1, and the electrode PD1 of chip 20 is bonded to the electrode PD2 of chip 10_1.

[0067] Chip 10_2 is bonded to the +Z side of chip 10_1. Chip 10_2 is bonded to chip 10_1 on the opposite side of chip 20. Chip 10_2 can also be bonded by direct bonding. Chip 10_1 has an insulating film (e.g., an oxide film) DL2 and an electrode PD3 on the +Z side. Chip 10_2 has an insulating film (e.g., an oxide film) DL3 and an electrode PD4 on the -Z side. At the bonding surface BF2 of chips 10_1 and 10_2, the insulating film DL2 of chip 10_1 is bonded to the insulating film DL3 of chip 10_2, and the electrode PD3 of chip 10_1 is bonded to the electrode PD4 of chip 10_2.

[0068] Chip 20 includes a substrate 4, a transistor Tr, an electrode PD1, wiring structures WS-1 to WS-10, and an insulating film DL1. The substrate 4 is disposed on the -Z side of chip 20 and extends in a plate-like shape along the XY direction. The substrate 4 may be formed of a material primarily composed of semiconductors (e.g., silicon). The substrate 4 has a surface 4a on the +Z side. The transistor Tr functions as a circuit element for controlling circuits (sequencer 21, voltage generation circuit 22, row driver 23, row decoder 24, sense amplifier 25, etc.) of the memory cell array 11. The transistor Tr includes a gate electrode disposed as a conductive film on the surface 4a of the substrate 4, a source electrode disposed as a semiconductor region near the surface 4a within the substrate 4, and a drain electrode. The electrode PD1, as described above, is disposed such that its surface is exposed at the bonding surface BF1 of chip 20, 10_1. Each wiring structure WS-1 to WS-10 extends primarily along the Z direction, connecting the gate electrode, source electrode, drain electrode, etc., of the transistor Tr to the electrode PD1.

[0069] Chip 10_1 has a stacked body SST1, conductive layer 103, conductive layer 104, multiple pillars CL, multiple plugs CP1, multiple plugs CP2, multiple conductive films BL_1, electrodes PD2, electrodes PD3, and insulating film DL2. In the stacked body SST1, multiple conductive layers 102 are stacked along the Z direction with the insulating layer 101 in between. The multiple conductive layers 102, from the -Z side to the +Z side, sequentially function as the select gate line SGD, word line WL5, word line WL4, word line WL3, word line WL2, word line WL1, word line WL0, and select gate line SGS.

[0070] Each conductive layer 102 extends in a plate-like shape along the XY direction. Each columnar body CL extends along the Z direction, penetrating multiple conductive layers 102. Each columnar body CL may also penetrate the laminate SST1 along the Z direction. Each columnar body CL extends in a columnar shape along the Z direction. Each columnar body CL contains a semiconductor film CH (refer to) that functions as a channel region. Figure 5 The semiconductor film CH extends in a columnar shape (e.g., in a columnar or cylindrical shape) with an axis along the Z direction. Multiple memory cells MC are formed at multiple intersections where multiple conductive layers 102 intersect with multiple columnar bodies CL, i.e., at multiple intersections where multiple conductive layers 102 intersect with multiple semiconductor films CH.

[0071] like Figure 5 (a) Figure 5 As shown in (b), each columnar body CL includes an insulating film CR, a semiconductor film CH, an insulating film TNL, a charge storage film CT, an insulating film BLK1, and an insulating film BLK2. Figure 5 (a) is an XZ sectional view showing the structure of the memory cell MC, and is Figure 4 An enlarged sectional view of part A. Figure 5(b) is an XY sectional view showing the structure of the memory cell MC, and it shows that... Figure 5 (a) Cross-section when cut along line BB. The insulating film CR extends along the Z direction and has a cylindrical shape with an axis along the Z direction. The insulating film CR can be formed from an insulating material such as silicon oxide. The semiconductor film CH extends along the Z direction, covering the insulating film CR from the outside in the XY direction, and has a cylindrical shape with an axis along the Z direction. The semiconductor film CH can be formed from a semiconductor such as polycrystalline silicon. The insulating film TNL extends along the Z direction, covering the semiconductor film CH from the outside in the XY direction, and has a cylindrical shape with an axis along the Z direction. The insulating film TNL can be formed from an insulating material such as silicon oxide. The charge storage film CT extends along the Z direction, covering the insulating film TNL from the outside in the XY direction, and has a cylindrical shape with an axis along the Z direction. The charge storage film CT can be formed from an insulating material such as silicon nitride. The insulating film BLK1 extends along the Z direction, covering the charge storage film CT from the outside in the XY direction, and has a cylindrical shape with an axis along the Z direction. The insulating film BLK1 can be formed from an insulating material such as silicon oxide. The insulating film BLK2 is configured to extend along the Z direction in such a way that it covers the insulating film BLK1 from the outside in the XY direction, and has a cylindrical shape along the Z direction axis. The insulating film BLK2 can be formed from an insulating material such as alumina. Figure 5 (a) Figure 5 (b) shows the portion enclosed by a dashed line, which functions as a storage unit (MC).

[0072] like Figure 4 As shown, the leading edge of the semiconductor film CH of the columnar body CL reaches the conductive layer 103. The semiconductor film CH is connected to the conductive layer 103 on the +Z side and connected to the conductive film BL_1 via a plug on the -Z side. The conductive film BL_1 serves as the bit line BL_1 (see reference). Figure 2 The conductive layer 103 is covered by the conductive layer 104 on the +Z side. The conductive layers 103 and 104 serve as the unit source portion CSL_1 of the source line SL (see reference). Figure 3 ) performs its function. The semiconductor film CH acts as a memory string MS (refer to Figure 2 The passage area functions as a channel.

[0073] Furthermore, the width in the Y direction of each conductive layer 102 can also be equal to each other. The width in the X direction of the multiple conductive layers 102 increases progressively from the -Z side to the +Z side. The multiple conductive layers 102 are configured such that the X-direction ends gradually move outward from the -Z side to the +Z side. Thus, a stepped structure is formed in which the select gate line SGD, word line WL5, word line WL4, word line WL3, word line WL2, word line WL1, word line WL0, and select gate line SGS are sequentially led out in a stepped manner to the plug connection portion of the memory cell array 11_1 from the -Z side to the +Z side.

[0074] Furthermore, the conductive layer 103 may have a larger width in the X direction compared to the conductive layer 102 closest to the +Z side, and the X-direction end may be located further outward. Thus, a stepped structure is formed in which the select gate line SGD, word line WL5, word line WL4, word line WL3, word line WL2, word line WL1, word line WL0, select gate line SGS, and cell source portion CSL_1 are sequentially led out in a stepped manner to the plug connection portion of the memory cell array 11_1 from the -Z side to the +Z side.

[0075] Multiple plugs CP1 correspond to multiple conductive layers 102 and 103. Each plug CP1 is disposed between an electrode PD1 in the Z direction and the corresponding conductive layer 102, 103, with its -Z side electrically connected to electrode PD2, extending along the Z direction, and its +Z side electrically connected to the corresponding conductive layer 102, 103. Thus, the plug CP1 electrically connects electrode PD2 to the corresponding conductive layer 102, 103. The plug CP1 connecting electrode PD2 to conductive layer 103 serves as the source connection line SCL_1 of the source line SL (refer to...). Figure 3 To fulfill its function.

[0076] Multiple plugs CP2 correspond to multiple electrodes PD2 and multiple electrodes PD3. Each plug CP2 is positioned between its corresponding electrode PD2 and corresponding electrode PD3 in the Z direction, with its -Z side electrically connected to electrode PD2, extending along the Z direction and penetrating multiple conductive films 102, and its +Z side electrically connected to its corresponding electrode PD3. Each plug CP2 penetrates the conductive film 102 with its outer surface covered by an insulating film, thus insulating it from the conductive film 102. Therefore, the plug CP2 electrically connects the corresponding electrode PD2 and corresponding electrode PD3. The plug CP2 connecting electrode PD2, corresponding electrode PD3, and conductive layer 103 of chip 10_2 serves as the source connection line SCL_2 of source line SL (refer to...). Figure 3 To fulfill its function.

[0077] Multiple conductive films BL_1 are disposed on the -Z side of the stack SST1. The multiple conductive films BL_1 are arranged relative to each other along the X direction. Each conductive film BL_1 extends along the Y direction. The multiple conductive films BL_1 correspond to multiple pillars CL. Each conductive film BL_1 is electrically connected to the -Z side end of the corresponding pillar CL, functioning as a bit line BL_1. The conductive films BL_1 are electrically connected to electrode PD2. Thus, the bit line BL_1 can be connected to the transistor Tr of chip 10 via electrode PD2, electrode PD1, and wiring structure WS.

[0078] Electrode PD2 is configured such that its surface is exposed at the bonding surface BF1 of chips 20 and 10_1, as described above. Electrode PD3 is configured such that its surface is exposed at the bonding surface BF2 of chips 10_1 and 10_2, as described above.

[0079] Chip 10_2 has a stacked body SST2, conductive layers 103 and 104, multiple pillars CL, multiple plugs CP3, multiple conductive films BL_2, electrodes PD4, and insulating film DL2. In the stacked body SST2, the multiple conductive layers 102 are stacked along the Z direction with the insulating layer 101 in between. The multiple conductive layers 102, from the -Z side to the +Z side, sequentially function as the select gate line SGD, word line WL5, word line WL4, word line WL3, word line WL2, word line WL1, word line WL0, and select gate line SGS.

[0080] Each conductive layer 102 extends in a plate-like shape along the XY direction. Each columnar body CL extends along the Z direction, penetrating multiple conductive layers 102. Each columnar body CL may also penetrate the stacked body SST2 along the Z direction. Each columnar body CL extends in a columnar shape along the Z direction. Each columnar body CL contains a semiconductor film CH (refer to) that functions as a channel region. Figure 5 The semiconductor film CH extends in a columnar shape (e.g., in a columnar or cylindrical shape) with an axis along the Z direction. Multiple memory cells MC are formed at multiple intersections where multiple conductive layers 102 intersect with multiple columnar bodies CL, i.e., at multiple intersections where multiple conductive layers 102 intersect with multiple semiconductor films CH.

[0081] like Figure 5 (a) Figure 5 As shown in (b), each columnar body CL comprises an insulating film CR, a semiconductor film CH, an insulating film TNL, a charge storage film CT, an insulating film BLK1, and an insulating film BLK2. The insulating film CR extends along the Z-direction and has a columnar shape with an axis along the Z-direction. The insulating film CR may be formed of an insulating material such as silicon oxide. The semiconductor film CH extends along the Z-direction, covering the insulating film CR from the outside in the XY direction, and has a cylindrical shape with an axis along the Z-direction. The semiconductor film CH may be formed of a semiconductor such as polycrystalline silicon. The insulating film TNL extends along the Z-direction, covering the semiconductor film CH from the outside in the XY direction, and has a cylindrical shape with an axis along the Z-direction. The insulating film TNL may be formed of an insulating material such as silicon oxide. The charge storage film CT extends along the Z-direction, covering the insulating film TNL from the outside in the XY direction, and has a cylindrical shape with an axis along the Z-direction. The charge storage film CT may be formed of an insulating material such as silicon nitride. The insulating film BLK1 is configured to extend along the Z direction, covering the charge storage film CT from the outside in the XY direction, and has a cylindrical shape along the Z direction axis. The insulating film BLK1 can be formed of an insulating material such as silicon oxide. The insulating film BLK2 is configured to extend along the Z direction, covering the insulating film BLK1 from the outside in the XY direction, and has a cylindrical shape along the Z direction axis. The insulating film BLK2 can be formed of an insulating material such as aluminum oxide. Figure 5 (a) Figure 5 (b) shows the portion enclosed by a dashed line, which functions as a storage unit (MC).

[0082] like Figure 4 As shown, the leading edge of the semiconductor film CH of the columnar body CL reaches the conductive layer 103. The semiconductor film CH is connected to the conductive layer 103 on the +Z side and connected to the conductive film BL_2 via a plug on the -Z side. The conductive film BL_2 serves as the bit line BL_2 (see reference). Figure 2 The conductive layer 103 is covered by the conductive layer 104 on the +Z side. The conductive layers 103 and 104 serve as the unit source portion CSL_2 of the source line SL (see reference). Figure 3 The semiconductor film CH acts as a memory string MS (refer to...). Figure 2 The passage area functions as a channel.

[0083] Furthermore, the width in the Y direction of each conductive layer 102 can also be equal to each other. The width in the X direction of the multiple conductive layers 102 increases progressively from the -Z side to the +Z side. The multiple conductive layers 102 are configured such that the X-direction ends gradually move outward from the -Z side to the +Z side. Thus, a stepped structure is formed in which the select gate line SGD, word line WL5, word line WL4, word line WL3, word line WL2, word line WL1, word line WL0, and select gate line SGS are sequentially led out in a stepped manner to the plug connection portion of the memory cell array 11_2 from the -Z side to the +Z side.

[0084] Furthermore, the conductive layer 103 may have a larger width in the X direction compared to the conductive layer 102 closest to the +Z side, and the X-direction end may be located further outward. Thus, a stepped structure is formed in which the select gate line SGD, word line WL5, word line WL4, word line WL3, word line WL2, word line WL1, word line WL0, select gate line SGS, and cell source portion CSL_2 are sequentially led out in a stepped manner to the plug connection portion of the memory cell array 11_2 from the -Z side to the +Z side.

[0085] Multiple plugs CP3 correspond to multiple conductive layers 102 and 103. Each plug CP3 is disposed between the electrode PD4 in the Z direction and the corresponding conductive layer 102, 103, with its -Z side electrically connected to the electrode PD4 and extending along the Z direction, and its +Z side electrically connected to the corresponding conductive layer 102, 103. Thus, the plugs CP3 electrically connect the electrode PD4 to the corresponding conductive layer 102, 103. The plugs CP3 connecting the electrode PD4 to the conductive layer 103 serve as the source connection line SCL_2 of the source line SL (refer to...). Figure 3 To fulfill its function.

[0086] Multiple conductive films BL_2 are disposed on the -Z side of the stack SST2. The multiple conductive films BL_2 are arranged relative to each other along the X direction. Each conductive film BL_2 extends along the Y direction. The multiple conductive films BL_2 correspond to multiple pillars CL. Each conductive film BL_2 is electrically connected to the -Z side end of the corresponding pillar CL, functioning as a bit line BL_2. The conductive films BL_2 are electrically connected to electrode PD4. Thus, the bit line BL_2 can be connected to the transistor Tr of chip 10 via electrode PD4, electrode PD1, and wiring structure WS.

[0087] As described above, electrode PD4 is configured such that its surface is exposed at the bonding surface BF2 of chips 10_1 and 10_2.

[0088] Comparing chip 10_1 and chip 10_2, the source connection line SCL_1 extending from the cell source portion CSL_1 to chip 20 and the source connection line SCL_2 extending from the cell source portion CSL_2 to chip 20 are insulated from each other. The connection configuration from the front end of the semiconductor film CH of chip 10_1 to the conductive layer 103 to the transistor Tr of chip 20 (plug CP1 → electrode PD2 → electrode PD1 → wiring structure WS-1) and the connection configuration from the front end of the semiconductor film CH of chip 10_2 to the conductive layer 103 to the transistor Tr of chip 20 (plug CP3 → electrode PD4 → electrode PD3 → plug CP2 → electrode PD2 → electrode PD1 → wiring structure WS-2) are insulated from each other.

[0089] Furthermore, bit line BL_1 extending from the rear end of the semiconductor film CH of chip 10_1 to the bit line BL_2 extending from the rear end of the semiconductor film CH of chip 10_2 to the bit line BL_2 of chip 20 is insulated from each other. The connection configuration from the rear end of the semiconductor film CH of chip 10_1 to the transistor Tr of chip 20 (plug (not shown) → electrode PD2 → electrode PD1 → wiring structure WS) is insulated from each other.

[0090] Therefore, erase voltage can be applied to the memory cell MC independently via the source line SL_1 and bit line BL_1, and erase voltage can be applied to the memory cell MC independently via the source line SL_2 and bit line BL_2. That is, memory cell array 11_1 and memory cell array 11_2 can perform different erase operations independently of each other. Thus, different functions can be achieved using memory cell array 11_1 and memory cell array 11_2 regarding erase operations, and memory cell array 11_1 and memory cell array 11_2 can be used differently depending on the application.

[0091] For example, during the erasure operation, data in memory cell array 11_1 can be erased while data in memory cell array 11_2 is not erased. That is, memory cell arrays 11_1 and 11_2 are selected by supplying a selection voltage to the conductive layer 102 on the -Z side of stack SST1 and the conductive layer 102 on the -Z side of stack SST2. At this time, an erasure voltage (e.g., approximately 20V) is applied to the channel region of the memory cell MC of memory cell array 11_1 via the source line SL_1 and the bit line BL_1, and a reference voltage (e.g., approximately 0V) is applied to the channel region of the memory cell MC of memory cell array 11_2 via the source line SL_2 and the bit line BL_2. Thus, essentially, data can be selectively erased in the sub-block SBK of memory cell array 11_1 whose address is specified by selecting memory cell array 11_1 but not memory cell array 11_2. At this time, data in memory cell array 11_2 is not erased. That is, it can reduce the size of the erased unit to the size of the sub-block SBK, which is divided into chips within the block BK.

[0092] Alternatively, during the erasure operation, it is possible to ensure that data in memory cell array 11_1 is not erased, while data in memory cell array 11_2 is erased. That is, memory cell arrays 11_1 and 11_2 are selected by supplying a selection voltage to the conductive layer 102 on the -Z side of stack SST1 and the conductive layer 102 on the -Z side of stack SST2. At this time, a reference voltage (e.g., approximately 0V) is applied to the channel region of the memory cell MC of memory cell array 11_1 via the source line SL_1 and the bit line BL_1, and an erasure voltage (e.g., approximately 20V) is applied to the channel region of the memory cell MC of memory cell array 11_2 via the source line SL_2 and the bit line BL_2. Therefore, essentially, it is possible to selectively erase data in the sub-block SBK of memory cell array 11_2 whose address is specified, by selecting memory cell array 11_2 instead of memory cell array 11_1. In this case, data in memory cell array 11_1 is not erased. That is, it can reduce the size of the erased unit to the size of the sub-block SBK, which is divided into chips within the block BK.

[0093] Furthermore, the wiring load of the source line SL_1 of memory cell array 11_1 may differ from that of the source line SL_2 of memory cell array 11_2. The wiring load may vary due to parasitic capacitance, parasitic resistance, etc., of the wiring. Correspondingly, during the erase operation, the erasure time of data in memory cell array 11_1 can be controlled to be different from the erasure time of data in memory cell array 11_2. The erasure time is the time from when the semiconductor memory device 1 receives the erase command to when it sends back an erase completion notification.

[0094] For example, suppose the parasitic capacitance of the connection from the conductive layer 103 of memory cell array 11_1 to the transistor Tr of chip 20, constituting CST1, is greater than the parasitic capacitance of the connection from the conductive layer 103 of memory cell array 11_2 to the transistor Tr of chip 20, constituting CST2. In this case, the wiring load constituting CST1 can be higher than the wiring load constituting CST2. Correspondingly, during the erase operation, the erasure time of data in memory cell array 11_1 can be controlled to be longer than the erasure time of data in memory cell array 11_2.

[0095] Assume that the conductive layer 104 of the memory cell array 11_1 is formed of a first conductive material, and the conductive layer 104 of the memory cell array 11_2 is formed of a second conductive material with a lower conductivity than the first conductive material. The first conductive material may be a material mainly composed of a metal such as copper, and the second conductive material may be a material mainly composed of a metal with a lower conductivity than a metal such as aluminum. In this case, by planarizing the memory cell array 11_1 during its formation and not planarizing it during the formation of the memory cell array 11_2, the total film thickness of the conductive layers 103 and 104 in the memory cell array 11_1 can be thinner than the total film thickness of the conductive layers 103 and 104 in the memory cell array 11_2. Therefore, the total parasitic resistance of the conductive layers 103 and 104 in the memory cell array 11_1 can be higher than the total parasitic resistance of the conductive layers 103 and 104 in the memory cell array 11_2. In this case, the wiring load of conductive layers 103 and 104 in memory cell array 11_1 can be higher than that of conductive layers 103 and 104 in memory cell array 11_2. Correspondingly, during the erase operation, the erasure time of data in memory cell array 11_1 can be controlled to be longer than the erasure time of data in memory cell array 11_2.

[0096] Alternatively, suppose that the parasitic capacitance of the connection from the conductive layer 103 of memory cell array 11_1 to the transistor Tr of chip 20, constituting CST1, is less than the parasitic capacitance of the connection from the conductive layer 103 of memory cell array 11_2 to the transistor Tr of chip 20, constituting CST2. In this case, the wiring load constituting CST1 can be lower than the wiring load constituting CST2. Correspondingly, during the erase operation, the erasure time of data in memory cell array 11_1 can be controlled to be shorter than the erasure time of data in memory cell array 11_2.

[0097] Assume that the conductive layer 104 of the memory cell array 11_1 is formed of a first conductive material, and the conductive layer 104 of the memory cell array 11_2 is formed of a second conductive material with a lower conductivity than the first conductive material. The first conductive material can also be a material primarily composed of a metal such as copper, and the second conductive material can also be a material primarily composed of a metal with a lower conductivity than a metal such as aluminum. In this case, the total film thickness of the conductive layers 103 and 104 in the memory cell array 11_1 can be equal to the total film thickness of the conductive layers 103 and 104 in the memory cell array 11_2. Therefore, the total parasitic resistance of the conductive layers 103 and 104 in the memory cell array 11_1 can be lower than the total parasitic resistance of the conductive layers 103 and 104 in the memory cell array 11_2. In this case, the wiring load of the conductive layers 103 and 104 in the memory cell array 11_1 can be lower than the wiring load of the conductive layers 103 and 104 in the memory cell array 11_2. Correspondingly, during the erasure operation, the erasure time of data in storage cell array 11_1 can be controlled to be shorter than the erasure time of data in storage cell array 11_2.

[0098] In addition, depending on the difference in wiring load, the erase voltage can be made different in addition to or instead of the erase time. During the erase operation, the erase voltage of the data in memory cell array 11_1 can also be controlled to be different from the erase voltage of the data in memory cell array 11_2.

[0099] For example, suppose the parasitic capacitance of the connection from the conductive layer 103 of memory cell array 11_1 to the transistor Tr of chip 20, constituting CST1, is greater than the parasitic capacitance of the connection from the conductive layer 103 of memory cell array 11_2 to the transistor Tr of chip 20, constituting CST2. In this case, the wiring load constituting CST1 can be higher than the wiring load constituting CST2. Correspondingly, during the erase operation, the erase voltage of the data in memory cell array 11_1 can be controlled to be higher than the erase voltage of the data in memory cell array 11_2.

[0100] Assume that the conductive layer 104 of the memory cell array 11_1 is formed of a first conductive material, and the conductive layer 104 of the memory cell array 11_2 is formed of a second conductive material with a lower conductivity than the first conductive material. The first conductive material may also be a material primarily composed of a metal such as copper, and the second conductive material may also be a material primarily composed of a metal with a lower conductivity than a metal such as aluminum. In this case, by planarizing the memory cell array 11_1 during its formation and not planarizing it during the formation of the memory cell array 11_2, the total film thickness of the conductive layers 103 and 104 in the memory cell array 11_1 can be thinner than the total film thickness of the conductive layers 103 and 104 in the memory cell array 11_2. Therefore, the total parasitic resistance of the conductive layers 103 and 104 in the memory cell array 11_1 can be higher than the total parasitic resistance of the conductive layers 103 and 104 in the memory cell array 11_2. In this case, the wiring load of conductive layers 103 and 104 in memory cell array 11_1 can be higher than that of conductive layers 103 and 104 in memory cell array 11_2. Correspondingly, during the erase operation, the erase voltage of data in memory cell array 11_1 can be controlled to be higher than that of data in memory cell array 11_2.

[0101] Alternatively, suppose that the parasitic capacitance of the connection from the conductive layer 103 of memory cell array 11_1 to the transistor Tr of chip 20, constituting CST1, is less than the parasitic capacitance of the connection from the conductive layer 103 of memory cell array 11_2 to the transistor Tr of chip 20, constituting CST2. In this case, the wiring load constituting CST1 can be lower than the wiring load constituting CST2. Correspondingly, during the erase operation, the erase voltage of the data in memory cell array 11_1 can be controlled to be lower than the erase voltage of the data in memory cell array 11_2.

[0102] Assume that the conductive layer 104 of the memory cell array 11_1 is formed of a first conductive material, and the conductive layer 104 of the memory cell array 11_2 is formed of a second conductive material with a lower conductivity than the first conductive material. The first conductive material can also be a material primarily composed of a metal such as copper, and the second conductive material can also be a material primarily composed of a metal with a lower conductivity than a metal such as aluminum. In this case, the total film thickness of the conductive layers 103 and 104 in the memory cell array 11_1 can be equal to the total film thickness of the conductive layers 103 and 104 in the memory cell array 11_2. Therefore, the total parasitic resistance of the conductive layers 103 and 104 in the memory cell array 11_1 can be lower than the total parasitic resistance of the conductive layers 103 and 104 in the memory cell array 11_2. In this case, the wiring load of the conductive layers 103 and 104 in the memory cell array 11_1 can be lower than the wiring load of the conductive layers 103 and 104 in the memory cell array 11_2. Correspondingly, during the erase operation, the erase voltage of the data in the memory cell array 11_1 can be controlled to be lower than the erase voltage of the data in the memory cell array 11_2.

[0103] Next, use Figure 6 This will illustrate the planar configuration of the storage cell array 11_2. Figure 6 This is an XY top view showing the configuration of the storage cell array 11_2.

[0104] In the memory cell array 11_2, blocks BK0, BK1, BK2, and BK3 are arranged sequentially from the +Y side to the -Y side. In each block BK, multiple conductive layers 102 are stacked at intervals in the Z direction. For example, each block BK has four conductive layers 102 stacked, functioning as the select gate line SGS, word lines WL0 to WL1, and select gate line SGD. A slit SLT extending in the XZ direction is disposed on the Y-direction side of each block BK. The slit SLT electrically separates the multiple blocks BK.

[0105] Block BK has a unit section and a plug connection section.

[0106] Multiple columnar bodies CL are arranged in the unit section. Each columnar body CL extends along the Z direction. The columnar body CL corresponds to the memory string MS (see reference). Figure 2 Multiple columnar bodies CL are arranged in two dimensions along the XY direction. Figure 6 In the example, there are 4 columns facing the X direction. The number of columns CL can be 3 or less, or more than 5. Multiple columns CL can be arranged in a staggered or lattice pattern.

[0107] On the +Z side of the columnar body CL, multiple position lines BL are arranged relative to each other in the X direction and extend along the Y direction. The columnar body CL is connected to any position line BL.

[0108] The plug connectors are located on both sides of the unit in the X direction. The plug connectors include the CP3 region.

[0109] In the CP3 region, multiple plugs CP3 are arranged. Each plug CP3 extends along the Z direction. Each plug CP3 is electrically connected to one conductive layer 102 and not to other conductive layers 102. Hereinafter, when the plugs CP3 connected to the conductive layers 102 that function as word lines WL0 to WL5 are defined, they are referred to as plugs CP3_w0 to CP3_w5. When the plugs CP3 connected to the conductive layers 102 that function as select gate lines SGD and SGS are defined, they are referred to as plugs CP3_d and CP3_s. Figure 6 In the example, from the X-direction end of the storage cell array 11_2 toward the cell section, plugs CP3_s, CP3_w0, CP3_w1, CP3_w2, CP3_w3, CP3_w4, CP3_w5, and plug CP3_d are arranged sequentially. Plug CP3 can be configured in one column or in two staggered columns.

[0110] A conductive layer 111 is disposed on the -Z side of plug CP3. The conductive layer 111 is electrically connected to the -Z side of plug CP3 and extends from its connection point with plug CP3 in the +Y or -Y direction to the adjacent block BK. For example, the conductive layer 111 extends from its connection point with plug CP3 in block BK0 in the -Y direction to its connection point with electrode PD4 in block BK1. In the adjacent block BK, on ​​the -Z side of conductive layer 111, electrode PD4 is disposed at a position corresponding to plug CP3, and an insulating layer 112 is disposed at other positions. The -Z side surface of electrode PD4 is exposed at the bonding surface BF2. The -Z side surface of insulating layer 112 is also exposed at the bonding surface BF2.

[0111] Next, use Figure 7 The planar configuration of the storage cell array 11_1 is described. Figure 7 This is an XY top view showing the configuration of the storage cell array 11_1.

[0112] The similarity between storage cell array 11_1 and storage cell array 11_2 is that each block BK has a cell section and a plug connection section. In addition, the structure of the cell section is the same as that of storage cell array 11_2.

[0113] The plug connectors are located on both sides of the unit in the X direction. The plug connectors include CP1 area and CP2 area.

[0114] In the CP1 region, multiple plugs CP1 are arranged. Each plug CP1 extends along the Z direction. Plug CP1 is electrically connected to one conductive layer 102, but not to other conductive layers 102. Plug CP1 at its X-direction end is electrically connected to conductive layer 103. Hereinafter, when the plug CP1 connected to the conductive layer 102 that functions as word lines WL0 to WL5 is defined, it is referred to as plug CP1_w0 to CP1_w5. When the plug CP1 connected to the conductive layer 102 that functions as select gate lines SGD and SGS is defined, it is referred to as plug CP1_d and CP1_s. When the plug CP1 connected to the conductive layer 103 that functions as the cell source section CSL is defined, it is referred to as plug CP1_csl. Figure 7 In the example, from the X-direction end of the storage cell array 11_1 toward the cell section, plugs CP1_csl, CP1_s, CP1_w0, CP1_w1, CP1_w2, CP1_w3, CP1_w4, CP1_w5, and plug CP1_d are arranged sequentially. Plug CP1 can be configured in one column or in two staggered columns.

[0115] A conductive layer 111 is disposed on the -Z side of the plug CP1_csl. The conductive layer 111 is electrically connected to the -Z side end of the plug CP1 and is connected to the electrode PD2 at the connection position with the plug CP1. The -Z side surface of the electrode PD2 is exposed at the bonding surface BF1. The -Z side surface of the insulating layer 112 is exposed at the bonding surface BF1.

[0116] A conductive layer 111 is disposed on the -Z side of plugs CP1_s to CP1_d, excluding plug CP1_csl. The conductive layer 111 is electrically connected to the -Z side of plug CP1 and extends from its connection point with plug CP1 in the +Y or -Y direction to the adjacent block BK. For example, the conductive layer 111 extends from its connection point with plug CP1 in block BK0 in the -Y direction to its connection point with electrode PD4 in block BK1. In the adjacent block BK, on ​​the -Z side of conductive layer 111, electrode PD2 is disposed at a position corresponding to plug CP2, and an insulating layer 112 is disposed at other positions. The -Z side surface of electrode PD2 is exposed at the bonding surface BF1. The -Z side surface of insulating layer 112 is exposed at the bonding surface BF1.

[0117] In the CP2 region, multiple plugs CP2 are configured. Each plug CP2 extends along the Z direction. Plugs CP2 are not electrically connected to the conductive layer 102 of the memory cell array 11_1. Plugs CP2 at their X-direction end sides are not electrically connected to the conductive layer 103 of the memory cell array 11_1. Plugs CP2 are electrically connected to one conductive layer 102 in the memory cell array 11_2, but not to the other conductive layers 102. Plugs CP2 at their X-direction end sides are electrically connected to the conductive layer 103 of the memory cell array 11_2. Hereinafter, when the plugs CP2 connected to the conductive layer 102 that functions as word lines WL0 to WL5 are defined, they will be referred to as plugs CP2_w0 to CP2_w5. When the plugs CP2 connected to the conductive layer 102 that functions as select gate lines SGD and SGS are defined, they will be referred to as plugs CP2_d and CP2_s. When the plug CP2 connected to the conductive layer 103, which functions as the source of the unit CSL, is defined, it is referred to as plug CP2_csl. Figure 7 In the example, from the X-direction end of the storage cell array 11_1 toward the cell section, plugs CP2_csl, CP2_s, CP2_w0, CP2_w1, CP2_w2, CP2_w3, CP2_w4, CP2_w5, and plug CP2_d are arranged sequentially. Plug CP2 can be configured in one column or in two staggered columns.

[0118] A conductive layer 111 is disposed on the -Z side of plug CP2_csl. The conductive layer 111 is electrically connected to the -Z side end of plug CP2 and connected to electrode PD2 at the connection position with plug CP1. The -Z side surface of electrode PD2 is exposed at the bonding surface BF1. The -Z side surface of insulating layer 112 is exposed at the bonding surface BF1.

[0119] A conductive layer 111 is disposed on the -Z side of plugs CP1_s to CP1_d, other than plug CP2_csl. The conductive layer 111 is electrically connected to the -Z side end of plugs CP2_s to CP2_d. At the connection position with plugs CP2_s to CP2_d, the conductive layer 111 is connected to electrode PD2 on the -Z side. The -Z side surface of electrode PD2 is exposed at the bonding surface BF1.

[0120] The conductive layer 111 extends from the connection position of the plugs CP1_s to CP1_d in block BK in the +Y or -Y direction to the connection position of the plugs CP2_s to CP2_d in the adjacent block BK.

[0121] For example, conductive layer 111 extends from the connection position of plugs CP1_s to CP1_d in block BK0 in the -Y direction to the connection position of plugs CP2_s to CP2_d in block BK1. Plugs CP1_s to CP1_d correspond to plugs CP2_s to CP2_d. Each plug CP1_s to CP1_d is electrically connected to its corresponding plug CP2 via conductive layer 111.

[0122] If Figure 7 The planar configuration of the storage cell array 11_1 shown is similar to... Figure 6 Comparing the planar configuration of the shown memory cell array 11_2, the number of CP1 plugs in region CP1 (e.g., 9) is equal to the number of CP3 plugs in region CP3 (e.g., 9). The number of electrode PDs in region CP1 (e.g., 1) is greater than the number of electrode PDs in region CP3 (e.g., 0). The number of CP2 plugs in region CP2 (e.g., 9) is equal to the number of CP3 plugs in region CP3 (e.g., 9). The number of electrode PDs in region CP2 (e.g., 18) is greater than the number of electrode PDs in region CP3 (e.g., 0).

[0123] Next, use Figure 8 To illustrate the cross-sectional structure of the plug connection. Figure 8 This is a YZ sectional view showing the structure of the plug connection. Figure 8 Corresponding to Figure 6 and Figure 7 The cross-sections when cut at the CC line.

[0124] In the plug connection section, chips 20, 10_1, and 10_2 are sequentially stacked and bonded. Chip 20 and chip 10_1 are electrically connected to each other via electrodes PD1 and PD2. Chip 10_1 and chip 10_2 are electrically connected to each other via electrodes PD3 and PD4.

[0125] Chip 10_1 includes a memory cell array 11_1 and its wiring. Chip 10_1 has insulating layers 101, 107, 110, 112, 114, a slit SLT, conductive layers 102, 103, 104, 111, conductors 106, 108, 109, and electrodes PD2 and PD3.

[0126] In the memory cell array 11_1, insulating layer 101 and conductive layer 102 are alternately deposited multiple times. Multiple conductive layers 102, from -Z side to +Z side, sequentially function as select gate line SGD, word line WL5, word line WL4, word line WL3, word line WL2, word line WL1, word line WL0, and select gate line SGS.

[0127] When the conductive layer 102 functions as word lines WL5, WL4, WL3, WL2, WL1, and WL0, it is referred to as conductive layers 102_w5, 102_w4, 102_w3, 102_w2, 102_w1, and 102_w0. When the conductive layer 102 functions as select gate lines SGD and SGS, it is referred to as conductive layers 102_d and 102_s.

[0128] The insulating layer 101 may be formed of an insulating material such as silicon oxide. The conductive layer 102 may be formed of a conductive material such as a metal with tungsten as the main component or a semiconductor that has been given conductivity.

[0129] Multiple conductive layers 102 are electrically separated from the conductive layers 102 of other blocks BK by slits SLT extending along the XZ direction. Insulators such as silicon oxide can be embedded in the slits SLT.

[0130] On the +Z side of conductive layer 102_s, conductive layer 103 is disposed with insulating layer 101 in between. Conductive layer 104 is disposed on the +Z side of conductive layer 103. Conductive layer 104 covers the +Z side surface of conductive layer 103. Conductive layers 103 and 104 function as the source portion CSL of the source line SL. The +Z side of conductive layer 104 is covered by insulating layer 114. The +Z side surface of insulating layer 114 is exposed at the bonding surface BF2.

[0131] The conductive layer 103 may be formed from a semiconductor (e.g., polysilicon) that has been imparted with conductivity. The conductive layer 104 may be formed from a conductor. The conductive layer 104 may be formed from either a first conductive material or a second conductive material. The first conductive material may be a material mainly composed of a metal such as copper, and the second conductive material may be a material mainly composed of a metal with a lower conductivity than a metal such as aluminum.

[0132] A plug CP1 is disposed on the -Z side of the conductive layer 103. The plug CP1 has a cylindrical shape, for example, a cylindrical shape. The plug CP1 includes a conductor 106 and an insulating layer 107. The conductor 106 has a cylindrical shape, for example, a cylindrical shape. The insulating layer 107 covers the side surface of the conductor 106. The insulating layer 107 has a cylindrical shape, for example, a cylindrical shape.

[0133] In the plug CP1_csl, the +Z side of the conductor 106 is connected to the conductive layer 103. The conductor 106 is electrically insulated from the multiple conductive layers 102_s to 102_d by the insulating layer 107 on its side, and penetrates the multiple conductive layers 102_s to 102_d. The -Z side of the conductor 106 is connected to the electrode PD2 via the conductive layer 111. Thus, the conductor 106 electrically connects the conductive layer 103 and the electrode PD2. The conductor 106 can be formed of a material mainly composed of metals such as copper. The insulating layer 107 can be formed of an insulating material such as silicon oxide.

[0134] In plugs CP1_s to CP1_d other than plug CP1_csl, the +Z side of conductor 106 is connected to a specific conductive layer 102, but is not shown. Conductor 106 is electrically insulated from other conductive layers 102 by an insulating layer 107 on its side, and penetrates the other conductive layers 102. The -Z side of conductor 106 is connected to electrode PD2 via conductive layer 111. Thus, conductor 106 electrically connects the specific conductive layer 102 to electrode PD2.

[0135] On the -Z side of conductive layer 111, an electrode PD2 is disposed at the connection position of plug CP1_csl, and an insulating layer 112 is disposed at the connection positions of plugs CP1_s to CP1_d. The -Z side surfaces of electrode PD2 and insulating layer 112 are exposed on the bonding surface BF1.

[0136] The plug CP2 extends through multiple conductive layers 102 in the Z direction. The plug CP2 has a cylindrical shape, for example, a cylindrical shape. The plug CP2 includes a conductor 109 and an insulating layer 110. The conductor 109 has a cylindrical shape, for example, a cylindrical shape. The insulating layer 110 covers the sides of the conductor 109. The insulating layer 110 has a cylindrical shape, for example, a cylindrical shape.

[0137] In the CP2 region where the plug CP2 is located, a conductor 108 is provided instead of conductive layers 103 and 104 on the +Z side of the plug CP2. The +Z side of the conductor 109 is connected to the electrode PD3 via the conductor 108. The conductor 109 is electrically insulated from the multiple conductive layers 102 by an insulating layer 110 on its side surface, and penetrates the multiple conductive layers 102. The -Z side of the conductor 109 is connected to the electrode PD2 via the conductive layer 111. Thus, the conductor 109 electrically connects the electrodes PD2 and PD3. The conductor 109 may be formed of a material mainly composed of metals such as copper. The insulating layer 110 may be formed of an insulating material such as silicon oxide.

[0138] Chip 10_2 includes a memory cell array 11_2 and its wiring. Chip 10_2 has insulating layers 101, 112, 117, a slit SLT, conductive layers 102, 103, 104, 111, a conductor 116, and an electrode PD4.

[0139] In the memory cell array 11_2, insulating layer 101 and conductive layer 102 are alternately deposited multiple times. Multiple conductive layers 102, from -Z side to +Z side, sequentially function as select gate line SGD, word line WL5, word line WL4, word line WL3, word line WL2, word line WL1, word line WL0, and select gate line SGS.

[0140] When the conductive layer 102 is defined as functioning as word lines WL5, WL4, WL3, WL2, WL1, and WL0, it is referred to as conductive layers 102_w5, 102_w4, 102_w3, 102_w2, 102_w1, and 102_w0. When the conductive layer 102 is defined as functioning as select gate lines SGD and SGS, it is referred to as conductive layers 102_d and 102_s.

[0141] The insulating layer 101 may be formed of an insulating material such as silicon oxide. The conductive layer 102 may be formed of a conductive material such as a semiconductor with tungsten or other metals as the main component and which is then imparted with conductivity.

[0142] Multiple conductive layers 102 are electrically separated from the conductive layers 102 of other blocks BK by slits SLT extending along the XZ direction. Insulators such as silicon oxide can be embedded in the slits SLT.

[0143] On the +Z side of conductive layer 102_s, conductive layer 103 is disposed with insulating layer 101 in between. Conductive layer 104 is disposed on the +Z side of conductive layer 103. Conductive layer 104 covers the +Z side surface of conductive layer 103. Conductive layers 103 and 104 function as source line SL.

[0144] The conductive layer 103 may be formed from a semiconductor (e.g., polycrystalline silicon) that is imparted with conductivity. The conductive layer 104 may be formed from a material whose main component is a metal such as aluminum.

[0145] A plug CP3 is disposed on the -Z side of the conductive layer 103. The plug CP3 has a cylindrical shape, for example, a cylindrical shape. The plug CP3 includes a conductor 116 and an insulating layer 117. The conductor 116 has a cylindrical shape, for example, a cylindrical shape. The insulating layer 117 covers the side surface of the conductor 116. The insulating layer 117 has a cylindrical shape, for example, a cylindrical shape.

[0146] In the plug CP3_csl, the +Z side of conductor 116 is connected to conductive layer 103. Conductor 116 is electrically insulated from multiple conductive layers 102_s to 102_d by its sidewalls separated by insulating layer 117, and penetrates multiple conductive layers 102_s to 102_d. The -Z side of conductor 116 is connected to electrode PD4 via conductive layer 111. Thus, conductor 116 electrically connects conductive layer 103 and electrode PD4. Conductor 116 can be formed of a material mainly composed of metals such as copper. Insulating layer 117 can be formed of an insulating material such as silicon oxide.

[0147] In plugs CP1_s to CP1_d, other than plug CP1_csl, the +Z side of conductor 116 is connected to a specific conductive layer 102, but is not shown. Conductor 116, with its side electrically insulated from other conductive layers 102 by an insulating layer 117, penetrates the other conductive layers 102. The -Z side of conductor 116 is connected to conductive layer 111 via electrode PD4. Thus, conductor 116 electrically connects the specific conductive layer 102 to electrode PD4.

[0148] On the -Z side of conductive layer 111, an insulating layer 112 is disposed at the connection position of plug CP1_csl, and an electrode PD4 is disposed at a position adjacent to block BK in the Y direction offset from its connection position. The -Z side surfaces of electrode PD4 and insulating layer 112 are exposed at the bonding surface BF2.

[0149] Chip 20 has a substrate 200, insulating layers 201, 202, 209, a gate electrode 203, conductors 204, 206, 208, 210, and conductive layers 205, 207.

[0150] Near the surface of substrate 200, well regions and device separation regions are disposed. Substrate 200 may be formed of a semiconductor (e.g., silicon). The device separation regions electrically isolate the well regions from other well regions. An insulating layer 201 is disposed in the device separation regions. The insulating layer 201 may be formed of an insulating material such as silicon oxide.

[0151] An insulating layer 202 is disposed on the +Z side of the substrate 200. The insulating layer 202 may be formed of an insulating material such as silicon oxide.

[0152] The transistor Tr includes a gate electrode 203 on the surface 200a of the substrate 200, and a source electrode, a drain electrode, etc., are included in the vicinity of the surface 200a within the substrate 200. The gate electrode 203 may be formed of a semiconductor (e.g., polysilicon) that has been imparted with conductivity. The source electrode and the drain electrode may be formed in regions of the substrate 200 that contain impurities.

[0153] The source electrode and drain electrode are connected to the conductive layer 205 via conductor 204. Conductor 204 extends along the Z direction. The conductive layer 205 is connected to the conductive layer 207 via conductor 206. Conductor 206 extends along the Z direction. The conductive layer 207 is connected to electrode PD1 via conductor 208. Conductor 208 extends along the Z direction. Conductors 204, 206, 208, 208 and conductive layers 205, 207 can be formed of materials with aluminum or copper as the main metal component.

[0154] On the +Z side of the insulating layer 202, an electrode PD1 is disposed at a position corresponding to electrode PD2, and an insulating layer 209 is disposed at other positions. Electrode PD1 may be formed of a material mainly composed of metals such as copper. The insulating layer 209 may be formed of an insulating material such as silicon oxide.

[0155] Next, use Figure 9 The cross-sectional structure of the unit section is explained. Figure 9 This is a YZ sectional view showing the structure of a unit section. Figure 9 Corresponding to Figure 6 and Figure 7 The cross-sections when cut at the DD line.

[0156] like Figure 9 As shown, columnar bodies CL are respectively configured in chips 10_1 and 10_2.

[0157] In chip 10_2, columnar bodies CL extend along the Z direction within the stacked body SST2, penetrating multiple conductive layers 102. Figure 9 In this example, the columnar body CL penetrates eight conductive layers 102. The +Z side of the columnar body CL is connected to the conductive layer 103, and the -Z side is connected to the conductor CP3. The -Z side of the conductor CP3 is connected to the conductor CP4. The conductor CP4 extends along the Z direction, and its -Z side is connected to the conductive film BL_2.

[0158] The columnar body CL has a columnar shape with an axis along the Z direction. Within the columnar body CL, an insulating film CR, a semiconductor film CH, an insulating film TNL, a charge storage film CT, an insulating film BLK1, and an insulating film BLK2 are arranged sequentially from the axis outwards, as described above (see reference). Figure 5 (a) Figure 5 (b) The leading edge of the semiconductor film CH reaches the conductive layer 103. The semiconductor film CH covers the +Z side of the insulating film CR at its +Z side end and is in contact with the conductive layer 103. The trailing edge of the semiconductor film CH reaches the semiconductor layer CA. The semiconductor film CH is in contact with the semiconductor layer CA at its -Z side end. The semiconductor layer CA can be formed of a semiconductor such as polysilicon. The -Z side surface of the semiconductor layer CA is in contact with the plug CP3. The -Z side end of the plug CP3 is in contact with the plug CP4. The -Z side end of the plug CP4 is in contact with the conductive film BL_2. The conductive layer 103 functions as the source line SL, and the conductive film BL_2 functions as the bit line BL_2. Thus, the +Z side end of the semiconductor film CH is electrically connected to the source line SL, and the -Z side end is electrically connected to the bit line BL_2, functioning as the channel region of the memory string MS.

[0159] In chip 10_2, multiple memory cells MC are formed at multiple intersection points where multiple conductive layers 102 intersect with pillars CL. These multiple memory cells MC arranged along the Z-direction are equivalent to the multiple memory cells MC contained in the memory string MS (see reference). Figure 2 At multiple intersections where multiple conductive layers 102 intersect with multiple columnar bodies CL2, multiple memory cells MC are formed, arranged along the XYZ direction.

[0160] The conductive film BL_2 extends along the Y direction. The -Z side of the conductive film BL_2 is connected to the electrode PD4 via the plug CP6 at a position offset from the laminate SST2 along the Y direction. The -Z side of the electrode PD4 is exposed at the bonding surface BF2.

[0161] In chip 10_1, columnar bodies CL extend along the Z direction within the stacked body SST1, penetrating multiple conductive layers 102. Figure 9 In this example, the columnar body CL penetrates eight conductive layers 102. The +Z side of the columnar body CL is connected to the conductive layer 103, and the -Z side is connected to the conductor CP3. The -Z side of the conductor CP3 is connected to the conductor CP4. The conductor CP4 extends along the Z direction, and its -Z side is connected to the conductive film BL_1.

[0162] The columnar body CL has a columnar shape with an axis along the Z direction. Within the columnar body CL, an insulating film CR, a semiconductor film CH, an insulating film TNL, a charge storage film CT, an insulating film BLK1, and an insulating film BLK2 are arranged sequentially from the axis outwards, as described above (see reference). Figure 5 (a) Figure 5 (b) The leading edge of the semiconductor film CH reaches the conductive layer 103. The semiconductor film CH covers the +Z side of the insulating film CR at its +Z side end and is in contact with the conductive layer 103. The trailing edge of the semiconductor film CH reaches the semiconductor layer CA. The semiconductor film CH is in contact with the semiconductor layer CA at its -Z side end. The semiconductor layer CA can be formed of a semiconductor such as polysilicon. The -Z side surface of the semiconductor layer CA is in contact with the plug CP3. The -Z side end of the plug CP3 is in contact with the plug CP4. The -Z side end of the plug CP4 is in contact with the conductive film BL_1. The conductive layer 103 functions as the source line SL, and the conductive film BL_1 functions as the bit line. Thus, the +Z side end of the semiconductor film CH is electrically connected to the source line SL, and the -Z side end is electrically connected to the bit line BL_1, functioning as the channel region of the memory string MS.

[0163] In chip 10_1, multiple memory cells MC are formed at multiple intersection points where multiple conductive layers 102 intersect with pillars CL, arranged along the Z direction. These multiple memory cells MC arranged along the Z direction are equivalent to the multiple memory cells MC contained in the memory string MS (see reference). Figure 2At multiple intersections where multiple conductive layers 102 intersect with multiple columnar bodies CL, multiple memory cells MC are formed, arranged along the XYZ direction.

[0164] The conductive film BL_1 extends along the Y direction. The -Z side of the conductive film BL_1 is connected to the electrode PD2 via the plug CP6. The -Z side of the electrode PD2 is exposed at the bonding surface BF1. The electrode PD2 is connected to the electrode PD1 at the bonding surface BF1. Figure 9 For simplicity, the example shows that the Y positions of plug CP6, electrode PD2, and electrode PD1 are included in the Y-direction width of the laminate SST1. However, the Y positions of plug CP6, electrode PD2, and electrode PD1 can also be positions offset from the laminate SST1 along the Y-direction.

[0165] like Figure 9 As shown, the semiconductor film CH of the pillar CL of memory cell array 11_1 is electrically connected to transistor Tr-1 of chip 10 via bit line BL_1. The semiconductor CH of the pillar CL of memory cell array 11_2 is electrically connected to transistor Tr-2 of chip 10 via bit line BL_2. The connection from memory cell array 11_1 to transistor Tr-1 via bit line BL_1 is insulated from the connection from memory cell array 11_2 to transistor Tr-2 via bit line BL_2.

[0166] As described above, in this embodiment, in the semiconductor memory device 1, the connection configuration (source connection line CSL_1) from the conductive layer 103 reaching the front end of the semiconductor film CH of chip 10_1 to the transistor Tr of chip 20 is insulated from each other. The connection configuration (bit line BL_1) from the rear end of the semiconductor film CH of chip 10_1 to the transistor Tr of chip 20 is insulated from each other. Therefore, the erase voltage applied to the memory cell MC via the driving of the source line SL_1 and the bit line BL_1, and the erase voltage applied to the memory cell MC via the driving of the source line SL_2 and the bit line BL_2, can be performed independently. That is, the memory cell array 11_1 and the memory cell array 11_2 can perform different erase operations independently. Therefore, different functions can be achieved by using the memory cell array 11_1 and the memory cell array 11_2 with respect to the erasure operation, and the memory cell array 11_1 and the memory cell array 11_2 can be used differently according to the purpose.

[0167] Furthermore, the configuration of the memory cell arrays 11_1 and 11_2 for commonly connecting word lines WL and driving word lines WL respectively is not limited to the configuration of commonly connecting select gate lines SGD and SGS, independently connecting source connection lines CSL, and independently connecting bit lines BL. It could also be a configuration of commonly connecting select gate line SGD, independently connecting source connection lines CSL, independently connecting bit lines BL, and independently connecting select gate line SGS. Alternatively, it could be a configuration of commonly connecting select gate line SGS, independently connecting source connection lines CSL, independently connecting bit lines BL, and independently connecting select gate line SGD. It could also be a configuration of independently connecting source connection lines CSL, independently connecting bit lines BL, independently connecting select gate line SGD, and independently connecting select gate line SGD.

[0168] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: Chip 1; The second chip is coupled to the first chip; and The third chip is bonded to the second chip on the side opposite to the first chip; The first chip has: Multiple first conductive layers are stacked with a first insulating layer in between; A plurality of first semiconductor films, extending along the stacking direction through the plurality of first conductive layers; and A plurality of first insulating films are respectively disposed between the plurality of first conductive layers and the first semiconductor film; and In the first chip, a plurality of memory cells are formed at a plurality of intersection positions where the plurality of first conductive layers intersect with the plurality of first semiconductor films; The second chip has: Multiple second conductive layers are stacked, separated by a second insulating layer; Multiple second semiconductor films, extending along the stacking direction through the multiple second conductive layers; and A plurality of second insulating films are respectively disposed between the plurality of second conductive layers and the second semiconductor film; and In the second chip, a plurality of memory cells are formed at a plurality of intersection positions where the plurality of second conductive layers intersect with the plurality of second semiconductor films; The first connection from the front end of the first semiconductor film in the plurality of first conductive layers to the third chip is configured to be insulated from each other as is the second connection from the front end of the second semiconductor film in the plurality of second conductive layers to the third chip.

2. The semiconductor memory device of claim 1, wherein the first connection comprises a first plug. The first plug extends along the stacking direction within the first chip, reaching the first conductive layer reached by the front end of the first semiconductor film. The second connection comprises a second plug and a third plug. The second plug extends along the stacking direction within the first chip, penetrating the first conductive layer reached by the front end of the first semiconductor film in an insulating manner; and The third plug extends along the stacking direction within the second chip, reaching the second conductive layer reached by the front end of the second semiconductor film.

3. The semiconductor memory device according to claim 1, wherein the third connection from the rear end of the first semiconductor film of the first chip to the third chip is configured to be insulated from each other as the fourth connection from the rear end of the first semiconductor film of the second chip to the third chip.

4. The semiconductor memory device according to claim 1, wherein the third conductive layer reaching the first conductive layer from the front end of the first semiconductor film and the fourth conductive layer reaching the second conductive layer from the front end of the second semiconductor film comprise different materials.

5. The semiconductor memory device of claim 4, wherein the fourth conductive layer comprises the first conductive material. The third conductive layer contains a second conductive material with a lower resistivity than the first conductive material.

6. The semiconductor memory device of claim 5, wherein the first conductive material comprises a conductive material with aluminum as its main component. The second conductive material comprises a conductive material with copper as its main component.

7. The semiconductor memory device according to claim 1, wherein the voltage of the first conductive layer reached by the front end of the first semiconductor film in the plurality of first conductive layers and the voltage of the second conductive layer reached by the front end of the second semiconductor film in the plurality of second conductive layers can be independently controlled.

8. The semiconductor memory device according to claim 7, wherein the first chip further comprises a first conductive film. The first conductive film is disposed on the third chip side relative to the plurality of first conductive layers, and is connected to the rear end of the first semiconductor film. The second chip also has a second conductive film. The second conductive film is disposed on the side of the first chip relative to the plurality of second conductive layers, and is connected to the rear end of the second semiconductor film. The voltage of the first conductive film and the voltage of the second conductive film can be controlled independently of each other.

9. The semiconductor memory device according to claim 1, which is capable of selecting at least one of a plurality of memory cells of the first chip and a plurality of memory cells of the second chip to perform a data erasure operation.

10. The semiconductor memory device of claim 1, which is capable of performing a data erasure operation by selecting a plurality of memory cells of the first chip but not a plurality of memory cells of the second chip.

11. The semiconductor memory device according to claim 1, which is capable of performing a data erasure operation by selecting a plurality of memory cells of the second chip instead of selecting a plurality of memory cells of the first chip.

12. The semiconductor memory device of claim 1, wherein applying an erase voltage to the memory cell of the first chip and applying an erase voltage to the memory cell of the second chip can be performed independently of each other.

13. The semiconductor memory device according to claim 1, wherein the erasure time of the data in the memory cell of the first chip is different from the erasure time of the data in the memory cell of the second chip.

14. The semiconductor memory device of claim 13, wherein the erasure time of data in the memory cell of the first chip and the erasure time of data in the memory cell of the second chip are different based on the difference between the wiring load formed by the first connection and the wiring load formed by the second connection.

15. The semiconductor memory device of claim 14, wherein the erasure time of data in the memory cell of the first chip and the erasure time of data in the memory cell of the second chip are different based on the difference between the parasitic capacitance formed by the first connection and the parasitic capacitance formed by the second connection.

16. The semiconductor memory device of claim 14, wherein the erasure time of data in the memory cell of the first chip and the erasure time of data in the memory cell of the second chip are different based on the difference between the parasitic resistance formed by the first connection and the parasitic resistance formed by the second connection.

17. The semiconductor memory device according to claim 1, wherein the erase voltage of the data in the memory cell of the first chip is different from the erase voltage of the data in the memory cell of the second chip.

18. The semiconductor memory device of claim 17, wherein the erase voltage of the data in the memory cell of the first chip and the erase voltage of the data in the memory cell of the second chip are different based on the difference in wiring load between the memory cell of the first chip and the memory cell of the second chip.

19. The semiconductor memory device of claim 18, wherein the erase voltage of the data in the memory cell of the first chip and the erase voltage of the data in the memory cell of the second chip are different based on the difference between the parasitic capacitance formed by the first connection and the parasitic capacitance formed by the second connection.

20. The semiconductor memory device of claim 18, wherein the erase voltage of the data in the memory cell of the first chip and the erase voltage of the data in the memory cell of the second chip are different based on the difference between the parasitic resistance formed by the first connection and the parasitic resistance formed by the second connection.

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