Display substrate, display panel and display device

Abstract

A display substrate, a display panel and a display device. The display substrate comprises a display area, at least part of the area being a transparent display area. The display substrate comprises a plurality of pixels in the transparent display area. The pixel comprises a plurality of sub-pixels, and each sub-pixel comprises an organic light emitting element (220) and a pixel circuit (221). The organic light emitting element (220) comprises a first electrode, a second electrode and an organic light emitting material between the first electrode and the second electrode. The first electrode of the sub-pixel is electrically connected to the pixel circuit (221). The number of the first electrodes is greater than the number of the second electrodes. The display substrate further comprises a first power supply signal line (VDD1) connected to the pixel circuit (221) and a second power supply signal line (VSS) connected to the second electrode. The first power supply signal line (VDD1) comprises a first sub-power supply signal line (VDD11) extending in a first direction and a second sub-power supply signal line (VDD12) extending in a second direction; and / or, the second power supply signal line (VSS) comprises a third sub-power supply signal line (VSS1) extending in the first direction and a fourth sub-power supply signal line (VSS2) extending in the second direction.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display substrate, display panel and display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) displays have many advantages, such as self-illumination, low driving voltage, high luminous efficiency, short response time, high clarity and contrast, wide operating temperature range, and the ability to achieve flexible displays. They are widely used in the display, lighting, and smart wearable fields. Summary of the Invention

[0003] This application provides a display substrate, a display panel, and a display device.

[0004] According to a first aspect of the present application, a display substrate is provided. The display substrate includes a display area, at least a portion of which is a transparent display area; the display substrate includes a substrate and a plurality of pixels located on the substrate and in the transparent display area; each pixel includes a plurality of sub-pixels, each sub-pixel including an organic light-emitting element and a pixel circuit driving the organic light-emitting element; each organic light-emitting element includes a first electrode, a second electrode, and an organic light-emitting material located between the first electrode and the second electrode; the first electrode of each sub-pixel is electrically connected to the pixel circuit; the number of first electrodes is greater than the number of second electrodes;

[0005] The display substrate is further provided with a first power signal line and a second power signal line. The pixel circuit is connected to the first power signal line, and the second electrode is connected to the second power signal line. The first power signal line includes a first sub-power signal line extending along a first direction and a second sub-power signal line extending along a second direction. And / or, the second power signal line includes a third sub-power signal line extending along the first direction and a fourth sub-power signal line extending along the second direction. The first direction intersects the second direction.

[0006] In one embodiment, the display substrate further includes an overlap portion electrically connected to the second power signal line, and at least two adjacent pixels have second electrodes in contact with the same overlap portion.

[0007] In one embodiment, when the second power signal line includes a third sub-power signal line extending along the first direction and a fourth sub-power signal line extending along the second direction, at least two adjacent pixels have their second electrodes electrically connected to the third sub-power signal line through the same overlap portion, or electrically connected to the fourth sub-power signal line through the same overlap portion.

[0008] In one embodiment, the plurality of overlapping portions arranged in the first direction are electrically connected via the third sub-power signal line, and / or the plurality of overlapping portions arranged in the second direction are electrically connected via the fourth sub-power signal line.

[0009] In one embodiment, the display substrate further includes an overlap portion electrically connected to the second power signal line, and at least four adjacent pixels have second electrodes in contact with the same overlap portion, the four adjacent pixels being arranged in two rows and two columns.

[0010] In one embodiment, when the second power signal line includes a third sub-power signal line extending along the first direction and a fourth sub-power signal line extending along the second direction, at least four adjacent pixels have second electrodes connected to the third sub-power signal line and the fourth sub-power signal line through the same overlap portion.

[0011] In one embodiment, the display substrate includes a plurality of said overlapping portions, at least one of said overlapping portions being electrically connected to other said overlapping portions arranged in the first direction via the third sub-power signal line, and electrically connected to other said overlapping portions arranged in the second direction via the fourth sub-power signal line.

[0012] In one embodiment, the display substrate further includes an electrode connection structure connected to the second electrode, and each of the second electrodes that contacts the same overlapping portion is connected to the same electrode connection structure, and the second electrode contacts the overlapping portion through the electrode connection structure.

[0013] In one embodiment, when the first power signal line includes a first sub-power signal line extending along a first direction and a second sub-power signal line extending along a second direction, at least two adjacent pixel circuits are connected to the same first sub-power signal line of the first power signal line or to the same second sub-power signal line.

[0014] In one embodiment, when the first power signal line includes a first sub-power signal line extending along a first direction and a second sub-power signal line extending along a second direction, at least one of the first sub-power signal lines is electrically connected to the pixel circuit through the second sub-power signal line.

[0015] At least a portion of the second sub-power signal line is disposed on a different layer than the first sub-power signal line.

[0016] In one embodiment, the display substrate further includes a driving signal line disposed on the same layer as the first sub-power signal line, the driving signal line being configured to provide a driving signal for the pixel circuit; the orthographic projection of the portion of the second sub-power signal line disposed on a different layer from the first sub-power signal line on the substrate overlaps with the orthographic projection of the driving signal line on the substrate.

[0017] In one embodiment, the orthographic projection of the first power signal line on the substrate does not overlap with the orthographic projection of the second power signal line on the substrate.

[0018] In one embodiment, when the first power signal line includes a first sub-power signal line extending along a first direction and a second sub-power signal line extending along a second direction, and the second power signal line includes a third sub-power signal line extending along the first direction and a fourth sub-power signal line extending along the second direction, the first power signal line further includes a plurality of first connecting segments extending along the second direction; the second power signal line further includes a plurality of second connecting segments extending along the second direction; each first sub-power signal line includes a plurality of first sub-signal segments spaced apart in the first direction, each second sub-power signal line includes a plurality of second sub-signal segments spaced apart in the second direction, and each first sub-signal segment is connected to at least one second sub-signal segment; each third sub-power signal line includes a plurality of third sub-signal segments spaced apart in the first direction, each fourth sub-power signal line includes a plurality of fourth sub-signal segments spaced apart in the second direction, and each third sub-signal segment is connected to at least one fourth sub-signal segment.

[0019] The first sub-signal segments adjacent in the second direction are connected by the first connecting segment, and the third sub-signal segments adjacent in the second direction are connected by the second connecting segment; at least one first connecting segment's orthographic projection on the substrate is located between the orthographic projections of two adjacent third sub-signal segments on the substrate; at least one second connecting segment's orthographic projection on the substrate is located between the orthographic projections of two adjacent first sub-signal segments on the substrate.

[0020] In one embodiment, the transparent display area includes a light-emitting area and a non-light-emitting area; the pixel is disposed in the light-emitting area;

[0021] The display substrate is also provided with a plurality of driving signal lines; at least one of the driving signal lines has a width in the portion located in the light-emitting area that is greater than the width in the portion located in the non-light-emitting area.

[0022] In one embodiment, the drive signal line includes a scan signal line configured to provide a scan signal to the pixel;

[0023] At least one of the scanning signal lines has a width greater than the width of its portion located in the light-emitting area than the width of its portion located in the non-light-emitting area; the width of the portion of the scanning signal line located in the light-emitting area ranges from 3.5 μm to 5.5 μm, and the width of the portion of the scanning signal line located in the non-light-emitting area ranges from 2 μm to 3.5 μm.

[0024] In one embodiment, the pixel circuit includes a driving transistor, and the display substrate further includes an active semiconductor layer, the active semiconductor layer including the channel of the driving transistor for each of the sub-pixels;

[0025] In at least one of the pixels, the channel of the driving transistor of at least one sub-pixel includes a first segment, a second segment, a third segment, a fourth segment, and a fifth segment connected in sequence, the first segment, the third segment, and the fifth segment extending along the second direction, and the second segment and the fourth segment extending along the first direction; the channel of the driving transistor of at least one sub-pixel includes a sixth segment, a seventh segment, and an eighth segment connected in sequence, the sixth segment and the eighth segment extending along the second direction, and the seventh segment extending along the first direction.

[0026] In one embodiment, the display substrate further includes a shielding line and a reset power signal line, wherein the reset power signal line is configured to provide a reset power signal to the sub-pixel; the shielding line is electrically connected to the reset power signal line.

[0027] In one embodiment, the transparent display area includes a light-emitting area and a non-light-emitting area, and the pixel is located in the light-emitting area; the display substrate further includes a pixel defining layer, and the pixel defining layer has an opening located in the non-light-emitting area;

[0028] The orthographic projection of the opening on the substrate is at least partially located outside the orthographic projection of the second electrode on the substrate, the orthographic projection of the second power signal line on the substrate, and the orthographic projection of the first power signal line on the substrate.

[0029] In one embodiment, the display substrate further includes a border area located on at least one side of the display area, and the display substrate further includes an auxiliary trace located in the border area, the auxiliary trace being electrically connected to the second electrode; the auxiliary trace includes a first conductive film layer and a second conductive film layer located on the side of the first conductive film layer facing away from the substrate, the orthographic projection of the first conductive film layer on the substrate near the edge of the display area is located inside the orthographic projection of the second conductive film layer on the substrate near the edge of the display area.

[0030] According to a second aspect of the embodiments of this application, a display panel is provided, including the display substrate described above.

[0031] According to a third aspect of the embodiments of this application, a display device is provided, including the display panel described above.

[0032] The display substrate, display panel, and display device provided in this application embodiment have a number of first electrodes greater than the number of second electrodes, resulting in at least two sub-pixels sharing one second electrode. Compared to a scheme where the second electrodes of each sub-pixel are independently set, the sharing of one second electrode by at least two sub-pixels in this application embodiment can reduce the total area of ​​the second electrodes in the transparent display area, which helps to improve the light transmittance of the transparent display area of ​​the display substrate. By setting one of the first power signal line and the second power signal line to a mesh structure, it helps to reduce the voltage drop of the first power signal line and the second power signal line, thereby improving the uniformity of the display effect of the display substrate. Attached Figure Description

[0033] Figure 1 This is a circuit diagram of a pixel circuit provided in an exemplary embodiment of this application;

[0034] Figures 2 to 7 This is a partial schematic diagram of the layers of a display substrate provided in an exemplary embodiment of this application; wherein, Figure 3 for Figure 2 A magnified view of a portion of the image;

[0035] Figure 8 This is a schematic diagram of multiple film layers stacked on a display substrate provided in an exemplary embodiment of this application;

[0036] Figure 9 This is a partial schematic diagram of the second conductive layer of a display substrate provided in an exemplary embodiment of this application;

[0037] Figure 10 This is a partial schematic diagram of the third conductive layer of a display substrate provided in an exemplary embodiment of this application;

[0038] Figure 11This is a partial schematic diagram of the superposition of the third conductive layer and the fourth conductive layer of a display substrate provided in an exemplary embodiment of this application;

[0039] Figure 12 This is a partial schematic diagram of multiple film layers stacked on a display substrate provided in an exemplary embodiment of this application;

[0040] Figure 13 This is a partial schematic diagram of the second conductive layer of a display substrate provided in another exemplary embodiment of this application;

[0041] Figure 14 This is a partial schematic diagram of the third conductive layer of a display substrate provided in another exemplary embodiment of this application;

[0042] Figure 15 This is a partial schematic diagram of the superposition of the third conductive layer and the fourth conductive layer of a display substrate provided in another exemplary embodiment of this application;

[0043] Figure 16 This is a partial schematic diagram of multiple film layers stacked on a display substrate provided in another exemplary embodiment of this application;

[0044] Figure 17 This is a partial schematic diagram of the superposition of the first power signal line and the second power signal line of the display substrate provided in an exemplary embodiment of this application;

[0045] Figure 18 This is a partial schematic diagram of multiple film layers stacked on a display substrate provided in an exemplary embodiment of this application. Detailed Implementation

[0046] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0047] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0048] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0049] This application provides a display substrate, a display panel, and a display device. The display substrate, display panel, and display device of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features in the following embodiments can complement or combine with each other.

[0050] This application provides a display substrate, a display panel, and a display device. The display substrate, display panel, and display device of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features in the following embodiments can complement or combine with each other.

[0051] This application provides a display substrate. The display substrate includes a display area, at least a portion of which is a transparent display area.

[0052] In one embodiment, the entire display area is a transparent display area, meaning the display substrate is a transparent display substrate. A transparent display area refers to a display area comprising sub-display areas and light-transmitting areas. Sub-display areas are areas with pixels, and light-transmitting areas are areas without pixels; alternatively, sub-display areas are areas with pixel circuitry, and light-transmitting areas are areas without pixel circuitry. In another embodiment, a portion of the display area is a transparent display area, while another portion is a non-transparent display area. For example, the area beneath the display substrate where a camera and light sensor are located is a transparent display area, while other areas are non-transparent display areas.

[0053] The display substrate includes a substrate and a plurality of pixels located on the substrate and in the transparent display area. The plurality of pixels are arranged at intervals on the substrate. It should be noted that, unless otherwise specified, the following description of pixels refers to the pixels in the transparent display area.

[0054] The pixel includes multiple sub-pixels, each sub-pixel including an organic light-emitting element (OLED) and a pixel circuit driving the OLED; the OLED includes a first electrode, a second electrode, and an organic light-emitting material located between the first electrode and the second electrode. The first electrode of the sub-pixel is electrically connected to the pixel circuit. In some embodiments, the first electrode can be an anode, and the second electrode can be a cathode. The first electrode is located on the side with the light-emitting material closer to the substrate, and the second electrode is located on the side with the light-emitting material away from the substrate. Each pixel may include three sub-pixels of different emitting colors, for example, it may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0055] In one embodiment, the display substrate further includes a pixel defining layer, which has pixel openings corresponding one-to-one with the sub-pixels. The pixel openings are used to define the light-emitting area of ​​each sub-pixel.

[0056] In some embodiments, the organic light-emitting material is located on the side of the first electrode away from the substrate. The first electrode of each sub-pixel contacts the organic light-emitting material at the pixel opening of the pixel defining layer, and the pixel opening of the pixel defining layer defines the shape of the light-emitting area of ​​the sub-pixel. For example, the first electrode (e.g., the anode) of the organic light-emitting element can be disposed below the pixel defining layer, and a portion of the first electrode is exposed by the pixel opening of the pixel defining layer. When the organic light-emitting material is formed in the pixel opening of the pixel defining layer, the organic light-emitting material contacts the first electrode, thereby enabling this portion of the first electrode to drive the organic light-emitting material to emit light.

[0057] In some embodiments, the orthographic projection of the pixel opening of the pixel defining layer onto the substrate lies within the orthographic projection of the corresponding organic light-emitting material onto the substrate, meaning the organic light-emitting material covers the pixel opening of the pixel defining layer. For example, the area of ​​the organic light-emitting material is larger than the area of ​​the corresponding pixel opening; that is, in addition to the portion located inside the pixel opening, the organic light-emitting material also includes at least the portion covering the solid structure of the pixel defining layer. Typically, the organic light-emitting material covers the solid structure of the pixel defining layer at each boundary of the pixel opening. It should be noted that the above description of the organic light-emitting material pattern is based on the patterned organic light-emitting material of each sub-pixel formed, for example, by an FMM process. Besides the FMM fabrication process, some organic light-emitting materials are formed as a monolithic film layer across the entire display area using an open mask process. The orthographic projection of its shape onto the substrate is continuous, so there must be a portion located inside the pixel opening and a portion located on the solid structure of the pixel defining layer.

[0058] In one embodiment, the number of the first electrodes is greater than the number of the second electrodes. The display substrate further includes a first power signal line and a second power signal line; the pixel circuit is connected to the first power signal line, and the second electrodes are connected to the second power signal line; the first power signal line includes a first sub-power signal line extending along a first direction and a second sub-power signal line extending along a second direction; and / or, the second power signal line includes a third sub-power signal line extending along the first direction and a fourth sub-power signal line extending along the second direction; the first direction intersects the second direction.

[0059] In the display substrate provided in this application embodiment, since the number of first electrodes is greater than the number of second electrodes, at least two sub-pixels share one second electrode. If the second electrode of each sub-pixel were independently set, each second electrode would require a large area to connect with the second power signal line. In this application embodiment, the sharing of one second electrode by at least two sub-pixels reduces the total area of ​​the second electrodes in the transparent display area, which helps to improve the light transmittance of the transparent display area of ​​the display substrate. By setting one of the first power signal line and the second power signal line to a mesh structure, it helps to reduce the voltage drop between the first power signal line and the second power signal line, thereby improving the uniformity of the display effect of the display substrate.

[0060] In one embodiment, each sub-pixel of the pixel may share a single second electrode. For example, when a pixel includes red, green, and blue sub-pixels, the red, green, and blue sub-pixels within the same pixel share a single second electrode. No second electrode is provided in the area between adjacent pixels to ensure the light transmittance of the display substrate.

[0061] In one embodiment, the first power signal line may be a high-level power signal line, and the second power signal line may be a low-level power signal line.

[0062] In some embodiments, the first direction is the column direction and the second direction is the row direction. In some embodiments, the pixel circuits of sub-pixels in each pixel are arranged at intervals in the second direction.

[0063] The transparent display area of ​​the display substrate includes a light-emitting area and a non-light-emitting area. All areas outside the light-emitting area are non-light-emitting areas. Pixels are located within the light-emitting area. This means that the pixel circuitry, the first electrode, the organic light-emitting material, and part of the second electrode are located within the light-emitting area.

[0064] In one embodiment, the area covered by the orthographic projection of the pixel circuit of the sub-pixel onto the substrate is approximately within a rectangular frame. The orthographic projection of the pixel circuit onto the substrate mainly includes the orthographic projection of the structures of various transistors, capacitors, and other components onto the substrate. The display substrate also includes multiple signal lines used to drive the pixel circuit. It should be noted that some signal lines include portions located within the rectangular frame as well as portions extending beyond the rectangular frame.

[0065] In one embodiment, such as Figure 1 As shown, the pixel circuit 221 includes a driving circuit 222. The driving circuit 222 includes a control terminal, a first terminal, and a second terminal, and is configured to provide a driving current to the organic light-emitting element 220 to drive the organic light-emitting element 220 to emit light.

[0066] In one embodiment, such as Figure 1 As shown, the pixel circuit 221 includes a first light-emitting control circuit 223 and a second light-emitting control circuit 224. For example, the first light-emitting control circuit 223 is connected to a first terminal and a first voltage terminal VDD of the driving circuit 222, and is configured to enable or disable the connection between the driving circuit 222 and the first voltage terminal VDD. The second light-emitting control circuit 224 is electrically connected to a second terminal of the driving circuit 222 and a first electrode of the organic light-emitting element 220, and is configured to enable or disable the connection between the driving circuit 222 and the organic light-emitting element 220.

[0067] In one embodiment, such as Figure 1 As shown, the pixel circuit 221 further includes a data writing circuit 226, a storage circuit 227, a threshold compensation circuit 228, and a reset circuit 229. The data writing circuit 226 is electrically connected to the first terminal of the driving circuit 222 and is configured to write data signals into the storage circuit 227 under the control of a scan signal. The storage circuit 227 is electrically connected to the control terminal and the first voltage terminal VDD of the driving circuit 222 and is configured to store data signals. The threshold compensation circuit 228 is electrically connected to the control terminal and the second terminal of the driving circuit 222 and is configured to perform threshold compensation on the driving circuit 222. The reset circuit 229 is electrically connected to the control terminal of the driving circuit 222 and the first electrode of the organic light-emitting element 220 and is configured to reset the control terminal of the driving circuit 222 and the first electrode of the organic light-emitting element 220 under the control of a reset control signal.

[0068] In one embodiment, such as Figure 1 As shown, the driving circuit 222 includes a driving transistor T1, the control terminal of the driving circuit 222 includes the gate of the driving transistor T1, the first terminal of the driving circuit 222 includes the first electrode of the driving transistor T1, and the second terminal of the driving circuit 222 includes the second electrode of the driving transistor T1.

[0069] In one embodiment, such as Figure 1 As shown, the data writing circuit 226 includes a data writing transistor T2, the storage circuit 227 includes a capacitor C, the threshold compensation circuit 228 includes a threshold compensation transistor T3, the first light-emitting control circuit 223 includes a first light-emitting control transistor T4, the second light-emitting control circuit 224 includes a second light-emitting control transistor T5, the reset circuit 229 includes a first reset transistor T6 and a second reset transistor T7, and the reset control signal may include a first sub-reset control signal and a second sub-reset control signal.

[0070] In one embodiment, such as Figure 1 As shown, the first terminal of data writing transistor T2 is electrically connected to the first terminal of driving transistor T1, the second terminal of data writing transistor T2 is configured to be electrically connected to data line Vd to receive data signals, and the gate of data writing transistor T2 is configured to be electrically connected to scan signal line Ga1 to receive scan signals; the first terminal of capacitor C is electrically connected to the first power supply terminal VDD, and the second terminal of capacitor C is electrically connected to the gate of driving transistor T1; the first terminal of threshold compensation transistor T3 is electrically connected to the second terminal of driving transistor T1, the second terminal of threshold compensation transistor T3 is electrically connected to the gate of driving transistor T1, and the gate of threshold compensation transistor T3 is configured to be electrically connected to scan signal line Ga2 to receive compensation control signals; the first terminal of first reset transistor T6 is configured to be electrically connected to reset power supply terminal Vinit1 to receive the first reset signal, the second terminal of first reset transistor T6 is electrically connected to the gate of driving transistor T1, and the gate of first reset transistor T6 is configured to be electrically connected to reset control signal line Rst1 to receive the first sub-reset control signal; the second... The first terminal of the reset transistor T7 is configured to be electrically connected to the reset power supply terminal Vinit2 to receive a second reset signal. The second terminal of the second reset transistor T7 is electrically connected to the first electrode of the organic light-emitting element 220. The gate of the second reset transistor T7 is configured to be electrically connected to the reset control signal line Rst2 to receive a second sub-reset control signal. The first terminal of the first light-emitting control transistor T4 is electrically connected to the first power supply terminal VDD. The second terminal of the first light-emitting control transistor T4 is electrically connected to the first terminal of the driving transistor T1. The gate of the first light-emitting control transistor T4 is configured to be electrically connected to the light-emitting control signal line EM1 to receive a first light-emitting control signal. The first terminal of the second light-emitting control transistor T5 is electrically connected to the second terminal of the driving transistor T1. The second terminal of the second light-emitting control transistor T5 is electrically connected to the second electrode of the organic light-emitting element 220. The gate of the second light-emitting control transistor T5 is configured to be electrically connected to the light-emitting control signal line EM2 to receive a second light-emitting control signal. The first electrode of the organic light-emitting element 220 is electrically connected to the second power supply terminal VSS.

[0071] In one embodiment, one of the first power supply terminal VDD and the second power supply terminal vss is a high-voltage terminal and the other is a low-voltage terminal. Figure 1 In the illustrated embodiment, the first power supply terminal VDD is a voltage source that outputs a constant first voltage, which is a positive voltage; while the second power supply terminal VSS can be a voltage source that outputs a constant second voltage, which is a negative voltage, etc. In some exemplary embodiments, the second power supply terminal VSS can be grounded.

[0072] In one embodiment, such as Figure 1 As shown, the scan signal and the compensation control signal can be the same. That is, the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 can be electrically connected to the same signal line, such as the scan signal line Ga1, to receive the same signal (e.g., the scan signal). In this case, the display substrate may not need to provide the scan signal line Ga2, reducing the number of signal lines. Alternatively, the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 can also be electrically connected to different signal lines. That is, the gate of the data writing transistor T2 is electrically connected to the scan signal line Ga1, and the gate of the threshold compensation transistor T3 is electrically connected to the scan signal line Ga2, while the scan signal lines Ga1 and Ga2 transmit the same signal.

[0073] It should be noted that the scan signal and the compensation control signal can also be different, so that the gate of the data writing transistor T2 and the threshold compensation transistor T3 can be controlled separately, increasing the flexibility of the pixel circuit control.

[0074] In one embodiment, such as Figure 1 As shown, the first light-emitting control signal and the second light-emitting control signal can be the same. That is, the gate of the first light-emitting control transistor T4 and the gate of the second light-emitting control transistor T5 can be electrically connected to the same signal line, such as the light-emitting control signal line EM1, to receive the same signal (e.g., the first light-emitting control signal). In this case, the display substrate may not need to provide the light-emitting control signal line EM2, reducing the number of signal lines. In other embodiments, the gate of the first light-emitting control transistor T4 and the gate of the second light-emitting control transistor T5 can also be electrically connected to different signal lines. That is, the gate of the first light-emitting control transistor T4 is electrically connected to the light-emitting control signal line EM1, and the gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line EM2, while the light-emitting control signal line EM1 and the light-emitting control signal line EM2 transmit the same signal.

[0075] It should be noted that when the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are transistors of different types, for example, the first light-emitting control transistor T4 is a P-type transistor and the second light-emitting control transistor T5 is an N-type transistor, the first light-emitting control signal and the second light-emitting control signal may also be different. The embodiments of this application do not limit this.

[0076] In one embodiment, the first sub-reset control signal and the second sub-reset control signal can be the same. That is, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 can be electrically connected to the same signal line, such as the reset control signal line Rst1, to receive the same signal (e.g., the first sub-reset control signal). In this case, the display substrate may not need to provide a reset control signal line Rst2, reducing the number of signal lines. Alternatively, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 can also be electrically connected to different signal lines. That is, the gate of the first reset transistor T6 is electrically connected to the reset control signal line Rst1, and the gate of the second reset transistor T7 is electrically connected to the reset control signal line Rst2, while the reset control signal lines Rst1 and Rst2 transmit the same signal. It should be noted that the first sub-reset control signal and the second sub-reset control signal can also be different. In another embodiment, the first sub-reset control signal differs from the second sub-reset control signal. The pulse width of the reset control signal line Rst2 is greater than the pulse width of the reset control signal line Rst1, and the pulse width of the reset control signal line Rst2 is less than the pulse width of the light-emitting control signal line EM2 when the second light-emitting control transistor T5 is off. This helps to improve the lifetime of the organic light-emitting element of the sub-pixel.

[0077] In one embodiment, the second sub-reset control signal can be the same as the scan signal, that is, the gate of the second reset transistor T7 can be electrically connected to the scan signal line Ga1 to receive the scan signal as the second sub-reset control signal.

[0078] In one embodiment, the gate of the first reset transistor T6 and the source of the second reset transistor T7 are respectively connected to the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be DC reference voltage terminals to output a constant DC reference voltage. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be the same; for example, the gate of the first reset transistor T6 and the source of the second reset transistor T7 are connected to the same reset power supply terminal. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be high-voltage terminals or low-voltage terminals, as long as they can provide the first reset signal and the second reset signal to reset the gate of the driving transistor T1 and the first electrode of the light-emitting element 220. This application does not impose any restrictions on this.

[0079] It should be noted that, Figure 1 The driving circuit 222, data writing circuit 226, storage circuit 227, threshold compensation circuit 228, and reset circuit 229 in the pixel circuit shown are only illustrative. The specific structure of the driving circuit 222, data writing circuit 226, storage circuit 227, threshold compensation circuit 228, and reset circuit 229 can be set according to actual application requirements. The embodiments of this application do not specifically limit this.

[0080] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. For clarity, the embodiments of this application use P-type transistors (e.g., P-type MOS transistors) as an example to illustrate the technical solution of this application. That is, in the description of this application, the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light-emitting control transistor T4, the second light-emitting control transistor T5, the first reset transistor T6, and the second reset transistor T7 can all be P-type transistors. Of course, the transistors in the embodiments of this application are not limited to P-type transistors. Those skilled in the art can also use N-type transistors (e.g., N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of this application according to actual needs.

[0081] It should be noted that the transistors used in the embodiments of this application can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Thin-film transistors can include oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, or polycrystalline silicon thin-film transistors, etc. The source and drain of the transistor can be symmetrical in structure, so their source and drain can be indistinguishable in physical structure. In the embodiments of this application, in order to distinguish the transistors, except for the gate, which serves as the control electrode, one electrode is directly described as the first electrode and the other electrode as the second electrode. Therefore, in the embodiments of this application, the first and second electrodes of all or some transistors can be interchanged as needed.

[0082] It should be noted that, in the embodiments of this application, the pixel circuit of the sub-pixel can be, in addition to being, Figure 1 In addition to the 7T1C (i.e., seven transistors and one capacitor) structure shown, other structures including other numbers of transistors are also possible, such as 7T2C, 6T1C, 6T2C or 9T2C structures. This application does not limit the specific structure to these.

[0083] Figure 2-7 This is a schematic diagram of the layers of a display substrate provided in one embodiment of this application. Figure 8 This is a schematic diagram showing the partial film layer stacking on a display substrate. See below for reference. Figure 2-8 Describe the positional relationship of the various circuits and signal lines in the pixel circuit on the backplane. Figure 2-8 The example shown uses the pixel circuit 221 of a single pixel as an example, and illustrates the position of each transistor in the pixel circuit included in sub-pixel 110. The components included in the pixel circuits of sub-pixel 120 and sub-pixel 130 are in roughly the same position as the transistors included in sub-pixel 110. Figure 2-7 It can be seen that the pixel circuit is located in the light-emitting area AA1, some signal lines are located only in the light-emitting area AA1, and some signal lines are partially located in the light-emitting area AA1 and partially located in the non-light-emitting area AA2. For example... Figure 2 As shown, the pixel circuit 221 of sub-pixel 110 includes Figure 1 The diagram shows a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, a second reset transistor T7, and a capacitor C.

[0084] Figure 2-8 The pixel circuit 121, which is electrically connected to each sub-pixel of the same pixel, also shows the scan signal line Ga1, reset control signal line Rst1, reset power signal line Init1, light emission control signal line EM1, data line Vd, second sub-power signal line VDD12 connected to the first power signal line VDD1 connected to the first power terminal VDD, second power signal line VSS connected to the second power terminal VSS, and shielding line 344. Figure 2-7 The third power signal line VDD2, the fourth power signal line VDD3, and the fifth power signal line VDD4 are also shown. The third power signal line VDD2, the fourth power signal line VDD3, and the fifth power signal line VDD4 are electrically connected to the first power signal line VDD1, respectively.

[0085] Scan signal line Ga1 is configured to provide a scan signal to the pixel; reset control signal lines Rst1 and Rst2 are configured to provide a reset control signal to the pixel; reset power signal line Init1 is configured to provide a reset power signal to the pixel; light emission control signal line EM1 is configured to provide a light emission control signal to the pixel; data line Vd is configured to provide a light emission data signal to the pixel; and first power signal line VDD1 and second power signal line VSS are configured to provide power signals to the pixel.

[0086] For example, Figure 2 The active semiconductor layer 310 of the pixel circuit in the display substrate is shown. The active semiconductor layer 310 can be formed by patterning semiconductor material. The active semiconductor layer 310 can be used to fabricate the channels of the aforementioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light-emitting control transistor T4, second light-emitting control transistor T5, first reset transistor T6, and second reset transistor T7. The active semiconductor layer 310 includes the channel and source / drain regions (i.e., the source region s and drain region d shown in the sub-pixel 120) of each transistor in each sub-pixel, and the channel and source / drain regions of each transistor in the same pixel circuit are integrally formed.

[0087] It should be noted that the active semiconductor layer may include an integrally formed low-temperature polycrystalline silicon layer, in which the source and drain regions can be conductiveized through doping to achieve electrical connections between the various structures. That is, the active semiconductor layer of each transistor in each sub-pixel is an integral pattern formed of p-silicon, and each transistor in the same pixel circuit includes a source-drain region (i.e., source region s and drain region d) and a channel, with the channels of different transistors separated by the source-drain regions.

[0088] In one embodiment, the active semiconductor layers in the pixel circuits of different color sub-pixels arranged along the second direction are not connected and are disconnected from each other. The active semiconductor layers in the pixel circuits of the same color sub-pixels arranged along the first direction can be integrally formed or disconnected from each other.

[0089] like Figure 3As shown, in at least one pixel, the channels 31 and 32 of the driving transistor T1 of at least one sub-pixel include a first segment 301, a second segment 302, a third segment 303, a fourth segment 304, and a fifth segment 305 connected in sequence. The first segment 301, the third segment 303, and the fifth segment 305 extend along the second direction Y, and the second segment 302 and the fourth segment 304 extend along the first direction X. The channel 33 of the driving transistor T1 of at least one sub-pixel includes a sixth segment 306, a seventh segment 307, and an eighth segment 308 connected in sequence. The sixth segment 306 and the eighth segment 308 extend along the second direction Y, and the seventh segment 307 extends along the first direction X. With this configuration, the channel width-to-length ratio of the driving transistors of different color sub-pixels on the display substrate can be optimized under the premise that the space occupied by the sub-pixel is fixed, thereby improving the brightness of the display substrate. In this embodiment, the aspect ratio of channel 33 is greater than that of channels 31 and 32. In some embodiments, channels 31 and 32 may be channels for red and green sub-pixels, and channel 33 may be a channel for blue sub-pixels.

[0090] In one embodiment, such as Figure 3 As shown, the driving transistor T1 of the sub-pixel includes a first source-drain region 311 and a second source-drain region 312. At least one of the first and second source-drain regions of the driving transistor T1 of the sub-pixel has different lengths. One of the first and second source-drain regions 311 and 312 is a source region, and the other is a drain region. In the driving transistors T1 containing channels 31 and 32, the first source-drain region 311 is connected to the first segment 301, and the second source-drain region 312 is connected to the fifth segment 305. In the driving transistor T1 containing channel 33, the first source-drain region 311 is connected to the sixth segment 306, and the second source-drain region 312 is connected to the eighth segment 308. This configuration optimizes signal writing to the pixel circuit and improves the light-shielding design of the channels.

[0091] Figure 3 In the embodiment shown, the lengths of the first source-drain region 311 and the second source-drain region 312 in the driving transistor T1 containing channels 31, 32 and 33 are different.

[0092] For example, the gate metal layer of the pixel circuit may include a first conductive layer and a second conductive layer. A gate insulating layer is formed on the active semiconductor layer 310 to protect the active semiconductor layer 310, which is located on the substrate 100. Figure 4The first conductive layer 320 of the display substrate is shown. The first conductive layer 320 is disposed on the gate insulating layer, thereby isolating it from the active semiconductor layer 310. The first conductive layer 320 may include the second plate CC2 of capacitor C, a scan signal line Ga1, a reset control signal line Rst1, a light emission control signal line EM1, and the gates of driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light emission control transistor T4, second light emission control transistor T5, first reset transistor T6, and second reset transistor T7. The scan signal line Ga1 includes a scan signal line body Ga11 and a protrusion P extending from one side of the scan signal line body Ga11.

[0093] For example, such as Figure 4 As shown, the gate of the data writing transistor T2 can be the portion where the scan signal line Ga1 overlaps with the active semiconductor layer 310; the gate of the first light-emitting control transistor T4 can be the first portion where the light-emitting control signal line EM1 overlaps with the active semiconductor layer 310, and the gate of the second light-emitting control transistor T5 can be the second portion where the light-emitting control signal line EM1 overlaps with the active semiconductor layer 310; the gate of the first reset transistor T6 is the first portion where the reset control signal line Rst1 overlaps with the active semiconductor layer 310, and the gate of the second reset transistor T7 is the second portion where the reset control signal line Rst1 overlaps with the active semiconductor layer 310; the threshold compensation transistor T3 can be a dual-gate thin-film transistor, the first gate of the threshold compensation transistor T3 can be the portion where the scan signal line Ga1 overlaps with the active semiconductor layer 310, and the second gate of the threshold compensation transistor T3 can be the portion where the protrusion P of the scan signal line Ga1 overlaps with the active semiconductor layer 310. Figure 1 and 4 As shown, the gate of the driving transistor T1 can be the second plate CC2 of the capacitor C.

[0094] It should be noted that, Figure 2 The dashed rectangles in the diagram show the various portions where the first conductive layer 320 overlaps with the active semiconductor layer 310.

[0095] For example, such as Figure 4 As shown, the scan signal line Ga1, reset control signal line Rst1, and light emission control signal line EM1 are arranged along the first direction X, and extend along the second direction Y. Wherein, "signal lines extending along the second direction" means that the entire row of signal lines extends along the second direction, and the area of ​​the portion extending along the second direction is much larger than the area of ​​the portion extending along the second direction; "signal lines extending along the first direction" means that the entire row of signal lines extends along the first direction, and the area of ​​the portion extending along the first direction is much larger than the area of ​​the portion extending along the second direction.

[0096] For example, in the first direction X, the second plate CC2 of capacitor C (i.e., the gate of driving transistor T1) is located between scan signal line Ga1 and light emission control signal line EM1. The protrusion P of scan signal line Ga1 is located on the side of scan signal line Ga1 away from light emission control signal line EM1.

[0097] For example, such as Figure 2 As shown, in the first direction X, the gates of the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6, and the second reset transistor T7 are all located on the first side of the gate of the driving transistor T1, and the gates of the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are both located on the second side of the gate of the driving transistor T1. For example, Figure 2-7 In the example shown, the first and second sides of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel are two opposing sides of the gate of the driving transistor T1 in the first direction X. For example, as Figure 2-8 As shown, in the XY plane, the first side of the gate of the driving transistor T1 of the pixel circuit of sub-pixel 110 can be the upper side of the gate of driving transistor T1, and the second side of the gate of driving transistor T1 of the pixel circuit of sub-pixel 110 can be the lower side of the gate of driving transistor T1. The lower side, for example, is the side of the display substrate used to bond the driving chip, and the lower side of the gate of driving transistor T1 is the side of the gate of driving transistor T1 closer to the driving chip. The upper side is the opposite side of the lower side, for example, the side of the gate of driving transistor T1 further away from the driving chip.

[0098] For example, in some embodiments, such as Figure 2-8 As shown, in the second direction Y, the gates of the data writing transistor T2 and the first light-emitting control transistor T4 are both located on the third side of the gate of the driving transistor T1, while the first gate of the threshold compensation transistor T3, the gate of the second light-emitting control transistor T5, and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1. For example, Figure 2-8 In the example shown, the third and fourth sides of the gate of the driving transistor T1 of the pixel circuit of sub-pixel 110 are two opposite sides of the gate of the driving transistor T1 in the second direction Y. For example, as Figure 2-7As shown, the third side of the gate of the driving transistor T1 of the pixel circuit of sub-pixel 110 can be the left side of the gate of the driving transistor T1 of the pixel circuit of sub-pixel 110, and the fourth side of the gate of the driving transistor T1 of the pixel circuit of sub-pixel 110 can be the right side of the gate of the driving transistor T1 of the pixel circuit of sub-pixel 110. For example, in the same pixel circuit, the data line is to the left of the first power signal line VDD1, and the first power signal line VDD1 is to the right of the data line.

[0099] For example, a first insulating layer is formed on the first conductive layer 320 to protect the first conductive layer 320. Figure 5 The second conductive layer 330 of the pixel circuit is shown. The second conductive layer 330 includes a first electrode CC1 of capacitor C, a reset power signal line Init1, and a third power signal line VDD2. The third power signal line VDD2 is integrally formed with the first electrode CC1 of capacitor C. The first electrode CC1 of capacitor C and the second electrode CC2 of capacitor C at least partially overlap to form capacitor C.

[0100] For example, a second insulating layer is formed on the second conductive layer 330 to protect the second conductive layer 330. Figure 6 The source-drain metal layer 340 of the pixel circuit is shown. The source-drain metal layer 340 includes a data line Vd, a fourth power signal line VDD3, and a shield line 344. The data line Vd, the fourth power signal line VDD3, and the shield line 344 all extend along a first direction X. The shield line 344 is disposed in the same layer and with the same material as the data line Vd, allowing the shield line to be formed simultaneously with the data line in the same patterning process. This avoids the need for additional patterning processes to fabricate the shield line, thereby simplifying the display substrate fabrication process and saving manufacturing costs. For example, the source-drain metal layer 340 also includes a connection structure 341, a connection portion 342, and a first sub-electrode connection structure 343 of the electrode connection portion. One end of the connection structure 341 is connected to the gate of the driving transistor T1, and the other end of the connection structure 341 is connected to the source-drain region of the threshold compensation transistor T3.

[0101] Figure 6 Exemplary locations of multiple vias are also shown, through which the source / drain metal layer 340 is connected to multiple film layers located between the source / drain metal layer 340 and the substrate. For example, the source / drain metal layer 340 is connected to vias 381, 382, ​​384, 387, and 352. Figure 2 The active semiconductor layer 310 and the source / drain metal layer 340 shown are connected to each other through vias 3832, 386, 385, and 332. Figure 5 The second conductive layer 330 is shown.

[0102] For example, a third insulating layer and a fourth insulating layer are formed on the aforementioned source-drain metal layer 340 to protect the source-drain metal layer 340. The organic light-emitting element of each sub-pixel can be disposed on the side of the third insulating layer and the fourth insulating layer away from the substrate.

[0103] Figure 7 The third conductive layer 350 of the pixel circuit is shown. The third conductive layer 350 includes a second sub-electrode connection structure 353 of the electrode connection portion, a second sub-power signal line VDD12 extending along a first power signal line VDD1 in a second direction, and a fifth power signal line VDD4 extending along a first direction X. The second sub-power signal line VDD12 intersects with each of the fifth power signal lines VDD4. The specific structure of the first power signal line VDD1 will be explained later. Figures 9 to 16 As described in the relevant description. Figure 7 Exemplary locations of a plurality of vias 351 and 354 are also shown, through which the third conductive layer 350 is connected to the source / drain metal layer 340.

[0104] Figure 8 This is a schematic diagram illustrating the stacking relationship of the active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the source / drain metal layer 340, and the third conductive layer 350. (See diagram below.) Figure 2-8 As shown, the data line Vd is connected to the source region of the data writing transistor T2 in the active semiconductor layer 310 through at least one via (e.g., via 381) in the gate insulating layer, the first insulating layer, and the second insulating layer. The fourth power signal line VDD3 is connected to the source region of the corresponding first light-emitting control transistor T4 in the active semiconductor layer 310 through at least one via (e.g., via 382) in the gate insulating layer, the first insulating layer, and the second insulating layer.

[0105] like Figure 2-8As shown, one end of connection structure 341 is connected to the drain region of the corresponding threshold compensation transistor T3 in the active semiconductor layer 310 through at least one via (e.g., via 384) in the gate insulating layer, the first insulating layer, and the second insulating layer. The other end of connection structure 341 is connected to the gate (i.e., the second plate CC2 of capacitor C) of driving transistor T1 in the first conductive layer 320 through at least one via (e.g., via 385) in the first insulating layer. One end of connection portion 342 is connected to the reset power signal line Init1 through a via (e.g., via 386) in the second insulating layer. The other end of connection portion 342 is connected to the drain region of the second reset transistor T7 in the active semiconductor layer 310 through at least one via (e.g., via 387) in the gate insulating layer, the first insulating layer, and the second insulating layer. The first sub-electrode connection structure 343 is connected to the drain region of the second light-emitting control transistor T5 in the active semiconductor layer 310 through at least one via (e.g., via 352) in the gate insulating layer, the first insulating layer, and the second insulating layer. It should be noted that the source and drain regions of the transistors used in the embodiments of this application may be structurally identical, so their source and drain regions may be structurally indistinguishable and can be interchanged as needed.

[0106] For example, such as Figure 2-7 As shown, the fourth power signal line VDD3 is connected to the first plate CC1 of the capacitor C in the second conductive layer 330 through at least one via (e.g., via 3832) in the second insulating layer located between the second conductive layer 330 and the source / drain metal layer 340.

[0107] For example, such as Figure 2-8 As shown, the shielding line 344 extends along the first direction X, and its orthographic projection on the substrate lies between the orthographic projections of the corresponding data lines of two adjacent pixels on the substrate. For example, the shielding line can reduce the impact of signals transmitted on the corresponding data lines of two adjacent pixels on the performance of the threshold compensation transistor T3, thus mitigating crosstalk problems.

[0108] For example, such as Figure 2-8 As shown, the shielding line 344 is connected to the reset power signal line Init1 through at least one via (e.g., via 332) in the second insulating layer. In addition to giving the shielding line a fixed potential, this also makes the voltage of the initialization signal transmitted on the reset power signal line more stable, which is more beneficial to the working performance of the pixel driving circuit.

[0109] For example, such as Figure 2-8As shown, the shielding line 344 is electrically connected to the reset power signal line to give the shielding line a fixed potential. The shielding line 344 can be electrically connected to two reset power signal lines Init1 extending along the Y direction, and these two reset power signal lines Init1 are located on opposite sides of the shielding line 344 along the X direction. For example, these two reset power signal lines correspond to the nth row pixel circuit and the (n+1)th row pixel circuit, respectively.

[0110] For example, the shield line 344 in the same column can be a single shield line, which includes multiple sub-sections located between two adjacent reset power signal lines, and each sub-section is located within the circuit area of ​​each pixel in that column. Pixels in the same column can share a single shield line 344.

[0111] For example, in addition to coupling the shielding wire 344 to the reset power signal line, the shielding wire 344 can also be coupled to the first power signal line, so that the shielding wire 344 has the same fixed potential as the power signal transmitted by the first power signal line.

[0112] For example, such as Figure 2-7 As shown, the fifth power signal line VDD4 is connected to the fourth power signal line VDD3 through at least one via 351 in the third and fourth insulating layers, and the second sub-electrode connection structure 353 is connected to the first sub-electrode connection structure 343 through vias 354 in the third and fourth insulating layers.

[0113] For example, the third insulating layer can be a passivation layer, and the fourth insulating layer can be a planarization layer. The third insulating layer is located between the fourth insulating layer and the substrate. The fourth insulating layer can be an organic layer, and the thickness of the organic layer is thicker than that of inorganic layers such as the passivation layer.

[0114] For example, vias 351 and 354 are both nested vias, that is, via 351 includes a first via in the third insulating layer and a second via in the fourth insulating layer. The positions of the first via in the third insulating layer and the second via in the fourth insulating layer are opposite, and the orthogonal projection of the second via in the fourth insulating layer on the substrate is located within the orthogonal projection of the first via in the third insulating layer on the substrate.

[0115] For example, the orthographic projection of the fifth power signal line VDD4 on the substrate approximately coincides with the orthographic projection of the fourth power signal line VDD3 on the substrate, or the orthographic projection of the fourth power signal line VDD3 on the substrate lies within the orthographic projection of the fifth power signal line VDD4 on the substrate. Electrical connection between the fifth power signal line VDD4 and the fourth power signal line VDD3 can reduce the voltage drop of the first power signal line VDD1, thereby improving the uniformity of the display device. For example, the fifth power signal line VDD4 can be made of the same material as the source / drain metal layers.

[0116] For example, such as Figure 6 As shown, the first sub-electrode connection structure 343 of each sub-pixel is a block structure. The first electrode of each color sub-pixel formed subsequently will be connected to the corresponding second sub-electrode connection structure 353 through vias to connect to the drain region of the second light-emitting control transistor T5.

[0117] This embodiment includes, but is not limited to, the position of the second sub-electrode connection structure in each sub-pixel is determined according to the arrangement of the organic light-emitting elements and the position of the light-emitting area.

[0118] For example, the first sub-electrode connection structure 343 of the sub-pixel is connected to the second electrode T5d of the second light-emitting control transistor T5 in the active semiconductor layer through vias 352 in the gate insulating layer, the first insulating layer, and the second insulating layer. The first sub-electrode connection structure 343 overlaps with both the third power supply signal line VDD2 and the light-emitting control signal line EM1. The second sub-electrode connection structure 353 is connected to the first sub-electrode connection structure 343 through nested vias 354 located in the third and fourth insulating layers, thereby achieving connection with the second light-emitting control transistor.

[0119] For example, the data line Vd is connected to the source T2s of the data writing transistor T2 through vias 381 in the gate insulating layer, the first insulating layer, and the second insulating layer; one end of the connection structure 341 is connected to the drain T3d of the threshold compensation transistor T3 through vias 384 in the gate insulating layer, the first insulating layer, and the second insulating layer, and the other end of the connection structure 341 is connected to the gate of the driving transistor T1 (i.e., the second plate CC2 of the capacitor C) through vias 385 in the first insulating layer and the second insulating layer; the channel T1c of the driving transistor T1 is located on the side of its gate facing the substrate and does not overlap with vias 385; the source T1d of the driving transistor T1 overlaps with its gate and the first plate CC1 of the capacitor C.

[0120] It should be noted that the arrangement of the driving circuit, first light-emitting control circuit, second light-emitting control circuit, data writing circuit, storage circuit, threshold compensation circuit, and reset circuit in each pixel circuit is not limited to the following. Figure 2-8 The example shown can be configured to specify the positions of the driving circuit, the first light-emitting control circuit, the second light-emitting control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit, and the reset circuit according to the actual application requirements.

[0121] For example, the first electrode of sub-pixel 110 is connected to the second sub-electrode connection structure 353 through a via (not shown) in the fifth insulating layer, thereby achieving connection with the drain region of the second light-emitting control transistor T5.

[0122] like Figures 9 to 16As shown, the first power signal line VDD1 includes a first sub-power signal line VDD1 extending along a first direction X and a second sub-power signal line VDD12 extending along a second direction Y. The second power signal line VSS includes a third sub-power signal line VSS1 extending along the first direction X and a fourth sub-power signal line VSS2 extending along the second direction Y.

[0123] The second sub-power signal line VDD12 includes a first connection signal line VDD13 and a second connection signal line VDD14. The first connection signal line VDD13 is located on the same layer as the first sub-power signal line VDD11 and is connected to the first sub-power signal segment VDD11. The first sub-power signal segment VDD11 and the first connection signal line VDD13 may be located on the source / drain metal layer 340. The second connection signal line VDD14 is located on a different layer than the first connection signal line VDD13. The second connection signal line VDD14 may be located on the third conductive layer 350.

[0124] For example, such as Figure 10 and Figure 11 As shown, the second connection signal line VDD14 intersects with the fifth power signal line VDD4, and the second connection signal line VDD14 is connected to the first connection signal line VDD13 through the through holes of the third and fourth insulating layers.

[0125] The third sub-power signal line VSS1 and the fourth sub-power signal line VSS2 of the second power signal line VSS intersect and can be located on the same layer. The third sub-power signal line VSS1 and the fourth sub-power signal line VSS2 can be located on the third conductive layer 350.

[0126] In one embodiment, such as Figures 10 to 12 , Figures 14 to 16 As shown, the display substrate further includes an overlap portion 40 connected to the second power signal line VSS. The overlap portion 40 can be disposed on the same layer as the second power signal line VSS.

[0127] like Figure 12 and Figure 16 As shown, the sub-pixel includes a first electrode 21 and a second electrode 22, and each sub-pixel in the same pixel shares a second electrode 22. The display substrate may also include a pixel defining layer, which has a plurality of pixel openings 23. The first electrode 21 and the pixel openings 23 are both located in the light-emitting area AA1. Each sub-pixel corresponds to one pixel opening, and the orthographic projection of the pixel opening 23 of the sub-pixel on the substrate is located within the orthographic projection of the first electrode 21 on the substrate.

[0128] In one embodiment, such as Figure 12As shown, at least two adjacent pixels have their second electrodes 22 in contact with the same overlap portion 40. Contact between the second electrode and the overlap portion means that the second electrode contacts the overlap portion through a contact hole in the insulating layer between it and the overlap portion. This arrangement allows the second electrodes 22 of adjacent pixels to contact the same overlap portion 40 to achieve electrical connection with the second power signal line VSS. Compared to a scheme where the second electrodes of each pixel contact different overlap portions, this reduces the number of overlap portions and contact holes, improving the light transmittance of the display substrate. Furthermore, in a scheme where the second electrodes of each pixel contact the second power signal line through the same overlap portion, the second electrodes of each pixel need to be relatively large to overlap with the overlap portion 40 in the film layer stacking direction. In this embodiment, by setting at least two pixels' second electrodes to contact the same overlap portion 40, the total area of ​​the second electrodes in the display substrate can be reduced, which helps improve the light transmittance of the display substrate. Additionally, this embodiment reduces the number of sub-power signal lines of the second power signal line VSS, which also helps improve the light transmittance of the display substrate.

[0129] Furthermore, at least two adjacent pixels have their second electrodes 22 electrically connected to the third sub-power signal line VSS1 via the same overlap portion 40, or electrically connected to the fourth sub-power signal line VSS2 via the same overlap portion 40. Figure 12 In the illustrated embodiment, the second electrodes 22 of two adjacent pixels are electrically connected to the same fourth sub-power signal line VSS2 via the same overlap 40. In other embodiments, the second electrodes 22 of two adjacent pixels can be electrically connected to the same third sub-power signal line VSS1 via the same overlap 40.

[0130] In the multiple sub-pixels of the display substrate, multiple pixels arranged at intervals in the second direction Y constitute a row of pixels, and multiple pixels arranged at intervals in the first direction X constitute a column of pixels.

[0131] In one embodiment, the second electrodes of two adjacent rows of sub-pixels can be connected to the same fourth sub-power signal line VSS2 via an overlap portion. Specifically, in two adjacent rows of pixels, the second electrodes of two adjacent pixels in the first direction X contact the same overlap portion 40. With this configuration, the number of fourth sub-power signal lines VSS2 can be reduced by half compared to a scheme where the second electrodes of different rows of pixels are connected to different fourth sub-power signal lines VSS2.

[0132] Furthermore, a plurality of overlapping portions 40 are provided between two adjacent rows of sub-pixels, arranged at intervals in the second direction Y, and the plurality of overlapping portions 40 arranged in the second direction Y are electrically connected through the fourth sub-power signal line VSS2.

[0133] In another embodiment, the second electrodes of two adjacent columns of pixels can be connected to the same third sub-power signal line VSS1 via an overlap portion. Specifically, in two adjacent columns of sub-pixels, the second electrodes of two adjacent sub-pixels in the second direction Y contact the same overlap portion 40. With this arrangement, the number of third sub-power signal lines VSS1 can be reduced by half compared to a scheme where the second electrodes of different columns of pixels are connected to different third sub-power signal lines VSS1.

[0134] In this embodiment, a plurality of overlapping portions 40 are provided between two adjacent columns of pixels, arranged at intervals in the first direction X, and the plurality of overlapping portions 40 arranged in the first direction X are electrically connected through the third sub-power signal line VSS1.

[0135] In one embodiment, such as Figure 16 As shown, at least four adjacent pixels have their second electrodes 22 in contact with the same overlap portion 40, and the four adjacent pixels are arranged in two rows and two columns. With this configuration, the total area of ​​the second electrodes of the display substrate is smaller, the number of overlap portions 40 is fewer, and the number of sub-power signal lines of the second power signal line VSS is fewer, thus helping to improve the light transmittance of the display substrate.

[0136] Furthermore, the orthographic projection of the overlapping portion 40 on the substrate is located between the orthographic projections of the second electrodes 22 of the four adjacent pixels on the substrate.

[0137] Furthermore, such as Figure 16 As shown, at least four adjacent pixels have their second electrodes 22 connected to the third sub-power signal line VSS1 and the fourth sub-power signal line VSS2 via the same overlap portion 40. The four adjacent pixels are arranged in two rows and two columns. A fourth sub-power signal line VSS2 is provided between the two rows of pixels, and a third sub-power signal line VSS1 is provided between the two columns of pixels. The overlap portion 40 is located between the four pixels, so the overlap portion 40 is connected to both the third sub-power signal line VSS1 and the fourth sub-power signal line VSS2.

[0138] Furthermore, at least one of the overlapping portions 40 is electrically connected to the other overlapping portions arranged in the first direction X via the third sub-power signal line VSS1, and is connected to the other overlapping portions arranged in the second direction Y via the fourth sub-power signal line VSS2. This arrangement helps to reduce the number of sub-power signal lines of the second power signal line VSS, thereby further improving the light transmittance of the display substrate.

[0139] In one embodiment, the display substrate includes a plurality of overlapping portions 40, each overlapping portion 40 contacting the second electrode of four adjacent pixels, and the plurality of overlapping portions 40 are arranged in multiple rows and columns. The plurality of overlapping portions 40 arranged at intervals in the first direction X are connected by the third sub-power signal line VSS1, and the plurality of overlapping portions 40 arranged in the second direction Y are connected by the fourth sub-power signal line VSS2.

[0140] In one embodiment, such as Figure 12 and Figure 16 As shown, the display substrate further includes an electrode connection structure 24 connected to the second electrode 22. Each second electrode 22 contacting the same overlapping portion 40 is connected to the same electrode connection structure 24, and the second electrode 22 contacts the overlapping portion 40 through the electrode connection structure 24. The electrode connection structures 24 corresponding to the plurality of second electrodes 22 contacting the same overlapping portion 40 are located between the plurality of second electrodes 22, so as to facilitate the connection of the electrode connection structure 24 to each second electrode 22. The electrode connection structure 24 and the second electrode 22 can be disposed on the same layer.

[0141] In one embodiment, the first power signal line VDD1 includes multiple sub-power signal lines VDD11 and VDD12. Each sub-power signal line extends along the first direction or the second direction, and at least two adjacent pixel circuits are connected to the same sub-power signal line of the first power signal line. This configuration reduces the number of sub-power signal lines of the first power signal line VDD1, thereby improving the light transmittance of the display substrate. Figure 12 In the embodiment shown, the pixel circuits of two adjacent sub-pixels in the second direction Y are connected to the same sub-power signal line VDD11.

[0142] In one embodiment, such as Figures 9 to 16 As shown, at least one of the first sub-power signal lines VDD11 of the first power signal line VDD1 is electrically connected to the pixel circuit through the second power signal line VDD12; at least a portion of the second sub-power signal line VDD12 is disposed in a different layer from the first sub-power signal line VDD11. This arrangement can prevent the driving signal line used to drive the pixel in the source / drain metal layer 340 from short-circuiting with the second sub-power signal line VDD12. Figures 9 to 16 In the embodiment shown, the second sub-power signal line VDD12 includes a first connection signal line VDD13 and a second connection signal line VDD14, with the second connection signal line VDD14 and the first sub-power signal line VDD11 being disposed on different layers.

[0143] Furthermore, the display substrate also includes a driving signal line disposed on the same layer as the first sub-power signal line, the driving signal line being configured to provide a driving signal to the pixel circuit. The orthographic projection of the portion of the second sub-power signal line VDD12 disposed on a different layer from the first sub-power signal line VDD11 on the substrate overlaps with the orthographic projection of the driving signal line on the substrate. This arrangement ensures that the first sub-power signal line VDD11 is electrically connected to the pixel circuit through the second sub-power signal line VDD12, while also preventing a short circuit between the second sub-power signal line VDD12 and the driving signal line. Figures 9 to 16 In the embodiment shown, the drive signal line includes a data line Vd, and the second connection signal line VDD14 of the second sub-power signal line VDD12 is disposed on a different layer from the first sub-power signal line VDD11. The orthographic projection of the second connection signal line VDD14 on the substrate overlaps with the orthographic projection of the data line Vd on the substrate.

[0144] In one embodiment, such as Figures 12 to 16 As shown, the pixel defining layer has an opening 25 located in the non-light-emitting region AA2. By opening the opening 25 in the non-light-emitting region AA2 on the pixel defining layer, the light transmittance of the non-light-emitting region AA2 can be improved. Multiple openings 25 can be formed on the pixel defining layer.

[0145] Furthermore, such as Figures 12 to 16 As shown, the orthographic projection of the opening 25 on the substrate is at least partially located outside the orthographic projection of the second electrode 22 on the substrate, the orthographic projection of the second power signal line VSS on the substrate, and the orthographic projection of the first power signal line VDD1 on the substrate.

[0146] Figure 12 and Figure 16 In the illustrated embodiment, the orthographic projection of the opening 25 on the substrate is located outside the orthographic projection of the second electrode 22 on the substrate. This avoids a small height difference in the film layer below the second electrode 22, preventing the second electrode 22 from breaking due to climbing.

[0147] Figure 12 and Figure 16 In the illustrated embodiment, the orthographic projection of the opening 25 on the substrate is located outside the orthographic projection of the first power signal line VDD1 on the substrate. Specifically, the orthographic projection of the opening 25 on the substrate is located outside the orthographic projection of the first sub-power signal line VDD11 of the first power signal line VDD1 on the substrate, and the orthographic projection of the opening 25 on the substrate partially overlaps with the orthographic projection of the second sub-power signal line VDD12 of the first power signal line VDD1 on the substrate.

[0148] Figure 12 and Figure 16 In the illustrated embodiment, the orthographic projection of the opening 25 on the substrate is located outside the orthographic projection of the second power signal line VSS on the substrate.

[0149] In one embodiment, such as Figure 17 As shown, the orthographic projection of the first power signal line VDD1 on the substrate and the orthographic projection of the second power signal line VSS on the substrate do not overlap. This arrangement avoids overlap between the first power signal line VDD1 and the second power signal line VSS in the film layer stacking direction of the display substrate, as the light transmittance of the overlapping area is relatively low, thus affecting the light transmittance of the display substrate. Furthermore, it avoids excessive heat generation in the overlapping area of ​​the first power signal line VDD1 and the second power signal line VSS during the operation of the display panel, which could easily lead to burns in the overlapping area, thereby helping to extend the service life of the display substrate.

[0150] In one embodiment, such as Figure 17 As shown, the first power signal line VDD1 includes a first sub-power signal line VDD11 extending along a first direction X, a second sub-power signal line VDD12 extending along a second direction Y, and a plurality of first connecting segments 63 extending along the second direction Y; the second power signal line VSS includes a third sub-power signal line VSS1 extending along the first direction X, a fourth sub-power signal line VSS2 extending along the second direction Y, and a plurality of second connecting segments 53 extending along the second direction Y. Each first sub-power signal line VDD11 includes a plurality of first sub-signal segments 61 spaced apart in the first direction X, and each second sub-power signal line VDD12 includes a plurality of second sub-signal segments 62 spaced apart in the second direction Y. Each first sub-signal segment 61 is connected to at least one second sub-signal segment 62, and the orthographic projections of the connected first sub-signal segments 61 and second sub-signal segments 62 on the substrate intersect. Each of the third sub-power signal lines VSS1 includes a plurality of third sub-signal segments 51 spaced apart in the first direction X, and each of the fourth sub-power signal lines VSS2 includes a plurality of fourth sub-signal segments 52 spaced apart in the second direction Y. Each of the third sub-signal segments 51 is connected to at least one of the fourth sub-signal segments 52, and the orthographic projections of the connected third sub-signal segments 51 and fourth sub-signal segments 52 on the substrate intersect.

[0151] Adjacent first sub-signal segments 61 in the second direction Y are connected by the first connecting segment 63, and at least one orthogonal projection of the first connecting segment 63 on the substrate lies between the orthogonal projections of two adjacent third sub-signal segments 51 on the substrate. Adjacent third sub-signal segments 51 in the second direction Y are connected by the second connecting segment 53; at least one orthogonal projection of the second connecting segment 53 on the substrate lies between the orthogonal projections of two adjacent first sub-signal segments 61 on the substrate.

[0152] By using the above configuration, each first sub-signal segment 61 and each second sub-signal segment 62 of the first power signal line VDD1 can be electrically connected, and each third sub-signal segment 51 and each fourth sub-signal segment 52 of the second power signal line VSS can be electrically connected. At the same time, the overlapping area of ​​the orthographic projections of the first power signal line VDD1 and the second power signal line on the substrate can be reduced, thereby improving the light transmittance and lifespan of the display substrate.

[0153] Furthermore, the orthographic projection of each first connection segment 63 on the substrate is located between the orthographic projections of two adjacent third sub-signal segments 51 on the substrate, and the orthographic projection of each second connection segment 53 on the substrate is located between the orthographic projections of two adjacent first sub-signal segments 61 on the substrate. This ensures that the orthographic projections of the first power signal line VDD1 and the second power signal line on the substrate do not overlap.

[0154] In one embodiment, the first connection segment 63 and the first sub-power signal line VDD11 of the first power signal line VDD1 can be arranged on the same layer, and the second connection segment 53 and the second power signal line VSS can be arranged on the same layer. This arrangement helps to simplify the complexity of the display substrate manufacturing process.

[0155] In one embodiment, the display substrate further includes a plurality of driving signal lines configured to provide driving signals to pixel circuits. At least one of the driving signal lines has a wider portion in the light-emitting area than the portion in the non-light-emitting area. By making the width of the driving signal line in the non-light-emitting area smaller, the light transmittance of the non-light-emitting area is improved, thereby increasing the light transmittance of the display substrate. Conversely, by making the width of the driving signal line in the light-emitting area larger, the higher resistance of the driving signal line in the non-light-emitting area can be avoided, which would prevent the heat from rising too quickly in the light-emitting area.

[0156] like Figure 4 and Figure 5As shown, the drive signal lines include a reset control signal line Rst1, a scan signal line Ga1, a light emission control signal line EM1, and a third power supply signal line VDD2. The widths of the portions of the reset control signal line Rst1, reset control signal line Rst2, scan signal line Ga1, light emission control signal line EM1, and third power supply signal line VDD2 located in the light emission area AA1 are all greater than the widths of their portions located in the non-light emission area AA2.

[0157] In one embodiment, the width of at least one scan signal line Ga1 located in the light-emitting region AA1 is greater than the width of its portion located in the non-light-emitting region AA2; the width of the scan signal line Ga1 located in the light-emitting region AA1 ranges from 3.5 μm to 5.5 μm, and the width of the scan signal line Ga1 located in the non-light-emitting region AA2 ranges from 2 μm to 3.5 μm. By setting the width of the scan signal line Ga1 located in the non-light-emitting region AA2 to 2 μm to 3.5 μm, it is possible to avoid both a small width in the scan signal line Ga1 located in the non-light-emitting region AA2 resulting in high resistance, and a large width in the scan signal line Ga1 located in the non-light-emitting region AA2 resulting in poor transmittance of the non-light-emitting region. In some embodiments, the width of the portion of the scanning signal line Ga1 located in the light-emitting region AA1 can be 3.5μm, 3.8μm, 4.0μm, 4.5μm, 5.0μm, 5.5μm, etc., and the width of the portion of the scanning signal line Ga1 located in the non-light-emitting region AA2 can be 2μm, 2.3μm, 2.5μm, 3.0μm, 3.2μm, 3.5μm, etc.

[0158] In one embodiment, such as Figure 18 As shown, the display substrate further includes a bezel area CC located on at least one side of the display area AA. The display substrate also includes an auxiliary trace 70 located in the bezel area CC, and the auxiliary trace 70 is electrically connected to the second electrode 22. The auxiliary trace 70 can be electrically connected to the second power signal line VSS. The auxiliary trace can reduce the resistance of the second electrode 22, thereby improving the IR drop problem of the second electrode 22.

[0159] The auxiliary trace 70 includes a first conductive film layer 71 and a second conductive film layer 72 located on the side of the first conductive film layer 71 facing away from the substrate. The edge of the orthographic projection of the first conductive film layer 71 on the substrate near the display area AA is located inside the edge of the orthographic projection of the second conductive film layer 72 on the substrate near the display area AA. This arrangement ensures the overlap effect between the second conductive film layer 72 and the first conductive film layer 71.

[0160] Furthermore, the edge of the first conductive film layer's orthographic projection on the substrate away from the display area AA is located inside the edge of the second conductive film layer 72's orthographic projection on the substrate away from the display area AA, so as to more effectively ensure the overlap effect between the second conductive film layer 72 and the first conductive film layer 71.

[0161] In some embodiments, the first conductive film layer 71 is disposed in the same layer as the first electrode 21, and the second conductive film layer 72 is disposed in the same layer as the second electrode 22. The auxiliary trace 70 may further include a third conductive film layer located between the first conductive layer and the substrate, and the third conductive film layer may be located in the source / drain metal layer.

[0162] In one embodiment, the display substrate may further include an encapsulation layer located above the pixels. The encapsulation layer may be a thin-film encapsulation layer, comprising alternating organic and inorganic layers, with the inorganic layer being the topmost layer.

[0163] This application also provides a display panel, which includes the display substrate described in any of the above embodiments.

[0164] The display panel may also include a glass cover plate located on the side of the display substrate away from the substrate.

[0165] This application also provides a display device, which includes the display panel described above. The display device may further include a housing, in which the display panel may be embedded.

[0166] The display device in this embodiment can be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, laptop computer, digital photo frame, or vehicle display device.

[0167] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0168] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0169] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A display substrate, characterized in that, The display substrate includes a display area, at least a portion of which is a transparent display area; the display substrate includes a substrate and a plurality of pixels located on the substrate and in the transparent display area; each pixel includes a plurality of sub-pixels, each sub-pixel including an organic light-emitting element and a pixel circuit driving the organic light-emitting element; the organic light-emitting element includes a first electrode, a second electrode, and an organic light-emitting material located between the first electrode and the second electrode; the first electrode of each sub-pixel is electrically connected to the pixel circuit; the number of first electrodes is greater than the number of second electrodes; The display substrate is further provided with a first power signal line and a second power signal line. The pixel circuit is connected to the first power signal line, and the second electrode is connected to the second power signal line. The first power signal line includes a first sub-power signal line extending along a first direction and a second sub-power signal line extending along a second direction. The second power signal line includes a third sub-power signal line extending along the first direction and a fourth sub-power signal line extending along the second direction. The first direction and the second direction intersect. The first power signal line further includes a plurality of first connecting segments extending along the second direction; the second power signal line further includes a plurality of second connecting segments extending along the second direction; each first sub-power signal line includes a plurality of first sub-signal segments spaced apart in the first direction, each second sub-power signal line includes a plurality of second sub-signal segments spaced apart in the second direction, and each first sub-signal segment is connected to at least one second sub-signal segment; each third sub-power signal line includes a plurality of third sub-signal segments spaced apart in the first direction, each fourth sub-power signal line includes a plurality of fourth sub-signal segments spaced apart in the second direction, and each third sub-signal segment is connected to at least one fourth sub-signal segment; adjacent first sub-signal segments in the second direction are connected through the first connecting segments, and adjacent third sub-signal segments in the second direction are connected through the second connecting segments; At least one of the first connection segments has its orthographic projection on the substrate located between the orthographic projections of two adjacent third sub-signal segments on the substrate; At least one of the second connection segments has its orthographic projection on the substrate located between the orthographic projections of two adjacent first sub-signal segments on the substrate.

2. The display substrate according to claim 1, characterized in that, The display substrate further includes an overlap portion electrically connected to the second power signal line, and at least two adjacent pixels have their second electrodes in contact with the same overlap portion.

3. The display substrate according to claim 2, characterized in that, When the second power signal line includes a third sub-power signal line extending along the first direction and a fourth sub-power signal line extending along the second direction, at least two adjacent pixels have their second electrodes electrically connected to the third sub-power signal line through the same overlap portion, or electrically connected to the fourth sub-power signal line through the same overlap portion.

4. The display substrate according to claim 3, characterized in that, The plurality of overlapping portions arranged in the first direction are electrically connected by the third sub-power signal line, and / or the plurality of overlapping portions arranged in the second direction are electrically connected by the fourth sub-power signal line.

5. The display substrate according to claim 1, characterized in that, The display substrate also includes an overlap portion electrically connected to the second power signal line, and at least four adjacent pixels have their second electrodes in contact with the same overlap portion, with the four adjacent pixels arranged in two rows and two columns.

6. The display substrate according to claim 5, characterized in that, When the second power signal line includes a third sub-power signal line extending along the first direction and a fourth sub-power signal line extending along the second direction, at least four adjacent pixels have their second electrodes connected to the third sub-power signal line and the fourth sub-power signal line through the same overlap portion.

7. The display substrate according to claim 6, characterized in that, The display substrate includes a plurality of overlapping portions, at least one of the overlapping portions being electrically connected to other overlapping portions arranged in the first direction via the third sub-power signal line, and electrically connected to other overlapping portions arranged in the second direction via the fourth sub-power signal line.

8. The display substrate according to any one of claims 2 to 7, characterized in that, The display substrate further includes an electrode connection structure connected to the second electrode. Each of the second electrodes that contacts the same overlapping portion is connected to the same electrode connection structure, and the second electrode contacts the overlapping portion through the electrode connection structure.

9. The display substrate according to claim 1, characterized in that, When the first power signal line includes a first sub-power signal line extending along a first direction and a second sub-power signal line extending along a second direction, at least two adjacent pixel circuits are connected to the same first sub-power signal line of the first power signal line, or to the same second sub-power signal line.

10. The display substrate according to claim 1, characterized in that, When the first power signal line includes a first sub-power signal line extending along a first direction and a second sub-power signal line extending along a second direction, at least one of the first sub-power signal lines is electrically connected to the pixel circuit through the second sub-power signal line. At least a portion of the second sub-power signal line is disposed on a different layer than the first sub-power signal line.

11. The display substrate according to claim 10, characterized in that, The display substrate further includes a driving signal line disposed on the same layer as the first sub-power signal line, the driving signal line being configured to provide a driving signal for the pixel circuit; the orthographic projection of the portion of the second sub-power signal line disposed on a different layer from the first sub-power signal line on the substrate overlaps with the orthographic projection of the driving signal line on the substrate.

12. The display substrate according to claim 1, characterized in that, The orthographic projection of the first power signal line on the substrate does not overlap with the orthographic projection of the second power signal line on the substrate.

13. The display substrate according to claim 1, characterized in that, The transparent display area includes a light-emitting area and a non-light-emitting area; the pixels are disposed in the light-emitting area; The display substrate is also provided with a plurality of driving signal lines; at least one of the driving signal lines has a width in the portion located in the light-emitting area that is greater than the width in the portion located in the non-light-emitting area.

14. The display substrate according to claim 13, characterized in that, The drive signal line includes a scan signal line configured to provide a scan signal to the pixel; At least one of the scanning signal lines has a width greater than the width of its portion located in the light-emitting area than the width of its portion located in the non-light-emitting area; the width of the portion of the scanning signal line located in the light-emitting area ranges from 3.5 μm to 5.5 μm, and the width of the portion of the scanning signal line located in the non-light-emitting area ranges from 2 μm to 3.5 μm.

15. The display substrate according to claim 1, characterized in that, The pixel circuit includes a driving transistor, and the display substrate further includes an active semiconductor layer, the active semiconductor layer including the channel of the driving transistor of each sub-pixel; In at least one of the pixels, the channel of the driving transistor of at least one sub-pixel includes a first segment, a second segment, a third segment, a fourth segment, and a fifth segment connected in sequence, the first segment, the third segment, and the fifth segment extending along the second direction, and the second segment and the fourth segment extending along the first direction; the channel of the driving transistor of at least one sub-pixel includes a sixth segment, a seventh segment, and an eighth segment connected in sequence, the sixth segment and the eighth segment extending along the second direction, and the seventh segment extending along the first direction.

16. The display substrate according to claim 1, characterized in that, The display substrate further includes a shielding line and a reset power signal line, wherein the reset power signal line is configured to provide a reset power signal to the sub-pixel; the shielding line is electrically connected to the reset power signal line.

17. The display substrate according to claim 1, characterized in that, The transparent display area includes a light-emitting area and a non-light-emitting area, and the pixel is located in the light-emitting area; the display substrate further includes a pixel defining layer, and the pixel defining layer has an opening located in the non-light-emitting area; The orthographic projection of the opening on the substrate is at least partially located outside the orthographic projections of the second electrode, the second power signal line, and the first power signal line on the substrate.

18. The display substrate according to claim 1, characterized in that, The display substrate further includes a border area located on at least one side of the display area, and the display substrate further includes an auxiliary trace located in the border area. The auxiliary trace is electrically connected to the second electrode. The auxiliary trace includes a first conductive film layer and a second conductive film layer located on the side of the first conductive film layer away from the substrate. The orthographic projection of the first conductive film layer on the substrate near the edge of the display area is located inside the orthographic projection of the second conductive film layer on the substrate near the edge of the display area.

19. A display panel, characterized in that, The display panel includes the display substrate as described in any one of claims 1 to 18.

20. A display device, characterized in that, The display device includes the display panel as described in claim 19.

Images