Voltage adjustment circuit

Abstract

A voltage adjustment circuit includes a low dropout regulator for providing a driving voltage to drive a load circuit and receiving a first detection voltage from a first feedback terminal, and a reference voltage generating circuit coupled to the low dropout regulator for receiving a second detection voltage from a second feedback terminal, wherein a voltage difference between the first feedback terminal and the second feedback terminal is clamped by the first detection voltage and the second detection voltage.

Description

TECHNICAL FIELD

[0001] The present invention relates to a voltage regulation circuit, and more particularly, to a voltage regulation circuit for maintaining an operating voltage range of a load by keeping sufficient voltage margin. BACKGROUND

[0002] As the data transmission of mobile devices grows, the demand for power consumption also increases. In addition, high-capacity batteries cannot be applied to high-level processes of light, thin, and small mobile devices. However, as the process evolves, the core voltage of the digital logic circuit of the IC chip decreases. When the operating range of the digital logic circuit is affected by the path impedance of the IC chip to generate voltage drop, the core voltage of the operating range becomes smaller, causing the logic of the circuit to be abnormal.

[0003] Figure 1 A reference circuit 102 and a low dropout regulator 104 are included in the existing voltage regulation circuit 10 to provide power to the load circuit LC. In Figure 1 , the existing voltage regulation circuit 10 and the load circuit LC have a power path impedance R APR_PWR and a ground path impedance R APR_GND . Ideally, the current I APR of the digital logic circuit DLC flows through the power path impedance R APR_PWR and the ground path impedance R APR_GND , and the current I APR is equal to the current I PWR and the current I GND , (assuming that the resistance R APR_PWR and the resistance R APR_GND are small enough, the power path impedance R APR_PWR and the ground path impedance R APR_GND can be ignored).

[0004] However, in reality, the power path impedance R APR_PWR and the ground path impedance R APR_GND between the existing voltage regulation circuit 10 and the load circuit LC cannot be ignored. Therefore, the voltage difference across the digital logic circuit DLC will be affected by the voltage drop of the power path impedance R APR_PWR and the ground path impedance R APR_GND , and the voltage drop is proportional to its path impedance, causing the voltage operating range of the load circuit LC to become smaller.

[0005] Therefore, the prior art needs to be improved. SUMMARY

[0006] In view of this, embodiments of the present invention provide a voltage regulation circuit to compensate for the voltage rise and voltage drop components caused by the ground path impedance and power supply path impedance between the voltage regulation circuit and the load circuit, so as to maintain sufficient margin to drive the load.

[0007] This invention discloses a voltage regulation circuit, comprising a low-dropout regulator for providing a drive voltage to drive a load circuit and receiving a first detection voltage from a first feedback terminal; and a reference voltage generation circuit coupled to the low-dropout regulator for receiving a second detection voltage from a second feedback terminal; wherein a voltage difference between the first feedback terminal and the second feedback terminal is clamped by the first detection voltage and the second detection voltage. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of an existing voltage regulation circuit that includes a reference circuit and a low-dropout regulator for use in a load circuit.

[0009] Figure 2 This is a schematic diagram of a voltage adjustment circuit according to an embodiment of the present invention.

[0010] Figure 3 , Figure 5 , Figure 7 , Figure 9 This is a schematic diagram of a voltage adjustment circuit according to an embodiment of the present invention.

[0011] Figure 4 , Figure 6 , Figure 8 , Figure 10 Embodiments of the present invention Figure 3 , Figure 5 , Figure 7 as well as Figure 9 A waveform diagram of a voltage regulation circuit and a digital logic circuit.

[0012] Figure 11 , Figure 12 This is a schematic diagram of a voltage adjustment circuit according to an embodiment of the present invention.

[0013] The reference numerals in the attached figures are explained as follows:

[0014] 10. Voltage Regulation Circuit

[0015] 102 Reference Circuit

[0016] 104 Low Dropout Voltage Regulator

[0017] 20 Voltage Regulation Circuit

[0018] 202 Low Dropout Voltage Regulator

[0019] 204 Reference Voltage Generation Circuit

[0020] 30 Voltage Regulation Circuit

[0021] 302 Low Dropout Voltage Regulator

[0022] 304 Reference Voltage Generation Circuit

[0023] 1100 Voltage Regulation Circuit

[0024] 1102 Low Dropout Voltage Regulator

[0025] 1104 Reference Voltage Generation Circuit

[0026] 1200 Voltage Regulation Circuit

[0027] 1202 Low Dropout Voltage Regulator

[0028] 1204 Reference Voltage Generation Circuit

[0029] CM current mirror

[0030] DLC digital logic circuit

[0031] I APR Current

[0032] I DET_PWR Current

[0033] I DET_GND Current

[0034] I GND Current

[0035] I PWR Current

[0036] LC load circuit

[0037] MUX Selector

[0038] Resistors R1, R2, R3, R4

[0039] EM First Resistor Module

[0040] RM_1 First Resistor Module

[0041] RM_2 Second Resistor Module

[0042] R APR_PWR Power path impedance

[0043] R APR_GND Grounding path impedance

[0044] R DET_PWR Power feedback path impedance

[0045] R DET_GND Grounding detection path impedance

[0046] Switches S1, S2, S3, S4

[0047] T0, T1 interval

[0048] Time

[0049] V APR Voltage

[0050] VDD APR First feedback terminal

[0051] VDD DET First detection voltage

[0052] VDD DIFF_MAX voltage difference

[0053] VDD REG Drive voltage

[0054] V FB Power detection terminal

[0055] V N Input voltage

[0056] VSS APR Second feedback end

[0057] VSS DET Second detection voltage

[0058] VSS REG Second voltage

[0059] V REF First input voltage

[0060] V REF_VDD Reference voltage

[0061] V SEN Grounding detection terminal

[0062] ΔV1 pressure rise

[0063] ΔV2 pressure drop Detailed Implementation

[0064] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a voltage adjustment circuit 20 according to an embodiment of the present invention. The voltage adjustment circuit 20 includes a low-dropout regulator 202 and a reference voltage generation circuit 204, wherein the voltage adjustment circuit 20 is used to provide a stable output to a load circuit LC. The low-dropout regulator 202 is used to provide a drive voltage VDD.REG To pass through a power path impedance R APR_PWR The load circuit LC is driven and receives VDD from a first feedback terminal. APR The first detection voltage VDD DET The reference voltage generation circuit 204 is used to receive a second feedback terminal VSS from the load circuit LC. APR The second detection voltage VSS DET The reference voltage generation circuit 204 is coupled to the low-dropout regulator 202, wherein the first feedback terminal VDD APR With the second feedback terminal VSS APR The voltage difference between them is caused by the driving voltage VDD REG The clamped, and the driving voltage VDD REG It is based on the first detection voltage VDD DET With the second detection voltage VSS DET The power detection terminal V of the low dropout regulator 202 is determined. FB Receive the first detection voltage VDD DET A grounded detection terminal V of the reference voltage generation circuit 204 SEN Receive the second detection voltage VSS DET .

[0065] For details, please refer to Figure 3 as well as Figure 4 . Figure 3 This is a schematic diagram of a voltage adjustment circuit 30 according to an embodiment of the present invention. Figure 4 Embodiments of the present invention Figure 3 The waveform diagrams of the voltage adjustment circuit 30 and the load circuit LC are shown.

[0066] The voltage regulation circuit 30 includes a low-dropout regulator 302 and a reference voltage generation circuit 304. The voltage regulation circuit 30 provides a stable output to a load circuit LC. The low-dropout regulator 302 determines a drive voltage VDD. REG To pass through a power path impedance R APR_PWR Drives a load circuit LC and receives VDD from a first feedback terminal. APR The first detection voltage VDD DET Drive voltage VDD REG It is based on a power detection terminal V FB A received voltage and a reference voltage V REF_VDD The determined voltage is the first detection voltage VDD. DET The reference voltage generation circuit 304 includes a first resistor module RM_1, a second resistor module RM_2, a current mirror CM, and a selector MUX. The current mirror CM is used to generate a reference voltage based on a first input voltage V.REF The current from the first resistor module RM_1 is mirrored to the second resistor module RM_2, where both the first resistor module RM_1 and the second resistor module RM_2 can be series resistors of megaohms each, and their current is in microamperes. The selector MUX is used to select the resistor based on the current received from the second feedback terminal VSS. APR The voltage generates a reference voltage V. REF_VDD Low differential voltage regulator 302.

[0067] The voltage regulation circuit 30 further includes a plurality of switches S1-S4, which are respectively turned on to operate the voltage regulation circuit 30 in the following configuration:

[0068] a) Switches S1 and S2 are turned on to open or close the first feedback terminal VDD of a digital logic circuit (DLC) of the load circuit LC. APR A feedback function;

[0069] When switch S1 is turned on and switch S2 is turned off, the first feedback terminal VDD... APR Voltage feedback is activated; when switch S1 is closed and switch S2 is open, the drive voltage VDD is activated. REG It is fed back to the low-dropout regulator 302.

[0070] b) Switches S3 and S4 are turned on to open or close the second feedback terminal VSS of the digital logic circuit DLC of the load circuit LC. APR Detection function;

[0071] When switch S3 is turned on and switch S4 is turned off, the second feedback terminal VSS... APR The detection function is activated; when switch S3 is closed and switch S4 is open, the reference voltage generation circuit 304 detects a second voltage VSS of the low-dropout regulator 302. REG .

[0072] like Figure 3 As shown in the diagram, due to the power path impedance R between the low-dropout regulator 302 and the load circuit LC, APR_PWR With a grounding path impedance R APR_GND This cannot be ignored, thus generating a voltage drop in the digital logic circuit (DLC). In one embodiment, the current I... APR It is approximately several hundred milliamperes (mA), while the power supply feedback path impedance R DET_PWR With a ground detection path impedance R DET_GND The current is approximately tens of microamperes (μA). This is relative to the power path impedance R. APR_PWR and grounding path impedance R APR_GNDThe load, the power supply feedback path impedance R DET_PWR With ground detection path impedance R DET_GND The current load can usually be ignored.

[0073] In this scenario, a power feedback path is activated via switch S1, and a ground detection path is activated via switch S3 to compensate for the voltage drop of the digital logic circuit (DLC). The reference voltage generation circuit 304 is used to generate the voltage based on the first input voltage V. REF and a single-gain buffer to generate a first input voltage V REF In the first resistor module RM_1, the current mirror CM is based on the first input voltage V. REF The current of the first resistor module RM_1 is mirrored to the second resistor module RM_2, and then a reference voltage V is established according to the selector MUX. REF_VDD .

[0074] Furthermore, since switch S3 is turned on and switch S4 is turned off, the ground detection terminal V of the second resistor module RM_2 is... SEN Connect to the second feedback terminal VSS APR Assume I GND ≈I APR Grounding path impedance R APR_GND A pressure rise ΔV1 = I is generated GND *R APR_GND ≈I APR *R APR_GND In this case, the voltage rise ΔV1 can be detected at the grounding detection terminal V. SEN The reference voltage V is sensed and compensated by the reference voltage generation circuit 304. REF_VDD The voltage rise ΔV1 is provided to the low-dropout regulator 302 to compensate for the raised ground voltage of the digital logic circuit (DLC).

[0075] In addition, since switch S1 is turned on and switch S2 is turned off, the power detection terminal V... FB Connect to the first feedback terminal VDD APR Ensure the first feedback terminal VDD of the digital logic circuit DLC APR Limited by reference voltage V REF_VDD And it will not be affected by the digital logic circuit DLC and the power path impedance R. APR_PWR The change is made to compensate for a pressure drop ΔV2 = I. PWR *R APR_PWR ≈I APR *R APR_PWR (I PWR ≈I APR ), where the voltage drop ΔV2 is related to the current I APR The current flows through the power path impedance R APR_PWR What it produces.

[0076] By detecting the first feedback terminal VDD of the digital logic circuit (DLC) APR And the second feedback terminal VSS APR Through the power path impedance R APR_PWR and grounding path impedance R APR_GND The voltage drop ΔV2 and voltage rise ΔV1 can be compensated to maintain the first feedback terminal VDD. APR With the second feedback terminal VSS APR A voltage difference VDD between them DIFF_MAX In this way, digital logic circuits (DLCs) can operate with sufficient voltage margin under both light and heavy loads.

[0077] like Figure 4 As shown, in a range T0, when the digital logic circuit (DLC) is operated under no-load conditions, the current I... APR Approximately 0mA, and the first feedback terminal VDD APR With the second feedback terminal VSS APR The voltage difference VDD between them DIFF_MAX It is clamped without interference from power path impedance and ground path impedance.

[0078] In interval T1, when the digital logic circuit (DLC) starts drawing current from the voltage regulation circuit 30, the ground path impedance R APR_GND The pressure rise is ΔV1 = I GND *R APR_GND ≈I APR *R APR_GND (I GND ≈I APR Grounding detection terminal V SEN The voltage rise ΔV1 is sensed and used to compensate the reference voltage V of the reference voltage generation circuit 304. REF_VDD Next, the voltage rise ΔV1 is supplied to the low-dropout regulator 302 to compensate for the voltage rise ΔV1 of the digital logic circuit DLC. Simultaneously, the first feedback terminal VDD... APR The voltage is fed back to the power detection terminal V. FB This allows the low-dropout regulator 302 to maintain the first feedback terminal VDD. APR With the second feedback terminal VSS APR The voltage difference VDD between them DIFF_MAX To compensate for a pressure drop ΔV2=I PWR *R APR_PWR ≈I APR *R APR_PWR (I PWR ≈I APR ), where the voltage drop ΔV2 is related to the current I APR The current flows through the power path impedance R APR_PWRThis is generated at that time. In this way, the digital logic circuit (DLC) can operate with sufficient margin under both light and heavy loads.

[0079] In another embodiment, when the power path impedance R APR_PWR The ground path impedance R between the low-dropout regulator 302 and the compensation reference voltage generation circuit 304 can be ignored. APR_GND If it cannot be ignored, then only the grounding path impedance R needs to be considered. APR_GND For pressure rise ΔV1≈I APR *R APR_GND Compensation, and power path impedance R APR_PWR In this example, it can also be ignored.

[0080] To compensate for the grounding path impedance R APR_GND The voltage drop at the second feedback terminal VSS APR The detection function is activated, switch S3 is turned on and switch S4 is turned off, such as... Figure 5 and Figure 6 As shown.

[0081] exist Figure 5 In this configuration, switch S1 is closed, while switch S2 is open. That is, the first feedback terminal VDD... APR The feedback function was not activated. Furthermore, switch S3 was turned on while switch S4 was turned off to activate the feedback from the second feedback terminal VSS. APR The second detection voltage VSS DET The detection function. The reference voltage generation circuit 304 is used to detect the first input voltage V. REF and a single-gain buffer to generate the first input voltage V REF In the first resistor module RM_1, the current mirror CM is based on the first input voltage V. REF The current of the first resistor module RM_1 is mirrored to the second resistor module RM_2, and then a reference voltage V is established according to the selector MUX. REF_VDD Because switch S3 is on and switch S4 is off, the ground detection terminal V of the second resistor module RM_2... SEN Connect to the second feedback terminal VSS APR To detect the second detection voltage VSS DET Pressure rise ΔV1 = I GND *R APR_GND ≈I APR *R APR_GND Due to the grounding path impedance R APR_GND This occurs. In this case, the ground detection terminal V... SEN The sensed voltage rise ΔV1 is compensated by the reference voltage V of the reference voltage generation circuit 304. REF_VDDThe voltage rise ΔV1 is provided to the low-dropout regulator 302 to compensate for the raised ground voltage of the digital logic circuit (DLC).

[0082] Since switch S1 is closed and switch S2 is open, the power detection terminal V... FB Connected to drive voltage VDD REG To follow the reference voltage V REF_VDD The change. Furthermore, due to the power path impedance R... APR_PWR It can be ignored, that is, ΔV2=I PWR *R APR_PWR ≈I APR *R APR_PWR ≈0, the drive voltage VDD of the low dropout regulator 302 REG Accessible to the first feedback terminal VDD APR To ensure the first feedback terminal VDD of the digital logic circuit DLC APR Not affected by current I APR Influence.

[0083] Therefore, by detecting the second feedback terminal VSS of the digital logic circuit (DLC) APR , for current I APR The impedance R of the grounding path flows through APR_GND The resulting voltage rise ΔV1 can be used for compensation to ensure the first feedback terminal VDD is stable when the digital logic circuit (DLC) is under light or heavy load. APR With the second feedback terminal VSS APR The clamping voltage between them is fixed.

[0084] Figure 6 Embodiments of the present invention Figure 5 The waveform diagrams for the voltage regulation circuit 30 and the digital logic circuit DLC are shown. In the interval T0, when the digital logic circuit DLC operates under no-load conditions, the current I... APR Approximately 0mA, while the first feedback terminal VDD of the digital logic circuit DLC. APR With the second feedback terminal VSS APR The voltage difference between them can be clamped without power path impedance and ground path impedance, allowing the digital logic circuit (DLC) to operate on the voltage difference VDD. DIFF_MAX .

[0085] exist Figure 6 In interval T1, when the digital logic circuit DLC starts to draw current I from the voltage adjustment circuit 30... APR At that time, the pressure rise ΔV1≈I APR *R APR_GND For current I APR The impedance R of the grounding path flows through APR_GND This is generated at the time. Grounding detection terminal V SENThe sensed voltage rise ΔV1, and the reference voltage V of the reference voltage generation circuit 304. REF_VDD The voltage rise ΔV1 is increased and supplied to the low-dropout regulator 302. Drive voltage VDD REG Feedback is sent to a power detection terminal V FB This makes the driving voltage VDD REG Followable reference voltage V REF_VDD The changes.

[0086] Due to the power path impedance R APR_PWR It can be ignored (i.e., ΔV2≈I) APR *R APR_PWR ≈0), current I APR The current flows through the power path impedance R APR_PWR The resulting voltage drop can be ignored, i.e., the voltage drop at the first feedback terminal VDD. APR A voltage close to the drive voltage VDD REG In this way, by detecting the second feedback terminal VSS from the digital logic circuit (DLC), APR The second detection voltage VSS DET When the current I APR The impedance R of the grounding path flows through APR_GND The resulting voltage rise ΔV1 can be used for compensation to ensure the first feedback terminal VDD is stable when the digital logic circuit (DLC) is under light or heavy load. APR With the second feedback terminal VSS APR The clamping voltage between them is fixed.

[0087] In another embodiment, when the power path impedance R APR_PWR The grounding path impedance R cannot be ignored. APR_GND When it can be ignored, only the power path impedance R is considered. APR_PWR Used to compensate for voltage drop, grounding path impedance R APR_GND This can be ignored in this example.

[0088] To compensate for the power path impedance R APR_PWR The voltage drop is due to the first feedback terminal VDD. APR Feedback to reference voltage V REF_VDD The feedback function is activated, therefore switch S1 is turned on and switch S2 is turned off; switch S3 is turned off and switch S4 is turned on, such as... Figure 7 and Figure 8 As shown.

[0089] The reference voltage generation circuit 304 is used to generate voltage based on the first input voltage V. REF and a single-gain buffer to generate the first input voltage V REF In the first resistor module RM_1, the current mirror CM is based on the first input voltage V.REF The current of the first resistor module RM_1 is mirrored to the second resistor module RM_2, and then a reference voltage V is established according to the selector MUX. REF_VDD Since switch S3 is closed and switch S4 is open, the ground detection terminal V of the second resistor module RM_2 is... SEN Connected to the second voltage VSS REG And the grounding path impedance R APR_GND It can be ignored.

[0090] In addition, since switch S1 is turned on and switch S2 is turned off, the power detection terminal V of the low-dropout regulator 302... FB Connect to the first feedback terminal VDD APR Ensure the first feedback terminal VDD of the digital logic circuit DLC APR It can be locked to the reference voltage V REF_VDD Regardless of the digital logic circuit (DLC) and the power path impedance R APR_PWR The change is made to compensate for a pressure drop ΔV2 = I. PWR *R APR_PWR ≈I APR *R APR_PWR (I PWR ≈I APR ), where the voltage drop ΔV2 is related to the current I APR The current flows through the power path impedance R APR_PWR What it produces.

[0091] like Figure 8 As shown, within the interval T0, when the digital logic circuit (DLC) operates under no-load conditions, the current I... APR Approximately 0mA, and the first feedback terminal VDD APR With the second feedback terminal VSS APR The voltage difference VDD between them DIFF_MAX It is clamped without interference from power path impedance and ground path impedance.

[0092] Within interval T1, when the digital logic circuit DLC starts to draw current I from the voltage adjustment circuit 30... APR At that time, due to the grounding path impedance R APR_GND The current I can be ignored. APR The impedance R of the grounding path flows through APR_GND The resulting pressure rise ΔV1 can be ignored.

[0093] Because the ground detection terminal V of the second resistor module RM_2 SEN Detecting the second voltage VSS REG Almost equivalent to the second feedback terminal VSS APR voltage, grounding path impedance R APR_GND It can be ignored, and the reference voltage VREF_VDD The pressure rise ΔV1 can also be ignored.

[0094] The low dropout regulator 302 can detect the power supply detection terminal V. FB The first detection voltage VDD DET To adjust the first feedback terminal VDD APR This compensates for the current I. APR The current flows through the power path impedance R APR_PWR The resulting voltage drop ΔV2 is used to maintain the first feedback terminal VDD. APR With the second feedback terminal VSS APR A voltage difference VDD between them DIFF_MAX .

[0095] In another embodiment, when the power path impedance R APR_PWR and grounding path impedance R APR_GND When both can be ignored, the driving voltage VDD REG Feedback is sent to the power detection terminal V FB And the second voltage VSS REG The voltage difference VDD is detected to ensure the clamping voltage of the digital logic circuit (DLC). DIFF_MAX It can be maintained.

[0096] like Figure 9 As shown, switch S1 is closed and switch S2 is open, and the power detection terminal V... FB Connected to drive voltage VDD REG To follow the reference voltage V REF_VDD The change is as follows: Switch S3 is closed, while switch S4 is turned on to close the second feedback terminal VSS. APR Its detection function.

[0097] The current mirror CM is based on the first input voltage V REF The current of the first resistor module RM_1 is mirrored to the second resistor module RM_2, and then a reference voltage V is established according to the selector MUX. REF_VDD Since switch S3 is closed and switch S4 is open, the ground detection terminal V of the second resistor module RM_2 is... SEN Connected to the second voltage VSS REG The grounding path impedance R APR_GND It can be ignored when the current I APR The impedance R of the grounding path flows through APR_GND The pressure rise is ΔV1 = I GND *R APR_GND ≈I APR *R APR_GND ≈0, where I GND ≈I APR .

[0098] Since switch S1 is closed and switch S2 is open, the power detection terminal V... FB Receive drive voltage VDD REG To follow the reference voltage V REF_VDD The change in [variable]. In addition, the power path impedance R [variable]. APR_PWR It can be ignored, that is, ΔV2=I PWR *R APR_PWR ≈I APR *R APR_PWR ≈0, where I PWR ≈I APR The driving voltage VDD of the low dropout regulator 302 REG Approaching the first feedback terminal VDD APR The voltage is adjusted to ensure the first feedback terminal VDD of the digital logic circuit DLC. APR It will not be affected by current I APR The impact.

[0099] like Figure 10 As shown, in interval T0, when the digital logic circuit (DLC) operates under no-load conditions, the current I... APR Approximately 0mA, first feedback terminal VDD APR With the second feedback terminal VSS APR The voltage difference VDD between them DIFF_MAX It is clamped without interference from power path impedance and ground path impedance.

[0100] In interval T1, when the digital logic circuit DLC starts to draw current I from the voltage adjustment circuit 30... APR At that time, due to the grounding path impedance R APR_GND Negligible current I APR The impedance R of the grounding path flows through APR_GND The resulting pressure rise ΔV1 can be ignored, and the second feedback terminal VSS APR With the second voltage VSS REG change.

[0101] Because the ground detection terminal V of the second resistor module RM_2 SEN Second voltage VSS detected REG Approaching the second feedback end VSS APR The voltage, then the reference voltage V REF_VDD It is output to the low-dropout regulator 302. Drive voltage VDD REG Feedback is sent to the power detection terminal V FB Ensure drive voltage VDD REG With reference voltage V REF_VDD change.

[0102] In addition, due to the power path impedance R APR_PWR Negligible current IAPR The current flows through the power path impedance R APR_PWR The resulting voltage drop ΔV2 can be ignored, and the first feedback terminal VDD APR The voltage can vary with the driving voltage VDD REG change.

[0103] When the power path impedance R APR_PWR and grounding path impedance R APR_GND When all can be ignored, the driving voltage VDD is detected. REG and the second voltage VSS REG When the digital logic circuit (DLC) is under light or heavy load, ensure that the first feedback terminal VDD is within safe limits. APR With the second feedback terminal VSS APR The voltage difference VDD between them DIFF_MAX Controlled.

[0104] Please refer to Figure 11 , Figure 11 This is a schematic diagram of a voltage adjustment circuit 1100 according to an embodiment of the present invention. The voltage adjustment circuit 1100 includes a low-dropout regulator 1102 and a reference voltage generation circuit 1104. Because... Figure 11 for Figure 3 One embodiment, therefore using the same component symbols. Figure 3 The difference lies in that the reference voltage generation circuit 1104 includes a first resistor module RM and a selector MUX. The selector MUX is used to generate a reference voltage V. REF_VDD Low differential voltage regulator 1102.

[0105] When the impedance of a power path is R APR_PWR and a grounding path impedance R APR_GND When the voltage drop is not negligible, a voltage drop occurs in a digital logic circuit (DLC). This is to compensate for the power path impedance R. APR_PWR and grounding path impedance R APR_GND The resulting voltage drop, first feedback terminal VDD APR Feedback function and second feedback terminal VSS APR The detection function was activated.

[0106] like Figure 11 As shown, when switch S1 is turned on and switch S2 is turned off, the reference voltage V... REF_VDD Feedback to the first feedback terminal VDD APR The feedback function is activated; when switch S3 is turned on and switch S4 is turned off, the second feedback terminal VSS... APR The detection function was activated.

[0107] The voltage regulation circuit 1100 is used to determine the reference voltage V based on the selection of the selector MUX.REF_VDD Because switch S3 is on and switch S4 is off, a ground terminal V... REF_VSS Connect to the second feedback terminal VSS APR To receive a second detection voltage VSS DET One pressure rise ΔV1=I GND *R APR_GND ≈I APR *R APR_GND (where I) GND ≈I APR ) at a current I APR The impedance R of the grounding path flows through APR_GND The voltage rise ΔV1 is generated and supplied to the low-dropout regulator 1102 to compensate for the raised ground voltage of the digital logic circuit (DLC).

[0108] The output voltage VDD of the low dropout regulator 1102 REG For [V] REF_VDD *(R2 / (R1+R2))+V REF_VSS *(R1 / (R1+R2))]*(1+R4 / R3)=V REF_VDD +ΔV1, where R1=R2=R3=R4=R、V REF_VSS =ΔV1, which can be used as the grounding path impedance R APR_GND Compensation for the pressure drop.

[0109] Furthermore, since switch S1 is turned on and switch S2 is turned off, the power detection terminal V... FB Connect to the first feedback terminal VDD APR To receive VDD from the first feedback terminal APR The first detection voltage VDD DET One pressure drop ΔV2=I PWR *R APR_PWR ≈I APR *R APR_PWR (wherein I PWR ≈I APR ) at current I APR The current flows through the power path impedance R APR_PWR produce.

[0110] By detecting VDD from the first feedback terminal APR The first detection voltage VDD DET And VSS from the second feedback terminal APR The second detection voltage VSS DET , for current I APR The current flows through the power path impedance R APR_PWR and grounding path impedance R APR_GNDThe resulting voltage rise ΔV1 and voltage drop ΔV2 can be compensated to ensure that the digital logic circuit (DLC) can operate with sufficient margin whether it is under light or heavy load.

[0111] For waveforms of the voltage regulation circuit 1100 and the digital logic circuit (DLC), please refer to... Figure 4 In the middle, the power path impedance R APR_PWR With grounding path impedance R APR_GND Examples of embodiments that cannot be ignored. Furthermore, other embodiments of the voltage regulation circuit 1100 and corresponding waveform diagrams can be found in [reference needed]. Figure 3 Examples of implementations.

[0112] Please refer to Figure 12 , Figure 12 This is a schematic diagram of a voltage adjustment circuit 1200 according to an embodiment of the present invention. The voltage adjustment circuit 1200 includes a low-dropout regulator 1202 and a reference voltage generation circuit 1204. Because... Figure 12 for Figure 3 One embodiment, therefore using the same component symbols. Figure 3 The difference lies in that the reference voltage generation circuit 1204 includes a first resistor module RM, wherein the first resistor module RM includes a resistor R1 and a resistor R2 connected in series. The reference voltage generation circuit 1204 is used to generate a reference voltage V. REF and a grounding detection terminal V SEN This generates an input voltage V. N Used in low dropout regulator 1202.

[0113] When the impedance of a power path is R APR_PWR and grounding path impedance R APR_GND When the voltage drop is not negligible, a voltage drop occurs in a digital logic circuit (DLC). This is to compensate for the power path impedance R. APR_PWR and grounding path impedance R APR_GND The resulting voltage drop, first feedback terminal VDD APR Feedback function and second feedback terminal VSS APR The detection function was activated.

[0114] like Figure 12 As shown, when switch S1 is turned on and switch S2 is turned off, the reference voltage V... REF_VDD Feedback to the first feedback terminal VDD APR The feedback function is activated; when switch S3 is turned on and switch S4 is turned off, the second feedback terminal VSS... APR The detection function was activated.

[0115] The voltage regulation circuit 1200 is used to generate a reference voltage V based on a single-gain buffer. REF_VDDReference voltage V REF_VDD One end of resistor R1 is connected to the first resistor module RM, and the other end of resistor R1 is connected to a ground terminal V through resistor R2. REF_VSS Input voltage V N It is generated by the voltage division of resistors R1 and R2, and then transmitted to the low dropout regulator 1202.

[0116] When switch S3 is turned on and switch S4 is turned off, the ground terminal V... REF_VSS Connect to the second feedback terminal VSS APR To receive a second detection voltage VSS DET When a current I APR The impedance R of the grounding path flows through APR_GND At that time, a pressure rise ΔV1 = I is generated. GND *R APR_GND ≈I APR *R APR_GND (I GND ≈I APR Second feedback terminal VSS APR A ground terminal V connected to the first resistor module RM REF_VSS Therefore, the input voltage V N =V REF_VDD *(R2 / (R1+R2))+V REF_VSS *(R1 / (R1+R2))] is provided to the low-dropout regulator 1202 to compensate for the boosted voltage. An effective output voltage of the low-dropout regulator 1202 is VDD. REG =[V REF_VDD *(R2 / (R1+R2))+V REF_VSS *(R1 / (R1+R2))]*(1+R4 / R3)=V REF_VD +ΔV1, where R1=R2=R3=R4=R、V REF_VSS =ΔV1.

[0117] Because switch S1 is turned on and switch S2 is turned off, the power detection terminal V of the low-dropout regulator 1202... FB Connect to the first feedback terminal VDD APR To receive VDD from the first feedback terminal APR The first detection voltage VDD DET Therefore, a voltage drop ΔV2 is equal to the current I. APR The current flows through the power path impedance R APR_PWR It is generated at that time.

[0118] By detecting VDD from the first feedback terminal APR The first detection voltage VDD DET and VSS from the second feedback end APRThe second detection voltage VSS DET When the current I APR The current flows through the power path impedance R APR_PWR and grounding path impedance R APR_GND The resulting voltage rise ΔV1 and voltage drop ΔV2 can be compensated to ensure that the digital logic circuit (DLC) can operate with sufficient margin whether it is under light or heavy load.

[0119] For waveforms of the voltage regulation circuit 1200 and the digital logic circuit (DLC), please refer to... Figure 4 In the middle, the power path impedance R APR_PWR With grounding path impedance R APR_GND Examples of implementations that cannot be ignored. Furthermore, other embodiments of the voltage regulation circuit 1200 and corresponding waveform diagrams can be found in [reference needed]. Figure 3 Examples of implementations.

[0120] In summary, the embodiments of the present invention provide a voltage regulation circuit to compensate for a voltage rise and a voltage drop caused by the path impedance between the voltage regulation circuit and a load circuit, and to maintain sufficient margin when operating the load.

[0121] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A voltage regulation circuit, characterized in that, Include: A low-dropout regulator is used to provide a drive voltage to drive a load circuit and to receive a first detection voltage from a first feedback terminal; and A reference voltage generation circuit, coupled to the low dropout regulator, is used to receive a second detection voltage from a second feedback terminal; Wherein, the voltage difference between the first feedback terminal and the second feedback terminal is clamped by the first detection voltage and the second detection voltage; The voltage at one power detection terminal is determined by the power path impedance between the low dropout regulator and the first feedback terminal. One power feedback path is activated to compensate for a voltage drop in the power path impedance between the low-dropout regulator and the first feedback terminal. The voltage at one ground detection terminal is determined by the ground path impedance between the reference voltage generation circuit and the second feedback terminal. In this process, a ground detection path is activated to compensate for a voltage rise in the ground path impedance between the reference voltage generating circuit and the second feedback terminal.

2. The voltage regulation circuit as described in claim 1, characterized in that, The reference voltage generation circuit includes: A first resistor module and a second resistor module; A current mirror, coupled to the first resistor module and the second resistor module, is used to mirror a current from the first resistor module to the second resistor module according to a first input voltage. as well as A selector, coupled to the second resistor module, is used to generate a reference voltage to the low-dropout regulator based on the second detected voltage.

3. The voltage adjustment circuit as described in claim 2, characterized in that, The low-dropout regulator is used to determine the drive voltage to drive the load circuit based on a power supply detection terminal and the reference voltage.

4. The voltage adjustment circuit of claim 1, wherein the reference voltage generating circuit comprises: a first resistor module; and A selector, coupled to the first resistor module, is used to generate a reference voltage to the low-dropout regulator.

5. The voltage regulation circuit as described in claim 4, characterized in that, The low-dropout regulator is used to determine the drive voltage to drive the load circuit, and receives the first detected voltage from the first feedback terminal according to a power detection terminal and a second input voltage, the second input voltage being determined according to an output of the reference voltage and a ground detection terminal of the low-dropout regulator.

6. The voltage regulation circuit as described in claim 5, characterized in that, The second input voltage is determined based on an output of the reference voltage and a voltage at the ground detection terminal.

7. The voltage regulation circuit as described in claim 5, characterized in that, A power feedback path between the low-dropout regulator and the first feedback terminal is connected to compensate for a voltage drop in the impedance of a power path between the low-dropout regulator and the first feedback terminal.

8. The voltage regulation circuit as described in claim 5, characterized in that, The ground detection terminal is determined based on the ground path impedance between the reference voltage generating circuit and the second feedback terminal.

9. The voltage adjustment circuit as described in claim 8, characterized in that, A ground detection path is activated to compensate for a voltage rise in the ground path impedance between the reference voltage generating circuit and the second feedback terminal.

10. The voltage regulation circuit as described in claim 1, characterized in that, The reference voltage generation circuit includes: A first resistor module, coupled to the second feedback terminal, is used to generate an input voltage to the low dropout regulator based on the reference voltage and a voltage at a ground detection terminal.

11. The voltage regulation circuit as described in claim 10, characterized in that, The low-dropout regulator is used to determine the drive voltage to drive the load circuit, and receives the first detected voltage from the first feedback terminal based on a power detection terminal and the input voltage.

12. The voltage regulation circuit as described in claim 10, characterized in that, The low-dropout regulator is connected to a power feedback path with the first feedback terminal to compensate for a voltage drop in the power path impedance between the low-dropout regulator and the first feedback terminal.

13. The voltage regulation circuit as described in claim 10, characterized in that, The ground detection terminal is determined based on the ground path impedance between the reference voltage generating circuit and the second feedback terminal.

14. The voltage regulation circuit as described in claim 13, characterized in that, A ground detection path is activated to compensate for a voltage rise in the ground path impedance between the reference voltage generating circuit and the second feedback terminal.

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