A radiation-hardened linear regulator circuit against single event effects

Abstract

The present invention discloses a radiation-hardened linear regulator circuit for single-particle effect resistance, belonging to the field of analog integrated circuits. The radiation-hardened linear regulator circuit for single-particle effect resistance includes a main loop and a secondary loop. The main loop is used to improve single-particle effects; the secondary loop is arranged in parallel with the main loop, skipping slow devices to directly control the main loop, and promptly correcting errors caused by single-particle transients. The present invention utilizes a dual-loop control structure to improve loop response speed and promptly correct errors caused by single-particle transients. It overcomes the differences in electrical performance of the three error amplifiers caused by device mismatch effects in traditional triple-mode redundant error amplifiers, which deteriorates the loop adjustment capability. The technology of adding diodes and capacitors at important nodes is used to improve the single-particle transient resistance performance, significantly reducing the required circuit area and power consumption, thereby reducing circuit costs.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and in particular to a single event effect radiation-hardened linear regulator circuit. Background Art

[0002] A linear voltage regulator generally consists of a reference voltage, an error amplifier, and a power device. It linearly adjusts the series power tube device connected between the input power supply and the modulated output voltage to ensure that the output voltage is a preset proportional value of the reference voltage.

[0003] Single event transients (SETs) are caused by high-energy particles bombarding devices in space, which trigger parasitic currents in devices and induce transient voltage excursions (voltage spikes) at nodes in integrated circuits. These events, which primarily occur in analog integrated circuits, can cause significant voltage excursions at key nodes, leading to circuit malfunction or even failure.

[0004] Current linear regulator circuits such as Figure 1 As shown, the circuit includes error amplifiers EA1, EA2, and EA3, a voting circuit MAJ, a PMOS power transistor MP, and resistors R1 and R2. This circuit uses a reference voltage VREF connected to the negative inputs of three identical error amplifiers. The outputs of the three error amplifiers are connected to the voting circuit MAJ, and the output of the voting circuit MAJ is connected to the gate of the power transistor MP. The drain of the power transistor MP is connected to feedback resistor R2. One end of resistor R2 is connected to resistor R1, and the other end is connected to the positive inputs of the three error amplifiers, ultimately forming negative feedback. The circuit uses the negative feedback loop formed by the error amplifiers to set the output voltage to:

[0005]

[0006] This circuit's radiation-hardening technology is achieved through triple-module redundancy: the error amplifier is triple-copied, resulting in three identical error amplifiers: EA1, EA2, and EA3. The outputs of these three error amplifiers are compared by a voting circuit to generate the signal that controls the power devices. If one error amplifier fails due to a single-event effect, the voting circuit only outputs the output of the majority error amplifier, so the signal controlling the power devices remains normal.

[0007] However, this circuit uses triple-module redundancy technology, which requires replicating three identical error amplifiers. This significantly increases chip area and power consumption, limiting the circuit's application scope. Furthermore, the error amplifiers are analog circuits, and device mismatches can lead to differences in their electrical performance, affecting the linear regulator's loop regulation. Furthermore, adding a voting circuit to integrate the outputs of the three error amplifiers increases design complexity. Summary of the Invention

[0008] The present invention aims to provide a single event effect radiation hardened linear regulator circuit to achieve good loop regulation performance and radiation resistance with small area and power consumption.

[0009] To solve the above technical problems, the present invention provides a single event effect radiation hardened linear regulator circuit, comprising:

[0010] Main loop, used to improve single event effects;

[0011] The secondary loop is arranged in parallel with the main loop, skipping the slow device to directly control the main loop, and promptly correcting the error caused by the single-particle transient.

[0012] In one embodiment, the single event effect radiation hardened linear regulator circuit includes PMOS transistors MP1 to MP5, NMOS transistors MN1 to MN6, a diode D1, resistors R1 to R4, capacitors C1 to C5, an error amplifier EA, and an equivalent current source I1;

[0013] The gates of the PMOS transistors MP1, MP2, and MP3 are all connected to the VB signal, and their sources are all connected to the power supply. The drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1. The drain of the PMOS transistor MP2 is connected to both its own gate and the drain of the NMOS transistor MN5. The drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN6.

[0014] The gate of the NMOS transistor MN1 is connected to both its own drain and the gate of the NMOS transistor MN2. The gates of the NMOS transistor MN5 and the NMOS transistor MN6 are both connected to a reference voltage VREF. The source of the NMOS transistor MN5 is connected to the drain of the NMOS transistor MN3. The gate of the NMOS transistor MN3 is connected to the gate of the NMOS transistor MN4. The source of the NMOS transistor MN6 is connected to the drain of the NMOS transistor MN2. A first terminal of the capacitor C1 is connected to both the gate of the NMOS transistor MN1 and the gate of the NMOS transistor MN2. The sources of the NMOS transistor MN1, the NMOS transistor MN2, the NMOS transistor MN3, and the second terminal of the capacitor C1 are all grounded.

[0015] The anode of diode D1 is connected to both the drain of PMOS transistor MP3 and the drain of NMOS transistor MN6, and the cathode of diode D1 is connected to a power supply. A first terminal of capacitor C2 is connected to the power supply, a second terminal is connected to the first terminal of resistor R3, and the second terminal of resistor R3 is connected to the anode of diode D1. A source of PMOS transistor MP4 is connected to the power supply, a gate is connected to both the second terminal of resistor R3 and the anode of diode D1, and a drain is connected to both the power input terminal of error amplifier EA, the source of PMOS transistor MP5, and the output terminal VOUT. The positive terminal of error amplifier EA is connected to reference voltage VREF, the negative terminal is connected to both the first terminal of resistor R1 and the first terminal of capacitor C5, and the output terminal is connected to both the gate of PMOS transistor MP5, the first terminal of resistor R4, and the first terminal of capacitor C4. The drain of PMOS transistor MP5 is connected to both the drain and gate of NMOS transistor MN4, and the source of NMOS transistor MN4 is grounded.

[0016] The positive electrode of the equivalent current source I1 is connected to the power supply, the negative electrode is connected to both the first end of the resistor R2 and the output terminal VOUT, the second end of the resistor R2 is connected to both the first end of the resistor R1 and the first end of the capacitor C5, the second end of the resistor R4 is connected to the first end of the capacitor C3; the second end of the capacitor C3, the second end of the capacitor C4, the second end of the resistor R1, and the second end of the capacitor C5 are all grounded.

[0017] In one embodiment, the main loop is composed of an error amplifier EA, PMOS transistors MP2, MP3, MP4, MP5, resistors R1, R2, capacitor C5, and NMOS transistors MN3, MN4, MN5, and MN6; wherein the PMOS transistor MP4 is a power transistor of the linear regulator circuit, and the resistors R2 and R1 are feedback resistors.

[0018] In one embodiment, the resistor R3 and the capacitor C2 form a filter circuit to suppress the voltage drop caused by a single event effect negative pulse.

[0019] In one embodiment, the capacitor C5 is a filter capacitor that improves single event effects while reducing loop adjustment speed.

[0020] In one embodiment, the resistor R4 and the capacitors C3 and C4 form a compensation network to provide compensation for the linear regulator; the PMOS transistor MP1 and the NMOS transistor MN1 are used to generate a current mirror bias; and the capacitor C1 filters the gate of the NMOS transistor MN1 to suppress single event effects.

[0021] The present invention provides a single event effect radiation hardened linear regulator circuit having the following features:

[0022] Beneficial effects:

[0023] (1) The dual-loop control structure is used to improve the loop response speed and promptly correct the errors caused by single-particle transients. This overcomes the problem of the traditional triple-mode redundant error amplifier, which has electrical performance differences between the three error amplifiers due to device mismatch effects and deteriorates the loop adjustment capability.

[0024] (2) The technology of adding diodes and capacitors at important nodes is used to improve the single-particle transient performance, which greatly reduces the required circuit area and power consumption and reduces the circuit cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The figure is a schematic diagram of the principle of the radiation-resistant linear regulator circuit in the prior art.

[0026] Figure 2 The diagram is a circuit diagram of a single event effect radiation hardened linear regulator proposed by the present invention. DETAILED DESCRIPTION

[0027] The following describes in further detail a single-event effect radiation-hardened linear regulator circuit according to the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.

[0028] The present invention provides a single event effect radiation hardened linear regulator circuit, the structural principle of which is as follows: Figure 2 As shown, the following devices are included: PMOS transistors MP1-MP5, NMOS transistors MN1-MN6, a diode D1, resistors R1-R4, capacitors C1-C5, an error amplifier EA and an equivalent current source I1.

[0029] The gates of the PMOS transistors MP1, MP2, and MP3 are all connected to the VB signal, and their sources are all connected to the power supply. The drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1. The drain of the PMOS transistor MP2 is connected to both its own gate and the drain of the NMOS transistor MN5. The drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN6.

[0030] The gate of NMOS transistor MN1 is connected to both its own drain and the gate of NMOS transistor MN2. The gates of NMOS transistor MN5 and MN6 are both connected to reference voltage VREF. The source of NMOS transistor MN5 is connected to the drain of NMOS transistor MN3. The gate of NMOS transistor MN3 is connected to the gate of NMOS transistor MN4. The source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN2. A first end of capacitor C1 is connected to both the gate of NMOS transistor MN1 and the gate of NMOS transistor MN2. The sources of NMOS transistor MN1, MN2, and MN3, as well as the second end of capacitor C1, are all grounded.

[0031] The anode of diode D1 is connected to both the drain of PMOS transistor MP3 and the drain of NMOS transistor MN6, and the cathode of diode D1 is connected to a power supply. A first terminal of capacitor C2 is connected to the power supply, and a second terminal is connected to the first terminal of resistor R3. The second terminal of resistor R3 is connected to the anode of diode D1. A source of PMOS transistor MP4 is connected to the power supply, a gate is connected to both the second terminal of resistor R3 and the anode of diode D1, and a drain is connected to both the power input terminal of error amplifier EA, the source of PMOS transistor MP5, and the output terminal VOUT. The positive terminal of error amplifier EA is connected to reference voltage VREF, the negative terminal is connected to both the first terminal of resistor R1 and the first terminal of capacitor C5, and the output terminal is connected to both the gate of PMOS transistor MP5, the first terminal of resistor R4, and the first terminal of capacitor C4. The drain of PMOS transistor MP5 is connected to both the drain and gate of NMOS transistor MN4, and the source of NMOS transistor MN4 is grounded.

[0032] The positive electrode of the equivalent current source I1 is connected to the power supply, the negative electrode is connected to both the first end of the resistor R2 and the output terminal VOUT, the second end of the resistor R2 is connected to both the first end of the resistor R1 and the first end of the capacitor C5, the second end of the resistor R4 is connected to the first end of the capacitor C3; the second end of the capacitor C3, the second end of the capacitor C4, the second end of the resistor R1, and the second end of the capacitor C5 are all grounded.

[0033] The linear voltage regulator circuit of the present invention utilizes dual negative feedback loop control. The main loop consists of an error amplifier EA, PMOS transistors MP2, MP3, MP4, MP5, resistors R1, R2, capacitor C5, and NMOS transistors MN3, MN4, MN5, and MN6. PMOS transistor MP4 is the power transistor of the linear voltage regulator circuit. Resistors R2 and R1 serve as feedback resistors, setting the output voltage to:

[0034]

[0035] The negative terminal of the error amplifier EA is the feedback node of the main loop and is sensitive to single-event effects. Capacitor C5 is used to suppress the impact of single-event effects. The gate of power transistor MP4 is also a single-event sensitive node. Diode D1 is connected in series between the gate of power transistor MP4 and the power supply to clamp the positive pulse generated by the single-event effect. Resistor R3 and capacitor C2 form a filter circuit to suppress the voltage drop caused by the negative pulse of the single-event effect.

[0036] The addition of filter capacitor C5 to the negative terminal of the error amplifier EA reduces loop adjustment speed while improving single-event effects, which is detrimental to the linear regulator's single-event immunity. Therefore, the present invention connects a fast secondary loop in parallel to the main loop. This secondary loop is composed of PMOS transistors MP2, MP3, MP4, MP5, and NMOS transistors MN3, MN4, MN5, and MN6. This secondary loop bypasses slower components such as the error amplifier EA, resistors R2 and R1, and capacitor C5, directly controlling the main loop. This improves the linear regulator's response speed to transients such as single-event effects and load steps, thereby enhancing the performance of the linear regulator.

[0037] Resistor R4 and capacitors C3 and C4 form a compensation network, providing compensation for the linear regulator and ensuring stability. Equivalent current source I1 provides the supply current for the error amplifier EA. PMOS transistor MP1 and NMOS transistor MN1 generate the current mirror bias. Capacitor C1 filters the gate of NMOS transistor MN1 to suppress single-event effects.

[0038] The linear regulator of this invention utilizes a parallel dual-loop control circuit to improve circuit response speed, suppress transient voltage and current spikes induced by single-event effects, and enhance the circuit's radiation resistance. Diodes and capacitors are also added at key nodes for additional radiation hardening. Compared to existing technologies, this eliminates the need for triple-module redundancy, reduces circuit power consumption, and offers a more economical and compact overall layout, making it easier to design and port, and potentially enabling a wider range of applications.

[0039] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A single event effect radiation hardened linear regulator circuit, characterized in that: The single event effect radiation hardened linear regulator circuit includes PMOS transistors MP1-MP5, NMOS transistors MN1-MN6, a diode D1, resistors R1-R4, capacitors C1-C5, an error amplifier EA and an equivalent current source I1; The gates of the PMOS transistors MP1, MP2, and MP3 are all connected to the VB signal, and their sources are all connected to the power supply. The drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1. The drain of the PMOS transistor MP2 is connected to both its own gate and the drain of the NMOS transistor MN5. The drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN6. The gate of the NMOS transistor MN1 is connected to both its own drain and the gate of the NMOS transistor MN2. The gates of the NMOS transistor MN5 and the NMOS transistor MN6 are both connected to a reference voltage VREF. The source of the NMOS transistor MN5 is connected to the drain of the NMOS transistor MN3. The gate of the NMOS transistor MN3 is connected to the gate of the NMOS transistor MN4. The source of the NMOS transistor MN6 is connected to the drain of the NMOS transistor MN2. A first terminal of the capacitor C1 is connected to both the gate of the NMOS transistor MN1 and the gate of the NMOS transistor MN2. The sources of the NMOS transistor MN1, the NMOS transistor MN2, the NMOS transistor MN3, and the second terminal of the capacitor C1 are all grounded. The anode of diode D1 is connected to both the drain of PMOS transistor MP3 and the drain of NMOS transistor MN6, and the cathode of diode D1 is connected to a power supply. A first terminal of capacitor C2 is connected to the power supply, a second terminal is connected to the first terminal of resistor R3, and the second terminal of resistor R3 is connected to the anode of diode D1. A source of PMOS transistor MP4 is connected to the power supply, a gate is connected to both the second terminal of resistor R3 and the anode of diode D1, and a drain is connected to both the power input of error amplifier EA, the source of PMOS transistor MP5, and the output terminal VOUT of the linear regulator circuit. The positive terminal of error amplifier EA is connected to reference voltage VREF, the negative terminal is connected to both the first terminal of resistor R1 and the first terminal of capacitor C5, and the output terminal is connected to both the gate of PMOS transistor MP5, the first terminal of resistor R4, and the first terminal of capacitor C4. The drain of PMOS transistor MP5 is connected to both the drain and gate of NMOS transistor MN4, and the source of NMOS transistor MN4 is grounded. The positive electrode of the equivalent current source I1 is connected to the power supply, and the negative electrode is connected to both the first end of the resistor R2 and the output terminal VOUT of the linear regulator circuit. The second end of the resistor R2 is connected to both the first end of the resistor R1 and the first end of the capacitor C5. The second end of the resistor R4 is connected to the first end of the capacitor C3. The second end of the capacitor C3, the second end of the capacitor C4, the second end of the resistor R1, and the second end of the capacitor C5 are all grounded.

2. The single event effect radiation hardened linear regulator circuit according to claim 1, wherein: The main loop is composed of an error amplifier EA, PMOS transistors MP2, MP3, MP4, MP5, resistors R1, R2, capacitor C5, NMOS transistors MN3, MN4, MN5, MN6; wherein the PMOS transistor MP4 is a power tube of the linear regulator circuit, and the resistors R2 and R1 are feedback resistors.

3. The single event effect radiation hardened linear regulator circuit according to claim 1, wherein: The resistor R3 and the capacitor C2 form a filter circuit to suppress the voltage drop caused by the single event effect negative pulse.

4. The single event effect radiation hardened linear regulator circuit according to claim 1, wherein: The capacitor C5 is a filter capacitor that improves the single event effect while reducing the loop adjustment speed.

5. The single event effect radiation hardened linear regulator circuit according to claim 1, wherein: The resistor R4 and the capacitors C3 and C4 form a compensation network to provide compensation for the linear regulator; the PMOS transistor MP1 and the NMOS transistor MN1 are used to generate a current mirror bias; the capacitor C1 filters the gate of the NMOS transistor MN1 to suppress single event effects.

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