Method for generating quantum state preparation circuit, quantum state preparation method, and quantum device

Abstract

The present application relates to a method for generating a quantum state preparation circuit, a quantum state preparation method, and a quantum device. The method for generating a quantum state preparation circuit includes: configuring an input register for the quantum state preparation circuit based on the circuit preparation parameters of the quantum state preparation circuit, and determining the number of auxiliary qubits; configuring a copy register and a target register for the quantum state preparation circuit according to the number of auxiliary qubits; constructing a circuit through the input register, the copy register, and the target register according to the qubit copying method, to obtain a diagonal unitary matrix quantum circuit, where the qubit copying method is obtained based on grid constraint conditions; combining the diagonal unitary matrix quantum circuit and single-qubit quantum gates to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit; generating a quantum state preparation circuit based on at least one uniform control gate circuit. By using this method, a quantum state preparation circuit with effectively compressed circuit depth can be obtained, achieving a reduction in the influence of decoherence.

Description

Technical Field

[0001] The present application relates to the technical field of quantum computing, and in particular, to a method for generating a quantum state preparation circuit, a method for preparing a quantum state, and a quantum device. Background Art

[0002] With the development of quantum computing technology, quantum state preparation technology has emerged. Quantum state preparation refers to loading data that meets given conditions into a quantum state to obtain quantum state data.

[0003] In traditional technologies, without any restrictive conditions, a quantum state preparation circuit is designed based on the number of input qubits to obtain a quantum state preparation circuit, and then quantum state preparation is performed based on the quantum state preparation circuit.

[0004] However, the physical implementation of existing quantum devices has decoherence. That is to say, as time increases, the coherence of the quantum system will gradually disappear and degenerate into a classical system. The inventors believe that for the case where the connectivity of qubits in a quantum device is restricted by a grid structure, the depth of the quantum state preparation circuit obtained by using traditional technologies is large, which will lead to the appearance of decoherence phenomena and affect quantum state preparation. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a method, apparatus, computer device, computer-readable storage medium, and computer program product for generating a quantum state preparation circuit that can effectively compress the circuit depth to reduce the influence of decoherence, and to provide a method, apparatus, computer device, computer-readable storage medium, and computer program product for preparing a quantum state that can reduce the influence of decoherence, as well as a quantum device that can compress the depth of the quantum state preparation circuit to avoid decoherence phenomena.

[0006] In a first aspect, the present application provides a method for generating a quantum state preparation circuit. The method includes:

[0007] Based on the circuit preparation parameters of the quantum state preparation circuit, configure an input register for the quantum state preparation circuit and determine the number of auxiliary qubits;

[0008] According to the number of auxiliary qubits, configure a copy register and a target register for the quantum state preparation circuit;

[0009] According to the qubit copying method, construct a circuit through the input register, the copy register, and the target register to obtain a diagonal unitary matrix quantum circuit, where the qubit copying method is obtained based on grid restriction conditions;

[0010] Combine the diagonal unitary matrix quantum circuit and single-qubit quantum gates to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit;

[0011] Generate a quantum state preparation circuit based on at least one uniform control gate circuit.

[0012] In a second aspect, the present application also provides a quantum state preparation circuit generation device. The device includes:

[0013] A first configuration module, configured to configure an input register for the quantum state preparation circuit based on the circuit preparation parameters of the quantum state preparation circuit, and determine the number of auxiliary qubits;

[0014] A second configuration module, configured to configure a copy register and a target register for the quantum state preparation circuit according to the number of auxiliary qubits;

[0015] A circuit construction module, configured to perform circuit construction through the input register, the copy register, and the target register according to the qubit copying method to obtain a diagonal unitary matrix quantum circuit, where the qubit copying method is obtained based on grid constraint conditions;

[0016] A circuit combination module, configured to combine the diagonal unitary matrix quantum circuit and single-qubit quantum gates to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit;

[0017] A processing module, configured to generate a quantum state preparation circuit based on at least one uniform control gate circuit.

[0018] In a third aspect, the present application also provides a computer device. The computer device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0019] Configure an input register for the quantum state preparation circuit based on the circuit preparation parameters of the quantum state preparation circuit, and determine the number of auxiliary qubits;

[0020] Configure a copy register and a target register for the quantum state preparation circuit according to the number of auxiliary qubits;

[0021] Perform circuit construction through the input register, the copy register, and the target register according to the qubit copying method to obtain a diagonal unitary matrix quantum circuit, where the qubit copying method is obtained based on grid constraint conditions;

[0022] Combine the diagonal unitary matrix quantum circuit and single-qubit quantum gates to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit;

[0023] Generate a quantum state preparation circuit based on at least one uniform control gate circuit.

[0024] Fourth aspect, the present application further provides a computer-readable storage medium. On the computer-readable storage medium, there is a computer program stored, and when the computer program is executed by a processor, the following steps are implemented:

[0025] Based on the circuit preparation parameters of the quantum state preparation circuit, configure an input register for the quantum state preparation circuit and determine the number of auxiliary qubits;

[0026] According to the number of auxiliary qubits, configure a copy register and a target register for the quantum state preparation circuit;

[0027] According to the qubit copying method, perform circuit construction through the input register, the copy register, and the target register to obtain a diagonal unitary matrix quantum circuit, where the qubit copying method is obtained based on grid constraint conditions;

[0028] Combine the diagonal unitary matrix quantum circuit and single-qubit quantum gates to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit;

[0029] Generate a quantum state preparation circuit based on at least one uniform control gate circuit.

[0030] Fifth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented: ]>

[0031] Based on the circuit preparation parameters of the quantum state preparation circuit, configure an input register for the quantum state preparation circuit and determine the number of auxiliary qubits;

[0032] According to the number of auxiliary qubits, configure a copy register and a target register for the quantum state preparation circuit;

[0033] According to the qubit copying method, perform circuit construction through the input register, the copy register, and the target register to obtain a diagonal unitary matrix quantum circuit, where the qubit copying method is obtained based on grid constraint conditions;

[0034] Combine the diagonal unitary matrix quantum circuit and single-qubit quantum gates to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit;

[0035] Generate a quantum state preparation circuit based on at least one uniform control gate circuit.

[0036] Sixth aspect, the present application provides a quantum state preparation method. The method includes:

[0037] Perform quantum state preparation on the circuit initial state data based on the quantum state preparation circuit to obtain quantum state data, where the quantum state preparation circuit is implemented by the above-mentioned quantum state preparation circuit generation method.

[0038] In a seventh aspect, the present application provides a quantum state preparation device. The device includes:

[0039] A preparation module configured to perform quantum state preparation on circuit initial state data based on a quantum state preparation circuit to obtain quantum state data, where the quantum state preparation circuit is implemented by the above-mentioned quantum state preparation circuit generation method.

[0040] In an eighth aspect, the present application further provides a quantum computer. The quantum computer includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0041] Performing quantum state preparation on circuit initial state data based on a quantum state preparation circuit to obtain quantum state data, where the quantum state preparation circuit is implemented by the above-mentioned quantum state preparation circuit generation method.

[0042] In a ninth aspect, the present application further provides a computer-readable storage medium. On the computer-readable storage medium, a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0043] Performing quantum state preparation on circuit initial state data based on a quantum state preparation circuit to obtain quantum state data, where the quantum state preparation circuit is implemented by the above-mentioned quantum state preparation circuit generation method.

[0044] In a tenth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0045] Performing quantum state preparation on circuit initial state data based on a quantum state preparation circuit to obtain quantum state data, where the quantum state preparation circuit is implemented by the above-mentioned quantum state preparation circuit generation method.

[0046] In an eleventh aspect, the present application further provides a quantum device. The quantum device implements a quantum state preparation circuit by the above-mentioned quantum state preparation circuit generation method.

[0047] The above quantum state preparation circuit generation method, device, computer device, storage medium, and computer program product can configure an input register for the quantum state preparation circuit and determine the number of auxiliary qubits based on circuit preparation parameters. Thus, the copy register and the target register can be configured according to the number of auxiliary qubits. According to the qubit copying method, a circuit is constructed through the input register, copy register, and target register. Considering the grid constraint conditions, a diagonal unitary matrix quantum circuit can be constructed using combinatorial techniques. Furthermore, a uniform control gate circuit can be obtained by combining the diagonal unitary matrix quantum circuit and single-qubit quantum gates. Based on the uniform control gate circuit, a quantum state preparation circuit is generated. Throughout the process, the use of auxiliary qubits and combinatorial techniques realizes the parallelization of the quantum state preparation circuit under grid constraint conditions, and a quantum state preparation circuit with effectively compressed circuit depth can be obtained, reducing the impact of decoherence.

[0048] The above quantum state preparation method, device, quantum computer, storage medium, and computer program product perform quantum state preparation on the initial circuit state data using a quantum state preparation circuit with effectively compressed circuit depth to obtain quantum state data, which can reduce the impact of decoherence.

[0049] The above quantum device can obtain a quantum state preparation circuit with effectively compressed circuit depth, reducing the impact of decoherence. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is an application environment diagram of the quantum state preparation circuit generation method in an embodiment;

[0051] Figure 2 It is a schematic diagram of the grid constraint limitation of a quantum circuit in an embodiment;

[0052] Figure 3 It is a schematic flowchart of the quantum state preparation circuit generation method in an embodiment;

[0053] Figure 4 It is a schematic diagram of the \(n1\times n2\)-grid limitation of an \(n1n2\)-qubit circuit in an embodiment;

[0054] Figure 5 It is a schematic diagram of the path limitation in an embodiment;

[0055] Figure 6 It is a schematic diagram of a quantum circuit of any \(n\)-qubit in an embodiment;

[0056] Figure 7 It is a schematic diagram of a copy circuit under column limitation in an embodiment;

[0057] Figure 8Schematic diagram of controlling a NOT gate circuit in an embodiment;

[0058] Figure 9 Schematic diagram of the steps of quantum state preparation circuit design in an embodiment;

[0059] Figure 10 Structural block diagram of a quantum state preparation circuit generation device in an embodiment;

[0060] Figure 11 Internal structure diagram of a computer device in an embodiment. Detailed implementation manners

[0061] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0062] The quantum state preparation circuit generation method provided by the embodiments of the present application can be applied to the application environment as shown in Figure 1 including a classical computer 102 and a quantum computer 104. Among them, the quantum computer 104 can communicate with the classical computer 102 through a network. A quantum computer is a physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, store, and process quantum information. A classical computer is relative to a quantum computer. A classical computer can also be called an ordinary computer and is a currently developed and mature computing device. The qubits in a quantum computer may not be fully connected, and the connectivity of the qubits in a quantum computer is restricted, that is, only some qubits can be connected. A quantum computer can only perform quantum operations between qubit pairs with a connectivity relationship or on a single qubit, that is, the qubits on which a two-bit quantum gate acts are restricted by a graph. For example, as shown in Figure 2 in a quantum computer, a quantum circuit is often restricted by a grid constraint, and only two qubits connected by an adjustable coupler can act on a two-bit quantum gate. The inventor believes that traditional quantum state preparation circuit design does not consider that in an actual quantum computer, the connectivity of qubits is restricted by the grid structure, and the depth of the designed quantum state preparation circuit is large, which will cause the decoherence phenomenon to occur and affect quantum state preparation. Therefore, auxiliary qubits and combination techniques can be used to realize the parallelization of the quantum state preparation circuit under the grid constraint conditions, obtain a quantum state preparation circuit with effectively compressed circuit depth, and reduce the influence of decoherence. Combining the application scenario shown in Figure 1 the quantum state preparation circuit generation method can be executed by the classical computer in Figure 1 .

[0063] In one embodiment, a classical computer is communicatively connected to a quantum computer. The classical computer configures an input register for the quantum state preparation circuit based on the circuit preparation parameters of the quantum state preparation circuit, determines the number of auxiliary qubits, configures a copy register and a target register for the quantum state preparation circuit according to the number of auxiliary qubits, and constructs a circuit through the input register, the copy register, and the target register according to the qubit copying method to obtain a diagonal unitary matrix quantum circuit. The qubit copying method is obtained based on grid constraint conditions. The diagonal unitary matrix quantum circuit and single-qubit quantum gates are combined to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit. A quantum state preparation circuit is generated based on at least one uniform control gate circuit, and a quantum program composed of the quantum state preparation circuits is sent to the quantum computer for execution.

[0064] Among them, the classical computer 102 can be, but is not limited to, various personal computers, laptop computers, smartphones, tablet computers, Internet of Things devices, and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, etc. The portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The quantum computer 104 is a physical device that performs high-speed mathematical and logical operations, storage, and processing of quantum information in accordance with the laws of quantum mechanics.

[0065] In one embodiment, as Figure 3 shown, a method for generating a quantum state preparation circuit is provided. Taking the method applied to the classical computer 102 in Figure 1 as an example, the method includes the following steps:

[0066] Step 302, configure an input register for the quantum state preparation circuit based on the circuit preparation parameters of the quantum state preparation circuit, and determine the number of auxiliary qubits.

[0067] Among them, quantum state preparation refers to loading data that meets given conditions into a quantum state to obtain quantum state data. The quantum state preparation circuit refers to a circuit used to prepare a quantum state. It should be noted that the quantum state preparation circuit in this embodiment is a quantum computing model, also known as a quantum circuit model, which consists of a series of qubit gate sequences and the qubit gates complete the calculation. The quantum state preparation circuit in this embodiment can be implemented by actual quantum components, and each qubit gate in the quantum state preparation circuit corresponds to an operation of an actual quantum component. In a specific application, the mathematical description of the quantum state preparation problem is as follows: Given classical data (complex vector) and the classical data satisfies ‖v‖2 = 1 (the modulus length is 1), design an (n + m)-qubit quantum state preparation circuit QSP, and this circuit satisfies:

[0068]

[0069] where n is the number of input qubits, is the given initial state, {|k>: k = 0, 1, …, 2 n - 1} is a set of computational bases of the quantum system, and are m auxiliary qubits.

[0070] The inventors believe that the problem of quantum state preparation widely exists in various quantum machine learning algorithms. Therefore, efficiently implementing the quantum state preparation circuit QSP helps improve the efficiency of quantum machine learning algorithms. Moreover, due to the decoherence in the physical implementation of existing quantum devices, that is, as time increases, the coherence of the quantum system gradually disappears and finally degenerates into a classical system. Therefore, in order to minimize the impact of decoherence as much as possible, the quantum circuit must be parallelized to reduce its circuit depth.

[0071] Among them, a qubit is the basic unit for storing data, and specific functions can be realized by performing corresponding operations on the qubit. In this embodiment, mainly corresponding operations are performed on the qubit to realize quantum state preparation. A quantum gate can change the state of the qubit it acts on, thereby realizing a specific quantum operation. According to the number of qubits it acts on, quantum gates can be divided into single - qubit quantum gates and two - qubit quantum gates. A single - qubit quantum gate acts only on a specific qubit and can only change the state of that qubit. A two - qubit quantum gate acts on two qubits and can change the states of the two qubits, such as the controlled - NOT gate.

[0072] Among them, the circuit preparation parameters refer to the parameters used to design the quantum state preparation circuit. For example, the circuit preparation parameters can specifically include the preparation target of the quantum state preparation circuit and the qubit parameters of the quantum computer. The preparation target is the target quantum state to be prepared based on the quantum state preparation circuit. The qubit parameters include the total number of qubits and the qubit connectivity relationship. The input register refers to the input qubits, that is, the set of qubits storing the input initial state. The input initial state is the data to be prepared input into the quantum state preparation circuit. For example, the input initial state can specifically be a qubit string composed of any n - qubits, where n is the number of input qubits. The number of auxiliary qubits refers to the number of auxiliary qubits in the quantum state preparation circuit. The quantum state preparation circuit includes an input register and auxiliary qubits.

[0073] Specifically, based on the circuit preparation parameters of the quantum state preparation circuit, a classical computer can determine the number of input qubits. Thus, based on the number of input qubits and the qubit connection relationship, an input register can be configured for the quantum state preparation circuit, and the number of qubits in the input register is the same as the number of input qubits. After determining the number of input qubits, the classical computer can determine the number of auxiliary qubits according to the number of input qubits and the total number of qubits. In a specific application, the classical computer can use the difference between the total number of qubits and the number of input qubits as the number of auxiliary qubits.

[0074] Step 304: Configure a copy register and a target register for the quantum state preparation circuit according to the number of auxiliary qubits.

[0075] Among them, the copy register refers to a set of qubits that store copied data. The target register refers to a set of qubits that store the target function to be achieved during the quantum state preparation process.

[0076] Specifically, the classical computer will configure a copy register and a target register for the quantum state preparation circuit according to the number of auxiliary qubits, that is, divide the auxiliary qubits into a copy register and a target register. In a specific application, when the number of auxiliary qubits is m, the number of qubits in the copy register is m / 2, and the number of qubits in the target register is m / 2. In another specific application, when the number of auxiliary qubits is m, the number of qubits in the copy register is m / 3, the number of qubits in the target register is m / 3, and the remaining m / 3 qubits in the auxiliary qubits are divided into an auxiliary register for assisting the quantum state preparation to further compress the circuit depth.

[0077] Step 306: Construct a circuit through the input register, the copy register, and the target register according to the qubit copying method to obtain a diagonal unitary matrix quantum circuit, and the qubit copying method is obtained based on the grid constraint conditions.

[0078] Among them, the qubit copying method refers to a method of copying qubits designed based on the grid constraint conditions. Since under the grid constraint conditions, a controlled-NOT gate can only act on two adjacent qubits, if the traditional copying method is used for copying, it will result in a large depth of the copy circuit for implementing the copying. Therefore, a copy circuit needs to be designed based on the grid constraint conditions. For example, the qubit copying method can specifically be to first perform column copying on the qubits, and then perform row copying based on the column copying result. The traditional copying method is to copy once to obtain the first copy result, then copy twice based on the first copy result to obtain the second copy result, and then copy four times based on the second copy result to obtain the third copy result, and so on in an iterative copying manner to achieve qubit copying.

[0079] Among them, the grid constraint condition means that in a quantum device, a quantum circuit is often restricted by grid constraints. For example, as Figure 4 shown, it represents the n1×n2-grid constraint of an n1n2-qubit circuit, where n1 refers to the number of qubits in a single column of the grid, n2 is the number of qubits in a single row of the grid, and the vertices respectively represent n1×n2 qubits. If two qubits are connected by an edge in the grid, a controlled-NOT gate can act on these two qubits. When n1 or n2 is 1, the grid constraint degenerates into a path constraint (as Figure 5 shown). In this application, without loss of generality, it is assumed that n1≥n2. A diagonal unitary matrix quantum circuit refers to a quantum circuit that can be represented by a diagonal unitary matrix. For example, the definition of an n-qubit diagonal unitary matrix is: where, diag refers to a diagonal matrix, and the matrix elements such as

[0080] can be determined by splitting the quantum state preparation circuit based on the preparation target. iθ(x) Specifically, a classical computer will construct a circuit through an input register, a copy register, and a target register according to the qubit replication method to obtain a diagonal unitary matrix quantum circuit. In a specific application, the role of a diagonal unitary matrix quantum circuit is to perform the following transformation on each vector |x> of a set of computational bases in a quantum system: |x>→e |x>, iθ(x) that is, for each vector of a set of computational bases, an output corresponding vector with a phase is generated, where the e

[0081] is the matrix element of the diagonal unitary matrix in the diagonal unitary matrix quantum circuit. s Based on this, we can define the parameter {α n :s∈{0,1} n -{0 s}} that satisfies: Σ s <s,x>α =θ(x), s where s and x are qubit strings, n is the number of input qubits, α n is the phase, <s,x> represents the inner product of the qubit string s and the qubit string x. Thus, a diagonal unitary matrix quantum circuit can be implemented by generating all the phases α s corresponding to 2 n qubit strings s. For each qubit string s in the 2 s qubit strings s, there is a corresponding phase α where the inner product can be represented by the symbol <x,y> and is defined as n where, x=(x1,…,x) T ,y=(y1,…,y n ) T ∈{0,1} n , addition and multiplication are operations under the binary field.

[0082] In a specific application, the classical computer will generate 2 according to the quantum bit replication method through the input register, the replication register and the target register. n All phases α corresponding to the quantum bit string s s The circuit is constructed for the target and a diagonal unitary matrix quantum circuit is obtained. Further, the classical computer will gradually generate 2 according to the quantum bit replication method through the input register, replication register and target register. n Each qubit string s in the qubit string s, and realizes the corresponding phase α when generating each qubit string s s The phase α corresponding to each quantum bit string s is s All can be based on Σ s <s,x> α s =θ(x) is calculated. In the case where x can take a non-zero quantum bit string, there will be a corresponding equation for each quantum bit string x. By combining all the equations, the phase α corresponding to each quantum bit string s can be obtained. s .

[0083] For example, for the case of 2 qubits, the qubit string s can be 01, 10, 11, and the qubit string x can also be 01, 10, 11. For the qubit string x being 01, the corresponding equation is <01,01>α s(01) +<10,01>α s(10) +<11,01>α s(11) =θ(01), where <01,01>, <10,01> and <11,01> are the inner products of each qubit string s and the qubit string x when it is 01, α s(01) , α s(10) , α s(11) Represents the phase α corresponding to each quantum bit string s s .

[0084] Step 308: Combine the diagonal unitary matrix quantum circuit and the single-bit quantum gate to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit.

[0085] Among them, a single-bit quantum gate only acts on a specific qubit and can only change the state of that qubit. A uniformly controlled gate circuit refers to a quantum circuit that can be represented by uniformly controlled gates. For example, an n-qubit uniformly controlled gate (UCG) V n is defined as:

[0086]

[0087] where, for any k ∈ [2 n-1 , is a unitary matrix. Any n-qubit quantum circuit can be decomposed into a combination of n uniformly controlled gates with different scales, that is where represents the identity operator of n - k qubits. Based on the circuit decomposition principle, ignoring a global phase, a uniformly controlled gate can be decomposed into a diagonal unitary matrix and a single-bit quantum gate, that is, a uniformly controlled gate circuit includes a diagonal unitary matrix quantum circuit and a single-bit quantum gate. For example, a uniformly controlled gate can be decomposed into a combination of 3 diagonal unitary matrices and 4 single-bit quantum gates.

[0088] Specifically, since any n-qubit quantum circuit can be decomposed into a combination of n uniformly controlled gates with different scales, and a uniformly controlled gate can be decomposed into a combination of a diagonal unitary matrix and a single-bit quantum gate, therefore, when designing a quantum state preparation circuit, a classical computer needs to first decompose the quantum state preparation circuit based on the circuit preparation parameters of the quantum state preparation circuit, decompose the quantum state preparation circuit into a combination of uniformly controlled gates, and then decompose the uniformly controlled gate into a combination of a diagonal unitary matrix and a single-bit quantum gate, so as to obtain a diagonal unitary matrix quantum circuit by first constructing the circuit, and then combine the diagonal unitary matrix quantum circuit and the single-bit quantum gate to obtain a uniformly controlled gate circuit corresponding to the diagonal unitary matrix quantum circuit.

[0089] Step 310, generate a quantum state preparation circuit based on at least one uniformly controlled gate circuit.

[0090] Specifically, since any n-qubit quantum circuit can be decomposed into a combination of n uniformly controlled gates with different scales, after a classical computer decomposes the quantum state preparation circuit and decomposes the quantum state preparation circuit into a combination of uniformly controlled gates, it can generate a quantum state preparation circuit based on at least one uniformly controlled gate circuit after obtaining the uniformly controlled gate circuit. For example, assume that the initial state of the circuit is The schematic diagram of any n-qubit quantum circuit can be as Figure 6 shown and decomposed into a combination of n uniformly controlled gates with different scales.

[0091] The above method for generating a quantum state preparation circuit can configure an input register for the quantum state preparation circuit and determine the number of auxiliary qubits based on circuit preparation parameters. Thus, the copy register and the target register can be configured according to the number of auxiliary qubits. According to the qubit copying method, a circuit is constructed through the input register, the copy register, and the target register. Considering the grid constraint conditions, a diagonal unitary matrix quantum circuit can be constructed using combinatorial techniques. Furthermore, a uniform control gate circuit can be obtained by combining the diagonal unitary matrix quantum circuit and single-qubit quantum gates. Based on the uniform control gate circuit, a quantum state preparation circuit is generated. In the whole process, the use of auxiliary qubits and combinatorial techniques realizes the parallelization of the quantum state preparation circuit under grid constraint conditions, and a quantum state preparation circuit with effectively compressed circuit depth can be obtained, reducing the impact of decoherence.

[0092] In one embodiment, the qubit copying method includes performing column copying on qubits under grid constraint conditions to obtain a column copying result, and performing row copying based on the column copying result.

[0093] Among them, column copying means copying qubits in the column direction. Row copying means copying qubits in the row direction.

[0094] Specifically, the qubit copying method includes performing column copying on qubits under grid constraint conditions to obtain a column copying result, and performing parallel row copying based on the column copying result. In a specific application, performing column copying means single-column copying, copying the qubits into the first column. Parallel row copying means that through the action of controlled-NOT gates, the qubits in the first column are copied into each row. Based on the grid constraint conditions and the qubit copying method, the circuit depth of the qubit copying circuit can be determined. For example, under the n1×n2 grid constraint, for any x = x1x2…x n ∈{0,1} n , the copy transformation can be implemented by a CNOT (controlled-NOT) circuit with a depth of O(n 2 + n1 + n2).

[0095] In a specific application, the qubit copying method under the n1×n2 grid constraint can include the following two steps.

[0096] Step 1: Copying under the first column constraint (n1 - path constraint n), that is, implementing the following transformation:

[0097]

[0098] That is, copying |x> and copying it to On one qubit, copying the above transformation can be achieved by a copy circuit under the column constraint as shown in Figure 7 . In the copy circuit under this column constraint, through the action of the controlled-NOT gates, x1…x are copied n (n1 - n) times respectively, and each controlled-NOT gate realizes one copy. Among them, the first controlled-NOT gate acts from the position (n, 1) to (2n, 1) to realize the copy of x n . Further, from the circuit implementation of the controlled-NOT gate under the path constraint, it can be known that each controlled-NOT gate in the copy circuit under the column constraint can be realized by a controlled-NOT gate circuit with a depth of O(n) under the (n + 1)-path constraint. Therefore, under the n1-path constraint n, the circuit depth of the above transformation is

[0099] Among them, the circuit implementation of the controlled-NOT gate under the path constraint means that under the path constraint, it can be realized by a CNOT circuit with both depth and size of O(|i - j|) (as shown in Figure 8 , where the small black dots represent the control bits and the large circles represent the target bits), where i is the control bit of the controlled-NOT gate and j is the target bit of the controlled-NOT gate. For example, in the copy circuit under the column constraint as shown in Figure 7 , the first controlled-NOT gate acts from the position (n, 1) to (2n, 1), where (n, 1) is the control bit and (2n, 1) is the target bit.

[0100] Step 2: Under the constraint of the n2-path (i, 1)-(i, 2)-…-(i, n2) (the i-th row of the grid), each qubit (i, 1) is copied n2 - 1 times. For any i ∈ [n1], this step can be implemented by a quantum circuit with a depth of O(n2) Since the above n1 path constraints do not intersect, they can be implemented in parallel.

[0101] In this embodiment, by designing a qubit copying method that first performs column copying based on the grid constraint conditions and then performs row copying based on the column copying results, the circuit depth of the qubit copying circuit can be reduced, effectively compressing the circuit depth of the quantum state preparation circuit and realizing the reduction of the decoherence effect.

[0102] In one embodiment, the input register includes a prefix part of qubits and a suffix part of qubits; according to the qubit copying method, a circuit is constructed through the input register, the copy register, and the target register, and the diagonal unitary matrix quantum circuit obtained includes:

[0103] According to the qubit copying method, the suffix part of the qubits in the input register is copied, and the suffix part of the qubits is copied into the copy register to obtain the suffix copy stage circuit;

[0104] Perform Gray initialization processing on the suffix part qubits in the copy register and the target register to obtain the Gray initialization stage circuit;

[0105] According to the qubit copying method, copy the prefix part qubits in the input register and copy the prefix part qubits to the copy register to obtain the prefix copying stage circuit;

[0106] Perform Gray path processing on the prefix part qubits in the copy register and the target register to obtain the Gray path stage circuit;

[0107] Perform inversion processing based on the suffix copying stage circuit, Gray initialization stage circuit, prefix copying stage circuit, and Gray path stage circuit to obtain the inversion processing stage circuit;

[0108] Based on the suffix copying stage circuit, Gray initialization stage circuit, prefix copying stage circuit, Gray path stage circuit, and inversion processing stage circuit, obtain the diagonal unitary matrix quantum circuit.

[0109] Among them, the input register includes prefix part qubits and suffix part qubits. For example, when the input register is an n-qubit, the prefix part qubits refer to the first n-p qubits in the input register, and the suffix part qubits refer to the last p qubits in the input register, where n-p can be configured according to the actual application scenario. In a specific application, the number of qubits in the prefix part qubits and the suffix part qubits can be the same or close. For example, when the input register is a 4-qubit, the prefix part qubits can refer to the first 2 qubits in the input register, and the suffix part qubits refer to the last 2 qubits in the input register.

[0110] Among them, Gray initialization processing is mainly used to implement the target function and phase rotation matching the Gray initialization stage on each qubit of the target register. The target function matching the Gray initialization stage implemented on each qubit is a linear function based on the suffix part qubits. For example, the target function can specifically be a function determined based on a pre-constructed set of qubit strings. The pre-constructed set of qubit strings is constructed based on the conditions that the set of qubit strings needs to meet and the Gray code cycle.

[0111] In a specific application, the pre-constructed set of qubit strings {0, 1} corresponding to the n-qubit n can be divided into a 2D array composed of n-bit strings {s(j, k): j ∈ [2 n-p , k ∈ [2p ]}, where p = log2(m / 3), m is the number of auxiliary qubits, then the target function matched in the Gray initialization phase can be specifically f 1,k (x)=<s(1,k),x> , where s(1,k) is the first row of the bit string in the 2D array, and x is the input register. Phase rotation is used to change the phase of the implemented objective function. The phase change on each qubit is determined based on the objective function that the qubit matches.

[0112] Among them, the Gray code circle is {0,1} n A sequence of all n-bit strings in the sequence, in which two adjacent bit strings differ by exactly one bit, and in which the first and last bit strings in the sequence also differ by exactly one bit. The following example illustrates the construction of the Gray code cycle. The construction of the 1-Gray code cycle is as follows: Define x 1 =0 n , for each i=1,2,…,2 n -1, by flipping x i The tth bit of x is obtained i+1 , where t represents x in the 1-Gray code circle i and x i+1 The labels of different bits, t satisfies 2 t-1 |iand For any k∈[n], the k-Gray code cycle is constructed as follows: define y 1 =0 n , for each i=1,2,…,2 n -1, if t+k-1≤n, then by flipping y i The t+k-1th bit of i+1 , if t+k-1>n, then by flipping y i The t+k-1-nth bit of i+1 , where t represents x in the 1-Gray code circle i and x i+1 To further illustrate, the 1-Gray code circle for a 2-bit string may be 00, 01, 11, 10.

[0113] In a specific application, the conditions that the quantum bit string set must meet may include the following: First, the first row of the array {s(1,k):k∈[2 p ]} the first (np) bits of the bit string are all 0, and each column of the array {s(j,k):j∈[2 n -p ]} have the same last p bits. Exactly one bit of s(j,k) and s(j + 1,k) is different. Thirdly The prefix bits of s(1+(l - 1)(n - p),k), s(2+(l - 1)(n - p),k), …, s(l(n - p),k) are 1-Gray code, 2-Gray code, …, n - p Gray code respectively.

[0114] Among them, Gray path processing is mainly used to implement the target function transformation and phase rotation that match the current processing stage on each qubit of the target register in each processing stage. For example, in the first processing stage of the Gray path processing stage, it is mainly to transform the target function implemented by Gray initialization processing. For another example, in the second processing stage of the Gray path processing stage, it is mainly to transform the transformed target function obtained in the first processing stage. The target function transformation here mainly refers to implementing a new target function. For example, the target function transformation can specifically be to implement a linear function based on the prefix qubits. In a specific application, for the 2D array divided from the pre-constructed qubit string set, the target function transformation in each processing stage is to implement the inner product of the bit strings in different rows and the input register respectively. For example, the target function transformation implemented in the first processing stage is f 2,k (x) = <s(2,k),x>, where s(2,k) is the bit string in the second row of the 2D array and x is the input register.

[0115] Specifically, the classical computer will divide the input register into prefix qubits and suffix qubits, copy the suffix qubits in the input register according to the qubit copying method, copy the suffix qubits into the copy register based on the suffix copy stage condition to obtain the suffix copy stage circuit, and then perform Gray initialization processing on the suffix qubits in the copy register and the target register to implement the target function and phase rotation that match the Gray initialization stage on each qubit of the target register, obtaining the Gray initialization stage circuit. Then, according to the qubit copying method, copy the prefix qubits in the input register, copy the prefix qubits into the copy register based on the prefix copy stage condition to obtain the prefix copy stage circuit, and then perform Gray path processing on the prefix qubits in the copy register and the target register to implement the target function transformation and phase rotation that match the current processing stage on each qubit of the target register in each processing stage of the Gray path processing, obtaining the Gray path stage circuit.

[0116] Among them, the condition in the suffix copying stage refers to the number of suffix partial qubits to be copied in the suffix copying stage, which can be configured based on the actual application scenario. For example, the number of suffix partial qubits to be copied can be n - p, where n is the number of input qubits, and p = log2(m / 3), and m is the number of auxiliary qubits. The condition in the prefix copying stage refers to the number of prefix partial qubits to be copied in the prefix copying stage, which can be configured based on the actual application scenario. For example, the number of prefix partial qubits to be copied can be n - p, where n is the number of input qubits, and p = log2(m / 3), and m is the number of auxiliary qubits.

[0117] Specifically, since the function of the diagonal unitary matrix quantum circuit is to output a corresponding vector with a phase for each vector of a set of computational bases, after obtaining the circuit in the Gray path stage, the classical computer will perform an inverse operation based on the circuit in the suffix copying stage, the circuit in the Gray initialization stage, the circuit in the prefix copying stage, and the circuit in the Gray path stage to restore the copied register and the target register, obtaining the circuit in the inverse processing stage, and then based on the circuit in the suffix copying stage, the circuit in the Gray initialization stage, the circuit in the prefix copying stage, the circuit in the Gray path stage, and the circuit in the inverse processing stage, obtaining the diagonal unitary matrix quantum circuit.

[0118] In a specific application, performing an inverse operation based on the circuit in the suffix copying stage, the circuit in the Gray initialization stage, the circuit in the prefix copying stage, and the circuit in the Gray path stage includes performing inverse operations on the circuit in the suffix copying stage, the circuit in the Gray initialization stage, the circuit in the prefix copying stage, and the circuit in the Gray path stage respectively, obtaining the corresponding inverse circuits for each stage, and combining the corresponding inverse circuits for each stage to obtain the circuit in the inverse processing stage.

[0119] Illustrating with an example, the circuit in the inverse processing stage can be expressed as Among them, represents the corresponding inverse circuit of the Gray path stage circuit, represents the corresponding inverse circuit of the prefix copying stage circuit, represents the corresponding inverse circuit of the Gray initialization stage circuit, represents the corresponding inverse circuit of the suffix copying stage circuit. Among them, means that the corresponding inverse circuit of the Gray path stage circuit can be obtained by performing an inverse operation on each processing stage of the Gray path processing.

[0120] Illustrating with another example, the circuit in the inverse processing stage can also be expressed as Among them, represents the corresponding inverse circuit of the Gray path stage circuit, represents the corresponding inverse circuit of the prefix copying stage circuit, represents the circuit corresponding to the inverse circuit in the Gray initialization stage, represents the circuit corresponding to the inverse circuit in the suffix copy stage. Among them, it means that the circuit corresponding to the inverse circuit in the Gray path stage can be obtained by transforming the objective function obtained in the last processing stage of the Gray path processing again. In a specific application, for the 2D array divided from the pre-constructed set of qubit strings, the objective function transformation in each processing stage is to respectively implement the inner product of the qubit strings in different rows and the input register. Then the objective function transformation in the last processing stage is to implement the inner product of the qubit string in the last row of the array and the input register, and transforming the objective function obtained in the last processing stage again means implementing the inner product of the qubit string in the first row of the array and the input register.

[0121] In this embodiment, according to the qubit copying method, through suffix copy processing, Gray initialization processing, prefix copy processing, Gray path processing, and inverse processing, it is possible to utilize the properties of the Gray code circle, the copy register, and the target register, and construct a diagonal unitary matrix quantum circuit based on combinatorial techniques, achieving compression of the circuit depth of the diagonal unitary matrix quantum circuit under grid constraints.

[0122] In one embodiment, according to the qubit copying method, the suffix part qubits in the input register are copied, and the suffix part qubits are copied into the copy register. The circuit obtained in the suffix copy stage includes:

[0123] According to the qubit copying method, the suffix part qubits in the input register are column-copied and copied onto different qubits in the copy register to obtain the first controlled-NOT gate circuit;

[0124] The suffix part qubits that have been copied onto different qubits in the copy register are iteratively copied in the row direction until the number of suffix part qubits in the copy register meets the conditions of the suffix copy stage, obtaining the second controlled-NOT gate circuit;

[0125] Based on the first controlled-NOT gate circuit and the second controlled-NOT gate circuit, the circuit in the suffix copy stage is obtained.

[0126] Specifically, the suffix copying stage is used to copy the suffix part of the qubits in the input register to the copy register under the grid constraint conditions. At this time, the classical computer will perform a column copy on the suffix part of the qubits in the input register according to the qubit copying method, and copy the suffix part of the qubits to different qubits in a single column of the copy register respectively to obtain the first controlled-NOT gate circuit. Then, the suffix part of the qubits that have been copied to different qubits in a single column of the copy register are iteratively copied in the row direction until the number of the suffix part of the qubits in the copy register meets the conditions of the suffix copying stage to obtain the second controlled-NOT gate circuit. The first controlled-NOT gate circuit and the second controlled-NOT gate circuit are combined to obtain the suffix copying stage circuit.

[0127] In a specific application, when the suffix part of the qubits that have been copied to different qubits in a single column of the copy register are iteratively copied in the row direction, the classical computer will determine the number of rows to be copied in the row direction according to the number of the suffix part of the qubits to be copied in the suffix copying stage conditions. The number of rows to be copied is the number of the suffix part of the qubits to be copied in the suffix copying stage conditions minus 1.

[0128] In this embodiment, by performing column copy on the suffix part of the qubits first and then iterative copy in the row direction according to the qubit copying method, the circuit depth of the suffix copying stage circuit can be reduced under the grid constraint conditions, effectively compressing the circuit depth of the quantum state preparation circuit and realizing the reduction of the decoherence effect.

[0129] In one embodiment, the Gray initialization process is performed on the suffix part of the qubits in the copy register and the target register, and the Gray initialization stage circuit obtained includes:

[0130] By the suffix part of the qubits in the copy register, a matching target function is implemented on each qubit of the target register to obtain the third controlled-NOT gate circuit;

[0131] Based on the matching target function of each qubit, the first phase matching each qubit of the target register is determined respectively;

[0132] The phase rotation of the first phase matching each qubit of the target register is implemented on each qubit of the target register to obtain the first phase rotation circuit;

[0133] Based on the third controlled-NOT gate circuit and the first phase rotation circuit, the Gray initialization stage circuit is obtained.

[0134] Among them, the matching target function refers to the linear function formed based on the suffix part of the qubits, that is, when performing the Gray initialization process, it is necessary to first convert the state of the qubits in the target register into

[0135] Among them, x n-p+1 ,x n-p+2 ,…,x n The process converts the kth qubit in the target register into |f 1,k (x)>, where f 1,k (x)=<s(1,k),x> , where s(1,k) represents the 2D array {s(j,k):j∈[2 n-p ],k∈[2 p ]}, where x is the input register, p = log2(m / 3) and m is the number of auxiliary qubits.

[0136] The first phase that matches the target function is the phase corresponding to the bit string in the target function. The classical computer generates 2 n All phases α corresponding to the quantum bit string s s The circuit is constructed for the target, so for each bit string in the target function, there will be a corresponding phase α s The phase α corresponding to each quantum bit string s is s All can be based on Σ s <s,x> α s =θ(x) is calculated. In the case where x can take a non-zero quantum bit string, there will be a corresponding equation for each quantum bit string x. By combining all the equations, the phase α corresponding to each quantum bit string s can be obtained. s In a specific application, the objective function can be f 1,k (x)=<s(1,k),x> , then the bit string in the objective function is s(1,k), where k∈[2 p ].

[0137] Specifically, the classical computer will determine the matching target function that needs to be implemented on each quantum bit of the target register, and then implement the matching target function on each quantum bit of the target register by copying the suffix quantum bits in the register, obtaining a third controlled NOT gate circuit. Then, based on the phase corresponding to the bit string in the target function that matches each quantum bit, the first phase that matches each quantum bit of the target register is determined respectively, and the phase rotation of the matching first phase is implemented on each quantum bit of the target register to obtain a first phase rotation circuit. The third controlled NOT gate circuit and the first phase rotation circuit are combined to obtain a Gray initialization stage circuit.

[0138] In a specific application, after the classical computer determines the matching target function to be implemented on each qubit of the target register, it separately determines the target qubits acting on each qubit of the target register. The target qubits can be at least one qubit in the suffix partial qubits or can be empty. Furthermore, based on the acting relationship between the target qubits and each qubit of the target register, the classical computer can select the copied suffix partial qubits from the copy register and act them on each qubit of the target register, so as to implement the matching target function on each qubit of the target register. It should be noted that if the target qubits acting on the qubits of the target register are empty, it means that there is no need to select the copied suffix partial qubits from the copy register and act them on this qubit.

[0139] For example, assume that the matching target function to be implemented on one of the qubits of the target register is f 1,k (x) = <s(1,k),x> = <0000,x> = <0000,x1x2x3x4>, where s(1,k) = 0000, x = x1x2x3x4. According to the inner product result (0 * x1 + 0 * x2 + 0 * x3 + 0 * x4 = 0), the classical computer knows that the target qubits acting on this qubit are empty, so there is no need to select qubits from the copy register and act them on this qubit of the target register.

[0140] Another example, assume that the matching target function to be implemented on one of the qubits of the target register is f 1,k (x) = <s(1,k),x> = <0010,x> = <0010,x1x2x3x4>, where s(1,k) = 0010, x = x1x2x3x4. According to the inner product result (0 * x1 + 0 * x2 + 1 * x3 + 0 * x4 = x3), the classical computer knows that the target qubit acting on this qubit is x3. Furthermore, it can select an x3 from the copy register and act it on this qubit of the target register. Among them, since x1x2x3x4 is a 4 - qubit, its suffix partial qubits can be x3x4. If the copying condition in the suffix stage is that the number of suffix partial qubits to be copied is 2, then the copy register can be x3x4x3x4 at this time.

[0141] In a specific application, the phase rotation of the first phase that matches and is implemented on each qubit of the target register can be achieved through a rotation gate, that is, by applying the rotation gate on the k - th qubit of the target register. That is to say, if <s(1,k),x> = 1, then the phase of the k - th qubit on the target register rotates by α s(1,k), otherwise the phase remains unchanged, where α s(1,k) refers to the phase corresponding to the bit string s(1,k).

[0142] In this embodiment, when implementing the target function that matches on each qubit of the target register by copying the suffix qubits in the copy register, since the suffix qubits in the copy register can act on different qubits of the target register respectively, the circuit during the action can be implemented in parallel, so that the third controlled-NOT gate circuit with a compressed circuit depth can be obtained. When implementing the phase rotation of the first phase that matches on each qubit of the target register, since all the phase rotations do not act on the same qubit, all the phase rotations can be arranged in the same layer of the circuit to achieve a compressed circuit depth.

[0143] In one embodiment, determining the first phase that matches each qubit of the target register based on the target function that matches each qubit includes:

[0144] Based on the target function that matches each qubit, respectively determine the qubit string corresponding to each qubit of the target register;

[0145] Determine the phase corresponding to the qubit string;

[0146] Take the phase corresponding to the qubit string as the first phase that matches the qubit corresponding to the qubit string.

[0147] Among them, the qubit string refers to the bit string that takes the inner product with the input register in the target function. For example, when the target function is f 1,k (x) = 〈s(1,k),x〉, the qubit string refers to s(1,k) that takes the inner product with the input register x. s(1,k) indicates that this qubit string is the k-th bit string of the first row bit string in the 2D array {s(j,k): j ∈ [2 n-p , k ∈ [2 p}, and the 2D array is obtained by partitioning the pre-constructed qubit string set.

[0148] Specifically, since the target function that matches each qubit is the inner product of the bit string and the input register, the classical computer can respectively determine the qubit string corresponding to each qubit of the target register based on the target function that matches each qubit, so that the phase α corresponding to each qubit string s obtained by calculation can be determined s , determine the phase corresponding to the qubit string, and take the phase corresponding to the qubit string as the first phase that matches the qubit corresponding to the qubit string.

[0149] In this embodiment, the determination of the qubit string corresponding to the qubit can be realized based on the objective function, so that the determination of the first phase matching the qubit can be realized based on the qubit string, so as to realize the corresponding phase rotation based on the first phase.

[0150] In one embodiment, according to the qubit replication method, the prefix qubits in the input register are replicated, and the prefix qubits are replicated into the replication register. The circuit in the prefix replication stage includes:

[0151] Perform a reduction process on the qubits in the replication register that have undergone the suffix processing stage;

[0152] According to the qubit replication method, the prefix qubits in the input register are column-replicated and replicated onto different qubits in the replication register to obtain a fourth controlled-NOT gate circuit;

[0153] Iteratively replicate the prefix qubits that have been replicated onto different qubits in the replication register in the row direction until the number of prefix qubits in the replication register meets the conditions of the prefix replication stage to obtain a fifth controlled-NOT gate circuit;

[0154] Based on the fourth controlled-NOT gate circuit and the fifth controlled-NOT gate circuit, obtain the circuit in the prefix replication stage.

[0155] Among them, the reduction process refers to restoring the quantum state obtained in the suffix replication stage to the state before the suffix replication stage.

[0156] Specifically, the prefix replication stage is used to replicate the prefix qubits in the input register into the replication register under the grid constraint conditions. At this time, since the qubits in the replication register have undergone the suffix processing stage, the classical computer needs to first perform a reduction process on the qubits in the replication register that have undergone the suffix processing stage to restore the replication register to the state before the suffix replication stage, and then according to the qubit replication method, perform a single column replication on the prefix qubits in the input register, and replicate the prefix qubits onto different qubits in a single column of the replication register to obtain a fourth controlled-NOT gate, and then iteratively replicate the prefix qubits that have been replicated onto different qubits in a single column of the replication register in the row direction until the number of prefix qubits in the replication register meets the conditions of the prefix replication stage to obtain a fifth controlled-NOT gate circuit, and combine the fourth controlled-NOT gate circuit and the fifth controlled-NOT gate circuit to obtain the circuit in the prefix replication stage.

[0157] In a specific application, when iteratively copying the prefix partial qubits on different qubits in a single column of the copy register in the row direction, the classical computer determines the number of rows to be copied in the row direction according to the number of prefix partial qubits to be copied on the copy register in the prefix copy phase condition. The number of rows to be copied is the number of prefix partial qubits to be copied on the copy register in the prefix copy phase condition minus 1.

[0158] In this embodiment, by first performing column copying on the prefix partial qubits according to the qubit copying method and then performing iterative copying in the row direction, the circuit depth of the prefix copy phase circuit can be reduced under the grid constraint conditions, effectively compressing the circuit depth of the quantum state preparation circuit and reducing the impact of decoherence.

[0159] In one embodiment, by performing Gray path processing on the prefix partial qubits in the copy register and the target register, the Gray path phase circuit obtained includes:

[0160] In each processing stage of the Gray path processing, by copying the prefix partial qubits in the copy register, a target function transformation matching the current processing stage is implemented on each qubit of the target register to obtain the processing circuit of the current processing stage;

[0161] Based on the processing circuits of each processing stage in the Gray path processing, the Gray path phase circuit is obtained.

[0162] Among them, the Gray path processing stage includes 2 n-p -1 processing stages, where n is the number of input qubits, p = log2(m / 3), and m is the number of auxiliary qubits. The target function transformation matching the current processing stage refers to transforming the target function obtained in the previous processing stage to implement a new target function. For example, the target function transformation can specifically be to implement a linear function composed of the prefix partial qubits. For the first processing stage, its previous processing stage refers to the Gray initialization stage, that is, in the first processing stage of the Gray path processing stage, it is mainly to transform the target function implemented by the Gray initialization processing. In a specific application, for the 2D array divided from the pre-constructed qubit string set, the target function transformation of each processing stage is to respectively implement the inner product of the bit strings in different rows and the input register. For example, the target function transformation implemented in the first processing stage is f 2,k (x) = <s(2,k),x>, where s(2,k) is the bit string in the second row of the 2D array and x is the input register.

[0163] Specifically, at each processing stage of Gray path processing, a classical computer transforms the target function obtained in the previous processing stage by copying the prefix part of qubits in the register, implements the target function transformation matching the current processing stage on each qubit in the target register, obtains the processing circuit of the current processing stage, and combines the processing circuits of each processing stage in Gray path processing to obtain the Gray path stage circuit.

[0164] In this embodiment, by copying the prefix part of qubits in the register and implementing the target function transformation matching the current processing stage on each qubit in the target register, the processing circuit of the current processing stage can be obtained, and then the Gray path stage circuit can be obtained based on the processing circuits of each processing stage in Gray path processing.

[0165] In one embodiment, by copying the prefix part of qubits in the register and implementing the target function transformation matching the current processing stage on each qubit in the target register, the processing circuit obtained in the current processing stage includes:

[0166] Based on the target function transformation matching the current processing stage, respectively determine the qubit control bits acting on each qubit in the target register and the second phase matching each qubit;

[0167] According to the qubit control bits, implement the target function transformation control by copying the prefix part of qubits in the register to obtain the target function transformation circuit;

[0168] Implement the phase rotation of the matching second phase on each qubit in the target register to obtain the second phase rotation circuit;

[0169] According to the target function transformation circuit and the second phase rotation circuit, obtain the processing circuit of the current processing stage.

[0170] Among them, the matching target function transformation refers to the transformation of the target function in the previous processing stage implemented based on the prefix part of qubits. The qubit control bit refers to the qubit that controls the change of the qubit. For example, the qubit control bit can specifically refer to the qubit in the input register that controls the change of the qubit. The control of the change of the qubit can be implemented through a controlled-NOT gate. The qubit control bit is the control bit in the controlled-NOT gate, and the qubit to be changed is the target bit.

[0171] Among them, the matching second phase refers to the phase corresponding to the bit string in the transformed target function of the current processing stage. The classical computer generates all phases α corresponding to the 2 n qubit strings s sThe circuit is constructed for the target, so for each bit string in the transformed target function, there will also be a corresponding phase α s The phase α corresponding to each quantum bit string s is s All can be based on Σ s <s,x> α s =θ(x) is calculated. In the case where x can take a non-zero quantum bit string, there will be a corresponding equation for each quantum bit string x. By combining all the equations, the phase α corresponding to each quantum bit string s can be obtained. s In a specific application, the transformed objective function can be f 2,k (x)=<s(2,k),x> , then the bit string in the transformed objective function is s(2,k), where k∈[2 p ].

[0172] Specifically, the classical computer will determine the matching objective function transformation that needs to be implemented on each quantum bit in the current processing stage, and based on the objective function transformation that matches the current processing stage, determine the quantum bit control bit acting on each quantum bit of the target register and the second phase matching each quantum bit, respectively. The quantum bit control bit is at least one quantum bit in the prefix part quantum bit, and then, based on the action relationship between the quantum bit control bit and each quantum bit of the target register, the copied prefix part quantum bit can be selected from the copy register and acted on each quantum bit of the target register, so as to realize the objective function function transformation on each quantum bit of the target register through the prefix part quantum bit in the copy register, and obtain the objective function transformation circuit.

[0173] Among them, after determining the target function transformation that matches the current processing stage, the classical computer can determine the second phase that matches each quantum bit based on the phase corresponding to the bit string in the transformed target function that matches the current processing stage. In a specific application, since the transformed target function is the inner product of the bit string and the input register, the classical computer can determine the quantum bit string corresponding to each quantum bit of the target register in the current processing stage based on the transformed target function, so that the phase α corresponding to each quantum bit string s can be calculated. s , determine the phase corresponding to the quantum bit string, and use the phase corresponding to the quantum bit string as the second phase that matches the quantum bit corresponding to the quantum bit string.

[0174] For example, suppose the target function to be implemented on one of the qubits of the target register is transformed from f 1,k (x)=<s(1,k),x> =<0000,x> =<0000,x1x2x3x4> is transformed into f 2kWhen (x) = <s(2,k),x> = <1000,x> = <1000,x1x2x3x4>, the classical computer can know from the inner product result (0*x1 + 0*x2 + 0*x3 + 0*x4 = 0, 1*x1 + 0*x2 + 0*x3 + 0*x4 = x1) that the qubit control bit acting on this qubit is x1, and then one x1 can be selected from the copy register and applied to this qubit in the target register. Among them, since x1x2x3x4 is a 4-qubit, its prefix qubits can be x1x2. If the copy condition in the suffix stage is that the number of qubits in the suffix part to be copied is 2, then the copy register can be x1x2x1x2 at this time.

[0175] Specifically, after obtaining the target function transformation circuit, the classical computer will implement the phase rotation of the matching second phase on each qubit in the target register to obtain the second phase rotation circuit. Based on the target function transformation circuit and the second phase rotation circuit, the processing circuit in the current processing stage is obtained. In a specific application, the phase rotation of the matching second phase on each qubit in the target register can be implemented through a rotation gate, that is, the rotation gate acts on the k-th qubit in the target register. That is to say, if <s(j,k),x> = 1, then the phase rotation α of the k-th qubit on the target register s(j,k) , otherwise the phase remains unchanged, where α s(j,k) refers to the phase corresponding to the bit string s(j,k), j is used to represent the current processing stage, and the Gray path processing includes 2 n-p -1 processing stages, where n is the number of input qubits, p = log2(m / 3), m is the number of auxiliary qubits, and j = 2, 3,..., 2 n-p are used to represent each processing stage respectively. Here, the Gray initialization stage can be regarded as the processing stage with j = 1.

[0176] In this embodiment, based on the target function transformation matching the current processing stage, the qubit control bits acting on each qubit in the target register and the matching second phase of each qubit can be determined respectively. When implementing the target function transformation control through the prefix qubits in the copy register according to the qubit control bits, since the prefix qubits in the copy register can act on different qubits in the target register respectively, the circuits during the action can be implemented in parallel, so that a target function transformation circuit with a compressed circuit depth can be obtained. When implementing the phase rotation of the matching second phase on each qubit in the target register, since all the phase rotations do not act on the same qubit, all the phase rotations can be placed in the same layer of the circuit to achieve circuit depth compression.

[0177] In one embodiment, the method for generating a quantum state preparation circuit further includes:

[0178] Configuring an auxiliary register for the quantum state preparation circuit based on the number of auxiliary qubits;

[0179] According to the qubit replication method, replicating the prefix part of the qubits in the input register, and copying the prefix part of the qubits into the replication register, the prefix replication stage circuit obtained includes:

[0180] According to the qubit replication method, replicating the prefix part of the qubits in the input register, copying the prefix part of the qubits into the replication register, and copying the prefix part of the qubits into the auxiliary register, to obtain the prefix replication stage circuit;

[0181] Performing a Gray path process on the prefix part of the qubits in the replication register and the target register, the Gray path stage circuit obtained includes:

[0182] Performing a Gray path process on the prefix part of the qubits in the replication register, the prefix part of the qubits in the auxiliary register, and the target register, to obtain the Gray path stage circuit.

[0183] Wherein, the auxiliary register refers to a set of qubits storing auxiliary data. In this embodiment, the auxiliary data mainly refers to the prefix part of the qubits. The auxiliary register is used to assist in quantum state preparation to further compress the circuit depth.

[0184] Specifically, in addition to configuring a replication register and a target register for the quantum state preparation circuit according to the number of auxiliary qubits, the classical computer will also configure an auxiliary register. In a specific application, when the number of auxiliary qubits is m, the number of qubits in the replication register is m / 3, the number of qubits in the target register is m / 3, and the remaining m / 3 qubits in the auxiliary qubits are divided into the auxiliary register. When replicating the prefix part of the qubits in the input register, the classical computer will perform a reduction process on the qubits in the replication register that have passed through the suffix processing stage, and according to the qubit replication method, perform column replication on the prefix part of the qubits in the input register and copy them to different qubits in the replication register, to obtain the fourth controlled-NOT gate circuit, and perform iterative replication on the prefix part of the qubits that have been copied to different qubits in the replication register in the row direction until the number of prefix part of the qubits in the replication register meets the prefix replication stage condition, to obtain the fifth controlled-NOT gate circuit.

[0185] Meanwhile, the classical computer copies the prefix part of the qubits to the auxiliary register according to the qubit copying method, obtaining the sixth controlled-NOT gate circuit, and then can obtain the prefix copying stage circuit by combining the fourth controlled-NOT gate circuit, the fifth controlled-NOT gate circuit, and the sixth controlled-NOT gate circuit.

[0186] In a specific application, when the classical computer copies the prefix part of the qubits to the auxiliary register according to the qubit copying method, it will first perform a column copy of the prefix part of the qubits in the input register, copying the prefix part of the qubits to different qubits in a single column of the auxiliary register, and then perform an iterative copy of the prefix part of the qubits on the different qubits in the single column of the auxiliary register in the row direction until the number of prefix part of the qubits in the auxiliary register meets the prefix copying stage condition, obtaining the sixth controlled-NOT gate circuit. In a specific application, when performing an iterative copy of the prefix part of the qubits on the different qubits in the single column of the auxiliary register in the row direction, the classical computer determines the number of rows to be copied in the row direction according to the number of prefix part of the qubits to be copied on the auxiliary register in the prefix copying stage condition, and the number of rows to be copied is the number of prefix part of the qubits to be copied on the auxiliary register in the prefix copying stage condition minus 1.

[0187] Specifically, in each processing stage of the Gray path processing, the classical computer realizes the target function transformation matching the current processing stage on each qubit of the target register by copying the prefix part of the qubits in the register and the prefix part of the qubits in the auxiliary register, obtaining the processing circuit of the current processing stage. Based on the processing circuits of each processing stage in the Gray path processing, the Gray path stage circuit is obtained. In a specific application, when realizing the target function transformation matching the current processing stage on each qubit of the target register by copying the prefix part of the qubits in the register and the prefix part of the qubits in the auxiliary register, the classical computer respectively determines the qubit control bits acting on each qubit of the target register and the second phase matching each qubit based on the target function transformation matching the current processing stage, controls the target function transformation by copying the prefix part of the qubits in the register and the prefix part of the qubits in the auxiliary register according to the qubit control bits, obtaining the target function transformation circuit, realizes the phase rotation of the matching second phase on each qubit of the target register, obtaining the second phase rotation circuit, and obtains the processing circuit of the current processing stage according to the target function transformation circuit and the second phase rotation circuit.

[0188] In a specific application, the qubit control bit is at least one qubit in the prefix part of the qubits. The classical computer can, based on the interaction relationship between the qubit control bit and each qubit of the target register, select the copied prefix part of the qubits from the copy register or the auxiliary register and apply them to each qubit of the target register, thereby realizing the transformation of the target function on each qubit of the target register through the prefix part of the qubits in the copy register and the qubits in the auxiliary register, and obtaining the target function transformation circuit.

[0189] In this embodiment, by introducing an auxiliary register for Gray path processing, the auxiliary register can assist the copy register, and can effectively reduce the circuit depth of the circuit in the Gray path stage.

[0190] In one embodiment, a quantum state preparation method is provided. Taking the quantum computer 104 in Figure 1 as an example for illustration, the method includes the following steps:

[0191] Perform quantum state preparation on the circuit initial state data based on the quantum state preparation circuit to obtain quantum state data. The quantum state preparation circuit is implemented by the above-mentioned quantum state preparation circuit generation method.

[0192] Among them, the circuit initial state data refers to the initial data for which quantum state data needs to be prepared. For example, the circuit initial state data can be where n is the number of input qubits. For another example, the circuit initial state data can be any set of computational bases of the quantum system.

[0193] Specifically, the classical computer will send the quantum program composed of the quantum state preparation circuit to the quantum computer. The quantum computer can, by executing the quantum program, perform quantum state preparation on the circuit initial state data based on the quantum state preparation circuit to obtain quantum state data.

[0194] The above-mentioned quantum state preparation method can, by using a quantum state preparation circuit with effectively reduced circuit depth, perform quantum state preparation on the circuit initial state data to obtain quantum state data, and can reduce the influence of decoherence.

[0195] This application also provides an application scenario. The quantum state preparation circuit generation method involved in the above embodiment can be used for the implementation of any n-qubit quantum circuit. The design of any n-qubit quantum circuit will be described below, that is, the quantum state preparation circuit generation method will be described. First, the symbols used in this application scenario are defined. The main symbols used in this application scenario are shown in Table 1.

[0196] Table 1

[0197]

[0198] Specifically, such as Figure 9 As shown in Figure 1, in this application scenario, the quantum state preparation circuit design can be divided into the following three steps. Step 1: Construct the circuit framework and decompose the quantum state preparation circuit into a series of uniform control gates V1, V2, ..., V n ; Step 2: Decompose each uniform control gate in the quantum state preparation circuit into 3 diagonal unitary matrices and 4 single-bit quantum gates; Step 3: Implement the diagonal unitary matrix quantum circuit with auxiliary quantum bits under grid constraints. Step 3 can be specifically achieved by generating 2 n All phases α corresponding to the quantum bit string s s The implementation includes: Step 3.1: Suffix copying phase; Step 3.2: Gray initialization phase; Step 3.3: Prefix copying phase; Step 3.4: Gray cycle phase; and Step 3.5: Inversion phase. Therefore, as long as a diagonal unitary matrix quantum circuit with auxiliary qubits can be realized under grid constraints, the diagonal unitary matrix quantum circuit can be combined with a single-bit quantum gate to obtain a uniform control gate circuit. By combining these uniform control gate circuits, a quantum state preparation circuit can be generated. Each step is explained in detail below.

[0199] Step 1: Construct the circuit framework and decompose the quantum state preparation circuit into a series of uniform control gates V1, V2, ..., V n .

[0200] First, define the uniform control gate, n-qubit uniform control gate V n Defined as:

[0201]

[0202] Among them, for any k∈[2 n-1 ], is a unitary matrix. Any n-qubit quantum circuit can be decomposed into a combination of n uniform control gates of different sizes, that is, in represents the unit operator of nk qubits. Based on the principle of circuit decomposition, ignoring a global phase, the uniform control gate can be decomposed into a diagonal unitary matrix and a single-bit quantum gate. That is, the uniform control gate circuit consists of a diagonal unitary matrix quantum circuit and a single-bit quantum gate. In this application scenario, the uniform control gate is decomposed into a combination of three diagonal unitary matrices and four single-bit quantum gates.

[0203] Step 2: Decompose each uniform control gate in the quantum state preparation circuit into three diagonal unitary matrices and four single-bit quantum gates.

[0204] First, define the n-qubit diagonal unitary matrix: According to the circuit decomposition principle, ignoring a global phase, a uniform control gate can be decomposed into the following form: where is an n-qubit diagonal unitary matrix, that is, each uniform control gate in the quantum state preparation circuit can be decomposed into 3 diagonal unitary matrices and 4 single-qubit quantum gates.

[0205] Step 3: Implement a diagonal unitary matrix quantum circuit with auxiliary qubits under grid constraints.

[0206] After Steps 1 and 2, the quantum state preparation circuit has been decomposed into a series of diagonal unitary matrices and some single-qubit quantum gates. Therefore, only by implementing the quantum circuit of any diagonal unitary matrix can the quantum state preparation circuit be obtained. So in Step 3, under grid constraints, this application scenario uses auxiliary qubits to implement the parallelism of the diagonal unitary matrix quantum circuit, thereby achieving the purpose of reducing the circuit depth.

[0207] Among them, the role of the diagonal unitary matrix quantum circuit is to implement the following transformation on each vector |x> of a set of computational bases of the quantum system: |x> → e iθ(x) |x>, Based on this, we can define the parameter {α s : s ∈ {0, 1} n -{0 n}} that satisfies: Σ s <s,x>α s = θ(x), where s and x are qubit strings, n is the number of input qubits, α s is the phase, <s, x> represents the inner product of the qubit string s and the qubit string x. Thus, the diagonal unitary matrix quantum circuit can be implemented by generating all the phases α n corresponding to 2 s qubit strings s. For each qubit string s in the 2 n qubit strings s, there is a corresponding phase α s .

[0208] First, we introduce three circuit constructions under grid constraints. The following three circuits will be used for the implementation of Step 3. One is the circuit implementation of the controlled-NOT gate under path constraints. Under path constraints, can be implemented by a CNOT circuit with a depth and size of O(|i - j|) (as shown in Figure 8 ). The second is the circuit implementation of the n-qubit reversible linear transformation under path constraints. Suppose U is an n-qubit reversible linear transformation. Under n-path constraints, U can be implemented by a circuit with a depth of O(n 2Implementation of the n-qubit CNOT quantum circuit for (). Third, the circuit implementation of the copy transformation under the grid constraint. Under the n1×n2 grid constraint, for any x = x1x2…x n ∈{0,1} n , the copy transformation can be implemented by a CNOT circuit with a depth of O(n 2 +n1+n2).

[0209] Among them, the implementation of the copy transformation under the n1×n2 grid constraint is divided into two steps.

[0210] Step 1: Copy under the first column constraint (n1-path constraint n), that is, implement the following transformation:

[0211]

[0212] The above transformation can be implemented by the copy circuit under the column constraint as Figure 7 shown. In the copy circuit under this column constraint, from the circuit implementation of the controlled-NOT gate under the path constraint, it can be seen that each controlled-NOT gate can be implemented by a CNOT circuit with a depth of O(n) under the (n + 1)-path constraint. Therefore, under the n1-path constraint, the circuit depth of the above transformation is

[0213] Step 2: Under the constraint of n2-path (i,1)-(i,2)-…-(i,n2) (the i-th row of the grid), copy each qubit (i,1) n2 - 1 times. For any i ∈ [n1], this step can be implemented by a quantum circuit with a depth of O(n2) Since the above n1 path constraints do not intersect, they can be implemented in parallel.

[0214] Furthermore, in order to more clearly describe the construction of the quantum circuit for each step, this application scenario first introduces some symbols. Define p = log(m / 3), r = 2 p / (n - t), x = x pre x suf ∈{0,1} n , x pre = x1x2…x n-p and x suf = x n-p+1 …x n . Where m is the number of auxiliary qubits, x is the qubit in the input register, x pre is the prefix part qubits in the input register, x sufLet the suffix part qubits be in the input register, and \(n\) be the number of input qubits. Without loss of generality, \(n_1\geq n_2\). Before designing the quantum state preparation circuit under the grid constraint, this application scenario first introduces the circuit implementation of the unitary transformation to be used later. Without loss of generality, assume \(n_2\leq2\). n / 3 And If \(n_2\) is greater than 2 n / 3 , this application scenario only uses a grid with a width of 2 n / 3 . If This invention only uses no more than auxiliary qubits. The input qubits are called the input register, denoted as \(I = \{\iota_1,\iota_2,\ldots,\iota n \}\). The auxiliary qubits are divided into three registers: the copy register \(C\): \(C=\{c_1,c_2,\ldots,c m / 3 \}\), the target register \(T\): \(T = \{t_1,t_2,\ldots,t m / 3 \}\), and the auxiliary register \(A\): \(A=\{a_1,a_2,\ldots,a m / 3 \}\).

[0215] In the \(n_1\times n_2\)-grid, there is a path with a length of \(n + m=n_1\times n_2\). The qubits in these three registers are arranged as follows under the \(n + m\)-path constraint:

[0216] R1: \(c_1,t_1,c_2,t_2,\ldots,c n-p ,t n-p ,a_1,a_2,\ldots,a n-p

[0217] R2: \(c n-p+1 ,t n-p+1 ,c n-p+2 ,t n-p+2 ,\ldots,c 2(n-p) ,t 2(n-p) ,a n-p+1 ,a n-p+2 ,\ldots,a 2(n-p)

[0218]

[0219] R k : \(c (k-1)(n-p)+1 ,t (k-1)(n-p)+1 ,c (k-1)(n-p)+2 ,t (k-1)(n-p)+2 ,\ldots,c k(n-p) ,t k(n-p) ,a (k-1)(n-p)+1 ,a (k-1)(n-p)+2 ,\ldots,a k(n-p)

[0220]

[0221]

[0222]

[0223] The following separately explains each sub-step included in Step 3.

[0224] Step 3.1: Suffix copying stage.

[0225] In the suffix copying stage, it is necessary to implement copying the last p qubits x n-p+1 , x n-p+2 , …, x n in the input register to the copy register C under the grid constraint. That is, it is to implement, under the grid constraint, the diagonal unitary matrix U acting on the input register and the copy register: copy,1 :

[0226]

[0227] where

[0228]

[0229] According to the circuit implementation of the copy transformation under the grid constraint, under the grid constraint, U copy,1 can be implemented by a CNOT circuit with a depth of O(p 2 + n1 + n2) = O(log 2 m + n1 + n2).

[0230] Step 3.2: Gray initialization stage.

[0231] In the Gray initialization stage, the circuit implementation is divided into two steps. The first step U1 implements m / 3 linear functions f 1,k (x) = <s(1, k), x>, where s(1, k) is an n-bit string, and the subscript j indicates that this linear function is implemented at the k-th bit of the target register. The second step is to implement a phase rotation in the target register. To clearly illustrate the linear functions implemented in the first step, the following set of bit strings is constructed in this application scenario.

[0232] Among them, let p = log(m / 3). The set {0, 1} n can be partitioned into a 2D array {s(j, k): j ∈ [2 n-p , k ∈ [2 p} composed of n-bit strings, and this 2D array satisfies the following three conditions: First, the first row of the array {s(1, k): k ∈ [2 p} The first (n - p) bits of the bit string are all 0, and each column of the array {s(j,k): j ∈ [2 n-p} has the same last p bits in the bit string. Second, s(j,k) and s(j + 1,k) differ in exactly 1 bit. Third, The prefix bits of s(1+(l - 1)(n - p),k), s(2+(l - 1)(n - p),k), …, s(l(n - p),k) are 1 - Gray code, 2 - Gray code, …, n - p Gray code respectively.

[0233] Among them, the goal of the first step U1 is to implement the quantum state |f 1,k (x)> on each qubit k of the target register at the end of this step, where f 1,k (x) = <s(1,k),x>. The second step is used to apply the rotation gate to the k - th qubit of the target register. That is, if <s(1,k),x> = 1, then the phase of the k - th qubit is rotated by α s(1,k) , otherwise the phase remains unchanged. Define R1 = R(α s(1,k) ).

[0234] Next, clarify the transformation implemented in the Gray initialization stage and the circuit depth to implement this transformation.

[0235] The Gray initialization stage is usually denoted by U GrayInit , and it can complete the following operations:

[0236]

[0237] Among them, Under the path (grid) constraint, the Gray initialization stage can be implemented by a quantum circuit with a depth of O(log 2 m).

[0238] First, explain how to implement p linear functions composed of the suffix variables x n-p+1 , x n-p+2 , …, x n in the first step U1. After the first step U1, the state of the 2 p qubits in the target register is transformed into That is, this process transforms the k - th qubit in the target register into |f 1,k (x)>. In the second step, for the basis |x> I |x SufCopy > C |0 m / 3 > T add the phase f 1,k(x)·α s(1,k) Therefore, it can be obtained that:

[0239]

[0240] After step 3.1, the qubits in the copy register C and the target register T have the following form:

[0241]

[0242] where c 1+(l-1)p , c 2+(l-1)p , … c lp respectively represent the qubits in the copy register C, and t 1+(l-1)p , t 2+(l-1)p , … t lp respectively represent the qubits in the target register T, that is, at this time, the suffix part of the qubits has been copied in the copy register, and the target register is still 0.

[0243] Therefore, the transformation of U1 can be written in the following form:

[0244]

[0245] For each transformation

[0246]

[0247] is a reversible linear transformation of p-qubits. Therefore, under the path (grid) constraint, the above process can be implemented by a CNOT circuit with a depth of O(p 2 ). Since the circuit constraint graphs of each of the above transformations do not intersect, all the transformations can be implemented in parallel. Therefore, the transformation U1 can be implemented by a CNOT circuit with a depth of O(p 2 ) under the path (grid) constraint.

[0248] For the operator R1, since all the rotation gates do not act on the same qubit, they can be placed in the same layer of the circuit, that is, the circuit depth is 1. To sum up, the circuit depth of the Gray initialization stage does not exceed O(p 2 ) = O(log 2 m).

[0249] Step 3.3: Prefix copy stage.

[0250] In the prefix copy stage, first, the quantum state obtained in the suffix copy stage is restored, and then the prefix variables x1, x2, …, x n-p are respectively implemented in the copy register and the auxiliary register. Copies. The prefix copy stage is similar to the suffix copy stage, and its circuit structure will not be elaborated here.

[0251] The prefix copy stage is usually denoted by U copy,2 and is used to copy the variables x1, …, x in the input register n-p to the copy register and the auxiliary register respectively. To achieve this, a CNOT circuit with a depth of at most O(n + n1 + n2) is required. 2 + n1 + n2) is required.

[0252] U copy,2 achieves the following effects:

[0253]

[0254] where |0 m / 3 > C represents the copy register, and |0 m / 3 > A represents the auxiliary register.

[0255] The operator in the prefix copy stage is with a depth of at most O(p 2 + n1 + n2) + 2·O((n - p) 2 + n1 + n2) = O(n 2 + n1 + n2), where is used to restore the quantum state obtained in the suffix copy stage. Therefore, the effect of the operator in this stage is:

[0256]

[0257] Step 3.4: Gray cycle stage (i.e., Gray path processing stage).

[0258] The Gray cycle stage contains 2 n-p - 1 processing stages, and j = 2, 3, …, 2 n-p is used as the subscript of these processing stages. The Gray initialization stage can be regarded as the processing stage with j = 1. In each processing stage j, the circuit C implements the following two steps: Step one is implemented by a quantum circuit U j composed of CNOT gates. The CNOT gates are controlled by , and the target bit is the k-th bit of the target register, where t jk represents the subscript of the bit where s(j, k) and s(j + 1, k) are different in the 2D array. Step two is to apply a rotation R(α s(j,k) ) to the k-th qubit of the target register. Let

[0259] Therefore, in the Gray circle stage, the actual transformation in the j-th stage is as follows:

[0260]

[0261]

[0262] where f j,k (x) = <s(j,k),x> and The circuit depth of the Gray circle stage is at most O(2 n-p ).

[0263] The following gives the proof of the construction of the circuit in the Gray circle stage. The Gray circle stage repeats the two steps implemented in each processing stage a total of 2 n-p -1 times.

[0264] For step one, for the convenience of description, we write the U j transformation in the j-th stage of the above Gray circle in the following equivalent form:

[0265]

[0266] On register R1, we implement the following transformation:

[0267]

[0268] where, f j,1 (x) = <s(j,1),x>, f j+1,1 (x) = <s(j + 1,1),x>, that is, on register R1, the implemented transformation corresponds to the transformation from the bit string in the j-th row to the bit string in the (j + 1)-th row in the constructed 2D array.

[0269] Without loss of generality, assume that s(j,1) and s(j + 1,1) are different in the γ-th bit. According to the properties of the Gray code circle, s(j,1), …, s(j,n - p) and s(j + 1,1), …, s(j + 1,n - p) are different in the γ, γ + 1, γ + 2, …, n - p, 1, 2, …, γ - 1 bits respectively.

[0270] If γ = 1, this transformation can be implemented by the following CNOT circuit:

[0271]

[0272] In this circuit, the control bit and the target bit of each CNOT gate are adjacent, and the control bits and target bits of any two CNOT gates are different, so its circuit depth is 1. If γ is strictly greater than 1, this transformation can be implemented by the following CNOT circuit:

[0273]

[0274] Among them, the above circuit indicates that the qubits in the auxiliary register can act on the target register, that is, γ - 1 qubits use the qubits in the auxiliary register, and the remaining qubits use the qubits in the copy register. Therefore, in the above circuit, all the CNOT gates in C k are restricted by non - intersecting paths, and these CNOT gates can be implemented in parallel, that is, the auxiliary register can be used to further compress the circuit depth. And the distance between the control bit and the target bit of the CNOT gate is O(γ). Therefore, under the grid (path) restriction, C k can be implemented by a circuit with a depth of O(γ). Therefore, under the grid restriction, can be implemented by a circuit with a depth of O(γ)·(γ - 1). On all registers R l the transformation is the same as that of R1, and the graph restrictions on these registers do not intersect. Therefore, the circuit depth of U j is O(γ 2 ).

[0275] For step 2, it only contains single - qubit quantum gates acting on different qubits. Therefore, this step can be implemented in parallel in one layer of the circuit.

[0276] It is worth mentioning that according to the properties of Gray code, in the 2 n-p -1 processing stages of the Gray cycle, the situation where s(j,1) and s(j + 1,1) are in the γ - th bit will occur 2 n-p-γ times. Therefore, under the path (grid) restriction, the Gray - cycle stage can be implemented by a circuit with a depth.

[0277] Step 3.5: Inverse stage;

[0278] The quantum circuit of the inverse stage is

[0279] which realizes the following transformation:

[0280]

[0281] that is, restoring the copy register, the target register, and the auxiliary register.

[0282] It should be noted that the quantum circuit of the inverse stage is the inverse circuit of all the CNOT circuits in steps 3.1 to 3.4, and the depth is

[0283] Combining the above five steps can obtain the quantum circuit of the diagonal unitary matrix corresponding to step 3 (the diagonal unitary matrix Λ n ).

[0284] The quantum circuit depth camera of the above five stages, that is, all circuit depths are

[0285] The process of implementing the diagonal unitary matrix Λ in the five stages in step 3 above n can be expressed by the following formula:

[0286]

[0287] where U copy,1 refers to the suffix copy stage, U GrayInit refers to the Gray initialization stage, refers to the prefix copy stage, R2U2 refers to the first processing stage of the Gray cycle stage, refers to the last processing stage of the Gray cycle stage, U Inverse refers to the inversion stage. e θ(x) refers to the phase rotation to be achieved by the diagonal unitary matrix.

[0288] From the above analysis, it can be concluded that when the number of auxiliary qubits is m ≥ 3n and m + n = n1n2, under the n1×n2-grid constraint, any n-qubit diagonal unitary matrix can be implemented by a quantum circuit with a circuit depth of .

[0289] Further reasoning shows that let m + n = n1n2. Given m (m ≥ 3n) auxiliary qubits, under the constraint of an n1×n2 two-dimensional grid, any n-qubit quantum state |ψ v > can be prepared by a quantum circuit with a depth of .

[0290] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least some of the steps or stages in other steps or other steps.

[0291] Based on the same inventive concept, an embodiment of the present application further provides a quantum state preparation circuit generation device for implementing the quantum state preparation circuit generation method involved above. The solution provided by this device for solving problems is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the quantum state preparation circuit generation device provided below can refer to the limitations on the quantum state preparation circuit generation method in the above text, and will not be elaborated here.

[0292] In one embodiment, as Figure 10 shown, a quantum state preparation circuit generation device is provided, including: a first configuration module 1002, a second configuration module 1004, a circuit construction module 1006, a circuit combination module 1008, and a processing module 1010, where:

[0293] The first configuration module 1002 is configured to configure an input register for the quantum state preparation circuit based on the circuit preparation parameters of the quantum state preparation circuit, and determine the number of auxiliary qubits;

[0294] The second configuration module 1004 is configured to configure a copy register and a target register for the quantum state preparation circuit according to the number of auxiliary qubits;

[0295] The circuit construction module 1006 is configured to construct a circuit through the input register, the copy register, and the target register according to the qubit copying method to obtain a diagonal unitary matrix quantum circuit, and the qubit copying method is obtained based on the grid constraint condition;

[0296] The circuit combination module 1008 is configured to combine the diagonal unitary matrix quantum circuit and single-qubit quantum gates to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit;

[0297] The processing module 1010 is configured to generate a quantum state preparation circuit based on at least one uniform control gate circuit.

[0298] The above quantum state preparation circuit generation device can configure an input register for the quantum state preparation circuit and determine the number of auxiliary qubits based on circuit preparation parameters. Thus, it can configure the copy register and the target register according to the number of auxiliary qubits. According to the qubit copying method, a circuit is constructed through the input register, the copy register, and the target register. It can construct a diagonal unitary matrix quantum circuit using combinatorial techniques considering the grid constraint conditions. Furthermore, a uniform control gate circuit can be obtained by combining the diagonal unitary matrix quantum circuit and single-qubit quantum gates. A quantum state preparation circuit is generated based on the uniform control gate circuit. Throughout the process, the use of auxiliary qubits and combinatorial techniques realizes the parallelization of the quantum state preparation circuit under grid constraint conditions, and a quantum state preparation circuit with effectively compressed circuit depth can be obtained, achieving a reduction in the impact of decoherence.

[0299] In one embodiment, the qubit copying method includes performing column copying on qubits under grid constraint conditions to obtain a column copying result, and performing row copying based on the column copying result.

[0300] In one embodiment, the input register includes a prefix part of qubits and a suffix part of qubits. The circuit construction module is further configured to copy the suffix part of qubits in the input register according to the qubit copying method, copy the suffix part of qubits into the copy register to obtain a suffix copying stage circuit, perform Gray initialization processing on the suffix part of qubits in the copy register and the target register to obtain a Gray initialization stage circuit, copy the prefix part of qubits in the input register according to the qubit copying method, copy the prefix part of qubits into the copy register to obtain a prefix copying stage circuit, perform Gray path processing on the prefix part of qubits in the copy register and the target register to obtain a Gray path stage circuit, perform an inversion process based on the suffix copying stage circuit, the Gray initialization stage circuit, the prefix copying stage circuit, and the Gray path stage circuit to obtain an inversion processing stage circuit, and obtain a diagonal unitary matrix quantum circuit based on the suffix copying stage circuit, the Gray initialization stage circuit, the prefix copying stage circuit, the Gray path stage circuit, and the inversion processing stage circuit.

[0301] In one embodiment, the circuit construction module is further configured to column-copy the suffix part of qubits in the input register according to the qubit copying method and copy them onto different qubits in the copy register to obtain a first controlled-NOT gate circuit, iteratively copy the suffix part of qubits that have been copied onto different qubits in the copy register in the row direction until the number of the suffix part of qubits in the copy register meets the suffix copying stage condition to obtain a second controlled-NOT gate circuit, and obtain a suffix copying stage circuit based on the first controlled-NOT gate circuit and the second controlled-NOT gate circuit.

[0302] In one embodiment, the circuit construction module is further configured to implement a matching target function on each qubit of the target register by copying the suffix part qubits in the register, obtain a third controlled-NOT gate circuit, determine a first phase matching each qubit of the target register respectively based on the target function matching each qubit, implement a phase rotation of the matching first phase on each qubit of the target register, obtain a first phase rotation circuit, and obtain a Gray initialization stage circuit based on the third controlled-NOT gate circuit and the first phase rotation circuit.

[0303] In one embodiment, the circuit construction module is further configured to determine qubit strings corresponding to each qubit of the target register respectively based on the target function matching each qubit, determine the phase corresponding to the qubit string, and use the phase corresponding to the qubit string as the first phase matching the qubit corresponding to the qubit string.

[0304] In one embodiment, the circuit construction module is further configured to perform a reduction process on the qubits in the copy register that have undergone the suffix processing stage, perform column copying on the prefix part qubits in the input register according to the qubit copying method, copy them to different qubits in the copy register, obtain a fourth controlled-NOT gate circuit, perform iterative copying on the prefix part qubits that have been copied to different qubits in the copy register in the row direction until the number of prefix part qubits in the copy register meets the prefix copying stage condition, obtain a fifth controlled-NOT gate circuit, and obtain a prefix copying stage circuit based on the fourth controlled-NOT gate circuit and the fifth controlled-NOT gate circuit.

[0305] In one embodiment, the circuit construction module is further configured to implement a target function transformation matching the current processing stage on each qubit of the target register by copying the prefix part qubits in the register at each processing stage of the Gray path processing, obtain a processing circuit for the current processing stage, and obtain a Gray path stage circuit based on the processing circuits for each processing stage in the Gray path processing.

[0306] In one embodiment, the circuit construction module is further configured to determine the qubit control bits acting on each qubit of the target register and the second phase matching each qubit respectively based on the target function transformation matching the current processing stage, implement the target function transformation control by copying the prefix part qubits in the register according to the qubit control bits, obtain a target function transformation circuit, implement a phase rotation of the matching second phase on each qubit of the target register, obtain a second phase rotation circuit, and obtain a processing circuit for the current processing stage according to the target function transformation circuit and the second phase rotation circuit.

[0307] In one embodiment, the second configuration module is further configured to configure an auxiliary register for the quantum state preparation circuit based on the number of auxiliary qubits. The circuit construction module is further configured to copy the prefix part of the qubits in the input register according to the qubit copying method, copy the prefix part of the qubits to the copy register, and copy the prefix part of the qubits to the auxiliary register to obtain the circuit in the prefix copying stage. The Gray path processing is performed on the prefix part of the qubits in the copy register, the prefix part of the qubits in the auxiliary register, and the target register to obtain the circuit in the Gray path stage.

[0308] Based on the same inventive concept, an embodiment of the present application further provides a quantum state preparation device for implementing the above-mentioned quantum state preparation method. The solution provided by the device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the quantum state preparation device provided below can refer to the limitations on the quantum state preparation method in the above text and will not be repeated here.

[0309] In one embodiment, a quantum state preparation device is provided, including: a preparation module, configured to perform quantum state preparation on the circuit initial state data based on a quantum state preparation circuit, and obtain quantum state data, where the quantum state preparation circuit is implemented by the above-mentioned quantum state preparation circuit generation method.

[0310] The above-mentioned quantum state preparation device can perform quantum state preparation on the circuit initial state data by using a quantum state preparation circuit with effectively compressed circuit depth, and obtain quantum state data, which can reduce the influence of decoherence.

[0311] Each module in the above-mentioned quantum state preparation circuit generation device and the quantum state preparation device can be implemented in whole or in part by software, hardware, and their combination. The above-mentioned modules can be embedded in the processor in the computer device in hardware form or independent of the processor, or stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the above-mentioned modules.

[0312] In one embodiment, a computer device is provided. The computer device can be a server, and its internal structure diagram can be as Figure 11As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O), and a communication interface. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data such as circuit preparation parameters. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals through a network connection. When the computer program is executed by the processor, it implements a method for generating a quantum state preparation circuit.

[0313] Those skilled in the art can understand that Figure 11 the structure shown in is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0314] In one embodiment, a computer device is further provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the steps in the above-mentioned embodiments of the method for generating a quantum state preparation circuit are implemented.

[0315] In one embodiment, a quantum computer is provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the steps in the above-mentioned embodiments of the quantum state preparation method are implemented.

[0316] In one embodiment, a computer-readable storage medium is provided, storing a computer program. When the computer program is executed by the processor, the steps in the above-mentioned method embodiments are implemented.

[0317] In one embodiment, a computer program product or a computer program is provided. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the steps in the above-mentioned method embodiments.

[0318] In one embodiment, a quantum device is provided. The quantum device realizes a quantum state preparation circuit through the above-mentioned method for generating a quantum state preparation circuit.

[0319] Among them, a quantum device refers to a device that uses the principles of quantum mechanics for computing. Based on the superposition principle and quantum entanglement of quantum mechanics, quantum devices have strong parallel processing capabilities and can solve some problems that are difficult to compute with classical computers. For example, a quantum device can specifically refer to a quantum computer. Another example is that a quantum device can specifically refer to a quantum chip. A quantum chip is the central processing unit of a quantum computer.

[0320] Specifically, a quantum device can implement a quantum state preparation circuit by executing a quantum program corresponding to the above-mentioned quantum state preparation circuit generation method. It should be noted that the implementation of the quantum state preparation circuit referred to in this embodiment means implementing the quantum state preparation circuit on actual quantum components, that is, the implemented quantum state preparation circuit is a physical circuit.

[0321] The above-mentioned quantum device can obtain a quantum state preparation circuit with effectively compressed circuit depth, achieving a reduction in the impact of decoherence.

[0322] It should be noted that the data involved in this application (including but not limited to data for analysis, stored data, displayed data, etc.) are all data authorized by users or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with relevant laws, regulations, and standards of relevant countries and regions.

[0323] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memories can include read-only memory (ROM), magnetic tapes, floppy disks, flash memories, optical memories, high-density embedded non-volatile memories, resistive random access memories (ReRAM), magnetoresistive random access memories (MRAM), ferroelectric random access memories (FRAM), phase change memories (PCM), graphene memories, etc. Volatile memories can include random access memory (RAM) or external cache memories, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logics, data processing logics based on quantum computing, etc., without limitation.

[0324] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0325] The above-described embodiments merely represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method for generating a quantum state preparation circuit, characterized in that The method for generating a quantum state preparation circuit includes: Based on the circuit preparation parameters of the quantum state preparation circuit, configure an input register for the quantum state preparation circuit and determine the number of auxiliary qubits; According to the number of auxiliary qubits, configure a copy register and a target register for the quantum state preparation circuit; According to the qubit copying method, perform circuit construction through the input register, the copy register, and the target register to obtain a diagonal unitary matrix quantum circuit, where the qubit copying method is obtained based on grid constraint conditions; the qubit copying method includes performing column copying on qubits under grid constraint conditions to obtain a column copying result, and performing row copying based on the column copying result; Combine the diagonal unitary matrix quantum circuit and single-qubit quantum gates to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit; Generate the quantum state preparation circuit based on at least one of the uniform control gate circuits.

2. The method according to claim 1, wherein The input register includes a prefix part qubit and a suffix part qubit; the performing circuit construction through the input register, the copy register, and the target register according to the qubit copying method to obtain a diagonal unitary matrix quantum circuit includes: According to the qubit copying method, copy the suffix part qubits in the input register, and copy the suffix part qubits into the copy register to obtain a suffix copying stage circuit; Perform Gray initialization processing through the suffix part qubits in the copy register and the target register to obtain a Gray initialization stage circuit; According to the qubit copying method, copy the prefix part qubits in the input register, and copy the prefix part qubits into the copy register to obtain a prefix copying stage circuit; Perform Gray path processing through the prefix part qubits in the copy register and the target register to obtain a Gray path stage circuit; Perform inversion processing based on the suffix copying stage circuit, the Gray initialization stage circuit, the prefix copying stage circuit, and the Gray path stage circuit to obtain an inversion processing stage circuit; Obtain a diagonal unitary matrix quantum circuit based on the suffix copying stage circuit, the Gray initialization stage circuit, the prefix copying stage circuit, the Gray path stage circuit, and the inversion processing stage circuit.

3. The method according to claim 2, wherein The performing, according to the qubit copying method, copying the suffix part qubits in the input register and copying the suffix part qubits into the copy register to obtain a suffix copying stage circuit includes: According to the qubit copying method, perform column copying on the suffix part qubits in the input register and copy them onto different qubits in the copy register to obtain a first controlled-NOT gate circuit; Iteratively copy the suffix part qubits that have been copied onto different qubits in the copy register in the row direction until the number of suffix part qubits in the copy register meets the suffix copying stage condition to obtain a second controlled-NOT gate circuit; Based on the first controlled-NOT gate circuit and the second controlled-NOT gate circuit, a suffix replication stage circuit is obtained.

4. The method according to claim 2, characterized in that, The Gray initialization stage circuit obtained by performing Gray initialization processing on the suffix part qubits in the replication register and the target register includes: By using the suffix part qubits in the replication register, a target function matching each qubit in the target register is implemented on each qubit in the target register to obtain a third controlled-NOT gate circuit; Based on the target function matching each qubit, a first phase matching each qubit in the target register is determined respectively; A phase rotation of the matching first phase is implemented on each qubit in the target register to obtain a first phase rotation circuit; Based on the third controlled-NOT gate circuit and the first phase rotation circuit, a Gray initialization stage circuit is obtained.

5. The method according to claim 4, wherein The step of respectively determining a first phase matching each qubit in the target register based on the target function matching each qubit includes: Based on the target function matching each qubit, a qubit string corresponding to each qubit in the target register is determined respectively; Determine the phase corresponding to the qubit string; Take the phase corresponding to the qubit string as the first phase matching the qubit corresponding to the qubit string.

6. The method according to claim 2, wherein The prefix replication stage circuit obtained by replicating the prefix part qubits in the input register according to the qubit replication method and copying the prefix part qubits into the replication register includes: Perform a reduction process on the qubits in the replication register that have passed through the suffix processing stage; According to the qubit replication method, perform column replication on the prefix part qubits in the input register and copy them to different qubits in the replication register to obtain a fourth controlled-NOT gate circuit; Iteratively replicate the prefix part qubits that have been copied to different qubits in the replication register in the row direction until the number of prefix part qubits in the replication register meets the prefix replication stage condition to obtain a fifth controlled-NOT gate circuit; Based on the fourth controlled-NOT gate circuit and the fifth controlled-NOT gate circuit, a prefix replication stage circuit is obtained.

7. The method according to claim 2, characterized in that The Gray path stage circuit obtained by performing Gray path processing on the prefix part qubits in the replication register and the target register includes: In each processing stage of the Gray path processing, by using the prefix part qubits in the replication register, a target function transformation matching the current processing stage is implemented on each qubit in the target register to obtain the processing circuit of the current processing stage; Based on the processing circuits of each processing stage in the Gray path processing, a Gray path stage circuit is obtained.

8. The method according to claim 7, wherein The step of obtaining the processing circuit of the current processing stage by implementing a target function transformation matching the current processing stage on each qubit in the target register by using the prefix part qubits in the replication register includes: Based on the objective function transformation matching the current processing stage, respectively determine the qubit control bits acting on each qubit of the target register and the second phase matching each qubit; According to the qubit control bits, implement the objective function transformation control through the prefix part qubits in the copy register to obtain the objective function transformation circuit; Implement the phase rotation of the matching second phase on each qubit of the target register to obtain the second phase rotation circuit; According to the objective function transformation circuit and the second phase rotation circuit, obtain the processing circuit of the current processing stage.

9. The method according to claim 2, characterized in that, The method further includes: Based on the number of auxiliary qubits, configure an auxiliary register for the quantum state preparation circuit; The prefix copy stage circuit that copies the prefix part qubits in the input register to the copy register according to the qubit copying method includes: According to the qubit copying method, copy the prefix part qubits in the input register to the copy register and also copy the prefix part qubits to the auxiliary register to obtain the prefix copy stage circuit; The Gray path stage circuit obtained by performing Gray path processing on the prefix part qubits in the copy register and the target register includes: Perform Gray path processing on the prefix part qubits in the copy register, the prefix part qubits in the auxiliary register, and the target register to obtain the Gray path stage circuit.

10. A method for preparing a quantum state, characterized in that, The quantum state preparation method includes: Perform quantum state preparation on the circuit initial state data based on the quantum state preparation circuit to obtain quantum state data, and the quantum state preparation circuit is implemented by the quantum state preparation circuit generation method according to any one of claims 1 to 9.

11. A quantum state preparation circuit generation device, characterized in that, The device includes: A first configuration module, configured to configure an input register for the quantum state preparation circuit based on the circuit preparation parameters of the quantum state preparation circuit and determine the number of auxiliary qubits; A second configuration module, configured to configure a copy register and a target register for the quantum state preparation circuit according to the number of auxiliary qubits; A circuit construction module, configured to perform circuit construction through the input register, the copy register, and the target register according to the qubit copying method to obtain a diagonal unitary matrix quantum circuit, where the qubit copying method is obtained based on grid constraint conditions; the qubit copying method includes column copying of qubits under grid constraint conditions to obtain a column copying result, and row copying is performed based on the column copying result; A circuit combination module, configured to combine the diagonal unitary matrix quantum circuit and single-bit quantum gates to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit; A processing module, configured to generate the quantum state preparation circuit based on at least one of the uniform control gate circuits.

12. The device according to claim 11, characterized in that, The input register includes a prefix partial qubit and a suffix partial qubit; the circuit construction module is further configured to copy the suffix partial qubit in the input register according to the qubit copying method, copy the suffix partial qubit into the copy register to obtain a suffix copy stage circuit, perform Gray initialization processing on the target register through the suffix partial qubit in the copy register to obtain a Gray initialization stage circuit, copy the prefix partial qubit in the input register according to the qubit copying method, copy the prefix partial qubit into the copy register to obtain a prefix copy stage circuit, perform Gray path processing on the target register through the prefix partial qubit in the copy register to obtain a Gray path stage circuit, perform an inversion process based on the suffix copy stage circuit, the Gray initialization stage circuit, the prefix copy stage circuit, and the Gray path stage circuit to obtain an inversion processing stage circuit, and obtain a diagonal unitary matrix quantum circuit based on the suffix copy stage circuit, the Gray initialization stage circuit, the prefix copy stage circuit, the Gray path stage circuit, and the inversion processing stage circuit.

13. The device according to claim 12, characterized in that, The circuit construction module is further configured to perform column copying on the suffix partial qubit in the input register according to the qubit copying method, copy it onto different qubits in the copy register to obtain a first controlled-NOT gate circuit, perform iterative copying on the suffix partial qubit that has been copied onto different qubits in the copy register in the row direction until the number of suffix partial qubits in the copy register meets the suffix copy stage condition to obtain a second controlled-NOT gate circuit, and obtain a suffix copy stage circuit based on the first controlled-NOT gate circuit and the second controlled-NOT gate circuit.

14. The device according to claim 12, characterized in that, The circuit construction module is further configured to implement a matching target function on each qubit of the target register through the suffix partial qubit in the copy register to obtain a third controlled-NOT gate circuit, respectively determine a first phase matching each qubit of the target register based on the matching target function of each qubit, perform a phase rotation of the matching first phase on each qubit of the target register to obtain a first phase rotation circuit, and obtain a Gray initialization stage circuit based on the third controlled-NOT gate circuit and the first phase rotation circuit.

15. The device according to claim 14, wherein The circuit construction module is further configured to respectively determine a qubit string corresponding to each qubit of the target register based on the matching target function of each qubit, determine a phase corresponding to the qubit string, and use the phase corresponding to the qubit string as the first phase matching the qubit corresponding to the qubit string.

16. The device according to claim 12, characterized in that, The circuit construction module is further configured to perform a reduction process on the qubits in the replication register that have undergone the suffix processing stage. According to the qubit replication method, the prefix qubits in the input register are column-replicated and copied onto different qubits in the replication register to obtain a fourth controlled-NOT gate circuit. The prefix qubits that have been copied onto different qubits in the replication register are iteratively replicated in the row direction until the number of prefix qubits in the replication register meets the conditions of the prefix replication stage, obtaining a fifth controlled-NOT gate circuit. Based on the fourth controlled-NOT gate circuit and the fifth controlled-NOT gate circuit, a prefix replication stage circuit is obtained.

17. The device according to claim 12, characterized in that, The circuit construction module is further configured to, in each processing stage of the Gray path processing, implement a target function transformation that matches the current processing stage on each qubit of the target register through the prefix qubits in the replication register, obtaining a processing circuit for the current processing stage. Based on the processing circuits for each processing stage in the Gray path processing, a Gray path stage circuit is obtained.

18. The device according to claim 17, wherein The circuit construction module is further configured to, based on a target function transformation that matches the current processing stage, respectively determine the qubit control bits acting on each qubit of the target register and the second phase that matches each qubit. According to the qubit control bits, the target function transformation control is implemented through the prefix qubits in the replication register to obtain a target function transformation circuit. The phase rotation of the matching second phase is implemented on each qubit of the target register to obtain a second phase rotation circuit. According to the target function transformation circuit and the second phase rotation circuit, a processing circuit for the current processing stage is obtained.

19. The device according to claim 12, characterized in that, The second configuration module is further configured to configure an auxiliary register for the quantum state preparation circuit based on the number of auxiliary qubits. The circuit construction module is further configured to, according to the qubit replication method, replicate the prefix qubits in the input register, copy the prefix qubits into the replication register, and copy the prefix qubits into the auxiliary register to obtain a prefix replication stage circuit. Gray path processing is performed through the prefix qubits in the replication register, the prefix qubits in the auxiliary register, and the target register to obtain a Gray path stage circuit.

20. A quantum state preparation device, characterized in that, The quantum state preparation device includes: A preparation module, configured to perform quantum state preparation on the circuit initial state data based on a quantum state preparation circuit to obtain quantum state data, where the quantum state preparation circuit is implemented by the quantum state preparation circuit generation method according to any one of claims 1 to 9.

21. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, the steps of the method according to any one of claims 1 to 10 are implemented.

22. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 10 are implemented.

23. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 10 are implemented.

24. A quantum device, characterized in that, The quantum device realizes a quantum state preparation circuit through the method for generating a quantum state preparation circuit according to any one of claims 1 to 9.

Images