A gate driving circuit and display device

Abstract

The application provides a gate drive circuit and a display device. The gate drive circuit comprises a plurality of gate drive units connected in cascade. Each gate drive unit comprises a forward and reverse scanning control module, a first output module, a second output module and a stabilization module. The forward and reverse scanning control module controls the high and low potentials of a first node according to a first gate signal provided by a previous stage and a next stage gate drive unit connected in cascade during forward and reverse scanning. The first output module is connected to the first node and the forward and reverse scanning control module, and outputs the first gate signal at a first output end according to a first clock signal. The second output module is connected to the first node and the forward and reverse scanning control module, and outputs a second gate signal at a second output end according to a second clock signal. The stabilization module is connected to the first node, the first output end and the second output end, and is used to maintain a low potential. The application can support forward and reverse scanning, effectively save the space occupied by the gate drive circuit, and realize a narrow frame of the display device.

Description

Technical Field

[0001] This invention relates to the field of display driving technology, and in particular to a gate driving circuit and a display device. Background Technology

[0002] Display devices, such as liquid crystal displays (LCDs), have gradually replaced traditional cathode ray tube displays due to their numerous advantages, including being lightweight, energy-efficient, and radiation-free. They are widely used in electronic devices such as high-definition digital televisions, desktop computers, personal digital assistants, laptops, mobile phones, and digital cameras.

[0003] Narrow bezel display technology is rapidly gaining popularity and gradually becoming the mainstream display technology. However, existing gate drive circuits occupy a large space, can only scan in the forward direction and not in the reverse direction, and each gate drive unit only outputs a single gate signal, requiring a large number of gate drive units, which is not conducive to the realization of narrow bezel LCD displays. Summary of the Invention

[0004] In view of this, the present invention provides a gate driving circuit and a display device that can support forward and reverse scanning, effectively save the space occupied by the gate driving circuit, and achieve a narrow bezel in the display device.

[0005] This invention provides a gate driving circuit, including multiple cascaded gate driving units. Each gate driving unit includes a forward and reverse scan control module, a first output module, a second output module, and a stabilization module. The forward and reverse scanning control module is connected to the first node. During forward scanning, it pulls the first node up to a high level according to the first gate signal output by the cascaded preceding gate driving unit, and pulls the first node down to a low level according to the first gate signal output by the cascaded following gate driving unit. During reverse scanning, it pulls the first node up to a high level according to the first gate signal output by the cascaded following gate driving unit, and pulls the first node down to a low level according to the first gate signal output by the cascaded preceding gate driving unit. The first output module is connected to the forward and reverse scanning control module and is connected to the first node. It outputs a first gate signal at the first output terminal according to a first clock signal. The second output module is connected to the forward and reverse scanning control module and is connected to the first node. It outputs a second gate signal at the second output terminal according to a second clock signal. The stabilization module is connected to the first node, the first output terminal, and the second output terminal. The stabilization module is used to maintain the first node, the first output terminal, and the second output terminal at a low level when the first node is pulled down to a low level.

[0006] Specifically, the forward and reverse scanning control module includes a first switching element and a second switching element; the first switching element includes a first control terminal, a first path terminal, and a second path terminal; the first control terminal of the first switching element receives a first gate signal output by the cascaded previous stage gate driving unit, the first path terminal of the first switching element receives a first reference voltage, and the second path terminal of the first switching element is connected to the first node; the second switching element includes a second control terminal, a third path terminal, and a fourth path terminal; the second control terminal of the second switching element receives the first gate signal output by the cascaded previous stage gate driving unit, the third path terminal of the second switching element receives a second reference voltage, and the fourth path terminal of the second switching element is connected to the first node; wherein, during forward scanning, the first reference voltage is high and the second reference voltage is low; during reverse scanning, the first reference voltage is low and the second reference voltage is high.

[0007] Specifically, the first output module includes a third switching element; the third switching element includes a third control terminal, a fifth path terminal, and a sixth path terminal; the third control terminal of the third switching element is connected to the first node, the fifth path terminal of the third switching element receives the first clock signal, and the sixth path terminal of the third switching element is connected to the first output terminal; and / or, the second output module includes a fourth switching element; the fourth switching element includes a fourth control terminal, a seventh path terminal, and an eighth path terminal; the fourth control terminal of the fourth switching element is connected to the first node, the seventh path terminal of the fourth switching element receives the second clock signal, and the eighth path terminal of the fourth switching element is connected to the second output terminal.

[0008] Specifically, the stabilization module includes a fifth switching element, a sixth switching element, a seventh switching element, an eighth switching element, and a ninth switching element; the fifth switching element includes a fifth control terminal, a ninth path terminal, and a tenth path terminal; the ninth path terminal of the fifth switching element is connected to the fifth control terminal of the fifth switching element and receives a third reference voltage, and the tenth path terminal of the fifth switching element is connected to a second node; the sixth switching element includes a sixth control terminal, an eleventh path terminal, and a twelfth path terminal; the sixth control terminal of the sixth switching element is connected to the first node, the eleventh path terminal of the sixth switching element is connected to the tenth path terminal of the fifth switching element, and the twelfth path terminal of the sixth switching element receives a fourth reference voltage; the seventh switching element includes a seventh control terminal, a thirteenth path terminal, and a fourteenth path terminal; the seventh control terminal of the seventh switching element is connected to... The tenth path terminal of the fifth switching element is connected, the thirteenth path terminal of the seventh switching element is connected to the first node, and the fourteenth path terminal of the seventh switching element receives the fourth reference voltage; the eighth switching element includes an eighth control terminal, a fifteenth path terminal, and a sixteenth path terminal; the eighth control terminal of the eighth switching element is connected to the tenth path terminal of the fifth switching element, the fifteenth path terminal of the eighth switching element is connected to the first output terminal, and the sixteenth path terminal of the eighth switching element receives the fourth reference voltage; the ninth switching element includes a ninth control terminal, a seventeenth path terminal, and an eighteenth path terminal; the ninth control terminal of the ninth switching element is connected to the tenth path terminal of the fifth switching element, the seventeenth path terminal of the ninth switching element is connected to the second output terminal, and the eighteenth path terminal of the ninth switching element receives the fourth reference voltage.

[0009] Specifically, the stabilization module further includes a tenth switching element and an eleventh switching element; the tenth switching element includes a tenth control terminal, a nineteenth path terminal, and a twentieth path terminal; the tenth control terminal of the tenth switching element receives a third clock signal, the nineteenth path terminal of the tenth switching element is connected to the first output terminal, and the twentieth path terminal of the tenth switching element receives the fourth reference voltage; the eleventh switching element includes an eleventh control terminal, a twenty-first path terminal, and a twenty-second path terminal, the eleventh control terminal of the eleventh switching element receives the fourth clock signal, the twenty-first path terminal of the eleventh switching element is connected to the second output terminal, and the twenty-second path terminal of the eleventh switching element receives the fourth reference voltage.

[0010] Specifically, the stabilization module further includes a twelfth switching element and a thirteenth switching element; the twelfth switching element includes a twelfth control terminal, a twenty-third channel terminal, and a twenty-fourth channel terminal; the twelfth control terminal of the twelfth switching element receives a screen clearing signal, the twenty-third channel terminal of the twelfth switching element is connected to the first output terminal, and the twenty-fourth channel terminal of the twelfth switching element receives the fourth reference voltage; the thirteenth switching element includes a thirteenth control terminal, a twenty-fifth channel terminal, and a twenty-sixth channel terminal, the thirteenth control terminal of the thirteenth switching element receives the screen clearing signal, the twenty-fifth channel terminal of the thirteenth switching element is connected to the second output terminal, and the twenty-sixth channel terminal of the thirteenth switching element receives the fourth reference voltage.

[0011] Specifically, in the gate driving circuit, each gate driving unit is arranged adjacent to the cascaded previous stage gate driving unit, and the first clock signal and the second clock signal have the same time period and are phased by 1 / 4 time period; or, each gate driving unit is arranged spaced apart from the cascaded previous stage gate driving unit, and the first clock signal and the second clock signal have the same time period and are phased by 1 / 8 time period.

[0012] Specifically, when the gate driving unit is in the starting or ending position of the gate driving circuit, it receives a start signal or an end signal provided by an external signal circuit.

[0013] Specifically, the gate driving unit further includes one or more of a first capacitor, a second capacitor, and a third capacitor; a first terminal of the first capacitor is connected to the first node, and a second terminal of the first capacitor is connected to a fourth reference voltage; a first terminal of the second capacitor is connected to the first node, and a second terminal of the second capacitor is connected to the first output terminal; a first terminal of the third capacitor is connected to the first node, and a second terminal of the third capacitor is connected to the second output terminal.

[0014] This invention also provides a display device including the gate driving circuit described above.

[0015] The gate driving circuit and display device provided by the present invention can support forward and reverse scanning, and can perform dual-stage output through the gate driving unit, thereby reducing the number of gate driving units, effectively saving the space occupied by the gate driving circuit, and realizing a narrow bezel of the display device.

[0016] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] Figure 1 This is a circuit connection diagram of the gate driving unit according to the first embodiment of the present invention.

[0018] Figure 2 This is a circuit connection diagram of the gate driving unit according to the second embodiment of the present invention.

[0019] Figure 3 yes Figure 2 Timing diagrams of the various input and output signals in the embodiment.

[0020] Figure 4 This is a circuit connection diagram of the gate driving unit according to the third embodiment of the present invention.

[0021] Figure 5 yes Figure 4 The timing diagrams of each input and output signal in the embodiment are shown.

[0022] Figure 6 This is a circuit connection diagram of the gate driving unit according to the fourth embodiment of the present invention. Detailed Implementation

[0023] To further illustrate the technical means and effects of the present invention in order to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, describes the specific implementation methods, steps, structures, features and effects of the gate driving circuit and display device proposed according to the present invention.

[0024] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the present invention.

[0025] Figure 1 This is a circuit connection diagram of the gate driving unit according to the first embodiment of the present invention. Please refer to [link / reference]. Figure 1 The gate driving circuit of this embodiment includes multiple cascaded gate driving units, each gate driving unit including: forward and reverse scan control module 10, first output module 20, second output module 30, and stabilization module 40.

[0026] The forward and reverse scanning control module 10 is connected to the first node Q. During forward scanning, the first node Q is pulled up to a high level according to the first gate signal output by the cascaded previous stage gate driving unit, and pulled down to a low level according to the first gate signal output by the cascaded next stage gate driving unit. During reverse scanning, the first node Q is pulled up to a high level according to the first gate signal output by the cascaded next stage gate driving unit, and pulled down to a low level according to the first gate signal output by the cascaded previous stage gate driving unit.

[0027] The first output module 20 is connected to the forward and reverse scanning control module 10 at the first node Q, and outputs the first gate signal Gn at the first output terminal according to the first clock signal CLK1.

[0028] The second output module 30 is connected to the forward and reverse scanning control module 10 at the first node Q, and outputs the second gate signal Gn+1 at the second output terminal according to the second clock signal CLK2.

[0029] The stabilization module 40 is connected to the first node Q, the first output terminal, and the second output terminal. The stabilization module 40 is used to keep the first node Q, the first output terminal, and the second output terminal at a low level when the first node Q is pulled down to a low level.

[0030] It is worth noting that, since the gate driving unit receives a start signal or an end signal from an external signal circuit when it is at the start or end position of the gate driving circuit, and there is no corresponding cascaded preceding gate driving unit providing the first gate signal, the gate driving unit receives the start signal or end signal from the external signal circuit. For example, if the starting gate driving unit does not have a cascaded preceding gate driving unit, the first gate signal output by the cascaded preceding gate driving unit required by the forward and reverse scan control module 10 of the starting gate driving unit needs to be provided by an external signal circuit, such as directly provided by the timing control circuit or provided via the source driving circuit.

[0031] In one embodiment of the present invention, such as Figure 1As shown, the forward and reverse scanning control module 10 may include a first switching element T1 and a second switching element T2. The first switching element T1 includes a first control terminal, a first path terminal, and a second path terminal. The first control terminal of the first switching element T1 receives a first gate signal output by the cascaded previous stage gate driving unit, the first path terminal of the first switching element T1 receives a first reference voltage DC_H, and the second path terminal of the first switching element T1 is connected to the first node Q. The second switching element T2 includes a second control terminal, a third path terminal, and a fourth path terminal. The second control terminal of the second switching element T2 receives the first gate signal output by the cascaded previous stage gate driving unit, the third path terminal of the second switching element T2 receives a second reference voltage DC_L, and the fourth path terminal of the second switching element T2 is connected to the first node Q. During forward scanning, the first reference voltage DC_H is high and the second reference voltage DC_L is low; during reverse scanning, the first reference voltage DC_H is low and the second reference voltage DC_L is high.

[0032] In one embodiment of the present invention, such as Figure 1 As shown, the first output module 20 may include a third switching element T3; the third switching element T3 includes a third control terminal, a fifth path terminal and a sixth path terminal; the third control terminal of the third switching element T3 is connected to the first node Q, the fifth path terminal of the third switching element T3 receives the first clock signal CLK1, and the sixth path terminal of the third switching element T3 is connected to the first output terminal.

[0033] In one embodiment of the present invention, such as Figure 1 As shown, the second output module 30 may include a fourth switching element T4; the fourth switching element T4 includes a fourth control terminal, a seventh path terminal and an eighth path terminal; the fourth control terminal of the fourth switching element T4 is connected to the first node Q, the seventh path terminal of the fourth switching element T4 receives the second clock signal CLK2, and the eighth path terminal of the fourth switching element T4 is connected to the second output terminal.

[0034] In one embodiment of the present invention, such as Figure 1As shown, the stabilization module 40 may include a fifth switching element T5, a sixth switching element T6, a seventh switching element T7, an eighth switching element T8, and a ninth switching element T9; the fifth switching element T5 includes a fifth control terminal, a ninth path terminal, and a tenth path terminal; the ninth path terminal of the fifth switching element T5 is connected to the fifth control terminal of the fifth switching element T5 and receives a third reference voltage DC, and the tenth path terminal of the fifth switching element T5 is connected to the second node QB; the sixth switching element T6 includes a sixth control terminal, an eleventh path terminal, and a twelfth path terminal; the sixth control terminal of the sixth switching element T6 is connected to the first node Q, the eleventh path terminal of the sixth switching element T6 is connected to the tenth path terminal of the fifth switching element T5, and the twelfth path terminal of the sixth switching element T6 receives a fourth reference voltage VGL; the seventh switching element T7 includes a seventh control terminal, a thirteenth path terminal, and a fourteenth path terminal; the seventh switching element... The seventh control terminal of T7 is connected to the tenth path terminal of the fifth switching element T5, the thirteenth path terminal of the seventh switching element T7 is connected to the first node Q, and the fourteenth path terminal of the seventh switching element T7 receives the fourth reference voltage VGL; the eighth switching element T8 includes an eighth control terminal, a fifteenth path terminal, and a sixteenth path terminal; the eighth control terminal of the eighth switching element T8 is connected to the tenth path terminal of the fifth switching element T5, the fifteenth path terminal of the eighth switching element T8 is connected to the first output terminal, and the sixteenth path terminal of the eighth switching element T8 receives the fourth reference voltage VGL; the ninth switching element T9 includes a ninth control terminal, a seventeenth path terminal, and an eighteenth path terminal; the ninth control terminal of the ninth switching element T9 is connected to the tenth path terminal of the fifth switching element T5, the seventeenth path terminal of the ninth switching element T9 is connected to the second output terminal, and the eighteenth path terminal of the ninth switching element T9 receives the fourth reference voltage VGL.

[0035] In one embodiment of the present invention, such as Figure 1As shown, the gate driving unit further includes one or more of a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first terminal of the first capacitor C1 is connected to the first node Q, and the second terminal of the first capacitor C1 is connected to the fourth reference voltage VGL. The first terminal of the second capacitor C2 is connected to the first node Q, and the second terminal of the second capacitor C2 is connected to the first output terminal. The first terminal of the third capacitor C3 is connected to the first node Q, and the second terminal of the third capacitor C3 is connected to the second output terminal. Since each gate driving unit has a two-stage output, the coupling frequency of the clock signal to the first node Q increases, leading to increased noise. The first capacitor C1 can effectively stabilize the first node Q, reduce noise, and improve circuit reliability. Simultaneously, one terminal of the first capacitor C1 receives the fourth reference voltage VGL. During the XON startup phase, the fourth reference voltage VGL can be set to a high level. Through the coupling effect of the first capacitor C1, the first node Q can be quickly coupled, causing the voltage of the first node Q to rise instantaneously, accelerating panel discharge, effectively reducing power-off ghosting, and improving panel image quality.

[0036] In one embodiment of the present invention, the second capacitor C2 may be, but is not limited to, an external capacitor between the first node Q and the first output terminal. By utilizing the coupling effect of the capacitor, the voltage pull-up effect of the first node Q can be improved. The third capacitor C3 may be, but is not limited to, an external capacitor between the first node Q and the second output terminal. By utilizing the coupling effect of the capacitor, the voltage pull-up effect of the first node Q can be improved.

[0037] In one embodiment of the present invention, such as Figure 1 As shown, in the gate driving circuit, each gate driving unit is arranged adjacent to the cascaded preceding gate driving unit. In one embodiment, the first clock signal CLK1 and the second clock signal CLK2 have the same time period (e.g., 4T) and are phase-differentiated by 1 / 4 time period (e.g., T). Thus, each gate driving unit receives the first gate signal Gn-2 from the adjacent cascaded preceding gate driving unit and also receives the first gate signal Gn+2 from the adjacent cascaded following gate driving unit; and when outputting the gate signal through the gate driving unit, the four clock signals CLK1 and CLK2 received by the odd-numbered row gate driving units and CLK1 and CLK2 received by the even-numbered row gate driving units can have the same time period (e.g., 4T) and are sequentially phase-differentiated by 1 / 4 time period (e.g., T). However, the present invention is not limited thereto. Those skilled in the art can make other settings for the first clock signal CLK1 and the second clock signal CLK2 according to their needs. For example, the first clock signal CLK1 and the second clock signal CLK2 can be set to have the same time period (e.g., 6T) and the phase difference can be 1 / 6 time period (e.g., T). All such technical solutions are within the protection scope of the present invention.

[0038] Figure 2 This is a circuit connection diagram of the gate driving unit according to the second embodiment of the present invention. Please refer to... Figure 2 This embodiment provides a gate driving circuit with the same structure as the first embodiment, except that the stabilization module 40 may further include a tenth switching element T10 and an eleventh switching element T11. The tenth switching element T10 includes a tenth control terminal, a nineteenth path terminal, and a twentieth path terminal. The tenth control terminal of the tenth switching element T10 receives a third clock signal CLK3, the nineteenth path terminal of the tenth switching element T10 is connected to the first output terminal, and the twentieth path terminal of the tenth switching element T10 receives a fourth reference voltage VGL. The eleventh switching element T11 includes an eleventh control terminal, a twenty-first path terminal, and a twenty-second path terminal. The eleventh control terminal of the eleventh switching element T11 receives a fourth clock signal CLK4, the twenty-first path terminal of the eleventh switching element T11 is connected to the second output terminal, and the twenty-second path terminal of the eleventh switching element T11 receives the fourth reference voltage VGL.

[0039] In one embodiment of the present invention, the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 have the same time period (e.g., 4T), the first clock signal CLK1 and the second clock signal CLK2 are out of phase by 1 / 4 time period (e.g., T), the third clock signal CLK3 and the fourth clock signal CLK4 are out of phase by 1 / 4 time period (e.g., T), and the first clock signal CLK1 and the third clock signal CLK3 are out of phase by 1 / 2 time period (e.g., 2T).

[0040] In one embodiment of the present invention, the first switching element T1 to the eleventh switching element T11 may be, but is not limited to, an N-type TFT, an NMOS transistor, or an N-type triode. The corresponding first control terminal to the eleventh control terminal of the first switching element T1 to the eleventh switching element T11 are all gates. The corresponding pass terminals of the first switching element T1 to the eleventh switching element T11 are drains or sources.

[0041] Figure 3 yes Figure 2 Timing diagrams of the various input and output signals in the embodiment are shown below. Figure 2 and Figure 3 Taking an example where each gate driving unit is adjacent to the cascaded gate driving unit of the previous stage, the first clock signal CLK1 and the second clock signal CLK2 have the same time period (e.g., 4T) and the phase difference is 1 / 4 time period (e.g., T), and the first switching element T1 to the eleventh switching element T11 are N-type TFTs, the working process of the gate driving unit in this embodiment is explained. The working process of the gate driving unit includes four stages: pre-charge stage, output stage, pull-down stage, and stabilization stage.

[0042] Pre-charging phase:

[0043] During forward scanning, the first gate signal Gn-2 output by the cascaded preceding gate driving unit transitions from low to high. The forward / reverse scanning control module 10 pulls the first node Q to high based on the first gate signal Gn-2 output by the cascaded preceding gate driving unit. During reverse scanning, the first gate signal Gn+2 output by the cascaded following gate driving unit transitions from low to high. The forward / reverse scanning control module 10 pulls the first node Q to high based on the first gate signal Gn+2 output by the cascaded following gate driving unit. Thus, the first node Q can be stably pulled to a high level, enabling the first output module 20 and the second output module 30 to enter the working state.

[0044] In one embodiment of the present invention, during forward scanning, the first control terminal of the first switching element T1 receives the first gate signal Gn-2 output by the cascaded previous stage gate driving unit, which transitions from a low level to a high level, thus turning on the first switching element T1. The first node Q, connected to the second path terminal of the first switching element T1, receives the first reference voltage DC_H through the turned-on first switching element T1. Since the first reference voltage DC_H is high (e.g., 18V) during forward scanning, the first node Q is charged and pulled up to a high level. During reverse scanning, the second control terminal of the second switching element T2 receives the first gate signal Gn+2 output by the cascaded next stage gate driving unit, which transitions from a low level to a high level, thus turning on the second switching element T2. The first node Q, connected to the third path terminal of the second switching element T2, receives the second reference voltage DC_L through the turned-on second switching element T2. Since the second reference voltage DC_L is high (e.g., 18V) during reverse scanning, the first node Q is charged and pulled up to a high level.

[0045] In one embodiment of the present invention, when the first node Q is charged and pulled up to a high level, the third control terminal of the third switching element T3 and the fourth control terminal of the fourth switching element T4 connected to the first node Q become high level, and the third switching element T3 and the fourth switching element T4 become conducting; thus, the first output module 20 and the second output module 30 enter the working state.

[0046] In one embodiment of the present invention, when the first node Q is charged and pulled up to a high level, the sixth control terminal of the sixth switching element T6 connected to the first node Q becomes high, and the sixth switching element T6 becomes on. Thus, the second node QB connected to the eleventh path terminal of the sixth switching element T6 receives the fourth reference voltage VGL through the on-state sixth switching element T6. The fourth reference voltage VGL can be a low level, such as -7V, which can be supplied by an internal circuit or an external driving system. The signal is stable and can effectively stabilize the first node Q. When the second node QB is pulled down to a low level, the seventh control terminal of the seventh switching element T7, the eighth control terminal of the eighth switching element T8, and the ninth control terminal of the ninth switching element T9 connected to the second node QB are low, and the seventh switching element T7, the eighth switching element T8, and the ninth switching element T9 are off. The stabilization module 40 enters a non-working state and has no effect on the first and second output terminals.

[0047] Output phase:

[0048] The first node Q is pulled up to a high level. According to the first clock signal CLK1 transitioning from low to high, the first output terminal of the first output module 20 receives the first clock signal CLK1 and outputs the first gate signal Gn. In one embodiment of the invention, the sixth path terminal of the third switching element T3 is connected to the first output terminal. The first output terminal receives the first clock signal CLK1 from the fifth path terminal of the third switching element T3 through the conducting third switching element T3, thereby outputting the first gate signal Gn. In another embodiment of the invention, the first node Q is further pulled up by the second capacitor C2, causing the level of the first node Q to rise further, fully opening the third switching element T3.

[0049] Furthermore, according to the transition of the second clock signal CLK2 from low to high, the second output terminal of the second output module 30 receives the second clock signal CLK2 and outputs the second gate signal Gn+1 at the second output terminal. In one embodiment of the present invention, the eighth path terminal of the fourth switching element T4 is connected to the second output terminal, and the second output terminal receives the second clock signal CLK2 on the seventh path terminal of the fourth switching element T4 through the conducting fourth switching element T4, thereby outputting the second gate signal Gn+1 at the second output terminal. In one embodiment of the present invention, the first node Q is further pulled up by the third capacitor C3 to further increase the level of the first node Q and fully turn on the fourth switching element T4.

[0050] Drop-down phase:

[0051] During forward scanning, the first gate signal Gn+2 output by the cascaded subsequent gate drive unit transitions from low to high. The forward / reverse scanning control module 10 pulls the first node Q down to low based on the first gate signal Gn+2 output by the cascaded subsequent gate drive unit. During reverse scanning, the first gate signal Gn-2 output by the cascaded preceding gate drive unit transitions from low to high. The forward / reverse scanning control module 10 pulls the first node Q down to high based on the first gate signal Gn-2 output by the cascaded preceding gate drive unit. Thus, the first node Q can be stably pulled down to low, causing the first output module 20 and the second output module 30 to enter a non-operating state.

[0052] In one embodiment of the present invention, during forward scanning, the second control terminal of the second switching element T2 receives the first gate signal Gn+2 output by the cascaded subsequent gate driving unit, which transitions from a low level to a high level, thus turning on the second switching element T2. The first node Q, connected to the third path terminal of the second switching element T2, receives the second reference voltage DC_L through the turned-on second switching element T2. Since the second reference voltage DC_L is low (e.g., -7V) during forward scanning, the first node Q discharges and is pulled down to a low level. During reverse scanning, the first control terminal of the first switching element T1 receives the first gate signal Gn-2 output by the cascaded preceding gate driving unit, which transitions from a low level to a high level, thus turning on the first switching element T1. The first node Q, connected to the second path terminal of the first switching element T1, receives the first reference voltage DC_H through the turned-on first switching element T1. Since the first reference voltage DC_H is low (e.g., -7V) during reverse scanning, the first node Q discharges and is pulled down to a low level.

[0053] In one embodiment of the present invention, when the first node Q is pulled down to a low level, the third control terminal of the third switch element T3 and the fourth control terminal of the fourth switch element T4 connected to the first node Q become low level, and the third switch element T3 and the fourth switch element T4 become disconnected, thereby causing the first output module 20 and the second output module 30 to enter a non-working state.

[0054] In one embodiment of the present invention, when the first node Q discharges and is pulled down to a low level, the sixth control terminal of the sixth switching element T6 connected to the first node Q becomes low, and the sixth switching element T6 becomes open. Simultaneously, the fifth control terminal and the ninth path terminal of the fifth switching element T5 receive the third reference voltage DC, making the fifth switching element T5 conduct. The third reference voltage DC can be a high level, such as 5V. Therefore, the second node QB connected to the eleventh path terminal of the sixth switching element T6 can receive the third reference voltage DC through the conducting fifth switching element T5. C. When the second node QB is pulled up to a high level, the seventh control terminal of the seventh switch element T7, the eighth control terminal of the eighth switch element T8, and the ninth control terminal of the ninth switch element T9 connected to the second node QB are at a high level. Then, the seventh switch element T7, the eighth switch element T8, and the ninth switch element T9 are in a conducting state, and the stabilization module 40 enters the working state. Then, the first node Q, the first output terminal, and the second output terminal receive the fourth reference voltage VGL through the conducting seventh switch element T7, the eighth switch element T8, and the ninth switch element T9 respectively, and are pulled down to a low level.

[0055] In one embodiment of the present invention, when the third clock signal CLK3 transitions from low to high, the tenth control terminal of the tenth switching element T10 receives the third clock signal CLK3 as high, and the nineteenth path terminal of the tenth switching element T10 is connected to the first output terminal. The first output terminal receives the fourth reference voltage VGL through the conducting tenth switching element T10 and is pulled down to a low level. Furthermore, when the fourth clock signal CLK4 transitions from low to high, the eleventh control terminal of the eleventh switching element T11 receives the fourth clock signal CLK4 as high, and the twenty-first path terminal of the eleventh switching element T11 is connected to the second output terminal. The second output terminal receives the fourth reference voltage VGL through the conducting eleventh switching element T11 and is pulled down to a low level.

[0056] Stable phase:

[0057] When both the first gate signal Gn-2 output by the cascaded preceding gate drive unit and the first gate signal Gn+2 output by the cascaded following gate drive unit are low, the forward and reverse scan control module 10 receives these low signals and enters a non-operating state. Simultaneously, the first node Q is pulled down to a low level, causing the first output module 20 and the second output module 30 to enter a non-operating state, without affecting the operation of the stabilization module 40. Therefore, the stabilization module 40 enters an operating state, which can be used to maintain the first node Q, the first output terminal, and the second output terminal at a low level.

[0058] In one embodiment of the present invention, if the first node Q is pulled down to a low level, then the third control terminal of the third switching element T3 and the fourth control terminal of the fourth switching element T4 connected to the first node Q are at a low level, and the third switching element T3 and the fourth switching element T4 are in an open state, thereby causing the first output module 20 and the second output module 30 to enter a non-working state.

[0059] In one embodiment of the present invention, when the first node Q is pulled down to a low level, the sixth control terminal of the sixth switching element T6 connected to the first node Q becomes low, and the sixth switching element T6 becomes open. Simultaneously, the fifth control terminal and the ninth path terminal of the fifth switching element T5 receive the third reference voltage DC, making the fifth switching element T5 conduct. The third reference voltage DC can be a high level, such as 5V. Therefore, the second node QB connected to the eleventh path terminal of the sixth switching element T6 can receive the third reference voltage DC through the conducting fifth switching element T5. When QB is pulled high, the seventh control terminal of the seventh switch element T7, the eighth control terminal of the eighth switch element T8, and the ninth control terminal of the ninth switch element T9, which are connected to the second node QB, are all at a high level. Thus, the seventh switch element T7, the eighth switch element T8, and the ninth switch element T9 are in a conducting state, and the stabilization module 40 enters the working state. The first node Q, the first output terminal, and the second output terminal receive the fourth reference voltage VGL through the conducting seventh switch element T7, the eighth switch element T8, and the ninth switch element T9, respectively, and maintain a low level during the stabilization phase to ensure the stability of the system.

[0060] In one embodiment of the present invention, according to the transition of the third clock signal CLK3 from low to high, the tenth control terminal of the tenth switching element T10 receives the third clock signal CLK3 as high, and the nineteenth path terminal of the tenth switching element T10 is connected to the first output terminal. The first output terminal receives the fourth reference voltage VGL through the conducting tenth switching element T10, maintaining a low level during the stable phase to ensure system stability. Furthermore, according to the transition of the fourth clock signal CLK4 from low to high, the eleventh control terminal of the eleventh switching element T11 receives the fourth clock signal CLK4 as high, and the twenty-first path terminal of the eleventh switching element T11 is connected to the second output terminal. The second output terminal receives the fourth reference voltage VGL through the conducting eleventh switching element T11, maintaining a low level during the stable phase to ensure system stability.

[0061] In addition, such as Figure 3As shown, multiple gate driving units can sequentially generate gate signals G1 to G4. When adjacent gate driving units receive the first clock signal CLK1 and the second clock signal CLK2, the first clock signal CLK1 and the second clock signal CLK2 received by the first gate driving unit, and the first clock signal CLK1 and the second clock signal CLK2 received by the second gate driving unit, have the same time period (e.g., 4T) and their phases differ by 1 / 4 time period (e.g., T). That is, if the first gate driving unit receives the first clock signal CLK1 and the second clock signal CLK2, then the first clock signal CLK1 received by the second gate driving unit is actually the third clock signal CLK3, and the second clock signal CLK2 received by the second gate driving unit is actually the fourth clock signal CLK4.

[0062] Therefore, the gate driving circuit of this embodiment can support forward and reverse scanning, and can perform dual-stage output through the gate driving unit, reducing the number of gate driving units, effectively saving the space occupied by the gate driving circuit, and realizing a narrow bezel of the display device.

[0063] In one embodiment of the present invention, the gate driving circuit of this embodiment can support the design of in-cell TDDI for embedded touch and display driving, such as the Long H touch mode, which uses the gate signal generated by the gate driving circuit for the detection of touch sensing signals to improve the touch effect.

[0064] In one embodiment of the present invention, the gate drive circuit of this embodiment can be used to turn on all switching elements by switching all the first reference voltage DC_H, the second reference voltage DC_L, the third reference voltage DC and the fourth reference voltage VGL to high voltage during the power-off phase, thereby releasing the in-plane charge and reducing the power-off afterimage.

[0065] Please see Figure 4 , Figure 4 This is a circuit connection diagram of the gate driving unit according to the third embodiment of the present invention. This embodiment provides a gate driving circuit, whose basic structure, principle, and resulting technical effects are the same as those of the second embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding contents in the above embodiments.

[0066] In one embodiment of the present invention, such as Figure 4As shown, each gate driving unit is spaced apart from the cascaded preceding gate driving unit. Specifically, the forward and reverse scanning control module 10 in the gate driving unit receives the first gate signal Gn-4 output from the cascaded preceding gate driving units spaced apart, and receives the first gate signal Gn+4 output from the cascaded following gate driving units spaced apart. In one embodiment, the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 have the same time period (e.g., 8T), the first clock signal CLK1 and the second clock signal CLK2 are phase-differentiated by 1 / 8 time period (e.g., T), the third clock signal CLK3 and the fourth clock signal CLK4 are phase-differentiated by 1 / 8 time period (e.g., T), and the first clock signal CLK1 and the third clock signal CLK3 are phase-differentiated by 1 / 2 time period (e.g., 4T). However, the present invention is not limited to this. Those skilled in the art can, according to requirements, space multiple gate driving units between each cascaded preceding gate driving unit, such as two, and all such technical solutions are within the protection scope of the present invention.

[0067] Figure 5 yes Figure 4 Timing diagrams of the various input and output signals in the embodiment. Combined with... Figure 4 and Figure 5 The operation of the gate drive circuit in this embodiment can be referred to the operation of the second embodiment, wherein, as shown... Figure 5 As shown, multiple gate driving units can sequentially generate gate signals G1 to G8. When adjacent gate driving units receive the first clock signal CLK1 and the second clock signal CLK2, the first clock signal CLK1 and the second clock signal CLK2 received by the first gate driving unit, and the first clock signal CLK1 and the second clock signal CLK2 received by the second gate driving unit, have the same time period (e.g., 8T) and their phases differ by 1 / 8 of the time period (e.g., T). That is, if the first gate driving unit receives the first clock signal CLK1 and the second clock signal CLK2, then the first clock signal CLK1 received by the second gate driving unit is actually the fifth clock signal CLK5, and the second clock signal CLK2 received by the second gate driving unit is actually the sixth clock signal CLK6.

[0068] Please see Figure 6 , Figure 6 This is a circuit connection diagram of the gate driving unit according to the fourth embodiment of the present invention. This embodiment provides a gate driving circuit, the basic structure and principle of which are the same as those of the third embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding contents in the above embodiments.

[0069] In one embodiment of the present invention, such as Figure 6As shown, the stabilization module 40 also includes a twelfth switching element T12 and a thirteenth switching element T13. The twelfth switching element T12 includes a twelfth control terminal, a twenty-third channel terminal, and a twenty-fourth channel terminal; the twelfth control terminal of the twelfth switching element T12 receives a clear screen signal STV, the twenty-third channel terminal of the twelfth switching element T12 is connected to the first output terminal, and the twenty-fourth channel terminal of the twelfth switching element T12 receives a fourth reference voltage VGL; the thirteenth switching element T13 includes a thirteenth control terminal, a twenty-fifth channel terminal, and a twenty-sixth channel terminal, the thirteenth control terminal of the thirteenth switching element T13 receives a clear screen signal STV, the twenty-fifth channel terminal of the thirteenth switching element T13 is connected to the second output terminal, and the twenty-sixth channel terminal of the thirteenth switching element T13 receives the fourth reference voltage VGL.

[0070] Therefore, when the device is powered off, the twelfth control terminal of the twelfth switch element T12 and the thirteenth control terminal of the thirteenth switch element T13 both receive the screen clear signal STV at a high level. This allows the first output terminal and the second output terminal to receive the fourth reference voltage VGL through the conducting twelfth switch element T12 and the thirteenth switch element T13, respectively, thereby quickly releasing the charge. This can improve the panel discharge efficiency during the power-off phase, effectively reduce power-off ghosting, and improve the panel image quality.

[0071] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the gate driving circuit as provided in the above embodiments, for providing gate signals to the gate lines of the display panel. Implementation of this display device can refer to the embodiments of the gate driving circuit described above; repeated details will not be elaborated further.

[0072] The gate driving circuit and display device of the present invention can support forward and reverse scanning, and can perform dual-stage output through the gate driving unit, thereby reducing the number of gate driving units and effectively saving the space occupied by the gate driving circuit, and realizing a narrow bezel of the display device.

[0073] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the invention without departing from the scope of the invention shall still fall within the scope of the present invention.

Claims

1. A gate driving circuit, comprising a plurality of cascaded gate driving units, characterized in that, Each of the gate driving units includes: A forward and reverse scanning control module (10) is connected to the first node (Q). During forward scanning, the first node (Q) is pulled up to a high level according to the first gate signal and the first reference voltage (DC_H) output by the cascaded previous stage gate driving unit, and pulled down to a low level according to the first gate signal and the second reference voltage (DC_L) output by the cascaded next stage gate driving unit. During reverse scanning, the first node (Q) is pulled up to a high level according to the first gate signal and the second reference voltage (DC_L) output by the cascaded next stage gate driving unit, and pulled down to a low level according to the first gate signal and the first reference voltage (DC_H) output by the cascaded previous stage gate driving unit. During forward scanning, the first reference voltage (DC_H) is high and the second reference voltage (DC_L) is low; during reverse scanning, the first reference voltage (DC_H) is low and the second reference voltage (DC_L) is high. The first output module (20) is connected to the first node (Q) and the forward and reverse scan control module (10). The first output module (20) outputs the first gate signal at the first output terminal according to the first clock signal (CLK1). The second output module (30) is connected to the first node (Q) and the forward and reverse scan control module (10). The second output module (30) outputs the second gate signal at the second output terminal according to the second clock signal (CLK2). A stabilization module (40) is connected to the first node (Q), the first output terminal and the second output terminal. The stabilization module (40) is used to keep the first node (Q), the first output terminal and the second output terminal at a low level when the first node (Q) is pulled down to a low level. The first output module (20) includes a third switching element (T3); the third switching element (T3) includes a third control terminal, a fifth path terminal and a sixth path terminal; the third control terminal of the third switching element (T3) is connected to the first node (Q), the fifth path terminal of the third switching element (T3) receives the first clock signal (CLK1), and the sixth path terminal of the third switching element (T3) is connected to the first output terminal; The second output module (30) includes a fourth switching element (T4); the fourth switching element (T4) includes a fourth control terminal, a seventh path terminal and an eighth path terminal; the fourth control terminal of the fourth switching element (T4) is connected to the first node (Q), the seventh path terminal of the fourth switching element (T4) receives the second clock signal (CLK2), and the eighth path terminal of the fourth switching element (T4) is connected to the second output terminal; The gate driving unit further includes a first capacitor (C1); the first end of the first capacitor (C1) is connected to the first node (Q), and the second end of the first capacitor (C1) is connected to a fourth reference voltage (VGL), which is low during the display phase; wherein, after the XON function is activated during the power-off phase, the fourth reference voltage (VGL) is driven to a high level. At this time, due to the presence of the first capacitor (C1), the first node (Q) will be synchronously coupled to a high level, causing the third switching element (T3) and the fourth switching element (T4) to turn on, and outputting a first gate signal at the first output terminal according to the first clock signal (CLK1), and outputting a second gate signal at the second output terminal according to the second clock signal (CLK2).

2. The gate driving circuit according to claim 1, characterized in that, The forward and reverse scanning control module (10) includes a first switching element (T1) and a second switching element (T2); The first switching element (T1) includes a first control terminal, a first path terminal, and a second path terminal; the first control terminal of the first switching element (T1) receives a first gate signal output by the cascaded previous stage gate driving unit, the first path terminal of the first switching element (T1) receives the first reference voltage (DC_H), and the second path terminal of the first switching element (T1) is connected to the first node (Q). The second switching element (T2) includes a second control terminal, a third path terminal, and a fourth path terminal; the second control terminal of the second switching element (T2) receives a first gate signal output by the cascaded previous stage gate drive unit, the third path terminal of the second switching element (T2) receives the second reference voltage (DC_L), and the fourth path terminal of the second switching element (T2) is connected to the first node (Q).

3. The gate driving circuit according to claim 1, characterized in that, The stabilization module (40) includes: The fifth switching element (T5) includes a fifth control terminal, a ninth path terminal, and a tenth path terminal; the ninth path terminal of the fifth switching element (T5) is connected to the fifth control terminal of the fifth switching element (T5) and receives a third reference voltage (DC); the tenth path terminal of the fifth switching element (T5) is connected to the second node (QB). The sixth switching element (T6) includes a sixth control terminal, an eleventh path terminal, and a twelfth path terminal; the sixth control terminal of the sixth switching element (T6) is connected to the first node (Q), the eleventh path terminal of the sixth switching element (T6) is connected to the tenth path terminal of the fifth switching element (T5), and the twelfth path terminal of the sixth switching element (T6) receives a fourth reference voltage (VGL); The seventh switching element (T7) includes a seventh control terminal, a thirteenth path terminal, and a fourteenth path terminal; the seventh control terminal of the seventh switching element (T7) is connected to the tenth path terminal of the fifth switching element (T5), the thirteenth path terminal of the seventh switching element (T7) is connected to the first node (Q), and the fourteenth path terminal of the seventh switching element (T7) receives the fourth reference voltage (VGL); The eighth switching element (T8) includes an eighth control terminal, a fifteenth path terminal, and a sixteenth path terminal; the eighth control terminal of the eighth switching element (T8) is connected to the tenth path terminal of the fifth switching element (T5), the fifteenth path terminal of the eighth switching element (T8) is connected to the first output terminal, and the sixteenth path terminal of the eighth switching element (T8) receives the fourth reference voltage (VGL); The ninth switching element (T9) includes a ninth control terminal, a seventeenth path terminal, and an eighteenth path terminal; the ninth control terminal of the ninth switching element (T9) is connected to the tenth path terminal of the fifth switching element (T5), the seventeenth path terminal of the ninth switching element (T9) is connected to the second output terminal, and the eighteenth path terminal of the ninth switching element (T9) receives the fourth reference voltage (VGL).

4. The gate driving circuit according to claim 3, characterized in that, The stabilization module (40) also includes: The tenth switching element (T10) includes a tenth control terminal, a nineteenth path terminal, and a twentieth path terminal. The tenth control terminal of the tenth switching element (T10) receives a third clock signal (CLK3), the nineteenth path terminal of the tenth switching element (T10) is connected to the first output terminal, and the twentieth path terminal of the tenth switching element (T10) receives the fourth reference voltage (VGL). The eleventh switching element (T11) includes an eleventh control terminal, a twenty-first path terminal, and a twenty-second path terminal. The eleventh control terminal of the eleventh switching element (T11) receives the fourth clock signal (CLK4). The twenty-first path terminal of the eleventh switching element (T11) is connected to the second output terminal. The twenty-second path terminal of the eleventh switching element (T11) receives the fourth reference voltage (VGL).

5. The gate driving circuit according to claim 3, characterized in that, The stabilization module (40) also includes: The twelfth switching element (T12) includes a twelfth control terminal, a twenty-third path terminal, and a twenty-fourth path terminal. The twelfth control terminal of the twelfth switching element (T12) receives a screen clearing signal, the twenty-third path terminal of the twelfth switching element (T12) is connected to the first output terminal, and the twenty-fourth path terminal of the twelfth switching element (T12) receives the fourth reference voltage (VGL). The thirteenth switching element (T13) includes a thirteenth control terminal, a twenty-fifth path terminal, and a twenty-sixth path terminal. The thirteenth control terminal of the thirteenth switching element (T13) receives the screen clearing signal, the twenty-fifth path terminal of the thirteenth switching element (T13) is connected to the second output terminal, and the twenty-sixth path terminal of the thirteenth switching element (T13) receives the fourth reference voltage (VGL).

6. The gate driving circuit according to claim 1, characterized in that, In the gate driving circuit, each gate driving unit is arranged adjacent to the cascaded previous stage gate driving unit. The first clock signal (CLK1) and the second clock signal (CLK2) have the same time period and are out of phase by 1 / 4 time period. Alternatively, each of the gate driving units is spaced apart from the cascaded previous gate driving unit, and the first clock signal (CLK1) and the second clock signal (CLK2) have the same time period and are phase-differentiated by 1 / 8 of the time period.

7. The gate driving circuit according to claim 1, characterized in that, When the gate driving unit is in the starting or ending position of the gate driving circuit, it receives a start signal or an end signal provided by an external signal circuit.

8. The gate driving circuit according to claim 1, characterized in that, The gate driving unit further includes one or more of a second capacitor (C2) and a third capacitor (C3); the first terminal of the second capacitor (C2) is connected to the first node (Q), and the second terminal of the second capacitor (C2) is connected to the first output terminal; the first terminal of the third capacitor (C3) is connected to the first node (Q), and the second terminal of the third capacitor (C3) is connected to the second output terminal.

9. A display device, characterized in that, Includes the gate drive circuit as described in any one of claims 1-8.

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