Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including device regions and isolation regions arranged along a first direction; forming a gate structure extending along a second direction on the substrate, the second direction being perpendicular to the first direction; forming a mask structure on the gate structure; performing a first patterning process on the mask structure to form a first opening, the first opening exposing a surface of a portion of the gate structure; removing the portion of the gate structure along the first opening to form a first trench in the gate structure, the first trench extending through the gate structure along the first direction; forming a first isolation structure in the first trench; performing a second patterning process on the mask structure to form a second opening, the second opening exposing a surface of the gate structure of the isolation region; removing the gate structure of the isolation region along the second opening to form a second trench; and forming a second isolation structure in the second trench. The method provided by the embodiments of the present application is beneficial to improving the performance of the formed semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. In the evolution of integrated circuits, the reduction in semiconductor device size has simultaneously increased the complexity of integrated circuit processing and manufacturing.

[0003] As an integral part of a device, the gate significantly impacts its performance. Traditional virtual gate dicing techniques suffer from numerous problems, such as incomplete metal coverage at the work function end of the subsequently formed metal gate and gate end defects, which severely affect the performance of the resulting semiconductor device.

[0004] Therefore, there is an urgent need to provide a metal gate dicing process to improve the performance of semiconductor structures. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, wherein after forming a gate structure, the gate structure is cut to form a gate-cut structure, thereby improving the performance of the semiconductor structure.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including device regions and isolation regions arranged along a first direction, the isolation regions being located between adjacent device regions; forming a gate structure on the device regions and the isolation regions, the gate structure extending along a second direction perpendicular to the first direction; forming a mask structure on the gate structure; performing a first patterning process on the mask structure to form a first opening within the mask structure, the first opening exposing a portion of the surface of the gate structure; removing a portion of the gate structure along the first opening to form a first trench within the gate structure, the first trench penetrating the gate structure along the first direction; forming a first isolation structure within the first trench, the first isolation structure further covering the top surface of the mask structure; performing a second patterning process on the mask structure to form a second opening within the mask structure, the second opening exposing the surface of the gate structure in the isolation region; removing the gate structure in the isolation region along the second opening to form a second trench; and forming a second isolation structure within the second trench.

[0007] Optionally, before forming the first mask structure on the gate structure, the method further includes forming a chemical mechanical polishing stop layer on the gate structure.

[0008] Optionally, the material of the chemical mechanical polishing stop layer includes titanium nitride, titanium, or carbon-doped tungsten.

[0009] Optionally, after forming the second isolation structure, the second isolation structure, the first isolation structure, and the mask structure are planarized until the top surface of the chemical mechanical polishing stop layer is exposed.

[0010] Optionally, the method for performing the first patterning process on the mask structure includes: forming a first patterned layer on the mask structure, the first patterned layer having a first patterned opening, the first patterned opening defining the position and size of the first trench; using the first patterned layer as a mask, etching the mask structure to form the first opening in the mask structure; and removing the first patterned layer.

[0011] Optionally, the method for performing a second patterning process on the mask structure includes: forming a second patterned layer on the first isolation structure, the second patterned layer having a second patterned opening, the second patterned opening defining the position and size of the second trench; using the second patterned layer as a mask, etching the first isolation structure and the mask structure to form the second opening in the first isolation structure and the mask structure; and removing the second patterned layer.

[0012] Optionally, the mask structure can be a single-layer structure or a multi-layer structure.

[0013] Optionally, when the mask structure is a multilayer structure, the mask structure includes an etch barrier layer located on the gate structure and a hard mask layer located on the surface of the etch barrier layer.

[0014] Optionally, the material of the etch barrier layer includes one or both of silicon oxide and polysilicon; the material of the hard mask layer includes one or both of silicon nitride and polysilicon.

[0015] Optionally, the formation process of the etching barrier layer and the hard mask layer includes furnace tube method, chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

[0016] Optionally, the material of the first isolation structure includes one or both of silicon nitride and silicon oxide; the deposition process of the first isolation structure includes atomic layer deposition.

[0017] Optionally, the material of the second isolation structure includes one or both of silicon nitride and silicon oxide; the formation process of the second isolation structure includes atomic layer deposition.

[0018] Optionally, it further includes: forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the gate structure and exposing the top surface of the gate structure.

[0019] Optionally, the method for forming the gate structure and the dielectric layer includes: forming a dummy gate structure on the substrate; forming an initial dielectric layer on the substrate, the initial dielectric layer covering the dummy gate structure; planarizing the initial dielectric layer until the top surface of the dummy gate structure is exposed, forming the dielectric layer; removing the dummy gate structure to form a gate opening in the dielectric layer; and forming a gate structure in the gate opening.

[0020] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0021] The formation method provided by this technical solution involves cutting the gate structure after its formation. First, a mask structure is patterned to form a first opening defining the location and size of a first trench. The gate structure is then etched along the first opening to form a first trench, and a first isolation structure (gate dicing structure) is formed within the first trench. Second, the mask structure is patterned a second time to form a second opening defining the location and size of a second trench. The gate structure is then etched along the second opening to form a second trench, and a second isolation structure (single-diffusion isolation structure) is formed within the second trench. On one hand, using a single mask process to form both the first and second isolation structures, followed by planarization after the second isolation structure is formed, simplifies the process steps and optimizes the process flow. On the other hand, forming the metal gate structure before the gate dicing improves the deposition of the gate structure material, thereby enhancing the performance of the formed semiconductor structure. Attached Figure Description

[0022] Figures 1 to 20 This is a schematic diagram of the structure corresponding to each step of the semiconductor structure formation method in one embodiment of the present invention. Detailed Implementation

[0023] As is known from the background art, the current common practice is to use a virtual gate dicing process to form a gate dicing structure. After forming the virtual gate, the virtual gate is first diced to form a trench in the virtual gate. The trench extends through the virtual gate along a direction perpendicular to the virtual gate. An isolation structure is formed in the trench, thereby forming the virtual gate dicing structure. Then the virtual gate is removed to form a gate opening. Finally, a gate structure is formed in the gate opening.

[0024] After forming the gate structure, a single-diffused isolation structure is usually required. During the process, on the one hand, multiple chemical mechanical polishing processes are required, which is complex and involves many steps. Furthermore, chemical mechanical polishing is performed after forming the single-diffused isolation structure, and the different loads between the single-diffused isolation structure region and other regions can easily have an adverse effect on subsequent processes. On the other hand, during the removal of dummy gates, dummy gate residues are likely to remain, affecting the performance of the formed semiconductor structure.

[0025] To address the aforementioned problems, this invention provides a method for forming a semiconductor structure. First, a gate structure is formed. Then, a mask structure is formed on the gate structure. The mask structure undergoes a first patterning process, forming a first opening within the mask structure. A portion of the gate structure is etched away along the first opening, forming a first trench within the gate structure. The first trench penetrates the gate structure along a first direction. A first isolation structure is then formed within the first trench, thereby forming a gate dicing structure. After forming the gate dicing structure, the mask structure undergoes a second patterning process, forming a second opening within the mask structure. The gate structure of the isolation region is removed along the second opening, forming a second trench. A second isolation structure is then formed within the second trench, thereby forming a single-diffused isolation structure. Using this method to form the semiconductor structure, on the one hand, reduces the number of planarization processes, avoiding differences caused by multiple planarization processes, simplifying the process steps, optimizing the process flow, and reducing the impact of grinding load differences between the single-diffused isolation region and other regions on subsequent processes. On the other hand, gate dicing after forming the gate structure reduces the residue of dummy gate structures, which is beneficial for improving the performance of the semiconductor structure.

[0026] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Figures 1 to 20 This is a schematic diagram of the structure corresponding to each step of the semiconductor structure formation method in one embodiment of the present invention.

[0028] refer to Figure 1 A substrate 100 is provided, the substrate 100 including a device region A1 and an isolation region B1 arranged along a first direction X, the isolation region B1 being located between adjacent device regions A1.

[0029] In this embodiment, the substrate 100 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0030] In this embodiment, the substrate 100 is used to form a fin field-effect transistor.

[0031] Continue to refer to Figure 1A plurality of discretely arranged fins 101 are formed on the substrate 100. The fins 101 span the device region A1 and the isolation region B1. The fins 101 extend along the first direction X and are arranged along the second direction Y, which is perpendicular to the first direction X.

[0032] refer to Figures 2 to 4 , Figure 2 This is a top view schematic diagram of a semiconductor structure. Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure along the a1-a1 direction. Figure 4 yes Figure 2 A cross-sectional view along the b1-b1 direction shows that a gate structure 102 is formed on the device region A1 and the isolation region B1. The gate structure 102 spans the fin 101 and extends along the second direction Y.

[0033] Continue to refer to Figures 2 to 4 A dielectric layer 103 is formed on the substrate 100, the dielectric layer 103 covering the sidewalls of the gate structure 102 and exposing the top surface of the gate structure 102.

[0034] The dielectric layer 103 is made of silicon dioxide, low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity of less than 3.9) or ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity of less than 2.5).

[0035] When the material of the dielectric layer 103 is a low-k dielectric material or an ultra-low-k dielectric material, the material of the dielectric layer 103 is silicon carbide hydride (SiCOH), fluorine-doped silicon dioxide (FSG), boron-doped silicon dioxide (BSG), phosphorus-doped silicon dioxide (PSG), boron-phosphorus-doped silicon dioxide (BPSG), hydride silsesquioxane, or methylsilsesquioxane.

[0036] In this embodiment, the material of the dielectric layer 103 is an ultra-low k dielectric material, which is silicon carbide (SiCOH).

[0037] In this embodiment, the gate structure 102 includes a gate dielectric layer 104, a gate layer 105 located on the surface of the gate dielectric layer 104, and sidewalls 106 located on the sidewall surfaces of the gate dielectric layer 104 and the gate layer 105.

[0038] It should be noted that, Figure 4 The gate dielectric layer 104 is omitted.

[0039] In this embodiment, the gate dielectric layer 104 is made of a high-k dielectric material; in other embodiments, the gate dielectric layer 104 may also be made of silicon oxide.

[0040] In this embodiment, the gate dielectric layer 104 is formed by thermal oxidation; in other embodiments, the gate dielectric layer 104 can also be formed by in-situ water vapor generation.

[0041] The gate layer 105 is made of a metal, which includes one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum; in this embodiment, the gate layer 105 is made of aluminum.

[0042] The sidewall 106 is made of one or more of silicon oxide, silicon nitride, and silicon oxynitride; in this embodiment, the sidewall 106 is made of silicon nitride.

[0043] In this embodiment, the sidewall 106 is formed using a chemical vapor deposition process; in other embodiments, the sidewall 106 may also be formed using an atomic layer deposition process or a physical vapor deposition process.

[0044] In this embodiment, the method for forming the gate structure 102 and the dielectric layer 103 includes: forming a dummy gate structure (not shown) on the substrate 100; forming the sidewall 106 on the sidewall surface of the dummy gate structure; forming an initial dielectric layer (not shown) on the substrate 100, the initial dielectric layer covering the dummy gate structure and the sidewall 106; planarizing the initial dielectric layer until the top surface of the dummy gate structure is exposed, thereby forming the dielectric layer 103; after forming the dielectric layer 103, removing the dummy gate structure to form a gate opening in the dielectric layer 103; and forming the gate structure 102 in the gate opening.

[0045] In this embodiment, the gate structure 102 also covers the dielectric layer 103. In subsequent processes, the gate structure 102 can protect the dielectric layer 103 from etching damage.

[0046] In other embodiments, the gate structure 102 may be chemically mechanically polished until the top surface of the gate structure 102 is flush with the top surface of the dielectric layer 103.

[0047] In this embodiment, the material of the pseudo-gate structure includes polycrystalline silicon.

[0048] The initial dielectric layer formation process includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or spin coating; in this embodiment, the initial dielectric layer formation process adopts chemical vapor deposition.

[0049] In this embodiment, the planarization process of the initial dielectric layer is a chemical mechanical polishing process; in other embodiments, the planarization process can also be an etching process.

[0050] In this embodiment, the process for removing the dummy gate structure is dry etching; in other embodiments, the process for removing the dummy gate structure may also be sequential plasma etching and wet etching.

[0051] In this embodiment, before forming the pseudo-gate structure, the method further includes forming an isolation layer 200 on the substrate 100, the isolation layer 200 covering a portion of the sidewall of the fin 101, and the top surface of the isolation layer 200 being lower than the top surface of the fin.

[0052] In this embodiment, the material of the isolation layer 200 is silicon oxide.

[0053] refer to Figure 5 , Figure 5 and Figure 3 With the view orientation consistent, a chemical mechanical polishing stop layer 107 is formed on the gate structure 102.

[0054] In this embodiment, the chemical mechanical polishing stop layer 107 is made of titanium nitride; in other embodiments, the chemical mechanical polishing stop layer 107 may also be made of metallic titanium or carbon-doped metallic tungsten.

[0055] In this embodiment, the chemical mechanical polishing stop layer 107 is used as a planarization stop layer in the subsequent planarization process, which can protect the gate structure 102 from damage.

[0056] After forming the chemical mechanical polishing stop layer 107, a mask structure is formed on the chemical mechanical polishing stop layer 107.

[0057] In this embodiment, the mask structure is a multi-layer structure, including an etching barrier layer located on the surface of the chemical mechanical polishing stop layer 107, and a hard mask layer located on the surface of the etching barrier layer.

[0058] In other embodiments, the mask structure may also be a single-layer structure.

[0059] refer to Figure 6 In this embodiment, the method for forming the mask structure includes: sequentially forming an etching barrier layer 108 and a hard mask layer 109 on the chemical mechanical polishing stop layer 107.

[0060] In this embodiment, the material of the etching barrier layer 108 is silicon oxide; in other embodiments, the material of the etching barrier layer 108 may also be polycrystalline silicon or a mixture of silicon oxide and polycrystalline silicon.

[0061] In this embodiment, the etching barrier layer 108 is formed by chemical vapor deposition; in other embodiments, the etching barrier layer 108 may also be formed by furnace tube method, physical vapor deposition or atomic layer deposition.

[0062] In this embodiment, the etching barrier layer 108 serves as an etching barrier to prevent over-etching of the gate structure in subsequent etching processes.

[0063] In this embodiment, the material of the hard mask layer 109 is silicon nitride; in other embodiments, the material of the hard mask layer 109 may also be polysilicon or a mixture of silicon oxide and polysilicon.

[0064] In this embodiment, the hard mask layer 109 is formed by chemical vapor deposition; in other embodiments, the hard mask layer 109 can also be formed by physical vapor deposition or atomic layer deposition.

[0065] After the mask structure is formed, the mask structure undergoes a first patterning process, the method of which includes:

[0066] refer to Figure 7 A first patterned layer 110 is formed on the mask structure. The first patterned layer 110 has a first patterned opening 111, which defines the position and size of the first trench to be formed.

[0067] In this embodiment, the first patterning layer 110 is a patterned photoresist layer.

[0068] refer to Figure 8 and Figure 9 , Figure 8 This is a top-down structural diagram. Figure 9 for Figure 8 A cross-sectional structural diagram along the a2-a2 direction shows that, using the first patterned opening 111 as a mask, the hard mask layer 109 and the etching barrier layer 108 are etched until the top surface of the chemical mechanical polishing stop layer 107 is exposed, forming the first opening 112 within the hard mask layer 109 and the etching barrier layer 108; the first patterned layer 111 is then removed.

[0069] In this embodiment, the first opening 112 exposes a portion of the gate structure 102.

[0070] In this embodiment, specifically, the first opening 112 exposes part of the top surface of the chemical mechanical polishing stop layer 107 above the gate structure 102.

[0071] In this embodiment, the first opening 112 extends along the first direction X.

[0072] refer to Figure 10 and Figure 11 , Figure 10 This is a top-down structural diagram. Figure 11 and Figure 9 With the view direction consistent, using the mask structure as a mask, the gate structure 102 is etched to form a first trench 113 in the gate structure 102. The first trench 113 penetrates the gate structure 102 along the first direction X.

[0073] In this embodiment, a portion of the thickness of the substrate 100, as well as the dielectric layer 103 and the isolation layer 200 between adjacent gate structures 102, are also etched.

[0074] refer to Figure 12 , Figure 12 and Figure 11 The cross-sectional directions are consistent. After the first groove 113 is formed, a first isolation structure 114 is formed in the first groove 113. The first isolation structure 114 also covers the top surface of the mask structure.

[0075] In this embodiment, the material of the first isolation structure 114 is silicon nitride; in other embodiments, the material of the first isolation structure 114 may also be silicon oxide or a mixture of silicon nitride and silicon oxide.

[0076] In this embodiment, the first isolation structure 114 is formed by atomic layer deposition, which has better pore-filling ability to improve the isolation performance of the formed first isolation structure.

[0077] After forming the first isolation structure 114, the mask structure undergoes a second patterning process. In this embodiment, the method for the second patterning process includes:

[0078] refer to Figure 13 , Figure 13 and Figure 4 The cross-sectional direction is consistent, and a second patterned layer 115 is formed on the first isolation structure 114. The second patterned layer 115 has a second patterned opening 116, which defines the position and size of the second groove to be formed.

[0079] In this embodiment, the second patterning layer 115 is a patterned photoresist layer.

[0080] refer to Figure 14 , Figure 14 and Figure 13With the cross-sectional direction consistent, using the second patterned layer 115 as a mask, the first isolation structure 114, the hard mask layer 109, and the etch barrier layer 108 are etched to form a second opening 117 in the first isolation structure 114, the hard mask layer 109, and the etch barrier layer 108, and the second opening 117 exposes the gate structure 102 of the isolation region B1; the second patterned layer 115 is then removed.

[0081] In this embodiment, specifically, the second opening 117 exposes the surface of the chemical mechanical polishing stop layer 107 on the surface of the gate structure 102 of the isolation region B1.

[0082] refer to Figure 15 , Figure 15 and Figure 14 With the cross-sectional direction consistent, the gate structure 102 of the isolation region B1 is etched away along the second opening 117, and a second trench 118 is formed in the dielectric layer 103.

[0083] In this embodiment, the portion of the fin 101 covered by the gate structure 102 and a portion of the substrate 100 are also etched away.

[0084] refer to Figure 16 , Figure 16 and Figure 15 The cross-sectional directions are consistent. After the second groove 118 is formed, a second isolation structure 119 is formed in the second groove 118. The second isolation structure 119 also covers the top surface of the first isolation structure 114.

[0085] In this embodiment, the material of the second isolation structure 119 is silicon nitride; in other embodiments, the material of the second isolation structure 119 may also be silicon oxide or a mixture of silicon nitride and silicon oxide.

[0086] In this embodiment, the second isolation structure 119 is formed by atomic layer deposition, which has better pore-filling ability to improve the isolation performance of the formed second isolation structure.

[0087] refer to Figure 17 , Figure 17 and Figure 16 With the cross-sectional direction consistent, the second isolation structure 119, the first isolation structure 114 and the mask structure are planarized until the top surface of the chemical mechanical polishing stop layer 107 is exposed.

[0088] In this embodiment, the planarization process is a chemical mechanical polishing process.

[0089] In this embodiment, the materials of the second isolation structure 119, the first isolation structure 114, the hard mask layer 109, and the etch barrier layer 108 are different from the material of the chemical mechanical polishing stop layer 107, and the polishing selectivity ratio is greater than 20:1. The polishing speed of the second isolation structure 119, the first isolation structure 114, the hard mask layer 109, and the etch barrier layer 108 is much greater than the polishing rate of the chemical mechanical polishing stop layer 107. Therefore, the chemical mechanical polishing stop layer 107 can protect the gate structure 102 from damage.

[0090] refer to Figures 18 to 20 , Figure 18 This is a top view schematic diagram of a semiconductor structure. Figure 19 yes Figure 18 A schematic diagram of the cross-sectional structure along the a3-a3 direction. Figure 20 yes Figure 18 A cross-sectional view along the b2-b2 direction shows that the first isolation structure 114, the second isolation structure 119, and the chemical mechanical polishing stop layer 107 are planarized until the top surface of the gate structure 102 is exposed; the gate structure 102 is further planarized until the top surface of the gate structure 102 is flush with the top surface of the dielectric layer 103.

[0091] In this embodiment, the planarization process further controls the flatness of the surfaces of the first isolation structure 114 and the second isolation structure 119, which is beneficial to improving the performance of the semiconductor structure. In addition, the gate structure 102 is planarized, which realizes effective control of the height of the gate structure 102.

[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including device regions and isolation regions arranged along a first direction, the isolation regions being located between adjacent device regions; A gate structure is formed on the device region and the isolation region, the gate structure extending along a second direction, the second direction being perpendicular to the first direction; A mask structure is formed on the gate structure; The mask structure is first patterned to form a first opening within the mask structure, the first opening exposing a portion of the surface of the gate structure; A portion of the gate structure is removed along the first opening, and a first trench is formed within the gate structure, the first trench penetrating the gate structure along the first direction; A first isolation structure is formed within the first trench, and the first isolation structure also covers the top surface of the mask structure; The mask structure is patterned a second time to form a second opening within the mask structure, the second opening exposing the surface of the gate structure in the isolation region; The gate structure of the isolation region is removed along the second opening to form a second trench; A second isolation structure is formed within the second trench.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the first mask structure on the gate structure, the method further includes forming a chemical mechanical polishing stop layer on the gate structure.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the chemical mechanical polishing stop layer includes titanium nitride, titanium, or carbon-doped tungsten.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, After the second isolation structure is formed, the second isolation structure, the first isolation structure, and the mask structure are planarized until the top surface of the chemical mechanical polishing stop layer is exposed.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for performing a first patterning process on the mask structure includes: forming a first patterned layer on the mask structure, the first patterned layer having a first patterned opening, the first patterned opening defining the position and size of the first trench; using the first patterned layer as a mask, etching the mask structure to form the first opening in the mask structure; and removing the first patterned layer.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for performing a second patterning process on the mask structure includes: forming a second patterned layer on the first isolation structure, the second patterned layer having a second patterned opening, the second patterned opening defining the position and size of the second trench; using the second patterned layer as a mask, etching the first isolation structure and the mask structure to form the second opening in the first isolation structure and the mask structure; and removing the second patterned layer.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The mask structure can be a single-layer structure or a multi-layer structure.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, When the mask structure is a multilayer structure, the mask structure includes an etch barrier layer located on the gate structure and a hard mask layer located on the surface of the etch barrier layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The etching barrier layer is made of one or both of silicon oxide and polysilicon; the hard mask layer is made of one or both of silicon nitride and polysilicon.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The formation processes of the etching barrier layer and the hard mask layer include furnace tube method, chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first isolation structure includes one or both of silicon nitride and silicon oxide; the deposition process of the first isolation structure includes atomic layer deposition.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the second isolation structure includes one or both of silicon nitride and silicon oxide; the formation process of the second isolation structure includes atomic layer deposition.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A dielectric layer is formed on the substrate, the dielectric layer covering the sidewalls of the gate structure and exposing the top surface of the gate structure.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The method of forming the gate structure and the dielectric layer includes: forming a dummy gate structure on the substrate; forming an initial dielectric layer on the substrate, the initial dielectric layer covering the dummy gate structure; planarizing the initial dielectric layer until the top surface of the dummy gate structure is exposed to form the dielectric layer; removing the dummy gate structure to form a gate opening in the dielectric layer; and forming a gate structure in the gate opening.

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