Method and device for decoding IRIG-B direct current time code

Abstract

The application provides a decoding method and device for IRIG-B direct current clock code, the method comprising: in response to a clock input signal input, judging the symbol type of multiple symbols in the clock input signal; according to the multiple symbols and the symbol type of the multiple symbols, obtaining valid symbols in the clock input signal; performing bit sequence processing on the valid symbols to obtain valid data, the valid data comprising a standard decoding time corresponding to the clock input signal; obtaining a clock compensation time corresponding to the valid data; and modifying the standard decoding time based on the clock compensation time to obtain decoding information of the clock input signal. By using the above method, the application solves the problem that the current decoding technology has a certain delay, which causes a certain delay between the issuance of the clock signal and the response of the device, and affects the real-time performance and response speed of the system.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of clock decoding, in particular to an IRIG-B direct current clock code decoding method. BACKGROUND

[0002] With the increasing application of industrial automation devices in systems, the cooperation between devices and between control systems is becoming closer and closer. An important aspect of realizing the cooperation between the devices or systems is that the automation devices running independently need a unified clock. When the clock is unified, there will be no deviation and misjudgment in aspects such as command delivery and fault coordination. The source of the clock is a satellite clock such as GPS and Beidou serving as a clock reference. The satellite clock delivers a second clock signal to each automation device in the form of broadcast. Each automation device needs to have the ability to recognize and decode the clock. Through corresponding decoding technology, the clock signal delivered by the satellite clock is converted into the internal clock signal of the device.

[0003] Due to the complexity of the decoding technology and the time delay of signal transmission and processing, the current decoding technology may have a certain delay. This will cause a certain delay between the delivery of the clock signal and the response of the device, affecting the real-time performance and response speed of the system.

[0004] At present, an IRIG-B direct current clock code decoding method is urgently needed to solve the problems existing in the current technology. SUMMARY

[0005] The application provides an IRIG-B direct current clock code decoding method and device, which is used to solve the problem that the current decoding technology has a certain delay, causing a certain delay between the delivery of the clock signal and the response of the device, affecting the real-time performance and response speed of the system.

[0006] The first aspect of the application provides an IRIG-B direct current clock code decoding method applied to a server, which comprises: in response to a clock input signal input, judging the symbol type of a plurality of symbols in the clock input signal; according to the plurality of symbols and the symbol type of the plurality of symbols, obtaining valid symbols in the clock input signal; performing bit sequence processing on the valid symbols to obtain valid data, the valid data including a standard decoding time corresponding to the clock input signal; obtaining a clock compensation time corresponding to the valid data; and modifying the standard decoding time based on the clock compensation time to obtain decoding information of the clock input signal.

[0007] The application eliminates the problem that there is a certain delay between the delivery of the clock signal and the response of the device in the decoding process, affecting the real-time performance and response speed of the system.

[0008] Optionally, in response to the clock input signal input, the symbol type of the plurality of symbols in the clock input signal is determined, specifically including: determining the signal type of the clock input signal; when the signal type of the clock input signal is a high-level signal, recording the first crystal oscillator clock cycle number of the high-level signal; when the signal type of the clock input signal is a low-level signal, recording the second crystal oscillator clock cycle number of the low-level signal; and according to the first crystal oscillator clock cycle number and the second crystal oscillator clock cycle number, obtaining the symbol type of the plurality of symbols in the clock input signal.

[0009] By using the above method, the symbol type of the plurality of symbols in the clock input signal is obtained according to the crystal oscillator clock cycle number of the high-level signal and the low-level signal in the clock input signal.

[0010] Optionally, the symbol type of the plurality of symbols includes a start position symbol, a high-low level symbol and a low-level symbol, and the valid symbol in the clock input signal is obtained according to the plurality of symbols and the symbol type of the plurality of symbols, specifically including: querying the decoding state of the clock input signal, the decoding state including a start decoding state and a plurality of intermediate decoding states, the plurality of intermediate decoding states including a first intermediate decoding state and a second intermediate decoding state; when a preset first number of start position symbols are continuously received, it is confirmed that the decoding state of the clock input signal is the start decoding state; when the clock input signal is in the start decoding state, the number of received start position symbols is a preset second number, and the sum of the number of received high-level symbols and the number of received low-level symbols is a third preset number, it is confirmed that the decoding state of the clock input signal changes from the start decoding state to the first intermediate decoding state; and all high-level symbols and low-level symbols received in the process of the clock input signal from the first intermediate decoding state to the second intermediate decoding state are recorded to obtain valid symbols.

[0011] By using the above method, the change of the next decoding state of the clock input signal is determined according to the number of start position symbols, high-level symbols and low-level symbols received in each decoding state, and then the valid symbols in the clock input signal are obtained, so that complete valid symbols can be obtained in the decoding process.

[0012] Optionally, the valid symbols are processed by bit sequence to obtain valid data, specifically including: rearranging the valid symbols in the order of high-bit data first and low-bit data last to obtain rearranged data; and removing the index bit data in the rearranged data to obtain valid data.

[0013] Optionally, the symbol types of multiple symbols include a reference symbol, and the clock compensation time includes a first compensation time, a second compensation time, and a third compensation time; the first compensation time is the time elapsed from the end of the initial decoding state to the acquisition of valid data; the second compensation time is the time elapsed from the first reception of the reference symbol to the second reception of the reference symbol; and the third compensation time is the time elapsed from the start of reception of the second received reference symbol to the end of the initial decoding state.

[0014] By adopting the above method, the delay of each decoding process in the decoding process of the clock compensation signal is obtained respectively, and the above time is used as the clock compensation time, thereby improving the accuracy of the output clock.

[0015] Optionally, the method further includes: when the clock input signal is in the third intermediate decoding state and the decoding action fails, changing the decoding state of the clock input signal to the starting decoding state, wherein the third intermediate decoding state is any one of the multiple intermediate decoding states.

[0016] Optionally, the method further includes: scanning the clock input signal to obtain a signal scanning result; when the first rising edge of the clock input signal appears in the signal scanning result, starting to record the number of crystal oscillator clock cycles for the high-level signal; when the first falling edge of the clock input signal appears in the signal scanning result, ending the recording of the number of crystal oscillator clock cycles for the high-level signal, obtaining the first number of crystal oscillator clock cycles; and starting to record the number of crystal oscillator clock cycles for the low-level signal; when the second rising edge of the clock input signal appears in the signal scanning result, ending the recording of the number of crystal oscillator clock cycles for the low-level signal, obtaining the second number of crystal oscillator clock cycles, wherein the second rising edge is the next rising edge of the first rising edge in the clock input signal.

[0017] By employing the above method, the number of crystal clock cycles for high-level signals and low-level signals is counted based on the rising and falling edges of the clock input signal, so as to obtain the symbol type of multiple symbols in the clock input signal according to the crystal clock cycle.

[0018] A second aspect of this application provides a decoding device for an IRIG-B DC clock code, comprising a signal input unit, a symbol acquisition unit, a data acquisition unit, a time compensation unit, and an information acquisition unit. The signal input unit is used to determine the symbol type of multiple symbols in the clock input signal in response to a clock input signal. The symbol acquisition unit is used to acquire valid symbols in the clock input signal based on the multiple symbols and their symbol types. The data acquisition unit is used to perform bit order processing on the valid symbols to obtain valid data, which includes the standard decoding time corresponding to the clock input signal. The time compensation unit is used to acquire the clock compensation time corresponding to the valid data. The information acquisition unit is used to correct the standard decoding time based on the clock compensation time to obtain the decoding information of the clock input signal.

[0019] A third aspect of this application provides an electronic device, which includes a processor, a memory, a user interface, and a network interface. The memory is used to store instructions, the user interface and the network interface are used to communicate with other devices, and the processor is used to execute the instructions stored in the memory to cause the electronic device to perform any of the methods described above.

[0020] A fourth aspect of this application provides a computer-readable storage medium storing instructions that, when executed, perform any of the methods described above.

[0021] Compared with related technologies, the beneficial effects of this application are:

[0022] 1. By adopting the above method, the problem of a certain delay between the clock signal and the device response during the decoding process is eliminated, which affects the real-time performance and response speed of the system.

[0023] 2. By adopting the above method, the symbol type of multiple symbols in the clock input signal can be obtained based on the number of crystal oscillator clock cycles of the high-level and low-level signals in the clock input signal.

[0024] 3. By adopting the above method, based on the number of start position symbols, high-level symbols, and low-level symbols received in each decoding state, the change in the next decoding state of the clock input signal is determined, thereby completing the acquisition of valid symbols in the clock input signal and ensuring that complete valid symbols can be acquired during the decoding process.

[0025] 4. By adopting the above method, the delay of each decoding process in the decoding process of the clock compensation signal is obtained respectively, and the above time is used as the clock compensation time, thereby improving the accuracy of the output clock. Attached Figure Description

[0026] Figure 1This is a first flowchart illustrating a decoding method for an IRIG-B DC clock code provided in an embodiment of this application;

[0027] Figure 2 This is a second flowchart illustrating a decoding method for an IRIG-B DC clock code provided in an embodiment of this application;

[0028] Figure 3 This is a schematic diagram of the principle of a symbol waveform provided in an embodiment of this application;

[0029] Figure 4 This is a schematic diagram illustrating the principle of pulse width counting provided in an embodiment of this application;

[0030] Figure 5 This is a third flowchart illustrating a decoding method for IRIG-B DC clock code provided in an embodiment of this application;

[0031] Figure 6 This is a schematic diagram illustrating the principle of an IRIG-B DC clock code decoding method provided in an embodiment of this application;

[0032] Figure 7 This is a schematic diagram illustrating the principle of time compensation for an IRIG-B DC clock code provided in an embodiment of this application;

[0033] Figure 8 This is a schematic diagram of the structure of an IRIG-B DC clock code decoding device provided in an embodiment of this application;

[0034] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0035] Reference numerals: 81, Signal input unit; 82, Symbol acquisition unit; 83, Data acquisition unit; 84, Time compensation unit; 85, Information acquisition unit; 900, Electronic device; 901, Processor; 902, Communication bus; 903, User interface; 904, Network interface; 905, Memory. Detailed Implementation

[0036] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0037] In the description of the embodiments of this application, words such as "illustrative," "for example," or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "illustrative," "for example," or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of words such as "illustrative," "for example," or "for example" is intended to present the relevant concepts in a specific manner.

[0038] In the description of the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, or A and B existing simultaneously. Furthermore, unless otherwise stated, the term "multiple" means two or more. For example, multiple systems refer to two or more systems, and multiple screen terminals refer to two or more screen terminals. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0039] This application provides a method for decoding IRIG-B DC clock codes, such as... Figure 1 As shown, the method includes steps S1-S5.

[0040] S1, in response to the clock input signal, determines the symbol type of multiple symbols in the clock input signal.

[0041] In this embodiment, the clock input signal is an IRIG-B DC clock code, a time encoding standard used for synchronizing precise time signals. The IRIG-B DC clock code converts time information into electrical signals. It uses binary encoding, where each symbol represents a unit of time. The IRIG-B DC clock code typically consists of a pulse sequence with a period of 1 second, where the width and polarity of each pulse represent specific time information. It can represent a binary bit as 1 or 0 by a rise or fall in voltage. The IRIG-B DC clock code can be transmitted over different physical media, such as cables and optical fibers. The specific encoding method of the IRIG-B DC clock code can vary depending on different standards, such as IRIG-B002 and IRIG-B003. These standards define parameters such as pulse width, amplitude, and polarity, as well as the specific encoding method for time information. By decoding the IRIG-B DC clock code, precise time information can be obtained for synchronizing various devices and systems, such as power systems, communication systems, and measuring equipment, ensuring they can operate accurately at the same point in time.

[0042] In one possible implementation, such as Figure 2 As shown, in response to the clock input signal, the symbol type of multiple symbols in the clock input signal is determined, specifically including steps S11-S14.

[0043] S11 determines the signal type of the clock input signal.

[0044] Specifically, in the embodiments of this application, the signal waveforms of the high-level signal and the low-level signal can be found in [reference needed]. Figure 3 ,like Figure 3 As shown, "1" symbol represents a high-level signal, and "0" symbol represents a low-level signal.

[0045] S12, when the clock input signal is a high-level signal, record the number of the first crystal clock cycles of the high-level signal.

[0046] S13, when the clock input signal is a low-level signal, record the number of the second crystal clock cycles of the low-level signal.

[0047] like Figure 3 As shown in the example, a waveform diagram of a crystal oscillator clock is given. When the clock input signal is a high-level signal, the number of the first crystal oscillator clock cycles with a positive pulse width is recorded; when the clock input signal is a low-level signal, the number of the second crystal oscillator clock cycles with a negative pulse width is recorded.

[0048] In one possible implementation, such as Figure 4 As shown, it also includes steps S15-S18.

[0049] S15, scan the clock input signal to obtain the signal scan result.

[0050] S16: When the first rising edge of the clock input signal appears in the signal scan result, start recording the number of crystal clock cycles of the high-level signal.

[0051] S17, when the first falling edge of the clock input signal appears in the signal scanning result, stop recording the number of crystal oscillator clock cycles for the high-level signal and obtain the first number of crystal oscillator clock cycles; and start recording the number of crystal oscillator clock cycles for the low-level signal.

[0052] S18, when the second rising edge of the clock input signal appears in the signal scanning result, the recording of the crystal oscillator clock cycle number of the low-level signal ends, and the second crystal oscillator clock cycle number is obtained. The second rising edge is the next rising edge of the first rising edge in the clock input signal.

[0053] Specifically, in this embodiment, the first rising edge of the clock input signal is the rising edge of the first occurrence of the clock pulse, and the first falling edge of the clock input signal is the falling edge of the first occurrence of the clock pulse. The higher the frequency of the crystal oscillator clock, the more accurate the measurement of the positive and negative pulse widths, the more accurate the symbol type determination, and the lower the bit error rate.

[0054] S14. Based on the number of clock cycles of the first crystal oscillator and the number of clock cycles of the second crystal oscillator, the symbol type of multiple symbols in the clock input signal is obtained.

[0055] Specifically, by using the first and second crystal oscillator clock cycles and following a preset correspondence between the crystal oscillator clock cycles and the symbol type, the symbol type of multiple symbols in the clock input signal can be obtained.

[0056] S2, based on multiple symbols and their symbol types, obtains the valid symbols from the clock input signal.

[0057] In one possible implementation, the symbol types of the multiple symbols include start position symbols, high and low level symbols, and low level symbols; based on the multiple symbols and the symbol types of the multiple symbols, the valid symbols in the clock input signal are obtained, specifically including steps S21-S24.

[0058] S21, query the decoding state of the clock input signal. The decoding state includes the initial decoding state and multiple intermediate decoding states, including the first intermediate decoding state and the second intermediate decoding state.

[0059] In this embodiment, the clock input signal contains 100 symbols, and the entire decoding process is divided into 11 states, including ST0, ST1...ST10. States ST0 to ST10 are executed sequentially, and after execution, they return to ST0, with each state repeating cyclically. ST0 is the initial decoding state, and ST1 to ST10 are intermediate decoding states. In this embodiment, the first intermediate decoding state can be ST1, and the second intermediate decoding state can be ST2.

[0060] S22, when a preset first number of start position symbols are received continuously, confirm that the decoding state of the clock input signal is the start decoding state.

[0061] For example, when two consecutive "P" symbols are received, the state is determined to be ST0. In this embodiment of the application, the "P" symbol can be set as the starting position symbol.

[0062] S23, when the clock input signal is in the initial decoding state, if the number of received start position symbols is a preset second number, and the sum of the number of received high-level symbols and low-level symbols is a third preset number, then confirm that the decoding state of the clock input signal has changed from the initial decoding state to the first intermediate decoding state.

[0063] S24 records all high-level and low-level symbols received during the process of the clock input signal from the first intermediate decoding state to the second intermediate decoding state, in order to obtain valid symbols.

[0064] For example, such as Figure 6 As described above, when the number of starting position symbols is 2, and the sum of the number of received high-level symbols and low-level symbols is 8, the decoding state of the clock input signal transitions from the initial decoding state to the ST1 state. When the number of starting position symbols is 1, and the sum of the number of received high-level symbols and low-level symbols is 9, the state machine transitions from ST1 to ST2, or from ST2 to ST3, and so on, until it transitions from ST10 to ST0. Executing ST0-ST10 sequentially once completes the decoding of all valid symbols for the entire second clock.

[0065] In one possible implementation, the valid symbols in the clock input signal are obtained according to the multiple symbols and the symbol types of the multiple symbols, and the implementation further includes step S25.

[0066] S25, when the clock input signal is in the third intermediate decoding state and the decoding action fails, change the decoding state of the clock input signal to the starting decoding state. The third intermediate decoding state is any one of the multiple intermediate decoding states.

[0067] In this embodiment, if decoding of any symbol between ST0 and ST10 fails, including the start position symbol, or if the data symbol '1' or '0' is not confirmed, the time decoding process in this state will be discarded, and the process will return to ST0 and restart the identification of the second clock start code.

[0068] In one possible implementation, the symbol type of the multiple symbols includes a reference symbol, and the clock compensation time includes a first compensation time, a second compensation time, and a third compensation time; the first compensation time is the time elapsed from the end of the initial decoding state to the acquisition of valid data; the second compensation time is the time elapsed from the first reception of the reference symbol to the second reception of the reference symbol; and the third compensation time is the time elapsed from the start of reception of the second received reference symbol to the end of the initial decoding state.

[0069] like Figure 7 As shown, the clock compensation time includes a first compensation time T1, a second compensation time T2, and a third compensation time T3; the number of milliseconds T1 elapsed from the end of ST0 to the device reading the clock via SPI is recorded. The time from the start of the reference symbol to the start of the next adjacent reference symbol is the accurate time T2 = 1000 milliseconds. The time from the start of the next adjacent reference symbol to the end of ST10 is one reference symbol T3 = 10 milliseconds, and the clock compensation time is Tc = T1 + T2 + T3.

[0070] S3 performs bit order processing on the valid symbols to obtain valid data, which includes the standard decoding time corresponding to the clock input signal.

[0071] In one possible implementation, the valid code elements are processed to obtain valid data, specifically including steps S31-S32.

[0072] S31: Rearrange the valid code elements in the order of high-order data first and low-order data last to obtain rearranged data.

[0073] S32 removes the index bits from the rearranged data to obtain the valid data.

[0074] S4, obtain the clock compensation time corresponding to the valid data.

[0075] S5 corrects the standard decoding time based on the clock compensation time to obtain the decoding information of the clock input signal.

[0076] When reading the clock via SPI, the accurate time is T = T0 + Tc. T0 is the valid data, including the standard decoding time corresponding to the clock input signal.

[0077] The beneficial effects that can be achieved by adopting the above method include:

[0078] 1. By adopting the above method, the problem of a certain delay between the clock signal and the device response during the decoding process is eliminated, which affects the real-time performance and response speed of the system.

[0079] 2. By adopting the above method, the symbol type of multiple symbols in the clock input signal can be obtained based on the number of crystal oscillator clock cycles of the high-level and low-level signals in the clock input signal.

[0080] 3. By adopting the above method, based on the number of start position symbols, high-level symbols, and low-level symbols received in each decoding state, the change in the next decoding state of the clock input signal is determined, thereby completing the acquisition of valid symbols in the clock input signal and ensuring that complete valid symbols can be acquired during the decoding process.

[0081] 4. By adopting the above method, the delay of each decoding process in the decoding process of the clock compensation signal is obtained respectively, and the above time is used as the clock compensation time, thereby improving the accuracy of the output clock.

[0082] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0083] This application provides a decoding device for IRIG-B DC clock code, such as... Figure 8 As shown, the decoding device includes a signal input unit 81, a symbol acquisition unit 82, a data acquisition unit 83, a time compensation unit 84, and an information acquisition unit 85.

[0084] The signal input unit 81 is used to determine the symbol type of multiple symbols in the clock input signal in response to the clock input signal input.

[0085] The symbol acquisition unit 82 is used to acquire the valid symbols in the clock input signal based on multiple symbols and the symbol types of the multiple symbols.

[0086] The data acquisition unit 83 is used to perform bit order processing on the valid symbols to obtain valid data, which includes the standard decoding time corresponding to the clock input signal.

[0087] The time compensation unit 84 is used to obtain the clock compensation time corresponding to the valid data.

[0088] The information acquisition unit 85 is used to correct the standard decoding time based on the clock compensation time to obtain the decoding information of the clock input signal.

[0089] In one possible implementation, the signal input unit 81 includes a signal judgment module, a period recording module, and a symbol judgment module.

[0090] The signal determination module is used to determine the signal type of the clock input signal.

[0091] The cycle recording module is used to record the first crystal oscillator clock cycle number when the clock input signal is a high-level signal; it is also used to record the second crystal oscillator clock cycle number when the clock input signal is a low-level signal.

[0092] The symbol determination module is used to determine the symbol type of multiple symbols in the clock input signal based on the number of clock cycles of the first crystal oscillator and the number of clock cycles of the second crystal oscillator.

[0093] In one possible implementation, the symbol acquisition unit 82 includes a status query module, a status change module, and a symbol recording module.

[0094] The status query module is used to query the decoding status of the clock input signal. The decoding status includes the initial decoding status and multiple intermediate decoding statuses, including the first intermediate decoding status and the second intermediate decoding status.

[0095] The state change module is used to confirm that the decoding state of the clock input signal is the starting decoding state when a preset first number of starting position symbols are continuously received; it is also used to confirm that the decoding state of the clock input signal is changed from the starting decoding state to the first intermediate decoding state when the clock input signal is in the starting decoding state, the number of received starting position symbols is a preset second number, and the sum of the number of received high-level symbols and low-level symbols is a third preset number.

[0096] The symbol recording module is used to record all high-level and low-level symbols received during the process of the clock input signal from the first intermediate decoding state to the second intermediate decoding state, so as to obtain valid symbols.

[0097] In a consistent possible implementation, the data acquisition unit 83 includes a data sorting module and a data removal module.

[0098] The data sorting module is used to rearrange the valid code elements in the order of high-order data first and low-order data last to obtain rearranged data.

[0099] The data removal module is used to remove index bits from the rearranged data to obtain valid data.

[0100] In one possible implementation, the symbol acquisition unit 82 further includes a state reset module.

[0101] The state reset module is used to change the decoding state of the clock input signal to the starting decoding state when the decoding action fails while the clock input signal is in the third intermediate decoding state. The third intermediate decoding state can be any one of the multiple intermediate decoding states.

[0102] In one possible implementation, the signal input unit 81 further includes a signal scanning module and a condition judgment module.

[0103] The signal scanning module is used to scan the clock input signal and obtain the signal scanning result.

[0104] The condition judgment module is used to start recording the number of crystal oscillator clock cycles for the high-level signal when the first rising edge of the clock input signal appears in the signal scan result; to stop recording the number of crystal oscillator clock cycles for the high-level signal when the first falling edge of the clock input signal appears in the signal scan result, thus obtaining the first number of crystal oscillator clock cycles; and to start recording the number of crystal oscillator clock cycles for the low-level signal when the second rising edge of the clock input signal appears in the signal scan result, thus obtaining the second number of crystal oscillator clock cycles. The second rising edge is the next rising edge of the first rising edge in the clock input signal.

[0105] It should be noted that the above embodiments of the apparatus are only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0106] Please see Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 9 As shown, the electronic device 900 may include: at least one processor 901, at least one network interface 904, a user interface 903, a memory 905, and at least one communication bus 902.

[0107] The communication bus 902 is used to enable communication between these components.

[0108] The user interface 903 may include a display screen and a camera. Optionally, the user interface 903 may also include a standard wired interface and a wireless interface.

[0109] The network interface 904 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0110] The processor 901 may include one or more processing cores. The processor 901 connects to various parts of the server using various interfaces and lines, and performs various server functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 905, and by calling data stored in the memory 905. Optionally, the processor 901 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 901 may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display; and the modem handles wireless communication. It is understood that the modem may also not be integrated into the processor 901 and may be implemented as a separate chip.

[0111] The memory 905 may include random access memory (RAM) or read-only memory. Optionally, the memory 905 may include a non-transitory computer-readable storage medium. The memory 905 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 905 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 905 may also be at least one storage device located remotely from the aforementioned processor 901. Figure 9 As shown, the memory 905, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and an application program for DC clock code decoding.

[0112] exist Figure 9In the electronic device 900 shown, the user interface 903 is mainly used to provide an input interface for the user and to obtain the user input data; while the processor 901 can be used to call the application program stored in the memory 905 that stores DC clock code decoding. When executed by one or more processors, the electronic device 900 performs one or more of the methods described in the above embodiments.

[0113] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0114] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0115] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some service interfaces; indirect couplings or communication connections between devices or units may be electrical or other forms.

[0116] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0117] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0118] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0119] The above description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of other embodiments of this disclosure upon considering the specification and the disclosure of practical truths. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described in this disclosure.

Claims

1. A method for decoding IRIG-B DC clock code, characterized in that, When applied to a server, the method includes: In response to a clock input signal, the symbol type of multiple symbols in the clock input signal is determined, and the symbol type of the symbol includes a start position symbol, a high / low level symbol, a low level symbol, and a reference symbol. The decoding state of the clock input signal is queried. The decoding state includes an initial decoding state and multiple intermediate decoding states. The multiple intermediate decoding states include a first intermediate decoding state and a second intermediate decoding state. When a preset first number of the starting position symbols are received continuously, it is confirmed that the decoding state of the clock input signal is the starting decoding state; When the clock input signal is in the initial decoding state, if the number of received start position symbols is a preset second number, and the sum of the number of received high-level symbols and low-level symbols is a third preset number, then it is confirmed that the decoding state of the clock input signal has changed from the initial decoding state to the first intermediate decoding state. Record all high-level and low-level symbols received by the clock input signal during the process from the first intermediate decoding state to the second intermediate decoding state to obtain valid symbols; The valid symbols are processed to obtain valid data, which includes the standard decoding time corresponding to the clock input signal. Obtain the clock compensation time corresponding to the valid data, wherein the clock compensation time includes a first compensation time, a second compensation time, and a third compensation time; the first compensation time is the time elapsed from the end of the initial decoding state to the acquisition of valid data; the second compensation time is the time elapsed from the first reception of the reference symbol to the second reception of the reference symbol; the third compensation time is the time elapsed from the start of reception of the second received reference symbol to the end of the initial decoding state. The standard decoding time is corrected based on the clock compensation time to obtain the decoding information of the clock input signal.

2. The method according to claim 1, characterized in that, The step of responding to a clock input signal and determining the symbol type of multiple symbols in the clock input signal specifically includes: Determine the signal type of the clock input signal; When the clock input signal is a high-level signal, record the first crystal clock cycle number of the high-level signal; When the clock input signal is a low-level signal, record the number of the second crystal clock cycles of the low-level signal; Based on the number of clock cycles of the first crystal oscillator and the number of clock cycles of the second crystal oscillator, the symbol types of multiple symbols in the clock input signal are obtained.

3. The method according to claim 1, characterized in that, The step of performing bit order processing on the valid code elements to obtain valid data specifically includes: The valid code elements are rearranged in the order of high-order data first and low-order data last to obtain rearranged data; Remove the index bits from the rearranged data to obtain the valid data.

4. The method according to claim 1, characterized in that, The method further includes: When the clock input signal is in the third intermediate decoding state and the decoding action fails, the decoding state of the clock input signal is changed to the starting decoding state. The third intermediate decoding state is any one of the multiple intermediate decoding states.

5. The method according to claim 2, characterized in that, The method further includes: Scan the clock input signal to obtain the signal scan result; When the first rising edge of the clock input signal appears in the signal scan result, the number of crystal clock cycles of the high-level signal is recorded. When the first falling edge of the clock input signal appears in the signal scanning result, the recording of the crystal clock cycle count of the high-level signal ends, and the first crystal clock cycle count is obtained; and the recording of the crystal clock cycle count of the low-level signal begins. When the second rising edge of the clock input signal appears in the signal scanning result, the recording of the crystal oscillator clock cycle number of the low-level signal ends, and the second crystal oscillator clock cycle number is obtained. The second rising edge is the next rising edge of the first rising edge in the clock input signal.

6. A decoding device for IRIG-B DC clock code, characterized in that, The device includes a signal input unit (81), a symbol acquisition unit (82), a data acquisition unit (83), a time compensation unit (84), and an information acquisition unit (85); The signal input unit (81) is used to determine the code type of multiple code elements in the clock input signal in response to the clock input signal input. The code type of the code element includes start position code element, high and low level code element, low level code element and reference code element. The symbol acquisition unit (82) is used to query the decoding state of the clock input signal. The decoding state includes a starting decoding state and multiple intermediate decoding states. The multiple intermediate decoding states include a first intermediate decoding state and a second intermediate decoding state. When a preset first number of starting position symbols are received continuously, the decoding state of the clock input signal is confirmed to be the starting decoding state. When the clock input signal is in the initial decoding state, if the number of received start position symbols is a preset second number, and the sum of the number of received high-level symbols and low-level symbols is a third preset number, then it is confirmed that the decoding state of the clock input signal has changed from the initial decoding state to the first intermediate decoding state. Record all high-level and low-level symbols received by the clock input signal during the process from the first intermediate decoding state to the second intermediate decoding state to obtain valid symbols; The data acquisition unit (83) is used to perform bit order processing on the valid symbols to obtain valid data, the valid data including the standard decoding time corresponding to the clock input signal; The time compensation unit (84) is used to obtain the clock compensation time corresponding to the valid data, wherein the clock compensation time includes a first compensation time, a second compensation time, and a third compensation time; the first compensation time is the time elapsed from the end of the initial decoding state to the acquisition of valid data; the second compensation time is the time elapsed from the first reception of the reference symbol to the second reception of the reference symbol; the third compensation time is the time elapsed from the start of reception of the second received reference symbol to the end of the initial decoding state. The information acquisition unit (85) is used to correct the standard decoding time based on the clock compensation time to obtain the decoding information of the clock input signal.

7. An electronic device, characterized in that, The electronic device includes a processor (901), a user interface (903), a network interface (904), and a memory (905). The memory (905) is used to store instructions. The user interface (903) and the network interface (904) are used to communicate with other devices. The processor (901) is used to execute the instructions stored in the memory (905) to cause the electronic device (900) to perform the method as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed, perform the method as described in any one of claims 1-5.

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