Reflective semiconductor devices with mirror elements and related methods, wherein an aluminum layer is covered by a double oxide layer.

Abstract

This disclosure relates to a reflective semiconductor device with a mirror element having a double oxide layer above an aluminum layer and related methods. A reflective semiconductor device includes an integrated circuit (IC) structure and a pair of mirror elements located above the IC structure. The pair of mirror elements is separated by trenches. Each mirror element includes a mirror layer, for example aluminum, located on the IC structure and a low-temperature oxide (LTO) layer located on the mirror layer. A high-temperature oxide (HTO) layer is located above the pair of mirror elements and fills the trenches. A liquid crystal layer located above the mirror elements provides a liquid crystal on semiconductor (LCOS) device. Without using a dedicated alloy, the double oxide layer prevents creep and / or coalescence of the mirror layer during HTO layer formation and provides a suitable surface for the LCOS assembly.

Description

Technical Field

[0001] This disclosure relates to reflective semiconductor devices, and more specifically to reflective semiconductor devices including a mirror element having a low-temperature oxide layer above a mirror layer, and a high-temperature oxide layer having a trench filled therebetween above the mirror element. Background Technology

[0002] Reflective semiconductor devices are used in liquid crystal on semiconductor (LCOS) technology, which is used in many applications such as illumination, switching, and near-field displays. LCOS technology uses a liquid crystal layer above a silicon backplane. In displays, LCOS provides an active-matrix liquid crystal display, in which an integrated circuit controls the voltage on a mirror element (e.g., an aluminum electrode) beneath the surface of the logic control chip—that is, the voltage for a pixel. The aluminum mirror element is separated by small trenches. A smooth overlay with a thin oxide layer provides a suitable surface for the LCOS assembly. High-temperature oxides are used to fill the trenches and provide local planarization. High-temperature oxides can cause defects in the aluminum due to temperature-dependent surface creep and / or agglomeration. Current methods use aluminum alloys specifically designed for mirrors, including significant amounts of, for example, copper or silicon, to suppress oxide creep, but the effectiveness of this approach is limited. Summary of the Invention

[0003] One aspect of this disclosure relates to a reflective semiconductor device, comprising: an integrated circuit (IC) structure; a pair of mirror elements located above the IC structure, the pair of mirror elements being separated by a trench, each mirror element comprising: a mirror layer located on the IC structure, and a low-temperature oxide (LTO) layer located on the aluminum layer; and a high-temperature oxide (HTO) layer located above the pair of mirror elements and filling the trench.

[0004] Another aspect of this disclosure includes a reflective semiconductor device comprising: an integrated circuit (IC) structure; a pair of mirror elements located above the IC structure, the pair of mirror elements being separated by a trench, each mirror element comprising: an aluminum layer located on the IC structure, and a low-temperature oxide (LTO) layer located above the aluminum layer; and a high-temperature oxide (HTO) layer located above the pair of mirror elements and filling the trench, wherein the sidewalls of the LTO layer are aligned with the sidewalls of the aluminum layer, and the HTO layer is adjacent to the sidewalls of the LTO layer and the aluminum layer, and wherein the surface of the HTO layer above the LTO layer deviates from the trench between the pair of mirror elements by no more than 10 nanometers.

[0005] Another aspect of this disclosure relates to a method comprising: forming an aluminum layer over an integrated circuit (IC) structure; forming a low-temperature oxide (LTO) layer over the aluminum layer; patterning the aluminum layer and the LTO layer into a pair of mirror elements separated by trenches; forming a high-temperature oxide (HTO) layer over the pair of mirror elements and filling the trenches; and planarizing the HTO layer.

[0006] The above and other features of this disclosure will become apparent from the following more specific description of embodiments thereof. Attached Figure Description

[0007] Embodiments of this disclosure will be described in detail with reference to the following accompanying drawings, wherein similar reference numerals denote similar elements, and wherein:

[0008] Figure 1 A cross-sectional view of the initial structure of a method according to an embodiment of the present disclosure is shown, including a mirror layer and an LTO layer located above the IC structure.

[0009] Figure 2 A cross-sectional view of a mask for patterning an LTO layer and a reflective layer according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A cross-sectional view of the mirror layer and LTO layer after being patterned into a pair of mirror elements according to an embodiment of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view is shown of an HTO layer formed above and between mirror elements according to an embodiment of the present disclosure.

[0012] Figure 5 An enlarged cross-sectional view of the HTO layer located above the pair of mirror elements according to an embodiment of the present disclosure is shown.

[0013] Figure 6 Cross-sectional views of a reflective semiconductor device and an LCOS device according to embodiments of the present disclosure are shown.

[0014] Please note that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, similar reference numerals indicate similar elements between the figures. Detailed Implementation

[0015] In the following description, reference is made to the accompanying drawings, which form a part of this invention, and specific exemplary embodiments in which the present teachings may be practiced are illustrated by way of example. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely illustrative.

[0016] It will be understood that when an element, such as a layer, region, or substrate, is described as being "on" or "above" another element, it can be directly on the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly on" or "directly above" another element, there are no intermediate elements. It should also be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0017] References to "one embodiment" or "embodiment" and other variations thereof in this specification mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment," and any other variations appearing throughout the specification, do not necessarily refer to the same embodiment. It should be understood that the use of " / ", "and / or", and "at least one" in cases such as "A / B", "A and / or B", and "at least one of A and B" is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B). As other examples, in the cases of “A, B, and / or C” and “at least one of A, B, and C”, these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to those skilled in the art, this can be extended to many of the listed items.

[0018] Embodiments of this disclosure provide a reflective semiconductor device comprising an integrated circuit (IC) structure and a pair of mirror elements situated above the IC structure. The pair of mirror elements is separated by trenches. Each mirror element includes a mirror layer, such as aluminum, situated on the IC structure, and a low-temperature oxide (LTO) layer situated on the mirror layer. A high-temperature oxide (HTO) layer is situated above the pair of mirror elements and fills the trenches. A liquid crystal layer situated above the mirror elements provides a liquid crystal on semiconductor (LCOS) device. Without using a dedicated aluminum alloy, the double oxide layer prevents aluminum creep and / or coalescence during HTO layer formation and provides a suitable surface for the LCOS assembly.

[0019] Figures 1 to 6 A reflective semiconductor device 100 according to an embodiment of the present disclosure is shown. Figure 6 A cross-sectional view of the method. Figure 1 An initial structure 110 including an integrated circuit (IC) structure 112 is shown. A portion of the IC structure 112 is located in a semiconductor layer 114. The IC structure 112 may include components suitable for a reflective semiconductor device 100. Figure 6 (For brevity, hereinafter referred to as "device 100") Any circuit now known or later developed for the application of the device. For example, for a display application, IC structure 112 would include logic control for operating the various devices 100 that form the display pixels. Semiconductor layer 114 may include any semiconductor material now known or later developed, such as silicon, silicon germanium, silicon carbide, etc. As understood, device 100, more specifically IC structure 112, is vertically scaled using a stack 120 (partially shown in dashed lines) of contacts in metal interconnect layers or dielectric layers. The final metal layer 122 and the final contact layer 124 of the stack 120 are shown in magnified view. The mirror element 140 of device 100 ( Figures 3 to 6 The interconnect layers are operatively coupled to the IC structure 112 via a stack of interconnect layers 120, which includes a final metal layer 122 and a final contact layer 124. The metal layer 122 may include metal lines, such as copper or aluminum, and the contact layer 124 may include metal contacts within a corresponding dielectric material, such as tungsten.

[0020] Figure 1A mirror layer 130 is also shown formed over the IC structure 112. In some embodiments of this disclosure, the mirror layer 130 may include an aluminum layer 132. The aluminum layer 132 is not an alloy and comprises, for example, >99% by weight, almost pure aluminum. In other embodiments, the mirror layer 130 may include silver or gold. The mirror layer 130 is formed by deposition, such as, but not limited to, physical vapor deposition (PVD) or metal-organic chemical vapor deposition (MOCVD). The mirror layer 130 is not formed by an edging method, for example, having trenches formed in a dielectric and filled with a material such as by electroplating. In some embodiments, the mirror layer 130 (e.g., the aluminum layer 132) may have a thickness of no more than 50 nanometers (nm); however, other thicknesses are also possible. The aluminum layer 132 may have a root mean square surface roughness of no more than 5 nanometers, which is protected and maintained by using a double oxide layer, as described herein.

[0021] Figure 1 Also shown is a low-temperature oxide (LTO) layer 138 formed above the mirror layer 130, for example, above the aluminum layer 132. The LTO layer 138 can be formed prior to patterning the mirror layer 130 using any now-known or later-developed low-temperature oxide formation technique. For example, the LTO layer 138 can be formed using a CVD process employing a silane (SiH4) precursor and a deposition temperature in the range of approximately 170-230°C (e.g., approximately 200°C). The LTO layer 138 thus comprises silane-based silicon oxide (SiO2).

[0022] Figures 2 to 3 The diagram shows a pair of mirror elements 140 patterned with a mirror layer 130 (e.g., aluminum layer 132) and an LTO layer 138 separated by trenches 142. Figure 3A cross-sectional view of the image is shown. Although a pair of mirror elements 140 are shown, it will be appreciated that for most applications, a much larger number of mirror elements 140 are typically formed in an array in this process. For example, for a display, a mirror element would be formed for each pixel, and for a high-definition display, there could be millions of mirror elements. The process can be performed by forming a mask 144 over the LTO layer 138 and the mirror layer 130, patterning the mask 144, and etching the LTO layer 138 and the mirror layer 130. The mask 144 can include any suitable mask material for layers 130, 138. Common mask materials are photoresists (resists) and nitrides. Nitrides are generally considered "hard masks". The mask can include a developable organic planarization layer (OPL) on the layer to be etched, a developable antireflective coating (ARC) on a developable OPL, and a photoresist mask layer on a developable ARC layer. The etching process can include any suitable etching chemistry for layers 130, 138. In a non-limiting example, etching may include a reactive ion etching (RIE) process.

[0023] Figure 3 The structure after removing mask 144 is shown. Mask 144 can be removed using any known removal process suitable for the mask material, such as wet etching for hard nitride masks or ashing processes (oxygen dry stripping processes) for soft resist-based masks. Each mirror element 140 includes a mirror layer 130 on IC structure 112 and an LTO layer 138 on mirror layer 130 (e.g., aluminum layer 132). Due to simultaneous formation, LTO layer 138 has sidewalls 146 aligned with sidewalls 148 of mirror layer 130. In some embodiments, trench 142 may have a width W1 not greater than 100 nm. For example, in some embodiments, trench 142 may have a width W1 as small as 53 nm.

[0024] Figure 4 The groove 142 formed and filled above the mirror element 140 is shown. Figure 3 A cross-sectional view of the high-temperature oxide (HTO) layer 150. The HTO layer 150 can be formed using any now-known or later-developed high-temperature oxide forming technique. For example, the HTO layer 150 can be formed using a CVD process that uses a tetraethyl orthosilicate (TEOS) precursor and a deposition temperature in the range of approximately 350-480°C, such as 415°C. Thus, the HTO layer 150 comprises TEOS-based silicon oxide (SiO2). Because the HTO layer 150 fills the trench 142, the HTO layer 150 is adjacent to the sidewalls 146, 148 of the LTO layer 138 and the mirror layer 130 (e.g., the aluminum layer 132), respectively.

[0025] Figure 5 An enlarged cross-sectional view of a mirror element 140 having an HTO layer 150 after planarization is shown. Planarization can include any planarization technique now known or developed later, such as, but not limited to, chemical mechanical planarization (CMP). Planarization smooths the surface of the HTO layer 150. If desired, optional removal steps can be performed to further refine the thickness of the HTO layer 150. For example, in Figure 5 After planarization, a portion of the HTO layer 150 (dashed box) can be removed using any suitable oxide etching process. In some embodiments, the LTO layer 138 and the HTO layer 150 have a cumulative thickness T of no more than 100 nm above the mirror layer 130 (e.g., aluminum layer 132). During the high-temperature formation of the HTO layer 150, the LTO layer 138 protects the mirror layer 130 from creep and coalescence. The surface 152 of the HTO layer 150 is relatively smooth to allow the formation of additional layers 168 thereon, including the liquid crystal layer 170. Figure 6 ), used to form a liquid crystal on semiconductor (LCOS) device 102 ( Figure 6 In some embodiments, the deviation of surface 152 above LTO layer 138 relative to trench 142 between pairs of mirror elements 140 is no greater than a distance D (e.g., 10 nm). Any deviation in surface 152 caused by HTO layer 150 filling trench 142 is minimized, providing a smooth surface for the LCOS assembly. Furthermore, because LTO layer 138 protects mirror layer 138 during HTO layer 150 formation, mirror layer 130 can have a deviation of no greater than D in device 100. Root mean square (RMS) surface roughness Figure 6 ).

[0026] Figure 6 A cross-sectional view is shown showing a plurality of additional layers 168 formed over an HTO layer 150 to form a device 100 and / or an LCOS device 102. In various embodiments, the additional layers 168 may include, but are not limited to: a transparent protective capping layer required to produce the LCOS device 102 according to embodiments of the present disclosure, a liquid crystal layer 170, alignment layers (e.g., a top alignment layer and a bottom alignment layer), a transparent electrode layer, a glass substrate with an anti-reflective coating, and polarization layers (e.g., a polarizer and analyzer, or a polarization beam splitter layer). Any suitable deposition technique can be used to form the additional layers 168.

[0027] like Figure 6As shown, the reflective semiconductor device 100 includes a pair of mirror elements 140 located above an IC structure 112. The pair of mirror elements 140 is separated by trenches 142 (filled by an HTO layer 150). In some embodiments, the trenches 142 may have a width W1 of no more than 100 nm. For example, in some embodiments, the trenches 142 may have a width W1 as small as 53 nm. Thus, there is a width W1 between the mirror elements 140. The mirror elements 140 of the device 100 may include a mirror layer 130 located on the IC structure 112. In some embodiments, the mirror layer 130 may include an aluminum layer 132. As previously stated, the aluminum layer 132 is not an alloy and comprises, for example, >99% by weight of almost pure aluminum. In other embodiments, the mirror layer 130 may include silver or gold. In some embodiments, the mirror layer 130 (e.g., the aluminum layer 132) may have a thickness of no more than 50 nanometers; however, other thicknesses are also possible. The mirror layer 130 may have a root mean square (RMS) surface roughness of no more than 50 angstroms.

[0028] The mirror element 140 may also include an LTO layer 138 located on the mirror layer 130. The LTO layer may include silane-based silicon oxide (SiO2). The LTO layer 138 has sidewalls 146 aligned with the sidewalls 148 of the mirror layer 130.

[0029] Device 100 may further include an HTO layer 150 located above the pair of mirror elements 140 and filling trench 142. The HTO layer 150 may comprise TEOS-based silicon oxide (SiO2). In some embodiments, the LTO layer 138 and HTO layer 150 have a cumulative thickness T of no more than 100 nm above the mirror layer 130 (e.g., aluminum layer 132). As previously described, during the high-temperature formation of the HTO layer 150, the LTO layer 138 protects the mirror layer 130 from creep and coalescence. In some embodiments, the surface 152 above the LTO layer 138 deviates from the trench 142 between the pair of mirror elements 140 by no more than a distance D (e.g., about 10 nm). Because the HTO layer 150 fills the trench 142, the HTO layer 150 is adjacent to the sidewalls 146, 148 of the LTO layer 138 and the mirror layer 130 (e.g., aluminum layer 132), respectively. Figure 6Device 100 including an additional layer 168 of LCOS components is also shown. These layers can vary depending on the device type and manufacturer. In a non-limiting example, these layers (not all shown) may include: an alignment or alignment layer disposed above the mirror element 140, a liquid crystal layer 170, another alignment layer, a top electrode layer (e.g., of a transparent conductive oxide), and a glass layer. Other layers may include other transparent protective capping layers, alignment layers for liquid crystal alignment, transparent electrode layers, anti-reflective coatings, glass substrates, polarizing layers, or similar layers required to produce LCOS device 102. In this way, reflective semiconductor device 100 may be LCOS device 102.

[0030] The embodiments disclosed herein offer various technical and commercial advantages, examples of which are discussed herein. Without the use of specialized alloys, the dual oxide layer arrangement disclosed herein prevents creep and / or coalescence of the mirror layer (aluminum) during HTO layer formation and provides a suitable surface for the LCOS assembly.

[0031] The methods described above are used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0033] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximate,” and “substantially” are not limited to the specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. The term “approximate” applied to a specific value within a range applies to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of said value.

[0034] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. A reflective semiconductor device, comprising: Integrated circuit (IC) structure; A pair of mirror elements located above the IC structure, the pair of mirror elements being separated by trenches, each mirror element comprising: The mirror layer located on the IC structure, and A low-temperature oxide (LTO) layer is located on the reflector layer; as well as A high-temperature oxide (HTO) layer is located above the mirror element and fills the trench.

2. The reflective semiconductor optical device of claim 1, wherein, The reflective layer is primarily composed of aluminum.

3. The reflective semiconductor device according to claim 1, wherein, The surface of the HTO layer above the LTO layer deviates by no more than 10 nanometers from the groove between the pairs of mirror elements.

4. The reflective semiconductor device according to claim 1, wherein, The reflector layer has a thickness of no more than 50 nanometers, and the LTO layer and the HTO layer have a cumulative thickness of no more than 100 nanometers above the reflector layer.

5. The reflective semiconductor device according to claim 1, wherein, The trench has a width of no more than 100 nanometers.

6. The reflective semiconductor device according to claim 1, wherein, The LTO layer comprises silane-based silicon oxide (SiO2), and the HTO layer comprises tetraethyl orthosilicate (TEOS)-based silicon oxide (SiO2).

7. The reflective semiconductor device according to claim 1, wherein, The sidewall of the LTO layer is aligned with the sidewall of the mirror layer, and the HTO layer is adjacent to the sidewall of the LTO layer and the mirror layer.

8. The reflective semiconductor device according to claim 1, further comprising a liquid crystal layer disposed above the mirror element, wherein, The reflective semiconductor device is a liquid crystal on semiconductor (LCOS) device.

9. A reflective semiconductor device, comprising: Integrated circuit (IC) structure; A pair of mirror elements located above the IC structure, the pair of mirror elements being separated by trenches, each mirror element comprising: The aluminum layer located on the IC structure, and A low-temperature oxide (LTO) layer located above the aluminum layer; and A high-temperature oxide (HTO) layer is located above the mirror element and fills the trench. Wherein, the sidewall of the LTO layer is aligned with the sidewall of the aluminum layer, and the HTO layer is adjacent to the sidewalls of the LTO layer and the aluminum layer, and Wherein, the surface of the HTO layer above the LTO layer deviates by no more than 10 nanometers from the groove between the pairs of the reflector elements.

10. The reflective semiconductor device according to claim 9, wherein, The aluminum layer has a thickness of no more than 50 nanometers, and the LTO layer and the HTO layer have a cumulative thickness of no more than 100 nanometers above the aluminum layer.

11. The reflective semiconductor device according to claim 9, wherein, The trench has a width of no more than 100 nanometers.

12. The reflective semiconductor device according to claim 9, wherein, The LTO layer comprises silane-based silicon oxide (SiO2), and the HTO layer comprises tetraethyl orthosilicate (TEOS)-based silicon oxide (SiO2).

13. The reflective semiconductor device according to claim 9 further includes a liquid crystal layer disposed above the mirror element, and the reflective semiconductor device is a liquid crystal on semiconductor (LCOS) device.

14. A method for forming a reflective semiconductor device, comprising: An aluminum layer is formed on top of the integrated circuit (IC) structure; A low-temperature oxide (LTO) layer is formed on top of the aluminum layer; The aluminum layer and the LTO layer are patterned into pairs of mirror elements separated by trenches; A high-temperature oxide (HTO) layer is formed above the mirror element and fills the trench; as well as Planarize the HTO layer.

15. The method according to claim 14, wherein, The surface of the HTO layer above the LTO layer deviates by no more than 10 nanometers from the groove between the pairs of mirror elements.

16. The method of claim 14, wherein, The trench has a width of no more than 100 nanometers.

17. The method of claim 14, further comprising removing a portion of the HTO layer after the planarization to refine the thickness of the HTO layer.

18. The method according to claim 14, wherein, The sidewall of the LTO layer is aligned with the sidewall of the aluminum layer, and the HTO layer is adjacent to the sidewalls of the LTO layer and the aluminum layer.

19. The method of claim 14, further comprising forming a liquid crystal layer disposed above the mirror element.

20. The method of claim 14, wherein, The LTO layer comprises silane-based silicon oxide (SiO2), and the HTO layer comprises tetraethyl orthosilicate (TEOS)-based silicon oxide (SiO2).

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