Data processing method based on reliability of NAND flash

Abstract

The application relates to a data processing method based on NAND Flash reliability, and belongs to the technical field of memories, and solves the problem of low data reliability of an existing NAND Flash data processing method. The method comprises the following steps: obtaining NAND Flash data to be written; selecting m logical pages for a shift operation, dividing the NAND Flash data to be written into sub-data, each sub-data being represented by a logical page sub-data, each logical page sub-data comprising data bit data, and adding an identification redundant bit data in the selected logical page for the shift operation; performing a cyclic shift on the data bit data of the selected logical page sub-data in each sub-data to obtain the minimum data reliability score of each sub-data; taking the data bit data and the shift number of the m shift logical page sub-data corresponding to the minimum data reliability score of each sub-data as the data bit data and the identification redundant bit data of the corresponding m logical page sub-data of each sub-data after coding to obtain each sub-data after coding, and further obtain the NAND Flash data after coding.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a data processing method based on the reliability of NAND Flash. Background Technology

[0002] Solid State Drives (SSDs) are now widely recognized in the market, widely used in electronic devices such as mobile phones, computers, and servers. Their high performance, low cost, and high reliability have gradually replaced the once mainstream storage device, the mechanical hard drive. As the primary storage medium in SSDs, NAND Flash plays a crucial role in the storage market, boasting significantly faster read and write speeds, very high storage density, and highly stable and reliable data storage capabilities. With the advent of the big data era, consumers' demand for increased data storage capacity is becoming increasingly urgent. To achieve greater storage density, NAND Flash has evolved from 2D NAND Flash to 3D NAND Flash. In the 3D NAND Flash era, storage density is increased by reducing the cell size or increasing the number of bits that each cell can represent. However, both methods reduce the data retention capacity and reliability of 3D NAND Flash.

[0003] Among the many factors that lead to a decline in NAND Flash reliability, the impact of data retention characteristics on the threshold voltage state of memory cells is the most severe, and has become a hot topic in 3D NAND Flash reliability research. For example, in a 3D TLC NAND Flash array, each memory cell can be represented by eight different threshold voltage states, each representing a different amount of charge stored in the cell. A higher voltage state indicates a higher electric field strength in the tunneling oxide direction. Since data retention characteristics are related to charge loss, leakage current, and charge detrapping processes, memory cells in higher threshold voltage states are more prone to leftward shift, which is the threshold voltage state asymmetric error related to flash memory data retention characteristics.

[0004] Current data processing methods involve transmitting data to be written to NAND Flash from the host to the NAND Flash Controller (NFC). This data may be transmitted directly without processing, resulting in a randomized distribution of threshold voltage state cells. Alternatively, traditional data processing methods may use a randomized data scrambling module implemented with a linear feedback shift register to improve data reliability by altering the data to an almost uniform quantity. However, neither approach takes into account reliability issues related to data retention characteristics, leading to a higher raw bit error rate and lower data reliability in NAND Flash when data retention time is long. Summary of the Invention

[0005] Based on the above analysis, the present invention aims to provide a data processing method based on NAND Flash reliability, in order to solve the problem that existing NAND Flash data processing methods do not consider the impact of data retention characteristics, resulting in low data reliability of NAND Flash.

[0006] This invention provides a data processing method based on NAND Flash reliability, comprising the following steps:

[0007] Obtain the data of each physical page of the NAND Flash to be written, wherein the storage unit of a physical page in the NAND Flash is represented by at least one logical page;

[0008] Select m logical pages for shifting operations, where m is greater than or equal to 1, and divide the data of each physical page of the NAND Flash to be written into sub-data based on the preset code length. Each sub-data is represented by the sub-data of each logical page, and each logical page sub-data includes data bits. Add redundant identification bits to the selected logical pages to be shifted.

[0009] The data bits of the selected logical page sub-data in each sub-data are cyclically shifted to obtain the data reliability score of each sub-data after each shift and the data reliability score before each shift, and then the minimum data reliability score of each sub-data is obtained; wherein, the maximum number of shifts for the selected logical page sub-data to be shifted is the number of data bits in the logical page data minus 1;

[0010] The data bits and shift count of the m shifted logical page sub-data corresponding to the minimum data reliability score of each sub-data are used as the data bits and redundancy flags of the corresponding m logical page sub-data after encoding each sub-data. The data bits of the remaining logical page sub-data in each sub-data remain unchanged, thus obtaining the encoded sub-data, and then obtaining the encoded NAND Flash data.

[0011] Furthermore, the data reliability score RS is obtained in the following way:

[0012]

[0013] In the formula, n represents the total number of storage cells in the current sub-data, and RBER(state(k)) represents the raw bit error rate of the voltage state corresponding to the k-th storage cell in the current sub-data.

[0014] Furthermore, the cyclic shift of the selected logical page sub-data bits to be shifted is either a cyclic right shift or a cyclic left shift, and each shift is 1 bit.

[0015] Alternatively, if m = 1, then

[0016] Data reliability score based on the corresponding sub-data obtained from each sub-data before shifting;

[0017] Based on the selected logical page, the data bits of the sub-data in each logical page are cyclically shifted in turn to obtain the voltage state of each storage cell after each shift of each sub-data, and then the data reliability score of each sub-data after each shift is obtained.

[0018] Based on the data reliability score after each shift and the data reliability score before each shift, the minimum data reliability score of each sub-data is obtained;

[0019] The data bits and shift count of the shifted logical page sub-data corresponding to the minimum data reliability score of each sub-data are used as the data bits and redundancy flags of the corresponding logical page sub-data after encoding each sub-data. The data bits of the remaining logical page sub-data in each sub-data remain unchanged, thus obtaining the encoded sub-data.

[0020] Alternatively, if m is greater than 1, then

[0021] Select one unshifted logical page from m logical pages and perform cyclic shifting to obtain the minimum data reliability score of each sub-data. Then, use the data bit data and shift count of the current logical page sub-data corresponding to the minimum data reliability score of each sub-data as the data bit data and redundancy identification bit data of the current logical page sub-data after encoding each sub-data.

[0022] Based on the current logical page of each encoded sub-data, repeat the above steps to perform cyclic shifting on the next unshifted logical page until all m logical pages have been shifted, thus obtaining the corresponding encoded logical page sub-data. The data bits of the remaining logical page sub-data in each sub-data remain unchanged, thereby obtaining the encoded sub-data.

[0023] Alternatively, if m is greater than 1, then

[0024] Based on the selected number of logical pages m, any logical page is selected in sequence as the 1st, ..., mth logical page; and the data reliability score of the corresponding sub-data obtained based on each sub-data before shifting is used as the initial value of the data reliability score of the corresponding sub-data.

[0025] By performing the following traversal steps to cyclically shift the data bits of the logical page sub-data in each sub-data, the minimum data reliability score of each sub-data is obtained:

[0026] Based on the first logical page, perform a cyclic shift on the data bits of the current sub-data within that logical page. For each shift, execute the following steps until the current shift count for that logical page equals the maximum shift count:

[0027] Based on the second logical page, the data bits of the current sub-data in that logical page are cyclically shifted. Each shift executes the following steps until the current shift count of that logical page equals the maximum shift count:

[0028] And so on,

[0029] Based on the m-th logical page, the data bits of the sub-data of the logical page in the current sub-data are cyclically shifted. After each shift, the data reliability score of the current sub-data is obtained. If the data reliability score is less than the initial value of the data reliability score, then the data reliability score is used as the initial value of the data reliability score.

[0030] The initial value of the data reliability score obtained after traversing is used as the minimum data reliability score of the current sub-data.

[0031] The data bits and shift count of the m shifted logical page sub-data corresponding to the minimum data reliability score of each sub-data are used as the data bits and redundancy flag bits of the corresponding m logical page sub-data after encoding each sub-data. The data bits of the remaining logical page sub-data in each sub-data remain unchanged, thus obtaining the encoded sub-data.

[0032] Furthermore, the total number of stored data bits d in each logical page sub-data is the same and corresponds one-to-one with the sub-data storage unit. The data bits and redundant flag bits in the selected logical page sub-data for shifting satisfy the following formula:

[0033] d = n′ + l,

[0034] in,

[0035] In the formula, l represents the number of redundant bits in the selected logical page sub-data to be shifted; n′ represents the number of data bits in the selected logical page sub-data to be shifted. This indicates rounding up to the nearest integer.

[0036] Furthermore, the preset code length is 8, 16, 32, 64 or 128 storage units.

[0037] Furthermore, the original bit error rate of each voltage state is obtained based on the bit error rate of each voltage state stored in the NAND Flash under different hold times and number of program erase cycles.

[0038] Furthermore, the data processing method also includes a decoding process, specifically:

[0039] The sub-data of the NAND Flash to be decoded is obtained according to the preset code length. The number of shifts of the data bits of each logical page sub-data is obtained according to the redundancy flag bits in each logical page sub-data. Then, the corresponding logical page data is cyclically shifted in reverse according to the corresponding number of shifts to obtain the decoded sub-data, and thus obtain the decoded NAND Flash data.

[0040] Compared with the prior art, the present invention can achieve the following beneficial effects:

[0041] This invention provides a data processing method based on NAND Flash reliability. After dividing the NAND Flash data into sub-data, the corresponding logical page sub-data within each sub-data is cyclically shifted according to the selected logical page. This yields a data reliability score for each sub-data after each shift and a data reliability score before the shift. The method then obtains the minimum data reliability score for each sub-data, resulting in encoded sub-data and finally encoded NAND Flash data. This encoding method provides higher data reliability. Furthermore, the data reliability score is obtained by using the original voltage-state bit error rate of each memory cell in each sub-data. This fully considers the asymmetry of voltage-state bit error rate in data retention characteristics, reducing the proportion of voltage states that dominate the bit error rate contribution and improving data reliability.

[0042] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0043] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0044] Figure 1This is a flowchart illustrating the data processing method based on NAND Flash reliability provided in Embodiment 1 of the present invention;

[0045] Figure 2 This is a schematic diagram of the system structure for implementing the data processing method provided in Embodiment 1 of the present invention;

[0046] Figure 3 This is a schematic diagram illustrating the threshold changes of various voltage states in the 3D TLC NAND Flash provided in Embodiment 2 of the present invention as the data retention time increases.

[0047] Figure 4 This is a schematic diagram of the encoding process in data processing provided in Embodiment 2 of the present invention;

[0048] Figure 5 This is a schematic diagram of the decoding process in data processing provided in Embodiment 2 of the present invention;

[0049] Figure 6 This is a statistical bar chart showing the proportion of each voltage state after method 1 encoding and random encoding provided in Embodiment 2 of the present invention;

[0050] Figure 7 This is a statistical bar chart showing the proportion of each voltage state after method 1 encoding and random encoding under different code lengths provided in Embodiment 2 of the present invention;

[0051] Figure 8 This is a statistical bar chart showing the proportion of each voltage state after different encoding methods and random encoding provided in Embodiment 2 of the present invention.

[0052] Figure 9 This is a statistical bar chart showing the proportion of each voltage state after three-code encoding and random encoding under different code lengths provided in Embodiment 2 of the present invention. Detailed Implementation

[0053] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0054] Example 1

[0055] A specific embodiment of the present invention discloses a data processing method based on NAND Flash reliability, such as... Figure 1 As shown, it includes the following steps:

[0056] S1. Obtain the data of each physical page of the NAND Flash to be written. Each physical page in the NAND Flash is represented by at least one logical page. It can be understood that each physical page in the NAND Flash stores bit data in a threshold voltage state. The number of bits is equal to the number of logical pages. By establishing a mapping relationship between the threshold voltage state, the bit data to be stored, and the logical pages, the relevant data is represented and stored. The threshold voltage state represents the amount of stored charge.

[0057] Specifically, the NAND Flash includes 3D SLC / MLC / TLC / QLC NAND Flash. In 3D SLC NAND Flash, each physical page contains one logical page, and each storage unit stores 1 bit of information; in 3D MLC NAND Flash, each physical page contains two logical pages, and each storage unit stores 2 bits of information; in 3D TLC NAND Flash, each physical page contains three logical pages, and each storage unit stores 3 bits of information; in 3D QLC NAND Flash, each physical page contains four logical pages, and each storage unit stores 4 bits of information. More specifically, the data processing method of this embodiment is applicable to SLC / MLC / TLC / QLC NAND Flash with any number of layers.

[0058] S2. Select m logical pages for shifting operations, where m is greater than or equal to 1. Based on a preset code length, divide the data of each physical page of the NAND Flash to be written into sub-data, where each sub-data is represented by the sub-data of each logical page, and each logical page sub-data includes data bits. Add redundant identification bits to the selected logical pages for shifting. Here, m is less than or equal to the total number of logical pages in the NAND Flash physical page. It is understandable that the number of logical pages that can be shifted is selected according to the total number of logical pages contained in the physical page of different types of NAND Flash. For example, if the physical page contains only one logical page, then m = 1 can be selected; if the physical page contains three logical pages, then m can be 1, 2, or 3.

[0059] In implementation, the code length is set according to actual needs. A smaller code length results in a lower data bitrate (because redundant identifier bits added by subsequent applications occupy storage unit area). Preferably, the preset code length is 8, 16, 32, 64, or 128 storage units. For example, each physical page of NAND Flash has 147,456 storage units; a code length of 8 results in a bitrate of 72.73%, and a code length of 128 results in a bitrate of 94.81%.

[0060] In implementation, the total number of stored data bits d in each logical page sub-data is the same and corresponds one-to-one with the sub-data storage unit. The data bits and redundant flag bits in the logical page sub-data selected for shifting satisfy the following formula:

[0061] d = n′ + l,

[0062] in,

[0063] In the formula, l represents the number of redundant bits in the logical page sub-data selected for shifting; n′ represents the number of data bits in the logical page sub-data selected for shifting. This indicates rounding up to the nearest integer.

[0064] It is understandable that the total number of data bits d in each logical page sub-data is equal to the number of storage units n in the preset code length, forming a one-to-one correspondence. That is, the sum of the number of data bits and the number of redundant flag bits in the selected shifted logical page sub-data is the total number of data bits d, and the number of data bits in the remaining unshifted logical page data is also the total number of data bits d. In this embodiment, redundant flag bits are added to each selected shifted logical page data to record the number of shifts during the encoding process. These redundant flag bits are used for decoding during the decoding process. Furthermore, the redundant flag bits are added horizontally along the logical page. When decoding subsequent logical pages, the redundant flag bits in the corresponding logical page data are used, avoiding the need to simultaneously obtain data from all logical pages when decoding a single logical page, which would complicate the operation.

[0065] S3. Circularly shift the data bits of the selected logical page sub-data in each sub-data to obtain the data reliability score after each shift and the data reliability score before the shift, and then obtain the minimum data reliability score of each sub-data; wherein, the maximum number of shifts for the selected logical page sub-data to be shifted is the number of data bits in the logical page data minus 1.

[0066] In practice, the data reliability score RS is obtained in the following way:

[0067]

[0068] In the formula, n represents the total number of storage cells in the current sub-data, and RBER(state(k)) represents the raw bit error rate of the voltage state corresponding to the k-th storage cell in the current sub-data. RS represents the data reliability score, and RBER represents the raw bit error rate.

[0069] In practice, the original bit error rate of each voltage state is obtained based on the bit error rate of each voltage state stored in the NAND Flash under different hold times and number of program erase cycles.

[0070] Specifically, the bit error rate (BER) of each voltage state stored in the NAND Flash under different hold times and program / erase cycles is statistical data obtained from extensive testing of actual chips. This data is stored in the host-side NAND Flash Controller as a lookup table during data processing and can be directly retrieved when needed. The program / erase cycle (P / E cycle) is defined as one program and one erase operation per memory cell. Since erasure is performed on a block basis, the basic unit of a P / E cycle is a block. For example, a P / E cycle of 0k means a block has been programmed / eraseed 0 times, and a P / E cycle of 3k means a block has been programmed / eraseed 3,000 times.

[0071] It is understandable that, for the non-uniformity of local data, the distribution ratio of voltage states in sub-data of each code length is non-uniform and random. This embodiment uses the inconsistency of data at different positions to perform a cyclic shift operation on sub-data of each code length. Based on the original bit error rate information corresponding to each voltage state measured by actual data, the average value of the original bit error rate corresponding to each voltage state in the sub-data is obtained by summing the original bit error rate of each voltage state in the sub-data as the data reliability score. By cyclic shifting, the proportion of voltage states in the sub-data is changed until the minimum data reliability score is reached. In this way, the reliability of stored data is improved.

[0072] In practice, the cyclic shift of the selected logical page sub-data bits to be shifted is either a cyclic right shift or a cyclic left shift, and each shift is 1 bit.

[0073] S4. Take the data bits and shift count of the m shifted logical page sub-data corresponding to the minimum data reliability score of each sub-data as the data bits and redundancy flags of the corresponding m logical page sub-data after encoding each sub-data. The data bits of the remaining logical page sub-data in each sub-data remain unchanged, thus obtaining the encoded sub-data, and then obtaining the encoded NAND Flash data.

[0074] During implementation, the encoded sub-data is obtained through the following specific methods:

[0075] Method 1: If m = 1, then

[0076] Data reliability score based on the corresponding sub-data obtained from each sub-data before shifting;

[0077] Based on the selected logical page, the data bits of the sub-data in each logical page are cyclically shifted in turn to obtain the voltage state of each storage cell after each shift of each sub-data, and then the data reliability score of each sub-data after each shift is obtained.

[0078] Based on the data reliability score after each shift and the data reliability score before each shift, the minimum data reliability score of each sub-data is obtained;

[0079] The data bits and shift count of the shifted logical page sub-data corresponding to the minimum data reliability score of each sub-data are used as the data bits and redundancy flags of the corresponding logical page sub-data after encoding each sub-data. The data bits of the remaining logical page sub-data in each sub-data remain unchanged, thus obtaining the encoded sub-data.

[0080] Understandably, before the shift, the data reliability score can be obtained based on the voltage state distribution of each sub-data. This data reliability score is compared with the data reliability score of each sub-data after each shift. If the data reliability score is the lowest, then the data bits of the sub-data of the shifted logical page before the shift and the number of shifts are used as the data bits and the redundancy flag of the sub-data of the logical page after the sub-data is encoded, where the number of shifts is 0.

[0081] Method 2: If m is greater than 1, then

[0082] Select one unshifted logical page from m logical pages and perform cyclic shifting to obtain the minimum data reliability score of each sub-data. Then, use the data bit data and shift count of the current logical page sub-data corresponding to the minimum data reliability score of each sub-data as the data bit data and redundancy identification bit data of the current logical page sub-data after encoding each sub-data.

[0083] Based on the current logical page of each encoded sub-data, repeat the above steps, cyclically shifting the next unshifted logical page until all m logical pages have been shifted, obtaining the corresponding encoded logical page sub-data. The data bits of the remaining logical page sub-data in each sub-data remain unchanged, thus obtaining the encoded sub-data. It can be understood that when shifting the m logical page sub-data, the next logical page sub-data is cyclically shifted based on the shift result of the previous logical page sub-data, i.e., the encoded logical page sub-data, to obtain the data reliability score.

[0084] It should be noted that before each logic page is shifted, a data reliability score can be obtained based on the voltage state distribution of each sub-data. This data reliability score is used to select the minimum data reliability score for each sub-data. In other words, when cyclically shifting the next unshifted logic page, the data reliability score before the shift of that logic page is obtained based on the logic sub-data in the current sub-data. That is, the minimum data reliability score obtained by the previous shifted logic page is used as the data reliability score before the shift of this logic page.

[0085] Method 3: If m is greater than 1, then

[0086] Based on the selected number of logical pages m, any logical page is selected in sequence as the 1st, ..., mth logical page; and the data reliability score of the corresponding sub-data obtained based on each sub-data before shifting is used as the initial value of the data reliability score of the corresponding sub-data.

[0087] By performing the following traversal steps to cyclically shift the data bits of the logical page sub-data in each sub-data, the minimum data reliability score of each sub-data is obtained:

[0088] Based on the first logical page, perform a cyclic shift on the data bits of the current sub-data within that logical page. For each shift, execute the following steps until the current shift count for that logical page equals the maximum shift count:

[0089] Based on the second logical page, the data bits of the current sub-data in that logical page are cyclically shifted. Each shift executes the following steps until the current shift count of that logical page equals the maximum shift count:

[0090] And so on,

[0091] Based on the m-th logical page, the data bits of the sub-data of the logical page in the current sub-data are cyclically shifted. After each shift, the data reliability score of the current sub-data is obtained. If the data reliability score is less than the initial value of the data reliability score, then the data reliability score is used as the initial value of the data reliability score.

[0092] The initial value of the data reliability score obtained after traversing is used as the minimum data reliability score of the current sub-data.

[0093] The data bits and shift count of the m shifted logical page sub-data corresponding to the minimum data reliability score of each sub-data are used as the data bits and redundancy flag bits of the corresponding m logical page sub-data after encoding each sub-data. The data bits of the remaining logical page sub-data in each sub-data remain unchanged, thus obtaining the encoded sub-data.

[0094] For example, if m=3, meaning three logical pages are selected, namely logical pages 1, 2, and 3, then for each shift of data bits in logical page 1, the data bits in logical page 2 undergo one round of shifting, i.e., the maximum number of shifts is performed. Similarly, for each shift of data bits in logical page 2, the data bits in logical page 3 also undergo one round of shifting. Each shift calculates the data reliability score of the current sub-data. If the data reliability score is less than the initial value of the data reliability score, then the data reliability score is used as the initial value of the data reliability score. After traversing all the shifts, the minimum reliability score can be obtained.

[0095] Furthermore, the data processing method also includes a decoding process, specifically:

[0096] The sub-data of the NAND Flash to be decoded is obtained according to the preset code length. The number of shifts of the data bits of each logical page sub-data is obtained according to the redundancy flag bits in each logical page sub-data. Then, the corresponding logical page data is cyclically shifted in reverse according to the corresponding number of shifts to obtain the decoded sub-data, and thus obtain the decoded NAND Flash data.

[0097] In practice, the above data processing method is implemented in the following systems, such as... Figure 2 As shown, the system includes a host, a data processing encoding module, a data processing decoding module, an ECC encoding and error correction module, an ECC decoding and error correction module, and a NAND Flash; wherein, the data processing encoding module is used to complete the encoding process in this embodiment, and the data processing decoding module is used to complete the decoding process in this embodiment.

[0098] Specifically, during the data encoding process, the data to be written to the NAND Flash is transmitted from the host to the NAND Flash and encoded by the cyclic shift encoding method in the data processing encoding module (Pattern Change Encode Module). Then, it is transmitted to the ECC encoding and error correction module (ECC Encode Module) for error correction, and finally input into the NAND Flash.

[0099] During the data reading process, the data to be read is first read from the NAND Flash and transmitted to the ECC Decode Module for error correction, then transmitted to the data processing and decoding module. After cyclic shift decoding, the decoded data is obtained and then transmitted to the host to complete the reading process.

[0100] Compared with existing technologies, this embodiment provides a data processing method based on NAND Flash reliability. By dividing the NAND Flash data into sub-data, and then cyclically shifting the corresponding logical page sub-data within each sub-data according to the selected logical page, the data reliability score after each shift and the data reliability score before the shift are obtained. This leads to the minimum data reliability score for each sub-data, resulting in encoded sub-data, and finally encoded NAND Flash data. The data reliability obtained through this encoding method is higher. Furthermore, the data reliability score is obtained by using the original voltage-state bit error rate of each memory cell in each sub-data, fully considering the asymmetry of voltage-state bit error rate in data retention characteristics, reducing the proportion of voltage states that dominate the bit error rate contribution, and improving data reliability.

[0101] Example 2

[0102] To verify the correctness of the data processing method based on NAND Flash reliability in the above embodiments, this embodiment uses 3D TLC NAND Flash as an example to conduct experimental verification of the scheme in the above embodiments.

[0103] In a 3D TLC NAND Flash array, each memory cell can be represented by eight different threshold voltage states. Each threshold voltage state represents a different amount of charge stored in the memory cell. A higher voltage state indicates a higher electric field strength in the tunneling oxide direction. Data retention characteristics are related to charge loss, leakage current, and charge detrapping process. Therefore, the higher the threshold voltage state of the memory cell, the more likely it is to shift to the left, which is the threshold voltage state asymmetric error related to flash memory data retention characteristics.

[0104] For example, data written to flash memory after randomization encoding of 384 pages (18KB each) in a block of 3D TLC NAND Flash was tested. Table 1 shows the raw bit error rate (RBER) for eight voltage states at P / E cycles = 0k, Temperature = 125°, and Retention Time = 600min. The E state represents the erase state, which is the lowest of the eight voltage states.

[0105] Table 1 Raw bit error rate at different voltage states

[0106] State E P1 P2 P3 P4 P5 P6 P7 RBER <![CDATA[3.31*10 -5 ]]> <![CDATA[4.26*10 -4 ]]> 0.015 0.066 0.094 0.147 0.215 0.248

[0107] like Figure 3 As shown, the threshold voltage distribution statistics for each unit in the test data are as follows ( Figure 3The table only lists states P1-P7 (solid lines represent the initial threshold voltage distribution, and dashed lines represent the threshold voltage distribution after the data holding time). A significant shift in the threshold voltage can be clearly observed, and the higher the threshold state, the more severe the shift.

[0108] In summary, in 3D TLC NAND Flash, each storage cell can represent 3 bits of information using 8 different voltage states. As the data retention time increases, the number of program / erase cycling cycles increases, and factors such as read operations cause the original threshold voltage state to shift and widen, data errors may occur under a fixed read voltage, leading to decreased reliability and affecting system performance.

[0109] In this embodiment, when processing 3D TLC NAND Flash data according to Embodiment 1, since each storage cell stores 3 bits of information, it can present 8 different threshold voltage states. During encoding, the information stored in the storage cell is also encoded into different voltage threshold states. Each voltage state corresponds to 3 bits of information, that is, the storage cell is represented by 3 logical pages (lower page, middle page, upper page). There are many mapping relationships between voltage states and bit information. Gray code encoding is used. In this embodiment, the mapping relationship represented by Gray code as shown in Table 2 below is adopted.

[0110] Table 2 Gray Mapping

[0111] State E P1 P2 P3 P4 P5 P6 P7 lower 1 1 1 1 0 0 0 0 middle 1 1 0 0 0 0 1 1 upper 1 0 0 1 1 0 0 1

[0112] In this embodiment, taking a code length of 8 storage units and selecting one logical page (lower page) for circular right shift as an example, the data bits of each logical page in each sub-data are 8 bits, and the redundancy flag is 3 bits. The data processing process is as follows:

[0113] Cyclic shift encoding process: By cyclically shifting the lower page to the right, the proportion of different voltage states is changed. After one cyclic shift to the right, the 0 / 1 of the lower page changes, while the values ​​and positions of the other two logic pages remain unchanged. According to the mapping relationship, the encoded voltage states change, the last three redundant bits change from 000 to 001, state P6 in the dashed box becomes state P1, state P2 becomes state P5, and the number of other voltage states remains unchanged. Gray code mapping and encoding method, as follows: Figure 4 As shown.

[0114] Cyclic shift decoding process: As known from the cyclic shift encoding process, a redundant flag is introduced by reducing the code rate. This redundant flag is stored horizontally within the logical page, meaning decoding can be performed when reading a single logical page from the TLC NAND Flash, without needing to simultaneously access information from all three logical pages. The information in the redundant flag indicates the number of cyclic shifts within the current logical page. Therefore, the decoding process is achieved by performing a reverse cyclic shift on the data using the flag information of the corresponding logical page. By cyclically shifting the lower page to the left according to the number of redundant flag shifts, the decoded data can be obtained, such as... Figure 5 As shown.

[0115] Table 3 compares the results of cyclic shift coding (Mode 1) and randomized data scrambling coding (both with a code length of 8) on individual logical pages (lower page, middle page, and upper page). The proportions of each voltage state after coding and the original bit error rate of the predicted values ​​are shown in Table 3. Figure 6 As shown in the diagram. Here, `randomizer` is the randomized scrambling code, `uppshift8CL` is the upper page cyclic shift code, `midshift8CL` is the middle page cyclic shift code, and `lowshift8CL` is the lower page cyclic shift code. Here, `CL` represents the code length.

[0116] Table 3 shows the percentage of each voltage state after Method 1 and random coding.

[0117] State E P1 P2 P3 P4 P5 P6 P7 randomizer 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 uppshift8CL 13.95 11.12 18.44 6.52 20.50 4.49 16.22 8.75 midshift8CL 18.08 15.51 9.38 6.82 20.53 15.65 9.41 4.61 lowshift8CL 18.46 17.28 14.31 9.32 15.60 10.85 7.77 6.40

[0118] From Table 3 and Figure 6 As can be seen, the cyclic shift encoding method provided in Example 1 changes the proportion of voltage states in the data, reduces the proportion of high voltage states that are prone to errors, and can reduce the overall bit error rate of the data, thus achieving a better effect. Furthermore, when cyclic shift encoding is performed using the first method, selecting any logical page for cyclic shifting can change the proportion of voltage states in the data and reduce the overall bit error rate of the data.

[0119] The lower page was selected as a separate logical page under different code lengths for Mode 1 cyclic shift coding and randomized data scrambling coding. The proportion of each voltage state after coding and the original bit error rate of the predicted values ​​after coding are shown in Table 4 (only the cases with code lengths of 128 and 8 are listed). The proportion of each voltage state after coding is shown in Table 4. Figure 7As shown in the diagram. Here, `randomizer` is a randomized scrambling code, `lowshift128CL` is a cyclic shift code with a code length of 128 (selecting the lower page), `lowshift64CL` is a cyclic shift code with a code length of 64 (selecting the lower page), `lowshift32CL` is a cyclic shift code with a code length of 32 (selecting the lower page), `lowshift16CL` is a cyclic shift code with a code length of 16 (selecting the lower page), and `lowshift8CL` is a cyclic shift code with a code length of 8 (selecting the lower page).

[0120] Table 4 shows the percentage of each voltage state after encoding with different code lengths using Method 1.

[0121] State E P1 P2 P3 P4 P5 P6 P7 random 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 lowshift128CL 15.61 14.54 12.08 8.86 16.00 13.09 10.39 9.43 lowshift8CL 18.46 17.28 14.31 9.32 15.60 10.85 7.77 6.40

[0122] From Table 4 and Figure 7 As can be seen, the cyclic shift coding method provided in Example 1 can change the proportion of voltage states in the data with different code lengths, reduce the proportion of high voltage states that are prone to errors, and reduce the overall bit error rate of the data. Furthermore, as the code rate decreases, i.e. the code length decreases, the effect of reducing the proportion of high voltage states becomes more and more significant. However, it will also sacrifice more and more storage units for marker redundancy bits.

[0123] Table 5 compares the cyclic shift coding of a single logical page (Method 1), cyclic shift coding of two logical pages (Methods 2 and 3), and random scrambling coding, with a code length of 8. The table shows the proportions of each voltage state after coding and the original bit error rate predicted after coding. Figure 8 As shown in the diagram. Here, `randomizer` is a randomized scrambling code, `1shift8CL` is a mode-1 cyclic shift code, `2shift8CL` is a mode-2 cyclic shift code for two logical pages, and `2optshift8CL` is a mode-3 cyclic shift code for two logical pages; `2shift8CL` and `2optshift8CL` represent the cases where the number of logical pages selected in mode-2 and mode-3 is m=2.

[0124] Table 5 shows the percentage of each voltage state after different encoding methods.

[0125] State E P1 P2 P3 P4 P5 P6 P7 random 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 1shift8CL 18.46 17.28 14.31 9.32 15.60 10.85 7.77 6.40 2shift8CL 18.18 17.96 13.23 7.28 21.15 11.60 7.22 3.38 2optshift8CL 22.88 20.39 12.65 6.79 16.98 9.58 7.39 3.33

[0126] From Table 5 and Figure 8 It can be seen that the three cyclic shift encoding methods provided in Example 1 can all change the proportion of voltage states in the data, reduce the proportion of high voltage states that are prone to errors, and reduce the overall bit error rate of the data. Furthermore, the data reliability after encoding by the two and three encoding methods is better than that of the one encoding method.

[0127] Table 5 compares the three-cycle shift coding and random scrambling coding methods that select two logical pages under different code lengths. The proportions of each voltage state after coding and the original bit error rate of the predicted values ​​after coding are shown in Table 5. Figure 9 As shown. Here, Randomizer is the randomized scrambling code, 2optshift128CL is the mode three cyclic shift code with a code length of 128, 2optshift64CL is the mode three cyclic shift code with a code length of 64, 2optshift32CL is the mode three cyclic shift code with a code length of 32, 2optshift16CL is the mode three cyclic shift code with a code length of 16, and 2optshift8CL is the mode three cyclic shift code with a code length of 8.

[0128] From Table 6 and Figure 9 As can be seen, the three-way cyclic shift coding method provided in Example 1 can change the proportion of voltage states in the data under different code lengths, reduce the proportion of high voltage states that are prone to errors, and reduce the overall bit error rate of the data.

[0129] Table 6 shows the percentage of each voltage state after encoding in Method 3 with different code lengths.

[0130] State E P1 P2 P3 P4 P5 P6 P7 random 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 2optshift128CL 15.75 15.43 12.52 7.79 18.75 10.90 11.07 7.80 2optshift8CL 22.88 20.39 12.65 6.79 16.98 9.58 7.39 3.33

[0131] In summary, the data processing method based on NAND Flash reliability provided in Example 1 fully considers the relevant characteristics of data retention time and can effectively improve data reliability.

[0132] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0133] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A data processing method based on NAND Flash reliability, characterized in that, Includes the following steps: Obtain the data of each physical page of the NAND Flash to be written, wherein the storage unit of a physical page in the NAND Flash is represented by at least one logical page; Select m Each logical page undergoes a shift operation. m The value is greater than or equal to 1, and the data of each physical page of the NAND Flash to be written is divided into sub-data based on the preset code length. Each sub-data is represented by the sub-data of each logical page. Each logical page sub-data includes data bits. Redundant identification bits are added to the selected logical pages to be shifted. The data bits of the selected logical page sub-data in each sub-data are cyclically shifted to obtain the data reliability score after each shift and the data reliability score before each shift, thereby obtaining the minimum data reliability score for each sub-data. The maximum number of shifts for the selected logical page sub-data is the number of data bits in the logical page sub-data minus 1. Specifically, the inconsistency of data at different positions is used to perform a cyclic shift operation on each code length of sub-data. Based on the original bit error rate information corresponding to each voltage state measured by actual data, the average value of the sum of the original bit error rates corresponding to each voltage state in the sub-data is used as the data reliability score. The proportion of voltage states in the sub-data is changed by cyclic shifting until the minimum data reliability score is reached. The cyclic shifting of the data bits of the selected logical page sub-data in each sub-data is either a cyclic right shift or a cyclic left shift, and each shift is 1 bit. The data reliability score corresponding to the smallest of each sub-data is... m The data bits and shift count of each shift logic page sub-data are used as the corresponding encoded sub-data. m The data bits of each logical page sub-data and the identification redundancy bit data are kept unchanged. The data bits of the remaining logical page sub-data in each sub-data remain unchanged, thus obtaining the encoded sub-data, and then obtaining the encoded NAND Flash data.

2. The data processing method based on NAND Flash reliability according to claim 1, characterized in that, The data reliability score RS Obtained through the following methods: In the formula, This indicates the total number of storage units in the current sub-data. Indicates the first sub-data item in the current sub-data. The raw bit error rate of the voltage state corresponding to each storage cell.

3. The data processing method based on NAND Flash reliability according to claim 1, characterized in that, like m =1, then Data reliability score based on the corresponding sub-data obtained from each sub-data before shifting; Based on the selected logical page, the data bits of the sub-data in each logical page are cyclically shifted in turn to obtain the voltage state of each storage cell after each shift of each sub-data, and then the data reliability score of each sub-data after each shift is obtained. Based on the data reliability score after each shift and the data reliability score before each shift, the minimum data reliability score of each sub-data is obtained; The data bits and shift count of the shifted logical page sub-data corresponding to the minimum data reliability score of each sub-data are used as the data bits and redundancy flags of the corresponding logical page sub-data after encoding each sub-data. The data bits of the remaining logical page sub-data in each sub-data remain unchanged, thus obtaining the encoded sub-data.

4. The data processing method based on NAND Flash reliability according to claim 1, characterized in that, like m If it is greater than 1, then from m One unshifted logical page is randomly selected from the logical pages and cyclically shifted to obtain the minimum data reliability score of each sub-data. Then, the data bit data and shift count of the current logical page sub-data corresponding to the minimum data reliability score of each sub-data are used as the data bit data and the identification redundancy bit data of the current logical page sub-data after the sub-data is encoded. Based on the current logical page of each encoded sub-data, repeat the above steps to perform a cyclic shift on the next unshifted logical page until... m Each logical page is shifted to obtain the corresponding encoded sub-data of each logical page. The data bits of the remaining logical page sub-data in each sub-data remain unchanged, thus obtaining the encoded sub-data.

5. The data processing method based on NAND Flash reliability according to claim 1, characterized in that, like m If it is greater than 1, then Based on the selected number of logical pages m Select any logical page in sequence, and designate it as the 1st, ... m Each logical page; and the data reliability score obtained based on each sub-data before shifting is used as the initial value of the data reliability score of the corresponding sub-data; By performing the following traversal steps to cyclically shift the data bits of the logical page sub-data in each sub-data, the minimum data reliability score of each sub-data is obtained: Based on the first logical page, perform a cyclic shift on the data bits of the current sub-data within that logical page. For each shift, execute the following steps until the current shift count for that logical page equals the maximum shift count: Based on the second logical page, the data bits of the current sub-data in that logical page are cyclically shifted. Each shift executes the following steps until the current shift count of that logical page equals the maximum shift count: And so on, Based on the m-th logical page, the data bits of the sub-data of the logical page in the current sub-data are cyclically shifted. After each shift, the data reliability score of the current sub-data is obtained. If the data reliability score is less than the initial value of the data reliability score, then the data reliability score is used as the initial value of the data reliability score. The initial value of the data reliability score obtained after traversing is used as the minimum data reliability score of the current sub-data. The data reliability score corresponding to the smallest of each sub-data is... m The data bits and shift count of each shift logic page sub-data are used as the corresponding encoded sub-data. m The data bits of each logical page sub-data and the identification redundancy bits remain unchanged, resulting in the encoded sub-data.

6. The data processing method based on NAND Flash reliability according to claim 1, characterized in that, Total number of bits of storage data for each logical page d The data bits and the redundant flag bits in the selected logical page sub-data are identical and correspond one-to-one with the sub-data storage units. The data bits and redundant flag bits in the selected logical page sub-data satisfy the following formula: ， in, , In the formula, l This indicates the number of redundant bits in the selected logical page sub-data to be shifted; This indicates the number of data bits in the selected logical page sub-data to be shifted. This indicates rounding up to the nearest integer.

7. The data processing method based on NAND Flash reliability according to claim 1, characterized in that, The preset code length is 8, 16, 32, 64 or 128 storage units.

8. The data processing method based on NAND Flash reliability according to claim 2, characterized in that, The raw bit error rate of each voltage state is obtained by measuring the bit error rate of each voltage state stored in the NAND Flash under different hold times and number of program erase cycles.

9. The data processing method based on NAND Flash reliability according to claim 1, characterized in that, The data processing method further includes a decoding process, specifically: The sub-data of the NAND Flash to be decoded is obtained according to the preset code length. The number of shifts of each logical page data is obtained according to the redundancy bits in each logical page data. Then, the corresponding logical page data is cyclically shifted in reverse according to the corresponding number of shifts to obtain the decoded sub-data, and thus obtain the decoded NAND Flash data.

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