Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a layer to be etched, the layer to be etched including adjacent first, second and third regions; forming a plurality of discrete first core layers on the first region and the third region, and forming a plurality of discrete second core layers on the second region; forming first side walls on the first core layers; forming second side walls on the second core layers; forming a sacrificial layer on the layer to be etched; forming a first mask structure on the sacrificial layer; etching the layer to be etched with the first mask structure and the second side walls as masks to form an initial first gate structure in the first region, a plurality of initial second gate structures in the second region, and an initial third gate structure in the third region; and removing part of the initial first gate structure and the initial third gate structure to form a discrete first gate structure in the first region and a discrete third gate structure in the third region. The semiconductor structure formed by the method has improved performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] In planar NAND flash memory blocks, the source select gate (SSG) and drain select gate (DSG), perpendicular to the word line or control gate, are gate lines used to determine whether the bit lines of the block can conduct. In current process engineering, the patterns of SSG and DSG are formed after the hard mask of the memory area is formed and then exposed. Finally, the control gate, source select gate, and drain select gate are formed simultaneously in one etching step. Therefore, when the memory area control gate pattern is formed, the areas where the source select gate and drain select gate are located do not have control gate patterns, and these two areas are also different in size. As a result, the pattern density at the block edge is different from that in the middle of the block. During exposure and etching, the loading effect causes the control gates at the edges of the memory blocks with different pattern densities to form non-uniform dimensions. To improve product yield and reliability, it is crucial to improve the uniformity of the control gate during the formation process. To achieve uniformity of the critical dimension (CD), optical proximity correction (OPC) is required for the design pattern.

[0003] The formation of advanced NAND control gates utilizes self-aligned dual-mode technology, which is itself a complex process. Especially in NAND flash memory processes below 20nm, the uniformity requirements for word line dimensions are even higher, while the load effects of exposure and etching become increasingly pronounced. Therefore, optical proximity correction of word lines at the edges of memory blocks to achieve dimensional uniformity is extremely difficult, requiring significant investment of manpower and resources to collect data and build optical proximity correction models. Even if the optical proximity correction model is successfully established, the subsequent exposure and etching process windows are very small. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of planar NAND flash memory structures.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a layer to be etched, the layer to be etched comprising an adjacent first region, a second region, and a third region, the second region being located between the first region and the third region; forming a plurality of discrete first core layers on the first region and the third region, and forming a plurality of discrete second core layers on the second region, the plurality of first core layers and second core layers being uniformly distributed in a first direction parallel to the surface of the layer to be etched, the first direction being the arrangement direction of the first region, the second region, and the third region; forming a first sidewall on the sidewall of the first core layer; forming a second sidewall on the sidewall of the second core layer; and after forming the first sidewall and the second sidewall, removing the first core layers. The process involves: a first core layer and a second core layer; removing the first core layer and the second core layer; forming a sacrificial layer on the layer to be etched, with several first sidewalls and second sidewalls located within the sacrificial layer; forming a first mask structure on the sacrificial layer, the first mask structure being located on the sacrificial layer in a first region and a third region; etching the layer to be etched using the first mask structure and the second sidewalls as masks, forming an initial first gate structure in the first region, several initial second gate structures in the second region, and an initial third gate structure in the third region; removing a portion of the initial first gate structure to form a discrete first gate structure in the first region; removing a portion of the initial third gate structure to form a discrete third gate structure in the third region.

[0006] Optionally, the first sidewall and the second sidewall are formed simultaneously, and the spacing between adjacent first sidewalls in the first direction and the spacing between second sidewalls in the first direction are the same.

[0007] Optionally, the ratio of the width of the first region in the first direction to the sum of the width of the first sidewall in the first direction and the spacing between the first sidewalls in the first direction is an integer greater than 1; the ratio of the width of the third region in the first direction to the sum of the width of the first sidewall in the first direction and the spacing between the first sidewalls in the first direction is an integer greater than 1.

[0008] Optionally, the projection pattern of the adjacent second sidewall on the layer to be etched is a closed "L" shape; the projection pattern of the adjacent first sidewall on the layer to be etched is a closed rectangle.

[0009] Optionally, the first gate structure and the third gate structure are formed simultaneously.

[0010] Optionally, the method for forming the first gate structure and the third gate structure includes: forming a second mask layer on the initial first gate structure, the initial third gate structure and the initial second gate structure, wherein the second mask layer exposes a portion of the top surface of the initial first gate structure and a portion of the top surface of the initial third gate structure; and etching the initial first gate structure and the initial third gate structure using the second mask layer as a mask to form a discrete first gate structure and a discrete third gate structure.

[0011] Optionally, the second core layer includes a first part and a second part connected to each other, the first part being perpendicular to a first direction and the second part being parallel to the first direction.

[0012] Optionally, while forming the first gate structure and the third gate structure, the method further includes: removing a portion of the initial second gate structure to form a discrete second gate structure; after removing the initial second gate structure, forming a plurality of isolation structures within the initial second gate structure, wherein the isolation structures penetrate the initial second gate structure along a first direction.

[0013] Optionally, the method for forming the first core layer and the second core layer includes: forming a core material layer on the layer to be etched; forming a mask structure on the core material layer, the mask structure including: a pad layer, an anti-reflection layer on the pad layer, and a patterned photoresist structure on the anti-reflection layer, the photoresist structure including a first photoresist layer on a first region and a third region, and a second photoresist layer on a second region, a plurality of the first photoresist layers and the second photoresist layers being uniformly distributed in a first direction parallel to the surface of the layer to be etched; etching the core material layer using the patterned photoresist layer as a mask until the surface of the layer to be etched is exposed, thereby forming the first core layer and the second core layer.

[0014] Optionally, the material of the core material layer is different from the material of the surface of the layer to be etched.

[0015] Optionally, the core material layer may be made of silicon oxide.

[0016] Optionally, the process of etching the layer to be etched using the first mask structure and the second sidewall as a mask includes a dry etching process, wherein the etching rate of the sacrificial layer in the dry etching process is greater than the etching rate of the second sidewall.

[0017] Optionally, the layer to be etched includes a plurality of memory cells, each memory cell including: a substrate; a gate structure material layer on the substrate; and a transition structure layer on the gate structure material layer, the transition structure layer including a first transition layer and a second transition layer on the first transition layer.

[0018] Optionally, the transition structure layer further includes a third transition layer located on the second transition layer, wherein the materials of the first transition layer, the second transition layer, and the third transition layer are different from each other.

[0019] Optionally, the material of the first transition layer includes silicon nitride, the material of the second transition layer includes silicon oxide, and the material of the third transition layer includes amorphous silicon.

[0020] Optionally, the material of the gate structure material layer includes a floating gate material layer, a control gate material layer, and an electrically insulating material layer located between the floating gate material layer and the control gate material layer on the substrate.

[0021] Optionally, the materials of the floating gate material layer and the control gate material layer include polycrystalline silicon.

[0022] Optionally, the substrate includes a plurality of active regions, which are parallel to a first direction; the first gate structure, the third gate structure, and the second gate structure span the active regions.

[0023] Optionally, the material of the sacrificial layer includes carbon-containing organic materials.

[0024] Optionally, the method for forming the first sidewall and the second sidewall includes: forming a sidewall material layer on the layer to be etched, the sidewall surface and top surface of the first core layer, and the sidewall surface and top surface of the second core layer; and etching back the sidewall material layer until the surface of the layer to be etched, the top surface of the first core layer, and the top surface of the second core layer are exposed to form the first sidewall and the second sidewall.

[0025] Optionally, the material of the sidewall material layer is different from the material of the first core layer, the second core layer, and the surface of the layer to be etched.

[0026] Optionally, the material of the sidewall material layer includes silicon nitride.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] The technical solution of the present invention forms a plurality of discrete first core layers on a first region and a third region, and forms a plurality of discrete second core layers on a second region. The plurality of first core layers and second core layers are uniformly distributed in a first direction parallel to the surface of the layer to be etched. This makes it possible to improve the pattern density around the second region when forming the exposure patterns of the first core layer, the second core layer and the third core layer, thereby improving the pattern exposure accuracy of the second core layer. This, in turn, improves the dimensional accuracy of the formed second core layer and the subsequently formed second gate structure, thereby improving the performance of the semiconductor structure.

[0029] Furthermore, the first sidewall and the second sidewall are formed simultaneously, and the spacing between adjacent first sidewalls in the first direction is the same as the spacing between second sidewalls in the first direction; the ratio of the width of the first region in the first direction to the sum of the width of the first sidewall in the first direction and the spacing between the first sidewalls in the first direction is an integer greater than 1; the ratio of the width of the third region in the first direction to the sum of the width of the first sidewall in the first direction and the spacing between the first sidewalls in the first direction is also an integer greater than 1. The width design of the first and third regions in the first direction allows for the formation of several first photoresist layers with uniform density on the first and third regions when several second photoresist layers are formed on the second region. This ensures that during exposure, the photoresist pattern density at the edge of the second region is approximately the same as the photoresist pattern density at the center of the second region, thereby improving the exposure accuracy of the second photoresist layer at the edge of the second region. Consequently, after pattern transfer, the dimensional accuracy of the subsequently formed second gate structure can be improved.

[0030] Furthermore, while forming the first gate structure and the third gate structure, the method also includes: removing a portion of the initial second gate structure, thereby forming a discrete second gate structure. The process of forming the first gate structure, the third gate structure, and the second gate structure is a single process, which saves process steps and improves production efficiency. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the semiconductor structure in one embodiment;

[0032] Figures 2 to 14 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0033] As described in the background section, the existing planar NAND flash memory block structure still needs improvement. This will now be analyzed and explained in conjunction with specific embodiments.

[0034] Figure 1 This is a schematic diagram of a semiconductor structure in one embodiment.

[0035] Please refer to Figure 1The semiconductor structure includes a plurality of memory cells, each memory cell comprising: a substrate 100, the substrate 100 including adjacent first region I, second region II and third region III, the second region II being located between the first region I and the third region III; the substrate 100 including a plurality of active regions 101 parallel to a first direction X, the first direction X being parallel to the surface of the substrate 100 and being the arrangement direction of the first region I, second region II and third region III; a first gate structure 102 located on the first region I, the first gate structure 102 being parallel to a second direction Y, the second direction Y being parallel to the surface of the substrate 100 and perpendicular to the first direction X, the first gate structure 102 spanning the plurality of active regions 101; a plurality of second gate structures 103 located on the second region II, the second gate structures 103 being parallel to the second direction Y; and a third gate structure 104 located on the third region III, the third gate structure 104 being parallel to the second direction Y.

[0036] In the semiconductor structure, the first region I is the source region, the second region II is the drain region, the second gate structure 103 is the word line, the first gate structure 102 is the source select gate, and the third gate structure 104 is the drain select gate. The width of the second gate structure 103 is smaller than the width of the first gate structure 102 and the width of the third gate structure 104, and the spacing between adjacent second gate structures 103 is smaller than the spacing between adjacent first gate structures 102 and adjacent third gate structures 104. During the formation of the semiconductor structure, since the spacing and width of the first gate structure 102 on the first region I, the second gate structure 103 on the second region II, and the third gate structure 104 on the third region III are all different, two photomasks are required to form the pattern. That is, the second gate structure 103 on the second region II is formed first, and then the first gate structure 102 on the first region I and the third gate structure 104 on the third region III are formed. When forming the second gate structure 103 on the second region II, since the first region I and the third region III adjacent to the second region II have no pattern, the pattern density at the edge of the second region II is sparser than the pattern density at the middle of the second region II. This results in the area with high pattern density having a brighter exposure intensity and higher pattern exposure accuracy when the pattern of the second gate structure 103 is exposed, while the area with sparse pattern density has a darker exposure intensity and lower pattern exposure accuracy. The load effect results in poor size uniformity of the second gate structure 103 located at the middle and edge of the second region II.

[0037] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure. This method involves forming a plurality of discrete first core layers on a first region and a third region, and forming a plurality of discrete second core layers on a second region. The plurality of first and second core layers are uniformly distributed in a first direction parallel to the surface of the layer to be etched. This arrangement, during the exposure patterning of the first, second, and third core layers, increases the pattern density around the second region, thereby improving the exposure accuracy of the second core layer. This, in turn, enhances the dimensional accuracy of the formed second core layer and the subsequently formed second gate structure, ultimately improving the performance of the semiconductor structure.

[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figures 2 to 14 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0040] Please refer to Figure 2 A layer to be etched is provided, the layer to be etched includes an adjacent first region I, a second region II and a third region III, the second region II being located between the first region I and the third region III.

[0041] The layer to be etched includes: a substrate 200; a gate structure material layer on the substrate 200; and a transition structure layer on the gate structure material layer, wherein the transition structure layer includes a first transition layer 205 and a second transition layer 206 on the first transition layer 205.

[0042] In this embodiment, the transition structure layer further includes a third transition layer 207 located on the second transition layer 206, and the materials of the first transition layer 205, the second transition layer 206, and the third transition layer 207 are different from each other. Since the gate structure material layer is a multi-layer structure, and the gate structure material layer is relatively thick, a thicker transition structure layer is required for pattern transfer, thereby improving the accuracy of pattern transfer.

[0043] In other embodiments, the third transition layer may be omitted.

[0044] In this embodiment, the first transition layer 205 is made of silicon nitride, the second transition layer 206 is made of silicon oxide, and the third transition layer 207 is made of amorphous silicon.

[0045] The material of the gate structure material layer includes a floating gate material layer 202, a control gate material layer 204, and an electrically insulating material layer 203 located between the floating gate material layer 202 and the control gate material layer 204 on the substrate 200.

[0046] In this embodiment, the floating gate material layer 202 and the control gate material layer 204 are made of polysilicon, and the electrically isolated material layer 203 is made of a silicon oxide layer, a silicon nitride layer on the silicon oxide layer, and a silicon oxide layer on the silicon nitride layer.

[0047] In this embodiment, the substrate 200 includes a plurality of active regions 201, which are parallel to a first direction X, wherein the first direction X is the arrangement direction of the first region I, the second region II, and the third region III.

[0048] Next, several discrete first core layers are formed on the first region I and the third region III, and several discrete second core layers are formed on the second region. These first and second core layers are uniformly distributed in a first direction parallel to the surface of the layer to be etched. Please refer to [link to documentation] for the formation process of the first and second core layers. Figures 3 to 6 .

[0049] Please refer to Figure 3 and Figure 4 , Figure 3 for Figure 4 The top view of several gate structure material layers, transition structure layers, and part of the mask structure located on the substrate is omitted. Figure 4 for Figure 3 A schematic diagram of the cross-sectional structure along the AA1 direction shows that a core material layer 208 is formed on the layer to be etched.

[0050] The core material layer 208 is used to subsequently form the first core layer and the second core layer.

[0051] The core material layer 208 is made of a different material than the surface of the layer to be etched. This is to minimize damage to the surface of the layer to be etched during subsequent etching of the core material layer 208.

[0052] In this embodiment, the core material layer 208 is made of silicon oxide.

[0053] Please continue to refer to this. Figure 3 and Figure 4 A mask structure is formed on the core material layer 208, the mask structure including: a pad layer 209, an anti-reflection layer 210 on the pad layer 209, and a patterned photoresist structure on the anti-reflection layer 210.

[0054] The photoresist structure includes a first photoresist layer 211 located on a first region I and a third region III, and a second photoresist layer 212 located on a second region II. A plurality of the first photoresist layers 211 and the second photoresist layers 212 are uniformly distributed in a first direction X parallel to the surface of the layer to be etched.

[0055] The first photoresist layer 211 is the pattern for the subsequent formation of the first core layer in the first region I and the third region III, and the second photoresist layer 212 is the pattern for the subsequent formation of the second core layer in the second region II.

[0056] A plurality of first photoresist layers 211 and second photoresist layers 212 are uniformly distributed in a first direction X parallel to the surface of the layer to be etched. This results in the patterning of the first photoresist layer 211 increasing the pattern density around the second region II during the exposure formation of the first photoresist layer 211 and the second photoresist layer 212, thereby improving the patterning exposure accuracy of the second photoresist layer 212. This, in turn, improves the dimensional accuracy of the formed second core layer and the subsequently formed second gate structure, thereby enhancing the performance of the semiconductor structure.

[0057] The antireflective layer 210 includes a thin silicon antireflective layer (Si-ARC), an organic material bottom antireflective layer (organicBARC), a dielectric antireflective layer (DARC), or a combination of an organic bottom antireflective layer and a dielectric antireflective layer. The material of the padding layer 209 includes a carbon-containing organic material.

[0058] Please refer to Figure 5 and Figure 6 , Figure 5 In order to be in Figure 3 A basic diagram. Figure 6 In order to be in Figure 4 Based on the schematic diagram, the pad layer 209, the anti-reflection layer 210 and the core material layer 208 are etched using the patterned photoresist structure as a mask until the surface of the layer to be etched is exposed. A first core layer 214 is formed on the first region I and the third region III, and a second core layer 215 is formed on the second region II.

[0059] In this embodiment, the second core layer 215 includes a first part and a second part connected to each other, the first part being perpendicular to the first direction X, and the second part being parallel to the first direction X.

[0060] In this embodiment, the first core layer 214 is parallel to the first portion of the second core layer 215.

[0061] Please refer to Figure 7 and Figure 8 , Figure 7 In order to be in Figure 5 A basic diagram. Figure 8 In order to be in Figure 6 Based on the schematic diagram, a first sidewall 216 is formed on the sidewall of the first core layer 214; and a second sidewall 217 is formed on the sidewall of the second core layer 215.

[0062] In this embodiment, the first sidewall 216 and the second sidewall 217 are formed simultaneously, and the distance d1 between adjacent first sidewalls 216 in the first direction X and the distance between adjacent second sidewalls 217 in the first direction X are the same.

[0063] The method for forming the first sidewall 216 and the second sidewall 217 includes: forming a sidewall material layer (not shown) on the layer to be etched, the sidewall surface and top surface of the first core layer 214 and the sidewall surface and top surface of the second core layer 215; and etching back the sidewall material layer until the surface of the layer to be etched, the top surface of the first core layer 214 and the top surface of the second core layer 215 are exposed, thereby forming the first sidewall 216 and the second sidewall 217.

[0064] The material of the sidewall material layer is different from that of the first core layer 214, the second core layer 215, and the surface of the layer to be etched. Therefore, when the sidewall material layer is etched back, the damage to the first core layer 214, the second core layer 215, and the surface of the layer to be etched is minimized.

[0065] In this embodiment, the material of the sidewall material layer includes silicon nitride.

[0066] In this embodiment, the projection pattern of the second sidewall 217 on the layer to be etched is a closed "L" shape.

[0067] In this embodiment, the ratio of the width of the first region I in the first direction X to the sum of the width d2 of the first sidewall 216 in the first direction X and the distance d1 of the first sidewall 216 in the first direction X is an integer greater than 1; the ratio of the width of the third region III in the first direction X to the sum of the width of the first sidewall 216 in the first direction X and the distance d1 of the first sidewall 216 in the first direction X is also an integer greater than 1. Since the first sidewall 216 and the second sidewall 217 are formed simultaneously, the widths of the first sidewall 216 and the second sidewall 217 in the first direction X are the same, that is, the ratio of the width of the first region I and the width of the third region III in the first direction X to the sum of the width of the second sidewall 217 in the first direction X and the distance d1 of the second sidewall 217 in the first direction X is an integer greater than 1.

[0068] The width design of the first region I and the third region III in the first direction X enables the formation of several second photoresist layers 212 on the second region II, while also enabling the formation of several first photoresist layers 211 with uniform density on the first region I and the third region III. This results in the photoresist pattern density at the edge of the second photoresist layer 212 on the second region II being approximately the same as that at the center of the second region II during exposure, thereby improving the exposure accuracy of the second photoresist layer 212 at the edge of the second region II. This, in turn, improves the dimensional accuracy of the subsequently formed second gate structure after pattern transfer.

[0069] Please refer to Figure 9 , Figure 9 In order to be in Figure 8 Based on the structural diagram, after forming the first sidewall 216 and the second sidewall 217, the first core layer 214 and the second core layer 215 are removed.

[0070] The materials of the first core layer 214 and the second core layer 215 are different from the materials of the first sidewall 216 and the second sidewall 217. The materials of the first core layer 214 and the second core layer 215 are also different from the materials of the surface of the layer to be etched. Therefore, the process of removing the first core layer 214 and the second core layer 215 causes less damage to the first sidewall 216, the second sidewall 217 and the surface of the etched layer.

[0071] In this embodiment, the process of removing the first core layer 214 and the second core layer 215 includes a wet etching process.

[0072] Please continue to refer to this. Figure 9 After removing the first core layer 214 and the second core layer 215, a sacrificial layer 218 is formed on the layer to be etched, and a plurality of the first sidewalls 216 and the second sidewalls 217 are located within the sacrificial layer 218.

[0073] In this embodiment, the material of the sacrificial layer 218 includes a carbon-containing organic material.

[0074] Please continue to refer to this. Figure 9 A first mask structure is formed on the sacrificial layer 218, which is located on the sacrificial layer 218 on the first region I and the third region III.

[0075] In this embodiment, the first mask structure includes a second anti-reflection layer 219 and a third photoresist layer 220 located on the second anti-reflection layer 219, wherein the third photoresist layer 220 exposes the surface of the second anti-reflection layer 219 on the second region II.

[0076] Please refer to Figure 10 and Figure 11 , Figure 10 for Figure 11 Top view, Figure 11 for Figure 10 A cross-sectional structural diagram along the AA1 direction shows that the layer to be etched is etched using the first mask structure and the second sidewall 217 as masks. An initial first gate structure 221 is formed in the first region I, several initial second gate structures 222 are formed in the second region II, and an initial third gate structure 223 is formed in the third region III.

[0077] The initial first gate structure 221, the initial second gate structure 222, and the initial third gate structure 223 span the active region 201.

[0078] The etching process using the first mask structure and the second sidewall 217 as masks to etch the layer to be etched includes a dry etching process. The dry etching process has a higher etching rate for the sacrificial layer 218 than for the second sidewall 217. Therefore, during the etching process, when the second antireflective layer 219 and the sacrificial layer 218 are etched using the third photoresist layer 220 as a mask, the sacrificial layer 218 is removed by the etching process, exposing several second sidewalls 217 on the second region II. Upon further etching, the patterns of the second sidewalls 218 and the third photoresist layer 220 are transferred to the gate structure material layer, forming the initial first gate structure 221, the initial second gate structure 222, and the initial third gate structure 223.

[0079] The projection of the initial second gate structure 222 onto the substrate 200 is a closed "L" shape.

[0080] During the formation of the initial first gate structure 221, the initial second gate structure 222, and the initial third gate structure 223, the transition structure material layer is naturally removed.

[0081] Next, a portion of the initial first gate structure 221 is removed to form a discrete first gate structure in the first region I; a portion of the initial third gate structure 223 is removed to form a discrete third gate structure in the third region III. For the process of forming the first and third gate structures, please refer to [reference needed]. Figures 12 to 14 .

[0082] Please refer to Figure 12 , Figure 12 In order to be in Figure 11The schematic diagram shows that a second pad layer 224 is formed on a substrate 200, and the initial first gate structure 221, the initial second gate structure 222, and the initial third gate structure 223 are located within the second pad layer 224; a second mask layer 225 is formed on the initial first gate structure 221, the initial third gate structure 223, and the initial second gate structure 222, and the second mask layer 225 exposes a portion of the top surface of the initial first gate structure 221 and a portion of the top surface of the initial third gate structure 223.

[0083] In this embodiment, the material of the second pad layer 224 includes a carbon-containing organic material; the material of the second mask layer 225 includes a photoresist.

[0084] Please refer to Figure 13 and Figure 14 , Figure 13 for Figure 14 Top view, Figure 14 for Figure 13 A cross-sectional view along the AA1 direction shows that the initial first gate structure 221 and the initial third gate structure 223 are etched using the second mask layer 225 as a mask to form a discrete first gate structure 226 and a discrete third gate structure 228.

[0085] In this embodiment, the etching process for the initial first gate structure 221 and the initial third gate structure 223 includes a dry etching process.

[0086] The first gate structure 226 and the third gate structure 228 are formed simultaneously.

[0087] While forming the first gate structure 226 and the third gate structure 228, the method further includes: removing a portion of the initial second gate structure 222 to form a discrete second gate structure 227; after removing a portion of the initial second gate structure 222, forming a plurality of isolation structures 229 within the initial second gate structure 222, wherein the isolation structures 229 penetrate the initial second gate structure 222 along a first direction X.

[0088] The process of forming the first gate structure 226, the second gate structure 227 and the third gate structure 228 is a single process, which can save process steps and improve production efficiency.

[0089] The second gate structure 227 includes a first portion and a second portion connected together, the first portion being perpendicular to a first direction X, and the second portion being parallel to the first direction X. The second portion is used to connect to a subsequently formed test board.

[0090] The first gate structure 226 includes a first floating gate layer (not shown), a first electrical isolation layer (not shown) on the first floating gate layer, and a first control gate layer (not shown) on the first electrical isolation layer; the second gate structure 227 includes a first floating gate layer (not shown), a second electrical isolation layer (not shown) on the second floating gate layer, and a second control gate layer (not shown) on the second electrical isolation layer; the third gate structure 228 includes a third floating gate layer (not shown), a third electrical isolation layer (not shown) on the third floating gate layer, and a third control gate layer (not shown) on the third electrical isolation layer.

[0091] In this embodiment, the width of the second gate structure 227 is smaller than the width of the first gate structure 226 and the width of the third gate structure 228, and the spacing between adjacent second gate structures 227 is smaller than the spacing between adjacent first gate structures 226 and adjacent third gate structures 228.

[0092] Thus, the second gate structure 227 formed has good dimensional uniformity at the middle and edge positions of the second region II, thereby improving the performance of the semiconductor structure.

[0093] In this embodiment, after forming the first gate structure 226 and the third gate structure 228, the method further includes forming source and drain doped regions (not shown) in the active regions 201 on both sides of the first gate structure 226 and in the active regions 201 on both sides of the third gate structure 228.

[0094] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A layer to be etched is provided, the layer to be etched comprising an adjacent first region, a second region and a third region, wherein the second region is located between the first region and the third region; Several discrete first core layers are formed on the first region and the third region, and several discrete second core layers are formed on the second region. Several first core layers and second core layers are evenly distributed in a first direction parallel to the surface of the layer to be etched. The first direction is the arrangement direction of the first region, the second region and the third region. A first sidewall is formed on the sidewall of the first core layer; A second sidewall is formed on the sidewall of the second core layer; After the first and second sidewalls are formed, the first and second core layers are removed. After removing the first core layer and the second core layer, a sacrificial layer is formed on the layer to be etched, and a plurality of the first sidewalls and the second sidewalls are located within the sacrificial layer; A first mask structure is formed on the sacrificial layer, the first mask structure being located on the sacrificial layer on the first region and the third region; The layer to be etched is etched using the first mask structure and the second sidewall as a mask, forming an initial first gate structure in the first region, forming a plurality of initial second gate structures in the second region, and forming an initial third gate structure in the third region. A portion of the initial first gate structure is removed to form a discrete first gate structure in the first region; A portion of the initial third gate structure is removed, and a discrete third gate structure is formed in the third region. After forming the first gate structure and the third gate structure, source and drain doped regions are formed in the active regions on both sides of the first gate structure and in the active regions on both sides of the third gate structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first sidewall and the second sidewall are formed simultaneously, and the spacing between adjacent first sidewalls in the first direction and the spacing between second sidewalls in the first direction are the same.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The ratio of the width of the first region in the first direction to the sum of the width of the first sidewall in the first direction and the spacing between the first sidewalls in the first direction is an integer greater than 1; the ratio of the width of the third region in the first direction to the sum of the width of the first sidewall in the first direction and the spacing between the first sidewalls in the first direction is an integer greater than 1.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The projection pattern of the adjacent second sidewall on the layer to be etched is a closed "L" shape; the projection pattern of the adjacent first sidewall on the layer to be etched is a closed rectangle.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first gate structure and the third gate structure are formed simultaneously.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method for forming the first gate structure and the third gate structure includes: forming a second mask layer on an initial first gate structure, an initial third gate structure and an initial second gate structure, wherein the second mask layer exposes a portion of the top surface of the initial first gate structure and a portion of the top surface of the initial third gate structure; and etching the initial first gate structure and the initial third gate structure using the second mask layer as a mask to form a discrete first gate structure and a discrete third gate structure.

7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The second core layer includes a first part and a second part connected to each other, the first part being perpendicular to a first direction and the second part being parallel to the first direction.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, While forming the first gate structure and the third gate structure, the method further includes: removing a portion of the initial second gate structure to form a discrete second gate structure; after removing the initial second gate structure, forming a plurality of isolation structures within the initial second gate structure, wherein the isolation structures penetrate the initial second gate structure along a first direction.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the first core layer and the second core layer includes: forming a core material layer on the layer to be etched; forming a mask structure on the core material layer, the mask structure including: a pad layer, an anti-reflection layer on the pad layer, and a patterned photoresist structure on the anti-reflection layer, the photoresist structure including a first photoresist layer on a first region and a third region, and a second photoresist layer on a second region, a plurality of the first photoresist layers and the second photoresist layers being uniformly distributed in a first direction parallel to the surface of the layer to be etched; etching the core material layer using the patterned photoresist layer as a mask until the surface of the layer to be etched is exposed, thereby forming the first core layer and the second core layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The material of the core material layer is different from the material of the surface of the layer to be etched.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The core material layer is made of silicon oxide.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of etching the layer to be etched using the first mask structure and the second sidewall as masks includes a dry etching process, wherein the etching rate of the sacrificial layer in the dry etching process is greater than the etching rate of the second sidewall.

13. The method for forming a semiconductor structure as described in claim 8, characterized in that, The layer to be etched includes a plurality of memory cells, each memory cell including: a substrate; a gate structure material layer on the substrate; and a transition structure layer on the gate structure material layer, the transition structure layer including a first transition layer and a second transition layer on the first transition layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The transition structure layer also includes a third transition layer located on the second transition layer, and the materials of the first transition layer, the second transition layer and the third transition layer are different from each other.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The first transition layer is made of silicon nitride, the second transition layer is made of silicon oxide, and the third transition layer is made of amorphous silicon.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, The material of the gate structure material layer includes a floating gate material layer, a control gate material layer, and an electrically insulating material layer located between the floating gate material layer and the control gate material layer on the substrate.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The materials of the floating gate material layer and the control gate material layer include polycrystalline silicon.

18. The method for forming a semiconductor structure as described in claim 13, characterized in that, The substrate includes a plurality of active regions, which are parallel to a first direction; the first gate structure, the third gate structure, and the second gate structure span the active regions.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, The sacrificial layer is made of carbon-containing organic materials.

20. The method for forming a semiconductor structure as described in claim 2, characterized in that, The method for forming the first sidewall and the second sidewall includes: forming a sidewall material layer on the layer to be etched, the sidewall surface and the top surface of the first core layer, and the sidewall surface and the top surface of the second core layer; and etching back the sidewall material layer until the surface of the layer to be etched, the top surface of the first core layer, and the top surface of the second core layer are exposed to form the first sidewall and the second sidewall.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The material of the sidewall material layer is different from that of the first core layer, the second core layer, and the surface of the layer to be etched.

22. The method for forming a semiconductor structure as described in claim 20, characterized in that, The material of the sidewall material layer includes silicon nitride.

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