Method of forming a semiconductor structure
By using a silicon oxide hard mask layer to protect the dielectric composite layer and performing a re-dissolution process after the conductive layer is formed, the problems of dielectric layer damage and conductive layer diffusion in through-silicon via (TSV) technology are solved, thereby improving the performance and production efficiency of semiconductor structures.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (BEIJING) CORP
- Filing Date
- 2022-06-09
- Publication Date
- 2026-07-24
AI Technical Summary
The performance of semiconductor structures formed by existing through-silicon via (TSV) technology needs further improvement, especially in terms of dielectric layer damage, conductive layer diffusion risk, and copper bridging risk caused during the etching process.
Using silicon oxide as a hard mask layer, and by etching to protect the sidewalls of the second region, a conductive layer is formed and then dissolved back to make the top surface of the conductive layer higher than or flush with the second dielectric composite layer, and lower than or flush with the top surface of the first region. This reduces the amount of conductive material used and protects the conductive layer during the planarization process.
It effectively protects the dielectric composite layer, reduces the risk of dielectric layer damage and conductive layer diffusion, improves the morphology and performance of the conductive layer, saves conductive materials, and reduces production costs.
Smart Images
Figure CN117219571B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology
[0002] Through-Silicon Via (TSV) technology is a cutting-edge technology that enables chip interconnection by creating vertical connections between chips and wafers. Unlike previous IC packaging bonding and bump stacking techniques, TSV allows for maximum chip density in three dimensions, minimizes form factor, and significantly improves chip speed and low-power performance.
[0003] Through-Silicon Via (TSV) technology differs significantly from conventional packaging techniques in that TSV fabrication can be integrated into different stages of the manufacturing process. Placing TSVs during the packaging production stage is commonly referred to as Via-last, and its significant advantage is that it does not alter existing integrated circuit flows and designs. Currently, some manufacturers have begun adopting Via-last technology in the high-end Flash and DRAM fields, which involves creating vias around the perimeter of the chip before stacking the chips or wafers.
[0004] However, the performance of structures formed by existing through-silicon via (TSV) technology needs further improvement. Summary of the Invention
[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.
[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a first wafer and a second wafer bonded together, the first wafer having a first functional surface, the first functional surface exposing a pad layer, and a first dielectric composite layer having a first functional surface; the second wafer having a second functional surface and a third surface opposite to the second functional surface, the first dielectric composite layer being bonded to the third surface, and a second dielectric composite layer having a second functional surface; forming a hard mask layer and a first opening located within the hard mask layer on the surface of the second dielectric composite layer, the first opening exposing the surface of the second dielectric composite layer; the hard mask layer including a first region and a second region located on the first region; and using the hard mask... The film layer serves as a mask. The second dielectric composite layer, the second wafer, and the first dielectric composite layer are etched until the pad layer is exposed. Through-holes are formed within the second dielectric composite layer, the second wafer, and the first dielectric composite layer. The second sidewall of the hard mask layer is etched during the etching process to form a second opening from the first opening. The width of the second opening on the second sidewall of the second region is greater than the width of the second opening on the sidewall of the first region. A conductive material layer is formed within the through-holes and the second opening on the surface of the hard mask layer. The conductive material layer is dissolved back to remove the conductive material layer from the surface of the hard mask layer, forming a conductive layer. The top surface of the conductive layer is lower than or flush with the top surface of the first region and higher than or flush with the top surface of the second dielectric composite layer.
[0007] Optionally, after forming the conductive layer, the process further includes: planarizing the hard mask layer until the surface of the conductive layer is exposed.
[0008] Optionally, the process for forming the conductive material layer includes an electroplating process. The electroplating process includes: providing an electroplating machine; immersing the through-hole, the second opening, and the surface of the hard mask layer in an electrolyte containing copper ions; using the mutually bonded first wafer and the second wafer as cathodes; placing a plating metal in the electrolyte; using the plating metal as an anode; and passing a direct current between the cathode and the anode to form a conductive material layer.
[0009] Optionally, the method for resolving the conductive material layer includes: after the electroplating process, swapping the anode and cathode of the electroplating machine in the electroplating process, so that the first and second wafers bonded together act as the anode and the plating metal acts as the cathode.
[0010] Optionally, the electrolyte may also contain additives that cause the conductive material layer located on the surface of the hard mask layer and in the second opening to dissolve before the conductive material layer located in the via.
[0011] Optionally, after forming the through-hole and the second opening, and before forming the conductive material layer, a protective layer is formed on the sidewalls of the through-hole and the second opening.
[0012] Optionally, the method of forming the protective layer includes: forming a protective material layer on the sidewalls and bottom surfaces of the via, the second opening, and the surface of the mask layer; and etching back the protective material layer until the top surface of the mask layer is exposed.
[0013] Optionally, the protective layer may be made of silicon dioxide.
[0014] Optionally, the first dielectric composite layer includes several first dielectric layers and a first etch stop layer between two adjacent first dielectric layers.
[0015] Optionally, the second dielectric composite layer includes several second dielectric layers and a second etch stop layer between two adjacent second dielectric layers.
[0016] Optionally, the material of the hard mask layer includes silicon oxide.
[0017] Optionally, the thickness of the hard mask layer ranges from 2500 Å to 6000 Å.
[0018] Optionally, the aspect ratio of the through hole can range from 1:5 to 1:12.
[0019] Optionally, the material of the hard mask layer includes silicon oxide.
[0020] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0021] In the semiconductor structure formation method provided by the present invention, the second region sidewall of the hard mask layer is etched during the etching process, while the first region is not excessively etched laterally, which can effectively protect the second dielectric composite layer. By forming a conductive material layer on the surface of the hard mask layer in the via and the second opening, and then dissolving it back, the top surface of the conductive layer in the via and the second opening is higher than or flush with the top surface of the second dielectric composite layer, and lower than or flush with the top surface of the first region. The height of the conductive layer depends on the growth height of the conductive material layer and the size of the dissolved conductive material layer. Since the top surface of the conductive material layer only needs to be lower than or flush with the top surface of the first region, it is not necessary to fill the second opening during the formation of the conductive material layer, which is beneficial to saving conductive material. On the other hand, the formed conductive layer is located in the sidewall of the first region that has not been excessively etched laterally and in the via, which is beneficial to improving the morphology of the conductive layer.
[0022] Furthermore, after forming the conductive layer, the method further includes: planarizing the hard mask layer to expose the surface of the conductive layer. In the process of planarizing the hard mask layer, only the hard mask layer needs to be polished, which helps to improve polishing efficiency and reduce the damage to the conductive layer caused by the planarization process, thereby improving the performance of the conductive layer.
[0023] Furthermore, the method for resolving the conductive material layer includes: after the electroplating process, reversing the anode and cathode of the electroplating machine, so that the first and second wafers bonded together act as the anode and the plating metal acts as the cathode. The resolved conductive material can be collected during the resolution process, which helps save production costs. Attached Figure Description
[0024] Figures 1 to 4 This is a schematic cross-sectional view of the semiconductor structure formation process;
[0025] Figures 5 to 12 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation
[0026] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.
[0027] As mentioned in the background section, the performance of structures formed by existing through-silicon via (TSV) technology needs further improvement. The following analysis will illustrate this with an example of a semiconductor structure.
[0028] Figures 1 to 4 This is a cross-sectional schematic diagram of the semiconductor structure formation process.
[0029] Please refer to Figure 1 The system provides a first wafer 100 and a second wafer 200 bonded together. The first wafer 100 has a first functional surface 100a, which exposes a first bonding pad 101. A first dielectric composite layer is located on the first functional surface 100a. The first dielectric composite layer includes several first dielectric layers 103 and a first etch stop layer 102 between two adjacent first dielectric layers 103. The second wafer 200 has a second functional surface 200a and a third surface 200b opposite to the second functional surface 200a. The first dielectric composite layer and the third surface 200b are bonded together. A second dielectric composite layer is located on the second functional surface 200a. The second dielectric composite layer includes several second dielectric layers 203 and a second etch stop layer 202 between two adjacent second dielectric layers 203. A hard mask material layer 204 is formed on the surface of the second dielectric composite layer.
[0030] Please refer to Figure 2 A patterned hard mask material layer 204 is formed to create a mask layer 205. Using the mask layer 205 as a mask, the second dielectric composite layer, the second wafer 200, and the first dielectric composite layer are etched until the first bonding pad 101 of the first wafer 100 is exposed. Through-holes 206 are formed in the mask layer 205, the second dielectric composite layer, the second wafer 200, and the first dielectric composite layer. A protective material layer 207 is formed on the surface of the through-holes 206 and the mask layer 205.
[0031] Please refer to Figure 3 The protective material layer 207 is etched back until the surface of the first wafer 100 is exposed, forming a protective layer 208 on the sidewall of the via 206.
[0032] Please refer to Figure 4 A conductive layer 209 is formed inside the through hole 206.
[0033] In the semiconductor structure formed by the aforementioned through-silicon via (TSV) process, the conductive layer 209 is made of copper, the mask layer 205, the first dielectric layer 103, and the second dielectric layer 203 are made of silicon oxide, and the first etch stop layer 104 and the second etch stop layer 204 are made of silicon nitride. In the first dielectric composite layer and the second dielectric composite layer, the ratio of silicon oxide to silicon nitride is greater than 8:1. During the process of forming the via 206, a process with a relatively large etching selectivity for silicon oxide and silicon nitride is selected, resulting in a large lateral etching of the mask layer 205 exposed at the top of the via 206, giving the top of the via 206 a "funnel" shape (e.g., ...). Figure 2 As shown in Figure A). Since the material of the protective layer 208 is also silicon oxide, the etching process during the formation of the protective layer 208 will cause the "flare" to further increase (e.g., Figure 3 (As shown in B).
[0034] The via 206 has a "trumpet mouth" shape at the top, which can cause the following problems: 1) The first dielectric composite layer may be etched and damaged due to the incompleteness of the mask layer 205, which may cause damage to the structure of the device within the first dielectric composite layer; 2) During the etching back of the protective material layer 207, the material at the "trumpet mouth" will be etched away, which may lead to the risk of metal ions in the conductive layer 209 diffusing to the second wafer 200; 3) The "trumpet mouth" will reduce the distance between adjacent conductive layers, leading to the risk of copper "bridging" and reducing the reliability of the device performance.
[0035] To reduce the size of the lateral etching of the mask layer, in another embodiment, a composite material layer of silicon oxide / silicon nitride is used as the mask layer. However, silicon nitride produces more byproducts during etching, which are more difficult to clean and mass-produce; in addition, during the planarization process of forming the conductive layer, silicon nitride has a lower etching rate than silicon oxide, making it difficult to remove completely.
[0036] To address the aforementioned issues, this invention provides a method for forming a semiconductor structure in which the second region sidewall of the hard mask layer is etched during the etching process, while the first region is not excessively etched laterally, effectively protecting the second dielectric composite layer. By forming a conductive material layer within the vias and second openings on the surface of the hard mask layer, followed by dissolution, the top surface of the conductive layer within the vias and second openings is higher than or flush with the top surface of the second dielectric composite layer, and lower than or flush with the top surface of the first region. The height of the conductive layer depends on the growth height of the conductive material layer and the size of the dissolved conductive material layer. Since the top surface of the conductive material layer only needs to be lower than or flush with the top surface of the first region, the second opening does not need to be filled during the formation of the conductive material layer, which helps to save conductive material. Furthermore, the formed conductive layer is located within the sidewall of the first region that has not been excessively etched laterally and within the vias, which helps to improve the morphology of the conductive layer.
[0037] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0038] Figures 5 to 12 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.
[0039] Please refer to Figure 5 A first wafer 300 and a second wafer 400 are provided and bonded to each other. The first wafer 300 has a first functional surface 300a, which exposes a pad layer 301. A first dielectric composite layer is provided on the first functional surface 300a. The second wafer 400 has a second functional surface 400a and a third surface 400b opposite to the second functional surface 400a. The first dielectric composite layer and the third surface 400b are bonded to each other. A second dielectric composite layer is provided on the second functional surface 400a.
[0040] The first dielectric composite layer includes several first dielectric layers 303 and a first etch stop layer 302 between two adjacent first dielectric layers 302.
[0041] The second dielectric composite layer includes several second dielectric layers 403 and a second etch stop layer 402 between two adjacent second dielectric layers 403.
[0042] The first dielectric composite layer 302 is formed by the back-end process of the first wafer 300, and the second dielectric composite layer 402 is formed by the back-end process of the second wafer 400. The thickness ratio of silicon oxide to silicon nitride is typically greater than 8:1. Specifically, the material of the first dielectric layer 303 is silicon oxide, the material of the first etch stop layer 304 is silicon nitride, the material of the second dielectric layer 403 is silicon oxide, and the material of the second etch stop layer 404 is silicon nitride.
[0043] In this embodiment, a third etch stop layer 304 is also provided between the first wafer 300 and the first dielectric layer 303. The third etch stop layer 304 is used as an etch stop layer in the subsequent via formation process to avoid etch damage to the first wafer 300 during the etch process.
[0044] Subsequently, conductive layers are formed within the second dielectric composite layer, the second wafer 400, and the first dielectric composite layer, achieving three-dimensional packaging of each structure in the vertical direction. This significantly shortens the interconnection distance between wafers and greatly improves chip speed and low power consumption performance.
[0045] Please refer to Figure 6 A hard mask layer 404 and a first opening 405 located within the hard mask layer 404 are formed on the surface of the second dielectric composite layer. The first opening 405 exposes the surface of the second dielectric composite layer. The hard mask layer 404 includes a first region I and a second region II located on the first region I.
[0046] Region I and Region II are used to define the areas of the hard mask layer 404 that are laterally over-etched and those that are not laterally over-etched during the formation of vias. Region I of the hard mask layer 404 is not laterally over-etched, which can effectively protect the second dielectric composite layer and reduce damage to the second dielectric composite layer during the etching process.
[0047] The method for forming the hard mask layer 404 includes: forming a hard mask material layer (not shown in the figure) on the surface of the second dielectric composite layer; etching the mask material layer until the surface of the second dielectric composite layer is exposed.
[0048] In this embodiment, the hard mask layer 404 is made of silicon oxide. Using silicon oxide as the mask layer makes it easier to clean up byproducts generated during the etching process of forming the hard mask layer 404, reducing adverse effects on device performance.
[0049] In this embodiment, the thickness of the hard mask layer 404 ranges from 6 μm to 10 μm. The reason for choosing this thickness range is that if the thickness is too small, the hard mask layer 404 will expose part of the surface of the second dielectric composite layer due to lateral over-etching during the formation of the via; at the same time, it avoids the situation where the thickness is too large, resulting in a large aspect ratio of the via and the second opening above the via, which would affect the etching morphology of the via.
[0050] Please refer to Figure 7Using a hard mask layer 404 as a mask, the second dielectric composite layer, the second wafer 400, and the first dielectric composite layer are etched until the pad layer 301 is exposed. Through-holes 406 are formed in the second dielectric composite layer, the second wafer 400, and the first dielectric composite layer. The second region II sidewall of the hard mask layer 404 is etched during the etching process so that the first opening 405 forms a second opening 407. The width of the second opening 407 on the second region II sidewall is greater than the width of the second opening 407 on the first region I sidewall.
[0051] The sidewalls of Zone II are tilted due to lateral over-etching, and need to be removed in subsequent processes to reduce bridging between adjacent conductive layers.
[0052] The aspect ratio of the 406 through hole ranges from 1:5 to 1:12.
[0053] Subsequently, a conductive material layer is formed inside the via 406 and the second opening 407 on the surface of the hard mask layer 404. In this embodiment, after the via 406 and the second opening 407 are formed, and before the conductive material layer is formed, a protective layer is formed on the sidewalls of the via 406 and the second opening 407.
[0054] In this embodiment, specifically, the hard mask layer 404 is used as a mask to etch the second dielectric composite layer, the second wafer 400 and the first dielectric composite layer until the third etch stop layer 304 on the pad layer 301 is exposed, forming a through hole in the second dielectric composite layer, the second wafer 400 and the first dielectric composite layer.
[0055] Please refer to the method for forming the protective layer. Figures 8 to 9 .
[0056] Please refer to Figure 8 A protective material layer 408 is formed on the sidewalls and bottom surfaces of the through hole 406, the second opening 407, and the surface of the mask layer 404.
[0057] The protective material layer 408 is used to form a protective layer.
[0058] The material of the protective layer 408 includes silicon oxide.
[0059] The thickness of the protective material layer 408 ranges from 2500 Å to 6000 Å.
[0060] Please refer to Figure 9 The protective material layer 408 is etched back until the top surface of the mask layer 404 is exposed to form the protective layer 409.
[0061] The process of etching back the protective material layer 408 includes a dry etching process. Due to the directional etching of the dry etching process, the protective material layer 408 on the inclined sidewall of the second region II will also be etched away.
[0062] In this embodiment, the material of the protective layer 409 includes silicon oxide. The protective layer 409 is used to block the diffusion of metal ions from the conductive layer into the second dielectric composite layer, the second wafer 400, and the first dielectric composite layer.
[0063] In this embodiment, the process of etching back the protective material layer 408 further includes etching the third etch stop layer 304 to expose the surface of the solder pad layer 301.
[0064] Please refer to Figure 10 A conductive material layer 410 is formed on the surface of the hard mask layer 404 within the through hole 406 and the second opening 407.
[0065] By forming a conductive material layer 410 on the surface of the hard mask layer 204 within the via 406 and the second opening 407, and then dissolving it back, the top surface of the conductive layer within the via 406 and the second opening 407 is higher than or flush with the top surface of the second dielectric composite layer, and lower than or flush with the top surface of the first region I. The height of the conductive layer depends on the growth height of the conductive material layer 410 and the size of the dissolved conductive material layer 410. Since the top surface of the conductive material layer 410 only needs to be lower than or flush with the top surface of the first region I, it is not necessary to fill the second opening during the formation of the conductive material layer, which helps to save conductive material.
[0066] In this embodiment, the formation process of the conductive material layer 410 includes an electroplating process. The electroplating process includes: providing an electroplating machine (not shown in the figure); immersing the surfaces of the through hole 406, the second opening 407, and the hard mask layer 404 in an electrolyte containing copper ions; using the mutually bonded first wafer and the second wafer as cathodes; placing a plating metal (not shown in the figure) in the electrolyte; using the plating metal as an anode; and passing a direct current between the cathode and the anode to form the conductive material layer 410.
[0067] Please refer to Figure 11 The conductive material layer 410 is dissolved back, and the conductive material layer 410 on the surface of the hard mask layer 404 is removed to form a conductive layer 411. The top surface of the conductive layer 411 is lower than or flush with the top surface of the first region I, and higher than or flush with the top surface of the second dielectric composite layer.
[0068] The formed conductive layer 411 is located in the sidewall of the first region I and the via 406, which is not excessively etched laterally, which is beneficial to improving the morphology of the conductive layer 411.
[0069] In this embodiment, the method for remelting the conductive material layer 410 includes: after the electroplating process, swapping the anode and cathode of the electroplating machine so that the first and second wafers bonded together act as the anode and the plating metal acts as the cathode. The remelted conductive material can be collected during the remelting process, which helps save production costs.
[0070] The electrolyte also contains additives that cause the conductive material layer 410 located on the surface of the hard mask layer 404 and in the second opening 407 to dissolve before the conductive material layer located in the through hole 406.
[0071] Please refer to Figure 12 Planarize the hard mask layer 404 until the surface of the conductive layer 411 is exposed.
[0072] During the planarization process, only the hard mask layer 404 needs to be polished, which helps to improve polishing efficiency and reduce the damage to the conductive layer 411 caused by the planarization process, thereby improving the performance of the conductive layer 411.
[0073] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A first wafer and a second wafer are provided bonded to each other. The first wafer has a first functional surface that exposes a pad layer and has a first dielectric composite layer. The second wafer has a second functional surface and a third surface opposite to the second functional surface. The first dielectric composite layer is bonded to the third surface, and the second functional surface has a second dielectric composite layer. A hard mask layer and a first opening located within the hard mask layer are formed on the surface of the second dielectric composite layer. The first opening exposes the surface of the second dielectric composite layer. The hard mask layer includes a first region and a second region located on the first region. Using the hard mask layer as a mask, the second dielectric composite layer, the second wafer, and the first dielectric composite layer are etched until the pad layer is exposed, forming vias in the second dielectric composite layer, the second wafer, and the first dielectric composite layer. The second sidewall of the hard mask layer is etched during the etching process to form a second opening from the first opening. The width of the second opening on the second sidewall of the second region is greater than the width of the second opening on the first sidewall of the first region. A conductive material layer is formed on the surface of the hard mask layer within the through hole and the second opening; The conductive material layer is re-dissolved, and the conductive material layer on the surface of the hard mask layer is removed to form a conductive layer. The top surface of the conductive layer is lower than or flush with the top surface of the first region, and higher than or flush with the top surface of the second dielectric composite layer.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the conductive layer, the method further includes: planarizing the hard mask layer to expose the surface of the conductive layer.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the conductive material layer includes an electroplating process. The electroplating process includes: providing an electroplating machine; immersing the through-hole, the second opening, and the surface of the hard mask layer in an electrolyte containing copper ions; using the mutually bonded first wafer and the second wafer as cathodes; placing a plating metal in the electrolyte; using the plating metal as an anode; and passing a direct current between the cathode and the anode to form the conductive material layer.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method for resolving the conductive material layer includes: after the electroplating process, swapping the anode and cathode of the electroplating machine in the electroplating process, so that the mutually bonded first wafer and second wafer serve as the anode and the plating metal serves as the cathode.
5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The electrolyte also contains an additive that causes the conductive material layer located on the surface of the hard mask layer and within the second opening to dissolve before the conductive material layer located within the via.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the through hole and the second opening are formed, and before the conductive material layer is formed, a protective layer is formed on the sidewalls of the through hole and the second opening.
7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for forming the protective layer includes: forming a protective material layer on the sidewalls and bottom surfaces of the through hole, the second opening, and the surface of the hard mask layer; and etching back the protective material layer until the top surface of the hard mask layer is exposed.
8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The material of the protective layer includes silicon oxide.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first dielectric composite layer includes several first dielectric layers and a first etch stop layer between two adjacent first dielectric layers.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second dielectric composite layer includes several second dielectric layers and a second etch stop layer between two adjacent second dielectric layers.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the hard mask layer includes silicon oxide.
12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the hard mask layer ranges from 2500 Å to 6000 Å.
13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The aspect ratio of the through hole ranges from 5:1 to 12:1.