An ultra-wideband vector modulation phase shifter and phased array system

Abstract

This application proposes an ultra-wideband vector modulation phase shifter and phased array system, comprising a cascaded quadrature signal generation circuit, a quadrature error correction circuit, an I-channel amplitude adjustment circuit, a Q-channel amplitude adjustment circuit, and a quadrature signal synthesis circuit. The quadrature signal generation circuit converts the initial differential signal into an I-channel differential signal and a Q-channel differential signal, and outputs the signals to the quadrature error correction circuit. The quadrature error correction circuit corrects the quadrature error of the received differential signal and outputs the corrected I-channel differential signal and Q-channel differential signal. The I-channel amplitude adjustment circuit and the Q-channel amplitude adjustment circuit adjust the amplitude of the received signal and transmit the adjusted signals to the quadrature signal synthesis circuit. The quadrature signal synthesis circuit combines the two received differential quadrature signals into a target differential signal. The integrated generation and correction circuit structure achieves the expansion of the quadrature signal bandwidth, effectively improving the operating bandwidth of the vector modulation phase shifter.

Description

Technical Field

[0001] The present application relates to the field of phased arrays, and in particular to an ultra-wideband vector modulation phase shifter and a phased array system. Background Art

[0002] Phased array technology has a wide range of applications in millimeter-wave communications, radar, and imaging. Phased array systems utilize large-scale transceiver elements to transmit signals through high-gain, narrow beams. This can improve the equivalent isotropic radiated power (EIRP) at the transmitter and the signal-to-noise ratio (SNR) at the receiver, thereby extending transmission distance and enhancing transmission quality. Each element in a phased array system contains a phase shifter, which is used to process the phase of the element signal, thereby performing functions such as beamforming, beam scanning, and spatial filtering. As one of the core components of a phased array system, the bandwidth, accuracy, and power consumption of the phase shifter directly affect the system's operating frequency band, beam accuracy, and system power consumption.

[0003] The vector modulation phase shifter structure is a widely used phase shifter structure, which is usually composed of three circuit parts: orthogonal signal generation, vector amplitude adjustment, and orthogonal signal synthesis. The orthogonal signal generation circuit generates a pair of orthogonal signals, and the two vector amplitude adjustment circuits adjust the amplitudes of the two orthogonal signals respectively. The orthogonal signal synthesis circuit synthesizes the amplitude-modulated orthogonal vector signals. By adjusting the amplitude ratio of the orthogonal signals, the signal phase can be controlled. However, the existing vector modulation phase shifter structure is relatively narrowband and has performance bottlenecks in application scenarios such as 5G millimeter wave multi-frequency coverage and ultra-wideband phased arrays, and cannot meet the phase control requirements of the system. Summary of the Invention

[0004] The purpose of this application is to provide an ultra-wideband vector modulation phase shifter and a phased array system to at least partially improve the above-mentioned problems.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0006] In a first aspect, an embodiment of the present application provides an ultra-wideband vector modulation phase shifter, the ultra-wideband vector modulation phase shifter comprising a quadrature signal generating circuit 100, a quadrature error correction circuit 200, an I-channel amplitude adjustment circuit 300, a Q-channel amplitude adjustment circuit 400, and an orthogonal signal synthesis circuit 500, which are cascaded in sequence;

[0007] The quadrature signal generating circuit 100 is used to convert the input initial differential signal into an I-channel differential signal and a Q-channel differential signal, and output the I-channel differential signal and the Q-channel differential signal to the quadrature error correction circuit 200;

[0008] The quadrature error correction circuit 200 is used to correct the quadrature error of the received I-channel differential signal and the Q-channel differential signal, and output the corrected I-channel differential signal to the I-channel amplitude adjustment circuit 300, and output the corrected Q-channel differential signal to the Q-channel amplitude adjustment circuit 400;

[0009] The I-channel amplitude adjustment circuit 300 and the Q-channel amplitude adjustment circuit 400 are used to adjust the amplitude of the received signal and transmit the adjusted signal to the orthogonal signal synthesis circuit 500;

[0010] The orthogonal signal synthesis circuit 500 is used to synthesize two received differential orthogonal signals into one target differential signal.

[0011] In a second aspect, an embodiment of the present application provides a phased array system, comprising: the above-mentioned ultra-wideband vector modulation phase shifter.

[0012] Compared with the prior art, the embodiments of the present application provide an ultra-wideband vector modulation phase shifter and phased array system, wherein the ultra-wideband vector modulation phase shifter includes an orthogonal signal generation circuit, an orthogonal error correction circuit, an I-channel amplitude adjustment circuit, a Q-channel amplitude adjustment circuit, and an orthogonal signal synthesis circuit that are cascaded in sequence; the orthogonal signal generation circuit is used to convert the input initial differential signal into an I-channel differential signal and a Q-channel differential signal, and output the I-channel differential signal and the Q-channel differential signal to the orthogonal error correction circuit; the orthogonal error correction circuit is used to correct the orthogonal error of the received I-channel differential signal and the Q-channel differential signal, and output the corrected I-channel differential signal to the I-channel amplitude adjustment circuit, and output the corrected Q-channel differential signal to the Q-channel amplitude adjustment circuit; the I-channel amplitude adjustment circuit and the Q-channel amplitude adjustment circuit are used to perform amplitude adjustment on the received signal and transmit the adjusted signal to the orthogonal signal synthesis circuit; the orthogonal signal synthesis circuit is used to combine the two received differential orthogonal signals into one target differential signal. The quadrature signal bandwidth is expanded by integrating generation and correction into a circuit structure, effectively increasing the operating bandwidth of the vector modulation phase shifter. The quadrature error correction circuit is easily scalable, allowing the operating frequency band of the phase shifter to be easily expanded by configuring the number of cascaded error correction circuits and the operating frequency of each stage. Inserting the quadrature error correction circuit between the quadrature signal generation circuit and the amplitude adjustment circuit provides isolation, reducing the impact of load impedance on the quadrature signal generation circuit and preventing the introduction of parasitic quadrature errors.

[0013] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 This is a schematic diagram of the structure of an ultra-wideband vector modulation phase shifter provided in an embodiment of the present application;

[0016] Figure 2 The second structural diagram of the ultra-wideband vector modulation phase shifter provided in an embodiment of the present application;

[0017] Figure 3 The third structural diagram of the ultra-wideband vector modulation phase shifter provided in an embodiment of the present application;

[0018] Figure 4 The fourth structural diagram of the ultra-wideband vector modulation phase shifter provided in an embodiment of the present application;

[0019] Figure 5 This is the fifth structural diagram of the ultra-wideband vector modulation phase shifter provided in an embodiment of the present application.

[0020] In the figure: 100-orthogonal signal generating circuit; 101-first differential trace; 102-second differential trace; 103-third differential trace; 104-fourth differential trace; 105-fifth differential trace; 106-sixth differential trace; 110-first layer sub-circuit; 120-second layer sub-circuit; 131-isolated load;

[0021] 200 - quadrature error correction circuit; 201 - first differential inductor; 202 - first capacitor; 203 - second capacitor; 204 - third capacitor; 205 - fourth capacitor; 206 - first resistor; 207 - second resistor; 208 - third resistor; 209 - fourth resistor; 210 - second differential inductor;

[0022] 300 - I-channel amplitude adjustment circuit; 301 - fifth capacitor; 302 - first transformer; 303 - first transistor; 304 - second transistor; 305 - third transistor; 306 - fourth transistor; 307 - fifth transistor; 308 - sixth transistor;

[0023] 400 - Q-channel amplitude adjustment circuit; 401 - sixth capacitor; 402 - second transformer; 403 - seventh transistor; 404 - eighth transistor; 405 - ninth transistor; 406 - tenth transistor; 407 - eleventh transistor; 408 - twelfth transistor;

[0024] 500 - orthogonal signal synthesis circuit; 501 - seventh differential trace; 502 - eighth differential trace; 503 - third transformer; 504 - seventh capacitor. DETAILED DESCRIPTION

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0027] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0028] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0029] In the description of this application, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0030] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, or electrical connections; direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0031] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0032] The bandwidth of a vector-modulated phase shifter is primarily limited by the bandwidth of the quadrature signal generation circuit. Commonly used quadrature signal generation circuit structures include RC-CR polyphase filters (PPFs), quadrature all-pass filters (QAFs), and 3dB quadrature couplers. PPFs, composed of a network of resistors and capacitors, offer the advantage of a small footprint. However, the use of resistors introduces significant losses, and a single-stage PPF only supports quadrature signal generation at a single frequency, resulting in a relatively narrow bandwidth. QAFs, consisting of inductors, capacitors, and resistors, offer lower losses than PPFs. However, the orthogonality of QAFs is more sensitive to load impedance, placing higher demands on the input impedance design of subsequent circuits. Compared to PPFs and QAFs, 3dB quadrature couplers offer the advantage of low losses, but they are larger in size and generate a relatively narrow bandwidth of quadrature signals. Consequently, performance bottlenecks exist in the bandwidth, loss, and area of ​​the quadrature signal generation circuit, limiting the performance of vector-modulated phase shifters. Therefore, it is necessary to explore new circuit structures to achieve ultra-wideband, low-loss, and miniaturized phase shifter designs.

[0033] The embodiment of the present application provides an ultra-wideband vector modulation phase shifter, which uses a circuit structure integrating generation and correction to expand the phase shift bandwidth and realizes flexible configuration of the working frequency band through the optional number of error correction cascades. Figure 1 , Figure 1 This is one of the structural schematic diagrams of the ultra-wideband vector modulation phase shifter provided in an embodiment of the present application.

[0034] like Figure 1As shown, the ultra-wideband vector modulation phase shifter includes a quadrature signal generating circuit 100, a quadrature error correction circuit 200, an I-channel amplitude adjustment circuit 300, a Q-channel amplitude adjustment circuit 400, and a quadrature signal synthesizing circuit 500, which are cascaded in sequence.

[0035] Optionally, the orthogonal signal generating circuit 100 has a two-port input and four-port output structure.

[0036] The quadrature signal generating circuit 100 is used to convert an input initial differential signal into an I-channel differential signal and a Q-channel differential signal, and output the I-channel differential signal and the Q-channel differential signal to the quadrature error correction circuit 200 .

[0037] In the present application, the orthogonal signal generating circuit 100 can be a passive structure, and the two differential signals (I-channel differential signal and Q-channel differential signal) generated by the orthogonal signal generating circuit 100 do not have to be broadband orthogonal signals, that is, they can be narrowband orthogonal signals. The I-channel differential signal and the Q-channel differential signal satisfy an orthogonal relationship with the same amplitude and a phase difference of 90 degrees at a single frequency point or multiple frequency points.

[0038] Optionally, the quadrature error correction circuit 200 has a four-port input and four-port output structure.

[0039] The quadrature error correction circuit 200 is used to correct the quadrature error of the received I-channel differential signal and Q-channel differential signal, and output the corrected I-channel differential signal to the I-channel amplitude adjustment circuit 300 and output the corrected Q-channel differential signal to the Q-channel amplitude adjustment circuit 400.

[0040] Optionally, the I-channel differential signal and the Q-channel differential signal received by the quadrature error correction circuit 200 are narrowband quadrature signals, and the corrected I-channel differential signal and the Q-channel differential signal are broadband quadrature signals.

[0041] Optionally, the structure of the I-channel amplitude adjustment circuit 300 and the structure of the Q-channel amplitude adjustment circuit 400 may be the same, both being differential input and differential output structures.

[0042] The I-channel amplitude adjustment circuit 300 and the Q-channel amplitude adjustment circuit 400 are used to adjust the amplitude of the received signal and transmit the adjusted signal to the orthogonal signal synthesis circuit 500 .

[0043] Optionally, the I-channel amplitude adjustment circuit 300 and the Q-channel amplitude adjustment circuit 400 have the ability to flip phase by 180 degrees. The amplitude adjustment function is managed by a digital control signal. The I-channel amplitude adjustment circuit 300 and the Q-channel amplitude adjustment circuit 400 use control codes with the same number of bits but are independent of each other. The control codes here are composed of the digital control signals mentioned above. The number of bits in the control code is the same as the number of parallel amplification units (first amplification unit and second amplification unit) in the adjustment circuit (I-channel amplitude adjustment circuit 300 and Q-channel amplitude adjustment circuit 400). The control codes of the I-channel amplitude adjustment circuit 300 and the Q-channel amplitude adjustment circuit 400 have the same number of bits but are independent of each other.

[0044] Optionally, the orthogonal signal synthesis circuit 500 has a four-port input and two-port output structure.

[0045] The orthogonal signal synthesis circuit 500 is used to synthesize two received differential orthogonal signals into one target differential signal.

[0046] exist Figure 1 On the basis of the specific structure of each module in the ultra-wideband vector modulation phase shifter, the embodiment of the present application also provides an optional implementation method, please refer to Figure 2 , Figure 2 This is the second structural diagram of the ultra-wideband vector modulation phase shifter provided in an embodiment of the present application.

[0047] like Figure 2 As shown, the quadrature signal generating circuit 100 is a fully differential structure, including a first-layer sub-circuit 110 , a second-layer sub-circuit 120 and an isolation load 131 .

[0048] The sub-circuits (including the first-layer sub-circuit 110 and the second-layer sub-circuit 120 ) are single-layer coupled lines, each including a first differential trace 101 , a second differential trace 102 , a third differential trace 103 , a fourth differential trace 104 , a fifth differential trace 105 and a sixth differential trace 106 .

[0049] In the sub-circuit on the same layer, the first end of the first differential trace 101 is connected to the first end of the third differential trace 103 via its third end, and the second end of the first differential trace 101 is connected to the second end of the third differential trace 103 via its fourth end.

[0050] The first end of the third differential trace 103 is connected to the first end of the fifth differential trace 105 via the third end thereof, and the second end of the third differential trace 103 is connected to the second end of the fifth differential trace 105 via the fourth end thereof.

[0051] The first end of the fifth differential trace 105 is connected to the first end of the fourth differential trace 104 through the third end thereof, and the second end of the fifth differential trace 105 is connected to the second end of the fourth differential trace 104 through the fourth end thereof.

[0052] The first end of the fourth differential trace 104 is connected to the second end of the second differential trace 102 via the fourth end thereof, and the second end of the fourth differential trace 104 is connected to the first end of the second differential trace 102 via the third end thereof.

[0053] The first end of the second differential trace 102 is connected to the fifth end of the third differential trace 103 via the third end thereof, and the second end of the second differential trace 102 is connected to the sixth end of the third differential trace 103 via the fourth end thereof.

[0054] The fifth end of the third differential trace 103 is connected to the first end of the sixth differential trace 106 through the seventh end thereof, and the sixth end of the third differential trace 103 is connected to the second end of the sixth differential trace 106 through the eighth end thereof.

[0055] The sub-circuit 110 of the first layer and the sub-circuit 120 of the second layer have the same layout and are coupled to each other, forming coupled coils of the upper and lower layers. Optionally, the coupling degree between the two is greater than 0.707.

[0056] The first end and the second end of the first differential trace 101 in the sub-circuit 110 of the first layer serve as input ends of the orthogonal signal generating circuit 100 for receiving the initial differential signal.

[0057] The first end and the second end of the first differential trace 101 in the second-layer sub-circuit 120 serve as a first set of output ends of the quadrature signal generating circuit 100 and are connected to a first set of input ends of the quadrature error correction circuit 200 .

[0058] The third and fourth ends of the sixth differential trace 106 in the first-layer sub-circuit 110 serve as the second set of output ends of the quadrature signal generating circuit 100 and are connected to the second set of input ends of the quadrature error correction circuit 200 .

[0059] The third end and the fourth end of the sixth differential trace 106 in the second-layer sub-circuit 120 serve as isolated output ports of the quadrature signal generating circuit 100 and are connected to two ends of the isolated load 131 , respectively.

[0060] In the solution of the present application, the differential signal received by the first differential trace 101 is transmitted backward through the third differential trace 103 and the fifth differential trace 105, and the polarity reversal of the differential signal is completed by the fourth differential trace 104, which is used to compensate for the inherent amplitude and phase errors of the differential signal under the coplanar layout of the coil, and achieve amplitude and phase balance of the differential signal; the signal after the polarity reversal is then transmitted backward through the second differential trace 102 and the third differential trace 103 to the sixth differential trace 106, and the sixth differential trace 106 is connected to the subsequent circuit as a direct output port of the orthogonal signal generating circuit 100.

[0061] exist Figure 1 On the basis of the specific structure of each module in the ultra-wideband vector modulation phase shifter, the embodiment of the present application also provides an optional implementation method, please refer to Figure 3 , Figure 3 This is the third structural diagram of the ultra-wideband vector modulation phase shifter provided in an embodiment of the present application.

[0062] like Figure 3 As shown, the quadrature error correction circuit 200 includes N stages of error correction sub-circuits cascaded in sequence, where N is a positive integer greater than or equal to 1. When N is greater than 1, the structures of the multiple error correction sub-circuits do not have to be exactly the same.

[0063] The first group of input terminals of the first-stage error correction sub-circuit serves as the first group of input terminals of the quadrature error correction circuit 200 and is connected to the first group of output terminals of the quadrature signal generating circuit 100 .

[0064] The second group of input terminals of the first-stage error correction sub-circuit serves as the second group of input terminals of the quadrature error correction circuit 200 and is connected to the second group of output terminals of the quadrature signal generating circuit 100 .

[0065] When N is greater than or equal to 2, the first group of input terminals of the i-th level error correction sub-circuit is connected to the Q-channel output terminals of the i-1-th level error correction sub-circuit, and the second group of input terminals of the i-th level error correction sub-circuit is connected to the I-channel output terminals of the i-1-th level error correction sub-circuit, 2≤i≤N.

[0066] The Q-path output terminal of the N-th stage error correction sub-circuit serves as the Q-path output terminal of the orthogonal error correction circuit 200 and is connected to the input terminal of the Q-path amplitude adjustment circuit 400 .

[0067] The I-channel output terminal of the N-th stage error correction sub-circuit serves as the I-channel output terminal of the orthogonal error correction circuit 200 and is connected to the input terminal of the I-channel amplitude adjustment circuit 300 .

[0068] Please continue to refer to Figure 2In an optional embodiment, each level of error correction sub-circuit includes a first differential inductor 201, a first capacitor 202, a second capacitor 203, a third capacitor 204, a fourth capacitor 205, a first resistor 206, a second resistor 207, a third resistor 208, a fourth resistor 209 and a second differential inductor 210.

[0069] The first end and the second end of the first differential inductor 201 serve as a first set of input ends of the error correction subcircuit, and the first end and the second end of the second differential inductor 210 serve as a second set of input ends of the error correction subcircuit.

[0070] Optionally, the first differential inductor 201 and the second differential inductor 210 are identical differential inductors. The I-path differential signal and the Q-path differential signal are connected to the error correction core circuit in the error correction subcircuit via the first differential inductor 201 and the second differential inductor 210, thereby achieving impedance matching with the preceding quadrature signal generating circuit 100.

[0071] Optionally, the first capacitor 202 , the second capacitor 203 , the third capacitor 204 and the fourth capacitor 205 are completely identical, and the first resistor 206 , the second resistor 207 , the third resistor 208 and the fourth resistor 209 are completely identical.

[0072] Among them, the resistance value of the first resistor 206, the second resistor 207, the third resistor 208 and the fourth resistor 209 is the same, which is R. The capacitance value of the first capacitor 202, the second capacitor 203, the third capacitor 204 and the fourth capacitor 205 is the same, which is C. The values ​​of R and C are determined by the operating frequency f of the orthogonal error correction circuit 200. The three parameters satisfy the condition 2πfCR=1.

[0073] In an optional implementation, the first resistor 206, the second resistor 207, the third resistor 208, and the fourth resistor 209 may be adjustable resistors (such as varistors), and the first capacitor 202, the second capacitor 203, the third capacitor 204, and the fourth capacitor 205 may be adjustable capacitors (such as varactors). Figure 4 As shown, the values ​​of R and C have reconfigurable characteristics to achieve adjustable error correction frequency.

[0074] One end of the first capacitor 202 is connected to one end of the first resistor 206 , and the third end of the first differential inductor 201 is connected between the first capacitor 202 and the first resistor 206 .

[0075] One end of the third capacitor 204 is connected to one end of the third resistor 208 , and the fourth end of the first differential inductor 201 is connected between the third capacitor 204 and the third resistor 208 .

[0076] One end of the second capacitor 203 is connected to one end of the second resistor 207 , and a third end of the second differential inductor 210 is connected between the second capacitor 203 and the second resistor 207 .

[0077] One end of the fourth capacitor 205 is connected to one end of the fourth resistor 209 , and a fourth end of the second differential inductor 210 is connected between the fourth capacitor 205 and the fourth resistor 209 .

[0078] The other end of the first capacitor 202 is connected to the other end of the second resistor 207, the other end of the second capacitor 203 is connected to the other end of the third resistor 208, the other end of the third capacitor 204 is connected to the other end of the fourth resistor 209, and the other end of the fourth capacitor 205 is connected to the other end of the first resistor 206.

[0079] A first terminal is connected between the fourth capacitor 205 and the first resistor 206 , and a second terminal is connected between the second capacitor 203 and the third resistor 208 . The first terminal and the second terminal are Q-path output terminals of the error correction sub-circuit.

[0080] A third terminal is connected between the third capacitor 204 and the fourth resistor 209 , and a fourth terminal is connected between the first capacitor 202 and the second resistor 207 . The third terminal and the fourth terminal are I output terminals of the error correction sub-circuit.

[0081] Please continue to refer to Figure 2 In an optional implementation, the I-channel amplitude adjustment circuit 300 includes a fifth capacitor 301, a first transformer 302, and a plurality of parallel first amplifying units.

[0082] The first end of the fifth capacitor 301 is connected to the first end of the primary coil of the first transformer 302, and a fifth terminal is led out at the connection between the two. The second end of the fifth capacitor 301 is connected to the second end of the primary coil of the first transformer 302, and a sixth terminal is led out at the connection between the two. The fifth terminal and the sixth terminal serve as input ends of the I-channel amplitude adjustment circuit 300 and are connected to the orthogonal error correction circuit 200.

[0083] Optionally, on the input side, input impedance matching is achieved by connecting the fifth capacitor 301 and the first transformer 302 in parallel.

[0084] The center tap of the secondary coil of the first transformer 302 is used to access the corresponding DC bias voltage Vbias to provide a DC bias for the amplitude control amplifier (ie, a plurality of parallel first amplifying units).

[0085] A first end of the secondary coil of the first transformer 302 is connected to the first input end of the first amplifying unit, and a second end of the secondary coil of the first transformer 302 is connected to the second input end of the first amplifying unit.

[0086] The first output ends of multiple first amplifying units are connected in parallel to lead out to the seventh terminal, and the second output ends of multiple first amplifying units are connected in parallel to lead out to the eighth terminal. The seventh terminal and the eighth terminal serve as the output ends of the I-channel amplitude adjustment circuit 300 and are connected to the orthogonal signal synthesis circuit 500.

[0087] Please continue to refer to Figure 2 In an optional implementation, the first amplifying unit includes a first transistor 303 , a second transistor 304 , a third transistor 305 , a fourth transistor 306 , a fifth transistor 307 and a sixth transistor 308 .

[0088] The first transistor 303 and the second transistor 304 have the same size, and the third transistor 305 , the fourth transistor 306 , the fifth transistor 307 and the sixth transistor 308 have the same size.

[0089] The gate of the first transistor 303 and the gate of the second transistor 304 are used to receive a pair of logically inverted digital control signals to implement a phase reversal function of the differential signal.

[0090] The source of the first transistor 303 and the source of the second transistor 304 are grounded.

[0091] The gate of the third transistor 305 and the gate of the fourth transistor 306 are connected together to serve as the first input terminal of the first amplifying unit.

[0092] The gate of the fifth transistor 307 and the gate of the sixth transistor 308 are connected together to serve as the second input terminal of the first amplifying unit.

[0093] The source of the third transistor 305 and the source of the sixth transistor 308 are connected together, and the drain of the second transistor 304 is connected between the two.

[0094] The source of the fourth transistor 306 and the source of the fifth transistor 307 are connected together, and the drain of the first transistor 303 is connected between the two.

[0095] The drain of the third transistor 305 and the drain of the fifth transistor 307 are connected together as a first output terminal of the first amplifying unit.

[0096] The drain of the fourth transistor 306 and the drain of the sixth transistor 308 are connected together as the second output terminal of the first amplifying unit.

[0097] Optionally, when the second transistor 304 is turned on and the first transistor 303 is turned off, the input differential signal is amplified by the third transistor 305 and the sixth transistor 308 and directly output; when the first transistor 303 is turned on and the second transistor 304 is turned off, the input differential signal is amplified by the fourth transistor 306 and the fifth transistor 307 and output after converting the polarity.

[0098] Please continue to refer to Figure 2 In an optional implementation, the Q-path amplitude adjustment circuit 400 includes a sixth capacitor 401, a second transformer 402, and a plurality of parallel second amplifying units.

[0099] The first end of the sixth capacitor 401 is connected to the first end of the primary coil of the second transformer 402, and the ninth terminal is led out at the connection between the two. The second end of the sixth capacitor 401 is connected to the second end of the primary coil of the second transformer 402, and the tenth terminal is led out at the connection between the two. The ninth terminal and the tenth terminal serve as input ends of the Q-path amplitude adjustment circuit 400 and are connected to the orthogonal error correction circuit 200.

[0100] The center tap of the secondary coil of the second transformer 402 is used to access the corresponding DC bias voltage.

[0101] A first end of the secondary coil of the second transformer 402 is connected to the first input end of the second amplifying unit, and a second end of the secondary coil of the second transformer 402 is connected to the second input end of the second amplifying unit.

[0102] The first output ends of multiple second amplifying units are connected in parallel to lead out to the eleventh terminal, and the second output ends of multiple second amplifying units are connected in parallel to lead out to the twelfth terminal. The eleventh terminal and the twelfth terminal serve as the output ends of the Q-path amplitude adjustment circuit 400 and are connected to the orthogonal signal synthesis circuit 500.

[0103] Please continue to refer to Figure 2 In an optional implementation, the second amplifying unit includes a seventh transistor 403, an eighth transistor 404, a ninth transistor 405, a tenth transistor 406, an eleventh transistor 407, and a twelfth transistor 408;

[0104] The gate of the seventh transistor 403 and the gate of the eighth transistor 404 are used to receive a pair of logically inverted digital control signals.

[0105] It should be noted that the gates of the seventh transistor 403 and the eighth transistor 404 are controlled independently from the gates of the first transistor 303 and the second transistor 304. Furthermore, the digital control signals (logic control signals) used by the multiple parallel units are also independent.

[0106] The source of the seventh transistor 403 and the source of the eighth transistor 404 are grounded.

[0107] The gate of the ninth transistor 405 and the gate of the tenth transistor 406 are connected together to serve as the first input terminal of the second amplifying unit.

[0108] The gate of the eleventh transistor 407 and the gate of the twelfth transistor 408 are connected together to serve as the second input terminal of the second amplifying unit.

[0109] The source of the ninth transistor 405 and the source of the twelfth transistor 408 are connected together, and the drain of the eighth transistor 404 is connected between the two.

[0110] The source of the tenth transistor 406 and the source of the eleventh transistor 407 are connected together, and the drain of the seventh transistor 403 is connected between the two.

[0111] The drain of the ninth transistor 405 and the drain of the eleventh transistor 407 are connected together as a first output terminal of the second amplifying unit.

[0112] The drain of the tenth transistor 406 and the drain of the twelfth transistor 408 are connected together as the second output terminal of the second amplifying unit.

[0113] It should be noted that the structure of the I-channel amplitude adjustment circuit 300 and the structure of the Q-channel amplitude adjustment circuit 400 are exactly the same, and the corresponding effects are also the same, which will not be described in detail here.

[0114] In one possible implementation, the structures of the I-channel amplitude adjustment circuit 300 and the Q-channel amplitude adjustment circuit 400 both use five parallel, size-doubled amplification units, which can achieve 1024 phase states and meet the accuracy requirements of a 6-bit phase shifter.

[0115] Please continue to refer to Figure 2 In an optional implementation, the orthogonal signal synthesis circuit 500 includes a seventh differential trace 501 , an eighth differential trace 502 , a third transformer 503 , and a seventh capacitor 504 .

[0116] The first end and the second end of the seventh differential trace 501 serve as a first set of input ends of the quadrature signal synthesis circuit 500 and are connected to the output end of the Q-path amplitude adjustment circuit 400 .

[0117] The first end of the seventh differential trace 501 is connected to the first end of the primary coil of the third transformer 503 through its third end, and the second end of the seventh differential trace 501 is connected to the second end of the primary coil of the third transformer 503 through its fourth end.

[0118] The first end and the second end of the eighth differential trace 502 serve as a second set of input ends of the orthogonal signal synthesis circuit 500 and are connected to the output end of the I-channel amplitude adjustment circuit 300 .

[0119] The first end of the eighth differential trace 502 is connected to the second end of the primary coil of the third transformer 503 through its third end, and the second end of the eighth differential trace 502 is connected to the first end of the primary coil of the third transformer 503 through its fourth end.

[0120] The center tap of the primary coil of the third transformer 503 is used to access the power supply voltage VDD, which can power the amplifying unit circuits in the preceding I-channel amplitude adjustment circuit 300 and the Q-channel amplitude adjustment circuit 400.

[0121] A first end of the seventh capacitor 504 is connected to a first end of the secondary coil of the third transformer 503, and a thirteenth terminal is led out from the connection between the two. A second end of the seventh capacitor 504 is connected to a second end of the secondary coil of the third transformer 503, and a fourteenth terminal is led out from the connection between the two. The thirteenth terminal and the fourteenth terminal serve as output ends of the orthogonal signal synthesis circuit 500 and are used to connect to subsequent circuits.

[0122] In the present application, since the I-channel amplitude adjustment circuit 300 and the Q-channel amplitude adjustment circuit 400 of the front stage are active structures with good reverse isolation, the orthogonal signal synthesis circuit 500 can adopt a direct current synthesis structure without isolation, that is, Figure 2 The seventh differential trace 501 and the eighth differential trace 502 are used to perform current synthesis on the two orthogonal signals after amplitude modulation.

[0123] Optionally, the seventh capacitor 504 and the third transformer 503 connected in parallel are used to achieve output impedance matching.

[0124] Optionally, the orthogonal signal synthesis circuit 500 may adopt Figure 2 The current combining structure or power combining structure shown is composed of a Wilkinson power divider with isolation.

[0125] In the present application, the I-channel amplitude adjustment circuit 300 and the Q-channel amplitude adjustment circuit 400 can adopt a unidirectional or bidirectional transmission circuit structure. When a bidirectional transmission circuit structure is adopted, the ultra-wideband vector modulation phase shifter in the present application also supports a bidirectional transmission function, that is, the input and output ends of each module are swapped, such as Figure 5 shown.

[0126] Optionally, an embodiment of the present application further provides a phased array system, which includes: the above-mentioned ultra-wideband vector modulation phase shifter.

[0127] In summary, an ultra-wideband vector modulation phase shifter and a phased array system are provided in an embodiment of the present application. The ultra-wideband vector modulation phase shifter includes an orthogonal signal generating circuit, an orthogonal error correction circuit, an I-channel amplitude adjustment circuit, a Q-channel amplitude adjustment circuit, and an orthogonal signal synthesis circuit cascaded in sequence; the orthogonal signal generating circuit is used to convert the input initial differential signal into an I-channel differential signal and a Q-channel differential signal, and output the I-channel differential signal and the Q-channel differential signal to the orthogonal error correction circuit; the orthogonal error correction circuit is used to correct the orthogonal error of the received I-channel differential signal and the Q-channel differential signal, and output the corrected I-channel differential signal to the I-channel amplitude adjustment circuit, and output the corrected Q-channel differential signal to the Q-channel amplitude adjustment circuit; the I-channel amplitude adjustment circuit and the Q-channel amplitude adjustment circuit are used to perform amplitude adjustment on the received signal, and transmit the adjusted signal to the orthogonal signal synthesis circuit; the orthogonal signal synthesis circuit is used to combine the two received differential orthogonal signals into one target differential signal. The quadrature signal bandwidth is expanded by integrating generation and correction into a circuit structure, effectively increasing the operating bandwidth of the vector modulation phase shifter. The quadrature error correction circuit is easily scalable, allowing the operating frequency band of the phase shifter to be easily expanded by configuring the number of cascaded error correction circuits and the operating frequency of each stage. Inserting the quadrature error correction circuit between the quadrature signal generation circuit and the amplitude adjustment circuit provides isolation, reducing the impact of load impedance on the quadrature signal generation circuit and preventing the introduction of parasitic quadrature errors.

[0128] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

[0129] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present application is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. An ultra-wideband vector modulation phase shifter, characterized in that: The ultra-wideband vector modulation phase shifter comprises an orthogonal signal generating circuit (100), an orthogonal error correction circuit (200), an I-channel amplitude adjustment circuit (300), a Q-channel amplitude adjustment circuit (400), and an orthogonal signal synthesis circuit (500) which are sequentially cascaded, and the orthogonal error correction circuit (200) comprises N-stage error correction sub-circuits which are sequentially cascaded; The orthogonal signal generating circuit (100) is used to convert an input initial differential signal into an I-path differential signal and a Q-path differential signal, and output the I-path differential signal and the Q-path differential signal to the orthogonal error correction circuit (200); The quadrature error correction circuit (200) is used to correct the quadrature error of the received I-channel differential signal and the Q-channel differential signal, and output the corrected I-channel differential signal to the I-channel amplitude adjustment circuit (300), and output the corrected Q-channel differential signal to the Q-channel amplitude adjustment circuit (400). The I-channel differential signal and the Q-channel differential signal received by the quadrature error correction circuit (200) are narrowband quadrature signals, and the corrected I-channel differential signal and the Q-channel differential signal are broadband quadrature signals. The I-channel amplitude adjustment circuit (300) and the Q-channel amplitude adjustment circuit (400) are used to adjust the amplitude of the received signal and transmit the adjusted signal to the orthogonal signal synthesis circuit (500); The orthogonal signal synthesis circuit (500) is used for synthesizing two received differential orthogonal signals into one target differential signal.

2. The ultra-wideband vector modulation phase shifter according to claim 1, wherein: The orthogonal signal generating circuit (100) comprises a first-layer sub-circuit (110), a second-layer sub-circuit (120), and an isolation load (131); The sub-circuits each include a first differential trace (101), a second differential trace (102), a third differential trace (103), a fourth differential trace (104), a fifth differential trace (105), and a sixth differential trace (106); In the sub-circuit on the same layer, the first end of the first differential trace (101) is connected to the first end of the third differential trace (103) via its third end, and the second end of the first differential trace (101) is connected to the second end of the third differential trace (103) via its fourth end; The first end of the third differential line (103) is connected to the first end of the fifth differential line (105) via its third end, and the second end of the third differential line (103) is connected to the second end of the fifth differential line (105) via its fourth end; The first end of the fifth differential line (105) is connected to the first end of the fourth differential line (104) via its third end, and the second end of the fifth differential line (105) is connected to the second end of the fourth differential line (104) via its fourth end; The first end of the fourth differential line (104) is connected to the second end of the second differential line (102) via its fourth end, and the second end of the fourth differential line (104) is connected to the first end of the second differential line (102) via its third end; The first end of the second differential line (102) is connected to the fifth end of the third differential line (103) via the third end thereof, and the second end of the second differential line (102) is connected to the sixth end of the third differential line (103) via the fourth end thereof; The fifth end of the third differential line (103) is connected to the first end of the sixth differential line (106) via the seventh end thereof, and the sixth end of the third differential line (103) is connected to the second end of the sixth differential line (106) via the eighth end thereof; The sub-circuit (110) of the first layer and the sub-circuit (120) of the second layer are coupled to each other; The first end and the second end of the first differential trace (101) in the sub-circuit (110) of the first layer serve as input ends of the orthogonal signal generating circuit (100) for receiving the initial differential signal; The first end and the second end of the first differential trace (101) in the second layer subcircuit (120) serve as a first group of output ends of the orthogonal signal generating circuit (100) and are connected to a first group of input ends of the orthogonal error correction circuit (200); The third end and the fourth end of the sixth differential trace (106) in the sub-circuit (110) of the first layer serve as the second set of output ends of the orthogonal signal generating circuit (100) and are connected to the second set of input ends of the orthogonal error correction circuit (200); The third end and the fourth end of the sixth differential trace (106) in the second-layer sub-circuit (120) are respectively connected to two ends of the isolation load (131).

3. The ultra-wideband vector modulation phase shifter according to claim 1, wherein: The first group of input terminals of the first-stage error correction subcircuit serves as the first group of input terminals of the quadrature error correction circuit (200), and is connected to the first group of output terminals of the quadrature signal generation circuit (100); The second group of input terminals of the first-stage error correction subcircuit serves as the second group of input terminals of the quadrature error correction circuit (200), and is connected to the second group of output terminals of the quadrature signal generation circuit (100); The first group of input terminals of the error correction sub-circuit of the i-th stage is connected to the Q-channel output terminal of the error correction sub-circuit of the i-1-th stage, and the second group of input terminals of the error correction sub-circuit of the i-th stage is connected to the I-channel output terminal of the error correction sub-circuit of the i-1-th stage, 2≤i≤N, The Q-path output end of the N-th stage error correction subcircuit serves as the Q-path output end of the orthogonal error correction circuit (200), and is connected to the input end of the Q-path amplitude adjustment circuit (400); The I-channel output end of the N-th stage error correction subcircuit serves as the I-channel output end of the orthogonal error correction circuit (200) and is connected to the input end of the I-channel amplitude adjustment circuit (300).

4. The ultra-wideband vector modulation phase shifter according to claim 3, wherein: Each level of the error correction subcircuit comprises a first differential inductor (201), a first capacitor (202), a second capacitor (203), a third capacitor (204), a fourth capacitor (205), a first resistor (206), a second resistor (207), a third resistor (208), a fourth resistor (209), and a second differential inductor (210); The first end and the second end of the first differential inductor (201) serve as a first set of input ends of the error correction subcircuit, and the first end and the second end of the second differential inductor (210) serve as a second set of input ends of the error correction subcircuit; One end of the first capacitor (202) is connected to one end of the first resistor (206), and a third end of the first differential inductor (201) is connected between the first capacitor (202) and the first resistor (206); One end of the third capacitor (204) is connected to one end of the third resistor (208), and a fourth end of the first differential inductor (201) is connected between the third capacitor (204) and the third resistor (208); One end of the second capacitor (203) is connected to one end of the second resistor (207), and a third end of the second differential inductor (210) is connected between the second capacitor (203) and the second resistor (207); One end of the fourth capacitor (205) is connected to one end of the fourth resistor (209), and a fourth end of the second differential inductor (210) is connected between the fourth capacitor (205) and the fourth resistor (209); The other end of the first capacitor (202) is connected to the other end of the second resistor (207), the other end of the second capacitor (203) is connected to the other end of the third resistor (208), the other end of the third capacitor (204) is connected to the other end of the fourth resistor (209), and the other end of the fourth capacitor (205) is connected to the other end of the first resistor (206); A first wiring terminal is led out between the fourth capacitor (205) and the first resistor (206), and a second wiring terminal is led out between the second capacitor (203) and the third resistor (208), the first wiring terminal and the second wiring terminal being Q-path output ends of the error correction sub-circuit; A third terminal is connected between the third capacitor (204) and the fourth resistor (209), and a fourth terminal is connected between the first capacitor (202) and the second resistor (207). The third terminal and the fourth terminal serve as I output terminals of the error correction subcircuit.

5. The ultra-wideband vector modulation phase shifter according to claim 1, wherein: The I-channel amplitude adjustment circuit (300) comprises a fifth capacitor (301), a first transformer (302), and a plurality of parallel first amplification units; A first end of the fifth capacitor (301) is connected to a first end of the primary coil of the first transformer (302), and a fifth terminal is led out from the connection between the two. A second end of the fifth capacitor (301) is connected to a second end of the primary coil of the first transformer (302), and a sixth terminal is led out from the connection between the two. The fifth terminal and the sixth terminal serve as input ends of the I-channel amplitude adjustment circuit (300) and are connected to the quadrature error correction circuit (200). The center tap of the secondary coil of the first transformer (302) is used to access a corresponding DC bias voltage; The first end of the secondary coil of the first transformer (302) is connected to the first input end of the first amplifying unit, and the second end of the secondary coil of the first transformer (302) is connected to the second input end of the first amplifying unit; The first output ends of the plurality of first amplifying units are connected in parallel to lead out a seventh terminal, and the second output ends of the plurality of first amplifying units are connected in parallel to lead out an eighth terminal. The seventh terminal and the eighth terminal serve as output ends of the I-channel amplitude adjustment circuit (300) and are connected to the orthogonal signal synthesis circuit (500).

6. The ultra-wideband vector modulation phase shifter according to claim 5, wherein: The first amplifying unit includes a first transistor (303), a second transistor (304), a third transistor (305), a fourth transistor (306), a fifth transistor (307) and a sixth transistor (308); The gate of the first transistor (303) and the gate of the second transistor (304) are used to receive a pair of logically inverted digital control signals; The source of the first transistor (303) and the source of the second transistor (304) are grounded; The gate of the third transistor (305) and the gate of the fourth transistor (306) are connected together to serve as a first input terminal of the first amplifying unit; The gate of the fifth transistor (307) and the gate of the sixth transistor (308) are connected together to serve as a second input terminal of the first amplifying unit; The source of the third transistor (305) and the source of the sixth transistor (308) are connected together, and the drain of the second transistor (304) is connected between the two; The source of the fourth transistor (306) and the source of the fifth transistor (307) are connected together, and the drain of the first transistor (303) is connected between the two; The drain of the third transistor (305) and the drain of the fifth transistor (307) are connected together as the first output terminal of the first amplifying unit, The drain of the fourth transistor (306) and the drain of the sixth transistor (308) are connected together as a second output terminal of the first amplifying unit.

7. The ultra-wideband vector modulation phase shifter according to claim 1, wherein: The Q-path amplitude adjustment circuit (400) comprises a sixth capacitor (401), a second transformer (402), and a plurality of parallel second amplification units; The first end of the sixth capacitor (401) is connected to the first end of the primary coil of the second transformer (402), and a ninth terminal is led out from the connection between the two. The second end of the sixth capacitor (401) is connected to the second end of the primary coil of the second transformer (402), and a tenth terminal is led out from the connection between the two. The ninth terminal and the tenth terminal serve as input ends of the Q-path amplitude adjustment circuit (400) and are connected to the quadrature error correction circuit (200). The center tap of the secondary coil of the second transformer (402) is used to access a corresponding DC bias voltage; A first end of the secondary coil of the second transformer (402) is connected to a first input end of the second amplifying unit, and a second end of the secondary coil of the second transformer (402) is connected to a second input end of the second amplifying unit; The first output ends of the plurality of second amplifying units are connected in parallel to lead out an eleventh wiring terminal, and the second output ends of the plurality of second amplifying units are connected in parallel to lead out a twelfth wiring terminal. The eleventh wiring terminal and the twelfth wiring terminal serve as output ends of the Q-path amplitude adjustment circuit (400) and are connected to the orthogonal signal synthesis circuit (500).

8. The ultra-wideband vector modulation phase shifter according to claim 7, wherein: The second amplifying unit includes a seventh transistor (403), an eighth transistor (404), a ninth transistor (405), a tenth transistor (406), an eleventh transistor (407) and a twelfth transistor (408); The gate of the seventh transistor (403) and the gate of the eighth transistor (404) are used to receive a pair of logically inverted digital control signals; The source of the seventh transistor (403) and the source of the eighth transistor (404) are grounded; The gate of the ninth transistor (405) and the gate of the tenth transistor (406) are connected together as a first input terminal of the second amplifying unit; The gate of the eleventh transistor (407) and the gate of the twelfth transistor (408) are connected together to serve as a second input terminal of the second amplifying unit; The source of the ninth transistor (405) and the source of the twelfth transistor (408) are connected together, and the drain of the eighth transistor (404) is connected between the two; The source of the tenth transistor (406) and the source of the eleventh transistor (407) are connected together, and the drain of the seventh transistor (403) is connected between the two; The drain of the ninth transistor (405) and the drain of the eleventh transistor (407) are connected together as the first output terminal of the second amplifying unit, The drain of the tenth transistor (406) and the drain of the twelfth transistor (408) are connected together as a second output terminal of the second amplifying unit.

9. The ultra-wideband vector modulation phase shifter according to claim 1, wherein: The orthogonal signal synthesis circuit (500) comprises a seventh differential trace (501), an eighth differential trace (502), a third transformer (503) and a seventh capacitor (504); The first end and the second end of the seventh differential trace (501) serve as a first set of input ends of the orthogonal signal synthesis circuit (500), and are connected to the output end of the Q-path amplitude adjustment circuit (400); The first end of the seventh differential line (501) is connected to the first end of the primary coil of the third transformer (503) via its third end, and the second end of the seventh differential line (501) is connected to the second end of the primary coil of the third transformer (503) via its fourth end; The first end and the second end of the eighth differential trace (502) serve as a second set of input ends of the orthogonal signal synthesis circuit (500), and are connected to the output end of the I-channel amplitude adjustment circuit (300); The first end of the eighth differential line (502) is connected to the second end of the primary coil of the third transformer (503) via its third end, and the second end of the eighth differential line (502) is connected to the first end of the primary coil of the third transformer (503) via its fourth end; The center tap of the primary coil of the third transformer (503) is used to connect to the power supply voltage; The first end of the seventh capacitor (504) is connected to the first end of the secondary coil of the third transformer (503), and a thirteenth terminal is led out from the connection between the two. The second end of the seventh capacitor (504) is connected to the second end of the secondary coil of the third transformer (503), and a fourteenth terminal is led out from the connection between the two. The thirteenth terminal and the fourteenth terminal serve as output terminals of the orthogonal signal synthesis circuit (500) and are used to connect to a subsequent circuit.

10. A phased array system, characterized in that: include: The ultra-wideband vector modulation phase shifter according to any one of claims 1 to 9.

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