Analog Adaptive Three-Tap Decision Feedback Equalizer Circuit in High-Speed ​​SerDes

Abstract

This invention provides an analog adaptive three-tap decision feedback equalizer circuit for high-speed SerDes, which splits the input signal into three paths, reducing the frequency. Compared to full-rate decision feedback equalizers, this invention reduces timing requirements and the design complexity of the corresponding phase-locked loop (PLL) providing the clock, making it applicable to higher data transmission rates. Furthermore, the analog adaptive loop allows for appropriate adjustment of the multiplier tap coefficients, more effectively eliminating inter-symbol interference. Compared to adaptive circuits in mixed-signal circuits that require counters and DACs, this invention has lower design complexity, better convergence, and meets the requirements of high-speed transmission.

Description

Technical Field

[0001] This invention belongs to the field of circuit design technology in communication systems, specifically relating to an analog adaptive three-tap decision feedback equalizer circuit in high-speed SerDes. Background Technology

[0002] The transmission characteristics of a communication channel are non-ideal. Signals transmitted through the channel are distorted by noise, high-frequency loss, reflection, crosstalk, and other factors. The distorted symbol signal will exhibit delay, broadening, and tailing in the time domain. These extensions will superimpose onto adjacent symbols, forming inter-symbol interference (ISI). The time-domain expression of the signal affected by ISI is:

[0003]

[0004] This refers to the leading index component of inter-symbol interference (ISI), also known as pre-symbol interference. This refers to the suffix component of the delayed inter-symbol interference (ISI). Excessive ISI can easily lead to misjudgments and a high bit error rate (BER). Especially when interference is strong, each symbol will have a long trailing effect, and multiple suffix components can overlap, further increasing ISI. To reduce the BER, the ISI needs to be reduced sufficiently, ideally making the suffix component of each ISI symbol zero at the sampling decision time. This is the fundamental principle behind decision feedback equalizers (DFEs) for ISI cancellation.

[0005] Decision feedback equalizers (DFEs) are commonly used in serial-to-deserialization (SerDes) systems to eliminate inter-symbol interference (ISI). A DFE is a nonlinear equalization technique; its structure is equivalent to an FIR filter with an added feedback loop. The DFE sets appropriate weighting coefficients based on the ISI generated by the current symbol for subsequent symbols, using negative feedback to eliminate ISI. From a circuit operation perspective, the sampled data is delayed, multiplied by the corresponding weighting coefficient, and subtracted from the corresponding symbol to eliminate the post-stamp component, thus achieving the goal of eliminating ISI. Because the DFE uses a sampler, and the sampler's output signal is a digital signal that does not carry noise, the DFE also has the advantage of not amplifying noise, thereby improving the signal-to-noise ratio.

[0006] Common full-rate DFE structures include Figure 1 As shown, it consists of a sampling decision unit and a feedback filter network. Figure 1 In the middle diagram, d(n) represents the original input signal. e(n) represents the equalized signal. The adder in the diagram sums the input signal and the sampled and weighted signal. The slicer is the reason for the nonlinearity of the DFE. It samples and decides on the equalized signal to obtain the rail-to-rail signal, eliminating the original noise. Simultaneously, the sampled signal is delayed and multiplied by a suitable coefficient (C1, C2, ..., Ck) to obtain the corresponding tap coefficient. This coefficient is then subtracted from the initial input signal to eliminate the post-stamp component. The essence of the DFE is to remove the decided, delayed, and weighted signal from the existing data signal, that is, to eliminate the post-stamp component in the target data by setting appropriate weights, thus achieving data recovery. Its functional expression is:

[0007]

[0008] The number of stub components to be eliminated depends on the number of taps selected. From this perspective, more taps are better. However, in practice, many factors must be considered, such as power consumption and whether the delay meets the requirements. Generally, the mutual influence between symbols that are far apart is small and can be ignored, so an excessive number of taps is meaningless. At the same time, each unit in the circuit introduces a non-ideal delay. When the total delay is greater than the width of one symbol, it not only fails to effectively eliminate inter-symbol interference (ISI) but also introduces new ISI. Too many taps also lead to unnecessary power consumption increases. Therefore, the number of taps and the tap coefficients are generally set according to the actual tail size and length of the data. As can be seen from the above expression, DFE can only eliminate the stub component in ISI, so it is generally not used alone in the circuit.

[0009] Existing patent document (CN 2016111401828) describes an analog decision feedback equalizer circuit for high-speed SerDes, which adopts a full-rate decision feedback equalizer structure. This patent includes a delay unit, a multiplier, and a coefficient update circuit. The delay unit and multiplier are analog delay units and analog multipliers. The analog delay unit implements signal delay; the analog multiplier implements multiplication of coefficients with the output signal of the analog delay unit; the output of the analog multiplier is achieved through current summation. Since a full-rate decision feedback equalizer requires each delay unit to introduce a delay of one symbol length, if the delay time is controlled by a clock, the pressure on the clock becomes too great as the data transmission rate increases, making it difficult to meet the requirements of high-rate data transmission in SerDes. When the rate reaches GHz or higher, the full-rate decision feedback equalizer often cannot effectively eliminate the post-symbol component of inter-symbol interference (ISI) and may even introduce new interference, causing bit errors, making it difficult to meet the requirement of effectively eliminating ISI.

[0010] This paper describes a high-speed decision feedback equalizer design based on 0.18μm CMOS technology. The design employs a mixed-signal adaptive structure to achieve adaptive functionality. The module uses a sensitive amplifier to detect the input equalization signal and convert it into the corresponding logic level. Then, a counter counts and processes the equalization signal, and the tap coefficient values ​​stored in the counter are input to a digital-to-analog converter (DAC) to convert it into a corresponding current, ultimately updating the tap coefficients. Because the digital adaptive loop requires channel estimation and equalization parameter updates, these calculations often involve high computational complexity, which can impact system performance and real-time performance, especially in high-speed data transmission scenarios. As data transmission rates increase, the design requirements for the counter and DAC in the circuit also increase, potentially introducing higher power consumption. Summary of the Invention

[0011] To address the aforementioned problems in the prior art, this invention provides an analog adaptive three-tap decision feedback equalizer circuit for high-speed SerDes. The technical problem to be solved by this invention is achieved through the following technical solution:

[0012] This invention provides an analog adaptive three-tap decision feedback equalizer circuit for high-speed SerDes, comprising: 3 multipliers, 3 samplers, 3 cascaded latches, a multiplexer, and an analog adaptive loop; each cascaded latch is composed of two latches connected in series.

[0013] In this configuration, each path's multiplier, sampler, and cascaded latch are connected sequentially. The output of each cascaded latch is connected to the input of the multiplexer, which outputs a result. The first sampler is controlled by a first clock, and its output feedback is connected to the input of the second multiplier. The second sampler is controlled by a second clock, and its output feedback is connected to the input of the third multiplier. The third sampler is controlled by a third clock, and its output feedback is connected to the input of the first multiplier. The first latch in the first cascaded latch is controlled by a second clock, and its output feedback is connected to the input of the third multiplier. The first latch in the second cascaded latch is controlled by a third clock, and its output is connected to the input of the first multiplier. The second latch in the third cascaded latch is controlled by a first clock, and its output is connected to the input of the first multiplier. The second latch in the third cascaded latch is controlled by a first clock, and its output is connected to the input of the second multiplier. The second latch in the third cascaded latch is controlled by a second clock, and its output is connected to the input of the third multiplier. The input of the analog adaptive loop is connected to the output of each multiplier.

[0014] Beneficial effects:

[0015] The analog adaptive three-tap decision feedback equalizer circuit for high-speed SerDes provided by this invention splits the input signal into three paths, reducing the frequency. Compared to a full-rate decision feedback equalizer, it reduces the timing requirements and the design difficulty of the corresponding phase-locked loop providing the clock, making it applicable to higher data transmission rates. Furthermore, the analog adaptive loop allows for appropriate adjustment of the tap coefficients of the multiplier, more effectively eliminating inter-symbol interference. Compared to the adaptive circuits in mixed-signal circuits that require counters and DAC circuits, this invention has lower design difficulty, better convergence, and can meet the requirements of high-speed transmission.

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a full-rate decision feedback equalizer in the prior art;

[0018] Figure 2 This is a schematic diagram of the analog adaptive three-tap decision feedback equalizer circuit in the high-speed SerDes provided by the present invention;

[0019] Figure 3 This is a timing diagram of one-third rate DFE input and sampling data under ideal conditions provided by the present invention;

[0020] Figure 4 This is a structural diagram of the simulated adaptive circuit provided by the present invention. Detailed Implementation

[0021] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0022] Before introducing the present invention, we will first introduce the origin of the technical concept of the present invention.

[0023] To address the signal attenuation issues caused by changes in channel parameters and other factors such as environmental influences in existing technologies, an adaptive module is needed. The adaptive module of a decision feedback equalizer dynamically adjusts the equalizer parameters based on received data and feedback information to adapt to changes in channel conditions, thereby improving system performance and stability. Specifically, the adaptive module of a decision feedback equalizer can achieve the following functions:

[0024] 1. Channel estimation: The adaptive module can estimate the channel based on the received signal and feedback information to obtain the current channel state.

[0025] 2. Calculate equalizer parameters: Based on the current channel state, the adaptive module can calculate appropriate equalizer parameters to minimize channel distortion and noise, thereby improving system performance and stability.

[0026] 3. Adjust equalizer parameters: The adaptive module can dynamically adjust the equalizer parameters based on the calculated parameters to adapt to changes in channel conditions.

[0027] 4. Monitor equalizer performance: The adaptive module can monitor the equalizer performance in order to detect problems in a timely manner and take appropriate measures.

[0028] In summary, the decision feedback equalizer adaptive module is a very important module, as it can help the system adapt to changes in the channel and improve the system's performance and stability.

[0029] The following section first introduces the specific structure of an analog adaptive three-tap decision feedback equalizer circuit in a high-speed SerDes system according to the present invention.

[0030] refer to Figure 2 The present invention provides an analog adaptive three-tap decision feedback equalizer circuit in high-speed SerDes, comprising: 3 multipliers, 3 samplers, 3 cascaded latches, a multiplexer, and an analog adaptive loop; each cascaded latch is composed of two latches connected in series.

[0031] In this configuration, each path's multiplier, sampler, and cascaded latch are connected sequentially. The output of each cascaded latch is connected to the input of the multiplexer, which outputs a result. The first sampler is controlled by a first clock, and its output feedback is connected to the input of the second multiplier. The second sampler is controlled by a second clock, and its output feedback is connected to the input of the third multiplier. The third sampler is controlled by a third clock, and its output feedback is connected to the input of the first multiplier. The first latch in the first cascaded latch is controlled by a second clock, and its output feedback is connected to the input of the third multiplier. The first latch in the second cascaded latch is controlled by a third clock, and its output is connected to the input of the first multiplier. The second latch in the third cascaded latch is controlled by a first clock, and its output is connected to the input of the first multiplier. The second latch in the third cascaded latch is controlled by a first clock, and its output is connected to the input of the second multiplier. The second latch in the third cascaded latch is controlled by a second clock, and its output is connected to the input of the third multiplier. The input of the analog adaptive loop is connected to the output of each multiplier.

[0032] This invention employs a three-tap decision feedback equalizer structure. A clock-controlled sampler divides the input data into three channels with frequencies reduced to one-third of the original. A latch introduces a delay of a fixed symbol length. A negative feedback structure multiplies the output data of the sampler and latch by a certain weighting coefficient and subtracts it from the original input signal. The weighting coefficients are adjusted according to the magnitude of the inter-symbol interference (ISI), effectively eliminating the three symbol post-index components. Furthermore, this invention introduces an analog adaptive loop and implements a symbol-to-symbol least mean square algorithm to detect and process the data. Finally, a convergence value is output to adjust the tap coefficients, further enhancing the elimination of symbol post-index components.

[0033] Combination Figure 2 and Figure 3 The following describes the working process of each component in the analog adaptive three-tap decision feedback equalizer circuit of the high-speed SerDes of this invention.

[0034] Each multiplier uses tap coefficients to multiply the feedback signal and the original input signal to obtain an equalized signal, which is then output to the analog adaptive loop and the corresponding sampler.

[0035] Each sampler is controlled by its own clock to sample the equalization signal to obtain a sampled signal, and feeds the sampled signal back to the corresponding multiplier and cascaded latch.

[0036] The first latch of each channel is controlled by its own clock to delay the sampled signal and feed it back to the corresponding multiplier and the second latch.

[0037] The second latch of each channel is controlled by its own clock to delay the delayed signal and feed it back to the multiplexer and the corresponding multiplier.

[0038] The multiplexer selects and outputs the signal from the first latch;

[0039] The analog adaptive circuit determines the tap coefficients of the multiplier based on the input equalization signal, and generates a voltage signal based on the tap coefficients to feed back to the first multiplier.

[0040] The working principle of each component in the analog adaptive three-tap decision feedback equalizer circuit of the high-speed SerDes of this invention is described in detail below.

[0041] Combination Figure 2 and Figure 3 Each sampler is controlled by its own clock. It completes data sampling on the rising edge of the clock, holds the data when the clock is low, and outputs a rail-to-rail full-swing signal to the next stage latch.

[0042] It's worth noting that due to the high data transmission rate, the requirements for the sampler's sampling speed and delay time are high. Generally, a sampler with a dynamic comparator structure is used to achieve correct data sampling while introducing minimal delay. The sampler in this paper is controlled by an external clock, completing data sampling on the rising edge of the clock and holding the data when the clock is low. Finally, it outputs a rail-to-rail full-swing signal, which is input to the next stage latch.

[0043] Combination Figure 2 and Figure 3 The cascaded latch is controlled by an external clock to complete data sampling on the rising edge of the clock and to hold the data when the clock is low.

[0044] It is worth noting that the latch is also controlled by an external clock to complete data sampling on the rising edge of the clock and to hold the data when the clock is low. Since the latch has high requirements for signal swing, it is connected after the rail-to-rail output sampler.

[0045] Combination Figure 2 and Figure 3 The multiplexer adopts a 3:1 multiplexer structure based on current-mode logic; the multiplexer consists of three cross-coupled differential pairs; the multiplexer is controlled by a square wave signal with a duty cycle of one-third and a period identical to the clock control of the three samplers; when the square wave signal is high, the multiplexer selects the corresponding channel and outputs the corresponding data, and integrates the three outputs into one output.

[0046] Combination Figure 2 and Figure 3 Each multiplier uses a current-mode structure to multiply the feedback signal with the corresponding tap coefficient and calculate the sum; the sum is subtracted from the original input signal to obtain the equalized signal.

[0047] The function of a current-mode multiplier is to multiply the feedback signal by the corresponding tap coefficients and subtract the sum of these weighted values ​​from the currently received signal with inter-symbol interference (the original input signal). The circuit first implements the multiplication function through voltage-current transformation, and then adds the currents of the three branches to achieve the addition function.

[0048] Ideally, the input data, sampling clock, and sampling data timing should be... Figure 3As shown, the overall system function is achieved as follows: After sampling by the sampler, the input data is divided into three paths. A latch then introduces a delay of one symbol length and stores the data. Next, the output data from each sampler and latch is multiplied by the corresponding weighting coefficient and subtracted from the original input data to eliminate the influence of the three postscript components of the corresponding symbol. The weighted data, after being added to the input data, is the output data of each of the three multipliers, which is the equalized signal output by the three multipliers, expressed as:

[0049] D1=Din-C1*D31-C2*D22-C3*D13;

[0050] D2=Din-C1*D11-C2*D32-C3*D23;

[0051] D3=Din-C1*D21-C2*D12-C3*D33;

[0052] Where C1, C2 and C3 all represent tap coefficients, Din represents the original input signal, and Dij represents the output signal of the j-th device in the i-th channel; j = 1 indicates a sampler, j = 2 indicates the first latch, and j = 3 indicates the third latch.

[0053] The processed data D1, D2, and D3 are sent to the analog adaptive circuit. Based on the input data, the adaptive module adjusts the first tap coefficient and returns the appropriate tap coefficient C1 to the main DFE module. Finally, the multiplexer (MUX) integrates the adjusted three data streams into one data stream and outputs it.

[0054] Non-ideal delays must be considered: Because the data transmission rate is very high, with periods of tens or hundreds of picoseconds, the setup time of the sampler and latch itself must be taken into account. Whether non-ideal delays in the feedback loop will introduce new interference must also be considered. If the data required to eliminate inter-symbol interference (ISI) has not returned by the time a sample is reached, it means that new ISI has been introduced. Therefore, if we assume the sampler's setup time is t... slicer The latch setup time is t. latch The delay introduced by the feedback loop is t. fb If it is required that no new inter-symbol interference is introduced, then the following must be satisfied:

[0055] t slicer +t fb <1UI;

[0056] t latch +t fb <1UI;

[0057] The simulated adaptive loop is implemented based on the symbol-to-symbol least mean square (SS-LMS) algorithm. The least mean square algorithm is based on the steepest gradient descent method and the minimum mean square error (MMSE) criterion. Its core idea is to compare the calculated value with the expected value, and by adjusting the weighting coefficients of each tap, make the calculated value approach the expected value as quickly as possible along the negative gradient direction, achieving equilibrium. After symbolizing and simplifying the error signal into the SS-LMS algorithm, the expression is: The simulated adaptive loop uses the symbol-to-symbol least mean square algorithm and determines the tap coefficients required for the multiplier based on any input equilibrium signal, expressed as:

[0058] C(n+1)=C(n)+2μ·sign[e(n)]·sign[x(n)];

[0059] Where C(n) is the tap coefficient at time n, μ is the convergence factor of the algorithm, x(n) represents the equalization signal of any path, and e(n) represents the error signal between the equalization signal and the desired signal.

[0060] To transform the tap coefficients into a form that can be implemented using analog circuits, we integrate both sides to transform the above expression into:

[0061] The analog adaptive circuit achieves C(n) by generating a voltage signal, as expressed in:

[0062]

[0063] Where T represents the sampling period.

[0064] Analog adaptive circuit structure designed from the above formula Figure 4 As shown, the analog adaptive loop includes a multiplier, an integrator, a sampling module, and a subtractor; wherein, the input terminals of the multiplier and the sampling module are both input with any equalization signal, the input of the subtractor is connected to the output of the sampling module and the equalization signal, the output of the subtractor is connected to the input of the multiplier, the output of the multiplier is connected to the input of the integrator, and the integrator outputs tap coefficients.

[0065] x(n) is the data input from the main circuit of the DFE to the analog adaptive section. After being sampled by the sampler, the signal is subtracted from x(n) to obtain the error signal e(n). The error signal e(n) is multiplied by x(n) and integrated to obtain the updated tap coefficient C(n), which is then returned to the main circuit of the DFE. The adaptive implementation implemented by the analog structure has good convergence and is suitable for high-speed paths.

[0066] The analog adaptive three-tap decision feedback equalizer circuit for high-speed SerDes provided by this invention splits the input signal into three paths, reducing the frequency. Compared to a full-rate decision feedback equalizer, it reduces the timing requirements and the design difficulty of the corresponding phase-locked loop providing the clock, making it applicable to higher data transmission rates. Furthermore, the analog adaptive loop allows for appropriate adjustment of the tap coefficients of the multiplier, more effectively eliminating inter-symbol interference. Compared to the adaptive circuits in mixed-signal circuits that require counters and DAC circuits, this invention has lower design difficulty, better convergence, and can meet the requirements of high-speed transmission.

[0067] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0068] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0069] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An analog adaptive three-tap decision feedback equalizer circuit for high-speed SerDes, characterized in that, include: It consists of 3 multipliers, 3 samplers, 3 cascaded latches, a multiplexer, and an analog adaptive loop; each cascaded latch is composed of two latches connected in series. In this configuration, each path's multiplier, sampler, and cascaded latch are connected sequentially. The output of each cascaded latch is connected to the input of the multiplexer, which outputs a result. The first sampler is controlled by a first clock, and its output feedback is connected to the input of the second multiplier. The second sampler is controlled by a second clock, and its output feedback is connected to the input of the third multiplier. The third sampler is controlled by a third clock, and its output feedback is connected to the input of the first multiplier. The first latch in the first cascaded latch is controlled by a second clock, and its output feedback is connected to the input of the third multiplier. The first latch in the second cascaded latch is controlled by a third clock, and its output is connected to the input of the first multiplier. The second latch in the third cascaded latch is controlled by a first clock, and its output is connected to the input of the first multiplier. The second latch in the third cascaded latch is controlled by a first clock, and its output is connected to the input of the second multiplier. The second latch in the third cascaded latch is controlled by a second clock, and its output is connected to the input of the third multiplier. The input of the analog adaptive loop is connected to the output of each multiplier. Each multiplier uses tap coefficients to multiply the feedback signal and the original input signal to obtain an equalized signal, which is then output to the analog adaptive loop and the corresponding sampler. Each sampler is controlled by its own clock to sample the equalization signal to obtain a sampled signal, and feeds the sampled signal back to the corresponding multiplier and cascaded latch. The first latch of each channel is controlled by its own clock to delay the sampled signal and feed it back to the corresponding multiplier and the second latch. The second latch of each channel is controlled by its own clock to delay the delayed signal and feed it back to the multiplexer and the corresponding multiplier. The multiplexer selects and outputs the signal from the first latch; The analog adaptive loop determines the tap coefficients of the multiplier based on the input equalization signal, and generates a voltage signal based on the tap coefficients to feed back to the first multiplier. The equalization signal output from the 3-way multiplier is represented as follows: D1=Din-C1*D31-C2*D22-C3*D13; D2=Din-C1*D11-C2*D32-C3*D23; D3=Din-C1*D21-C2*D12-C3*D33; Where C1, C2, and C3 all represent tap coefficients, Din represents the original input signal, and Dij represents the output signal of the j-th device in the i-th channel; j = 1 indicates a sampler, j = 2 indicates the first latch, and j = 3 indicates the third latch; The analog adaptive loop uses a symbol-to-symbol least mean square algorithm and determines the tap coefficients required by the multiplier based on any input equalization signal, as expressed as: C(n+1)=C(n)+2μ·sign[e(n)]·sign[x(n)]; Where C(n) is the tap coefficient at time n, μ is the convergence factor of the algorithm, x(n) represents the equalization signal of any path, and e(n) represents the error signal between the equalization signal and the desired signal. The analog adaptive circuit generates a voltage signal to achieve C(n), which is represented as follows: Where T represents the sampling period; The analog adaptive loop includes a multiplier, an integrator, a sampling module, and a subtractor. The input terminals of the multiplier and the sampling module are both connected to the equalization signal of any channel. The input of the subtractor is connected to the output of the sampling module and the equalization signal. The output of the subtractor is connected to the input of the multiplier. The output of the multiplier is connected to the input of the integrator. The integrator outputs tap coefficients.

2. The analog adaptive three-tap decision feedback equalizer circuit in high-speed SerDes according to claim 1, characterized in that, Each sampler is controlled by its own clock. It completes data sampling on the rising edge of the clock, holds the data when the clock is low, and outputs a rail-to-rail full-swing signal to the next stage latch.

3. The analog adaptive three-tap decision feedback equalizer circuit in high-speed SerDes according to claim 1, characterized in that, The cascaded latch is controlled by an external clock to complete data sampling on the rising edge of the clock and to hold the data when the clock is low.

4. The analog adaptive three-tap decision feedback equalizer circuit in high-speed SerDes according to claim 1, characterized in that, The multiplexer adopts a 3:1 multiplexer structure based on current-mode logic; the multiplexer consists of three cross-coupled differential pairs; the multiplexer is controlled by a square wave signal with a duty cycle of one-third and a period identical to the clock control of the three samplers; when the square wave signal is high, the multiplexer selects the corresponding channel and outputs the corresponding data, and integrates the three outputs into one output.

5. The analog adaptive three-tap decision feedback equalizer circuit in high-speed SerDes according to claim 1, characterized in that, Each multiplier uses a current-mode structure to multiply the feedback signal with the corresponding tap coefficient and calculate the sum; the sum is subtracted from the original input signal to obtain the equalized signal.

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