A verification device, method and equipment for a chip MAC layer half-duplex interface

Abstract

The embodiment of the present application provides a kind of chip MAC layer half duplex interface verification device, method and equipment, by sending first excitation message to interface, the message receiving function of interface is verified, the device comprises: signal sending module, for starting to set up CRS signal when starting to send first excitation message and falling CRS signal when ending to send first excitation message, and set up COL signal in one of the following positions: before CRS signal starts to set up, between the position of CRS signal start to set up and fall, after CRS signal falls;Interface verification module, for sending first excitation message to interface until its sending is completed, and the received message of interface is collected;Message comparison module, for comparing first excitation message and received message.The technical scheme of the present application verifies various timing combination situations by using a set of devices by the method of not stopping flow when verifying the message receiving function of chip interface, simplifies verification device, and improves verification efficiency.

Description

Technical Field

[0001] This invention relates to the field of digital communication, and in particular to a verification device, method and equipment for a chip MAC layer half-duplex interface. Background Technology

[0002] Currently, the verification method for Ethernet chip interface modules is a single-function black-box verification method that relies on determining whether the chip's response signal matches the expected signal. This method has limited control, only allowing modification of the configuration register to determine whether the chip successfully entered half-duplex mode. Therefore, a method needs to be developed to further verify the correctness of its behavior in half-duplex mode. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a verification apparatus, method, and device for a chip MAC layer half-duplex interface. The technical solution of the present invention verifies the message reception function of the chip interface using a single device with a non-stop method, verifying various timing combinations, simplifying the verification apparatus and improving verification efficiency. Furthermore, by actively activating the COL signal, it eliminates the need to consider the timing combinations of the chip MAC layer half-duplex interface's transmit and receive signals, further simplifying the verification apparatus.

[0004] In a first aspect, embodiments of the present invention provide a verification device for a half-duplex interface of a chip MAC layer, used to verify the message receiving function of the interface by sending a first stimulus message to the interface, comprising: a signal transmission module, used to start activating a CRS signal when the first stimulus message is started and deactivating the CRS signal when the first stimulus message is ended, and to activate a COL signal at one of the following positions: before the CRS signal is activated, between the activation and deactivation positions of the CRS signal, and after the deactivation position of the CRS signal; an interface verification module, used to send the first stimulus message to the interface until its transmission is completed, and to collect the received messages of the interface; and a message comparison module, used to compare the first stimulus message and the received messages to verify and test the message receiving function.

[0005] Therefore, when verifying the message receiving function of the chip's MAC layer half-duplex interface, messages are continuously sent to the chip's MAC layer half-duplex interface without interruption of power, regardless of the timing combination of the CRS and COL signals. This allows for verification of various timing combinations using a single device, eliminating the need to select different devices according to specifications, thus simplifying the verification process and improving efficiency. Furthermore, by actively activating the COL signal, the timing of the chip's MAC layer half-duplex interface's transmit and receive signals is eliminated, further simplifying the verification process.

[0006] In one possible implementation of the first aspect, when verifying the message transmission function of the interface by sending a second stimulus message to the sending unit of the interface, the signal sending module is configured to set the COL signal at one of the following locations: before the start position of the second stimulus message, between the start position of the second stimulus message and a set position, between the set position and the end position of the second stimulus message, and after the end position of the second stimulus message, wherein the set position is obtained according to the 802.3 protocol; the interface verification module is further configured to send the second stimulus message to the sending unit of the interface, causing the interface to send messages outward, and to collect all sent messages of the interface; the message comparison module is further configured to compare the second stimulus message and the sent messages to verify and test the message transmission function.

[0007] The above demonstrates the message transmission function of the chip's MAC layer half-duplex interface under various timing combinations of COL signals and CRS through the interface verification module.

[0008] In one possible implementation of the first aspect, when the COL signal is set between the start position of the second stimulus message and the set position, the set position of the COL signal includes each byte between the start position of the second stimulus message and the set position, and the duration is 1 clock cycle; when the COL signal is set between the set position and the end position of the second stimulus message, the set position of the COL signal includes: a position randomly selected from the set position to the end position of the second stimulus message for a set number of bytes.

[0009] As described above, the COL signal timing covers the verification of the message transmission function of the chip's MAC layer half-duplex interface under two scenarios of collision. Simultaneously, by actively activating the COL signal at the corresponding byte position of the second stimulus message, scenarios where the timing of the received and transmitted messages of the chip's MAC layer half-duplex interface is difficult to precisely align to the byte level are avoided, thereby reducing the workload of verification.

[0010] In one possible implementation of the first aspect, when the COL signal is set between the start position of the second stimulus message and the set position, the message comparison module compares the second stimulus message and the transmitted message, specifically for comparing whether the second stimulus message is consistent with the last transmitted message, and also for verifying whether the previous transmitted message was a discarded message.

[0011] In summary, the device was used to verify whether the message sending function of the chip's MAC layer half-duplex interface met the specification requirements when a message transmission conflict occurred between the start position of the second excitation message and the set position.

[0012] In one possible implementation of the first aspect, when the COL signal is set between the set position and the end position of the second excitation message, the message comparison module compares the second excitation message and the transmitted message, specifically to confirm whether the transmitted message is a discarded message.

[0013] Therefore, by using the above device, when a message transmission conflict occurs between the set position and the end position of the second excitation message, it was verified whether the message transmission function of the half-duplex interface of the chip's MAC layer meets the specification requirements.

[0014] In one possible implementation of the first aspect, it is built based on a UVM environment.

[0015] As shown above, devices built on a UVM environment are flexibly configurable and possess high scalability and versatility.

[0016] Secondly, embodiments of the present invention provide a verification method for a half-duplex interface of a chip MAC layer, which verifies the message receiving function of the interface by sending a first stimulus message to the interface, including: sending a first stimulus message to the interface until the transmission is completed, and collecting the received message of the interface; starting to set up the CRS signal when the first stimulus message is sent and dropping the CRS signal when the first stimulus message is dropped, and setting up the COL signal at one of the following positions: before the CRS signal is set up, between the position where the CRS signal is set up and the position where the CRS signal is dropped, and after the position where the CRS signal is dropped; comparing the first stimulus message and the received message to verify and test the message receiving function.

[0017] Therefore, when verifying the message receiving function of the chip's MAC layer half-duplex interface, messages are continuously sent to the chip's MAC layer half-duplex interface without interruption of power, regardless of the timing combination of the CRS and COL signals. This allows for verification of various timing combinations using a single device, eliminating the need to select different devices according to specifications, thus simplifying the verification process and improving efficiency. Furthermore, by actively activating the COL signal, the timing of the chip's MAC layer half-duplex interface's transmit and receive signals is eliminated, further simplifying the verification process.

[0018] In one possible implementation of the second aspect, the method further includes: sending a second stimulus message to the sending unit of the interface to cause the interface to send messages outward, and collecting all sent messages of the interface to verify the message sending function of the interface; setting the COL signal at one of the following locations: before the start position of the second stimulus message, between the start position of the second stimulus message and a set position, between the set position and the end position of the second stimulus message, and after the end position of the second stimulus message, wherein the set position is obtained according to the 802.3 protocol; comparing the second stimulus message and the sent messages to verify and test the message sending function.

[0019] The above method verifies the message transmission function of the chip's MAC layer half-duplex interface under various timing combinations of COL signals and CRS.

[0020] In one possible implementation of the second aspect, when the COL signal is set between the start position of the second stimulus message and the set position, the set position of the COL signal includes each byte between the start position of the second stimulus message and the set position, and the duration is 1 clock cycle; when the COL signal is set between the set position and the end position of the second stimulus message, the set position of the COL signal includes: a position randomly selected from the set position to the end position of the second stimulus message for a set number of bytes.

[0021] As described above, the COL signal timing covers the verification of the message transmission function of the chip's MAC layer half-duplex interface under two scenarios of collision. Simultaneously, by actively activating the COL signal at the corresponding byte position of the second stimulus message, scenarios where the timing of the received and transmitted messages of the chip's MAC layer half-duplex interface is difficult to precisely align to the byte level are avoided, thereby reducing the workload of verification.

[0022] In one possible implementation of the second aspect, when the COL signal is set between the start position of the second excitation message and the set position, the second excitation message and the transmitted message are compared, and the second excitation message is compared with the last transmitted message to confirm whether the previous transmitted message was a discarded message.

[0023] Based on the above method, when a message transmission conflict occurs between the start position of the second excitation message and the set position, it was verified whether the message transmission function of the chip's MAC layer half-duplex interface meets the specification requirements.

[0024] In one possible implementation of the second aspect, when the COL signal is set between the set position and the end position of the second excitation message, the message comparison module compares the second excitation message and the transmitted message, specifically to confirm whether the transmitted message is a discarded message.

[0025] Based on the above method, when a message transmission conflict occurs between the set position and the end position of the second excitation message, it was verified whether the message transmission function of the half-duplex interface of the chip's MAC layer meets the specification requirements.

[0026] In one possible implementation of the second aspect, the functionality of the half-duplex interface of the MAC layer of the chip is verified based on the UVM environment.

[0027] As shown above, the half-duplex interface of the MAC layer of the UVM environment verification chip can be flexibly configured and has high scalability and versatility.

[0028] Thirdly, embodiments of the present invention provide a computing device, including,

[0029] bus;

[0030] A communication interface, which is connected to the bus;

[0031] At least one processor connected to the bus; and

[0032] At least one memory is connected to the bus and stores program instructions that, when executed by the at least one processor, cause the at least one processor to perform any of the embodiments of the second aspect of the invention.

[0033] Fourthly, embodiments of the present invention provide a computer-readable storage medium having program instructions stored thereon, which, when executed by a computer, cause the computer to perform any of the embodiments described in the second aspect. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a first embodiment of the device for verifying a half-duplex interface of a chip MAC layer according to the present invention;

[0035] Figure 2 This is a schematic diagram of a second embodiment of the device for verifying a half-duplex interface of a chip MAC layer according to the present invention;

[0036] Figure 3 This is a flowchart illustrating a method for verifying a half-duplex interface at the MAC layer of a chip according to the present invention.

[0037] Figure 4 This is a flowchart illustrating the verification process of the receiving function of the chip MAC layer half-duplex interface in a second embodiment of the method for verifying the chip MAC layer half-duplex interface according to the present invention.

[0038] Figure 5 This is a flowchart illustrating the verification of the sending function of the chip MAC layer half-duplex interface in Embodiment 2 of the present invention.

[0039] Figure 6 This is a schematic diagram of the structure of the computing device according to various embodiments of the present invention. Detailed Implementation

[0040] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0041] In the following description, the terms “first, second, third, etc.” or module A, module B, module C, etc. are used only to distinguish similar objects or different embodiments and do not represent a specific ordering of objects. It is understood that a specific order or sequence may be interchanged where permitted so that the embodiments of the invention described herein can be implemented in an order other than that illustrated or described herein.

[0042] In the following description, the labels of the steps, such as S110, S120, etc., do not necessarily mean that the steps will be executed in this way. The order of the steps can be interchanged or executed simultaneously if permitted.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to limit the invention.

[0044] CRS signal: The transmit / receive indication signal of the MAC layer half-duplex interface. The CRS signal is set when the MAC layer half-duplex interface sends or receives messages.

[0045] COL signal: The transmit / receive conflict signal of the MAC layer half-duplex interface. The COL signal is set when the MAC layer half-duplex interface simultaneously sends and receives messages.

[0046] Start-up position and stop-down position: The start-up position is the time when a signal begins to be set to valid, and the stop-down position is the time when a signal begins to be set to invalid.

[0047] This invention provides a verification device, method, and apparatus for a chip MAC layer half-duplex interface. The method verifies the interface's message receiving function by sending a first stimulus message to the interface. The device includes: a signal transmission module, configured to start activating the CRS signal when the first stimulus message is sent and deactivate the CRS signal when the first stimulus message is sent, and to activate the COL signal at one of the following positions: before the CRS signal is activated, between the activation and deactivation positions, and after the deactivation position; an interface verification module, configured to send the first stimulus message to the interface until its transmission is complete, and to collect the received messages of the interface; and a message comparison module, configured to compare the first stimulus message and the received messages.

[0048] The technical solution of this invention is used to verify the function of the half-duplex interface of the MAC layer of a chip. When verifying the message receiving function of the chip interface, messages are continuously sent to the half-duplex interface of the MAC layer of the chip through a non-stop method under any timing combination of CRS signal and COL signal. Thus, a set of devices is used to verify various timing combinations, without the need to select different devices according to the specifications, which simplifies the verification device and improves the verification efficiency.

[0049] The embodiments of the present invention will now be described in conjunction with the accompanying drawings. First, in conjunction with... Figure 1 This invention introduces a verification device for a chip MAC layer half-duplex interface, embodiment one.

[0050] Figure 1 This invention illustrates a verification device for a chip MAC layer half-duplex interface according to the present invention. The device is used to verify the message receiving function of the chip MAC layer half-duplex interface by sending a first excitation message to the chip MAC layer half-duplex interface. The device includes a signal sending module 110, an interface verification module 120, and a message comparison module 130.

[0051] In all embodiments of the present invention, the chip MAC layer half-duplex interface is the half-duplex interface of the actual chip or the half-duplex interface corresponding to the chip verification environment.

[0052] The signal transmission module 110 is used to start setting up the CRS signal when the first excitation message is started and to drop the CRS signal when the first excitation message is dropped, and to set up the COL signal in one of the following positions: before the CRS signal is set up, between the position where the CRS signal is set up and the position where it drops, and after the position where the CRS signal drops.

[0053] The timing combination of the COL and CRS signals satisfies the full-scenario traversal requirements of the chip's MAC layer half-duplex interface, accurately and effectively covering various scenarios and avoiding inefficient random triggering methods.

[0054] To avoid overly complicated debugging and significant randomness, each embodiment of this invention employs an active activation of the COL signal, eliminating the need for verification based on the timing combinations of message transmission and reception at the chip's MAC layer half-duplex interface. Simultaneously, the results after a collision are simulated separately in both the TX and RX directions to verify whether the response signal output by the device under test to the COL signal meets expectations.

[0055] In some embodiments, when a verification device for a chip MAC layer half-duplex interface verifies its message transmission function by sending a second stimulus message to the sending unit of the chip MAC layer half-duplex interface, the signal sending module 110 is also used to set the COL signal in one of the following positions: before the start position of the second stimulus message, between the start position of the second stimulus message and the set position, between the set position and the end position of the second stimulus message, and after the end position of the second stimulus message. The set position is obtained according to the 802.3 protocol. For example, the set position specified by the 802.3 protocol is the 64th byte (hereinafter referred to as byte).

[0056] In some embodiments, when the COL signal is set between the start position of the second stimulus message and the set position, the set position of the COL signal includes each byte between the start position of the second stimulus message and the set position, and the duration is 1 clock cycle. By actively setting the COL signal according to the corresponding byte position of the second stimulus message, the scenario where the timing of the received and transmitted messages of the chip's MAC layer half-duplex interface is difficult to accurately align to the byte level is avoided, thereby reducing the workload of verification.

[0057] In some embodiments, when the COL signal is set between the set position and the second excitation message end position, the set position of the COL signal includes: a position randomly selected from the set position to the second excitation message end position for a set number of bytes, for example, the set number is 10.

[0058] The interface verification module 120 is used to send a first excitation message to the chip MAC layer half-duplex interface until the message receiving function is completed when verifying the message receiving function of the chip MAC layer half-duplex interface, and to collect the received messages of the chip MAC layer half-duplex interface.

[0059] Specifically, the interface verification module 120 and the signal transmission module 110 work in parallel. When the interface verification module 120 sends a first stimulus message to the chip MAC layer half-duplex interface instead of the actual scenario when the peer sends a message to the chip MAC layer half-duplex interface, the signal transmission module 110 sets up the CRS signal. The chip MAC layer half-duplex interface verifies the receiving function of the chip MAC layer half-duplex interface by receiving the received message obtained by receiving the first stimulus message.

[0060] Regardless of the positional relationship between the COL and CRS signals, during the duration of the CRS signal being activated, the interface verification module 120 continuously sends the first stimulus message to the chip MAC layer half-duplex interface and collects the messages received by the chip MAC layer half-duplex interface for relevant verification. This flow continues even when the COL signal is activated; this flow is the data stream sent by the interface verification module 120 to the chip MAC layer half-duplex interface. This verification method for the message receiver does not violate the protocol, because in this scenario, the protocol only specifies the message sender's pause behavior. Existing verification devices all adjust their verification methods according to this pause behavior, complicating the verification process.

[0061] Therefore, this embodiment does not require stopping the flow when the COL signal is activated according to the 802.3 protocol, nor does it require stopping the acquisition of received messages from the chip's MAC layer half-duplex interface when the COL signal is activated, nor does it require the message comparison module 130 to stop comparing messages when the COL signal is activated. A unified device is used to verify the message receiving function of the chip's MAC layer half-duplex interface for all time slot combinations of the COL signal and CRS signal.

[0062] In some embodiments, a verification device for a chip MAC layer half-duplex interface, embodiment one, further verifies the message transmission function of the chip MAC layer half-duplex interface by sending a second stimulus message to the chip MAC layer half-duplex interface. At this time, the interface verification module 120 is used to send the second stimulus message to the transmission unit of the chip MAC layer half-duplex interface, so that the chip MAC layer half-duplex interface sends messages outward. The signal transmission module 110 sets up the CRS signal at this time, and the interface verification module 120 is also used to collect the transmission messages of the chip MAC layer half-duplex interface, thereby comparing the second stimulus message and the transmission messages of the chip MAC layer half-duplex interface to verify the message transmission function of the chip MAC layer half-duplex interface.

[0063] In some embodiments, when the COL signal is set between the start position of the second excitation message and the set position, the interface verification module 120 continuously collects all transmitted messages of the chip MAC layer half-duplex interface when collecting the transmitted messages, including messages transmitted multiple times during the period. Among them, after the COL signal falls, the chip MAC layer half-duplex interface should retransmit the message after a random backoff time. The verification bit of the previously transmitted message is 0XAAAA...AAA, which is A, and it is a discarded message.

[0064] The message comparison module 130 is used to compare the first stimulus message and the received message from the MAC layer half-duplex interface to verify the message receiving function of the MAC layer half-duplex interface of the test chip.

[0065] Specifically, if the positional relationship between the COL signal and the CRS signal is one of the following: the COL signal falls before the CRS signal starts to rise, or the COL signal rises after the CRS signal falls, and the content of the received message from the chip's MAC layer half-duplex interface is consistent with the content of the first excitation message, then the message receiving function of the chip's MAC layer half-duplex interface is verified.

[0066] When the COL signal is between the CRS signal's start and stop positions, the comparison continues between the first excitation message and the received message from the chip's MAC layer half-duplex interface. Although in a real-world scenario, the peer-end transmitting interface of the chip's MAC layer half-duplex interface stops transmitting data at this point, continuing the comparison simplifies the verification device, eliminating the need to distinguish between different timing combinations.

[0067] In some embodiments, while verifying the message sending function of the chip MAC layer half-duplex interface, the message comparison module 130 is also used to compare the second stimulus message and the message sent by the chip MAC layer half-duplex interface received by the interface verification module to verify and test the message sending function of the MAC layer half-duplex interface.

[0068] In some embodiments for verifying the message transmission function of the chip MAC layer half-duplex interface, when the positional relationship between the COL signal and the CRS signal is one of the following: the COL signal falls before the CRS signal rises, or the COL signal rises after the CRS signal falls, and the content of the message sent by the chip MAC layer half-duplex interface received by the interface verification module is consistent with the content of the second excitation message, then the message transmission function of the chip MAC layer half-duplex interface is verified to be in the above positional relationship between the COL signal and the CRS signal.

[0069] In some embodiments for verifying the message transmission function of the chip MAC layer half-duplex interface, when the start position of the COL signal is between the start position of the second stimulus message and the set position, the message comparison module 130 compares the second stimulus message and the transmission message of the chip MAC layer half-duplex interface. Specifically, it is used to confirm whether the check bit of the transmission message of the chip MAC layer half-duplex interface before the COL signal falls is all A, i.e., whether it is a discarded message, and compare whether the second stimulus message is consistent with the last transmission message of the chip MAC layer half-duplex interface.

[0070] In some embodiments for verifying the message transmission function of the chip MAC layer half-duplex interface, when the start position of the COL signal is located between the set position and the end position of the second excitation message, the message comparison module 130 compares the second excitation message and the transmission message of the chip MAC layer half-duplex interface to specifically confirm whether the check bit of the transmission message of the chip MAC layer half-duplex interface is all A, i.e., whether it is a discarded message.

[0071] In summary, according to Embodiment 1 of a verification device for a half-duplex interface of a chip MAC layer, regardless of any of the following positional relationships between the COL signal and the CRS signal: the COL signal falls before the CRS signal rises, the COL signal is located between the CRS signal's rising and falling positions, or the COL signal rises after the CRS signal falls, a single device was used to verify various timing combinations in the message receiving function of the chip interface using a non-stop method. It also actively simulated the rising of the COL signal, simplifying the verification device and improving verification efficiency.

[0072] Embodiment 2 of a verification device for a chip MAC layer half-duplex interface inherits all the structures of Embodiment 1 of a verification device for a chip MAC layer half-duplex interface, has all its advantages, and adds verification of message sending function.

[0073] Embodiment 2 of a verification device for a chip MAC layer half-duplex interface is built on a UVM environment and is used to verify the chip MAC layer half-duplex interface in the chip implementation code. The device is flexibly configurable and has high scalability and versatility.

[0074] Figure 2 The following is a second embodiment of a verification device for a chip MAC layer half-duplex interface, which adds a second excitation message to the sending unit of the chip MAC layer half-duplex interface to verify the message sending function. The device includes a signal sending module 210, an interface verification module 220, and a message comparison module 230.

[0075] In addition to implementing the function of signal transmission module 110 in Embodiment 1 of a verification device for a chip MAC layer half-duplex interface, signal transmission module 210 is also used to set the COL signal in one of the following positions: before sending the second stimulus message, between the start position of the second stimulus message and the set position, between the set position and the end position of the second stimulus message, and after the end position of the second stimulus message, wherein the set position is obtained according to the 802.3 protocol.

[0076] In addition to implementing the functions of the interface verification module 120 in Embodiment 1 of a verification device for a chip MAC layer half-duplex interface, the interface verification module 220 is also used to send a second excitation message to the sending unit of the chip MAC layer half-duplex interface when verifying the message sending function of the chip MAC layer half-duplex interface, so that the chip MAC layer half-duplex interface sends messages outward. At this time, the signal sending module 210 sets up the CRS signal, and the interface verification module 220 is also used to collect all the sent messages of the chip MAC layer half-duplex interface.

[0077] In addition to implementing the functions of the message comparison module 130 in Embodiment 1 of a verification device for a chip MAC layer half-duplex interface, the message comparison module 230 is also used to compare the first excitation message and the received message from the MAC layer half-duplex interface to verify and test the message receiving function of the chip MAC layer half-duplex interface.

[0078] The following example uses the method of receiving messages in the RX direction or sending messages in the TX direction alone. The COL signal is actively set to simulate the simultaneous transmission of messages in both directions, which causes a collision. The working principle under various timing combinations is discussed by traversing the following three positional relationships between the COL signal and the CRS signal.

[0079] 1. When the COL signal falls to a position before the CRS signal starts to rise.

[0080] The duration of the CRS signal being set up exceeds a certain number of cycles (in this embodiment of the invention, one chip system cycle is 1 cycle). For example, the duration of the CRS signal being set up is at least 5 cycles. The time difference between the falling position of the COL signal and the starting position of the CRS signal includes at least the following values: less than a second set value, the second set value is less than 1 cycle, or it can be considered that the time difference between the falling position of the COL signal and the starting position of the CRS signal at least covers the case where the COL signal has just fallen and the CRS signal is immediately set up.

[0081] In this timing scenario, when verifying the message receiving function of the chip's MAC layer half-duplex interface in the RX direction, the first stimulus message is compared with the message received through the chip's MAC layer half-duplex interface. If the contents of the two messages are the same, then the message receiving function of the chip's MAC layer half-duplex interface in this timing scenario is verified as successful.

[0082] In this timing scenario, when verifying the message transmission function of the chip's MAC layer half-duplex interface in the TX direction, the starting position of the CRS signal is the starting position of the second stimulus message. If the content of the second stimulus message is the same as that of the message transmission message of the chip's MAC layer half-duplex interface, then the message transmission function of the chip's MAC layer half-duplex interface in this timing scenario is verified.

[0083] 2. When the starting position of the COL signal is between the starting position of the CRS signal and the falling position of the CRS signal.

[0084] In this timing scenario, when verifying the message receiving function of the chip MAC layer half-duplex interface in the RX direction, the interface verification module 220 continues to send messages to the chip MAC layer half-duplex interface without interrupting the flow. The message comparison module 230 continues to compare the comparison results of the first stimulus message with the message received through the chip MAC layer half-duplex interface. Although in actual scenarios, the chip MAC layer half-duplex interface has stopped sending messages according to the protocol, the method of continuing to send messages without interrupting the flow and continuing to compare eliminates the need for the verification device to distinguish this timing, thus simplifying the device.

[0085] When verifying the message transmission function of the MAC layer half-duplex interface in the TX direction, the start and end positions of the CRS signal correspond to the start and end positions of the second excitation message, respectively. This timing scenario can be divided into the following two scenarios.

[0086] 1. When the start position of the COL signal is between the start position of the second excitation message and the set position, the set position is obtained according to the 802.3 protocol.

[0087] The start position of the COL signal includes the position of each byte between the start position of the second excitation message and the set position.

[0088] Specifically, in this sub-timing scenario, when verifying the message transmission function of the chip's MAC layer half-duplex interface, for example, taking the set position at the end of the 64th byte (as specified by the 802.3 protocol) of the second stimulus message, the COL signal is only activated for one clock cycle. There are 64 traversal positions from the start of the second stimulus message to the set position COL signal. Each traversal position corresponds to one second stimulus message, and the corresponding byte position is within the first 64 bytes of that second stimulus message. The second stimulus message is longer than 80 bytes. By actively activating the COL signal at the corresponding byte position of the second stimulus message, the scenario where the timing of the received and transmitted messages of the chip's MAC layer half-duplex interface is difficult to precisely align to the byte level is avoided, thereby reducing the workload of verification.

[0089] At this point, when the chip's MAC layer half-duplex interface detects the COL signal, it considers a collision to exist. According to the protocol, it sets the checksum of the currently transmitted message to 0xAAAA_AAAA (i.e., all A's), which is equivalent to discarding the message being transmitted. After the COL signal falls, it retransmits the message. Therefore, the interface verification module 220 will receive multiple messages sent by the chip's MAC layer half-duplex interface. Except for the last received message, which is a correctly transmitted message, the checksum of the other received messages is set to 0xAAAA_AAAA, meaning the message is discarded.

[0090] At this time, the message comparison module 230 discards the message sent by the interface verification module 220 before the COL signal falls on the chip's MAC layer half-duplex interface. By comparing the second stimulus message with the message sent by the interface verification module 220 after the COL signal falls, i.e., the last received message, the message sending function of the chip's MAC layer half-duplex interface in this timing scenario is verified. When the contents of the two are the same, the message sending function of the chip's MAC layer half-duplex interface in this timing scenario is verified.

[0091] 2. When the start position of the COL signal includes the position between the set position and the end position of the second excitation message, the start position of the COL signal is the position where a set number of bytes are randomly selected, that is, the position where a set number of bytes are randomly selected from the set position to the end position of the CRS signal, and these positions are respectively used as the start positions of the COL signal.

[0092] In this timing scenario, when verifying the message sending function of the half-duplex interface of the MAC layer of the chip, for example, taking a second stimulus message with a length of 1518 bytes and the setting position at 64 bytes of the second stimulus message, the COL signal is set at a random position between 65 and 1518 bytes of the second stimulus message, and this is repeated 10 times.

[0093] At this point, when the chip's MAC layer half-duplex interface detects the COL signal, it considers a collision to exist. According to the protocol, it discards the currently transmitted message by setting the checksum of the message to 0xAAAA_AAAA (i.e., all A's) and does not retransmit the message. Therefore, the interface verification module 220 will receive one message from the chip's MAC layer half-duplex interface, and this message will be discarded.

[0094] At this time, the message comparison module 230 checks whether the verification part of the message received by the interface verification module 220 is 0xAAAA_AAAA (i.e., all A), that is, whether it is a discarded message.

[0095] 3. When the COL signal is set to a position after the CRS signal is set to a position.

[0096] The COL signal duration is at least a certain number of beats, and the time difference between the start position of the COL signal and the fall position of the CRS signal includes at least one of the following values: less than a second set value, and the second set value is less than 1 beat. Alternatively, it can be considered that the start position of the COL signal and the fall position of the CRS signal at least cover one instance where the CRS signal has just fallen and the COL signal immediately follows.

[0097] In this timing scenario, when verifying the message receiving function of the chip MAC layer half-duplex interface in the RX direction, the first stimulus message is compared with the message received through the chip MAC layer half-duplex interface. When the contents of the two messages are the same, the message receiving function of the chip MAC layer half-duplex interface in this timing scenario is verified as successful.

[0098] In this timing scenario, when verifying the message transmission function of the chip's MAC layer half-duplex interface in the TX direction, the position where the CRS signal falls is the end position of the second stimulus message. The second stimulus message is compared with the message transmitted through the chip's MAC layer half-duplex interface. When the contents of the two are the same, the message transmission function of the chip's MAC layer half-duplex interface in this timing scenario is verified.

[0099] In summary, Embodiment 2 of a verification device for a chip MAC layer half-duplex interface not only verifies the receiving function through a simple device, but also covers the combined timing of message receiving and sending in all scenarios, accurately and effectively covering various scenarios. Furthermore, it adopts the COL signal setting to avoid inefficient random triggering, thus achieving efficient and comprehensive verification of the chip MAC layer half-duplex interface.

[0100] The following is combined Figure 3 This invention introduces a verification method for a chip MAC layer half-duplex interface, embodiment one.

[0101] An embodiment of a verification method for a chip MAC layer half-duplex interface uses an embodiment of a verification device for a chip MAC layer half-duplex interface to verify the chip MAC layer half-duplex interface. By sending a first excitation message to the chip MAC layer half-duplex interface, the message receiving function of the chip MAC layer half-duplex interface is verified. This method has all the advantages of the embodiment of a verification device for a chip MAC layer half-duplex interface.

[0102] Figure 3 The flowchart of a verification method for a chip MAC layer half-duplex interface according to the present invention is shown, including steps S310 to S330.

[0103] S310: The interface verification module 120 starts sending the first stimulus message to the chip's MAC layer half-duplex interface until the message is sent, and collects the received messages of the chip's MAC layer half-duplex interface.

[0104] S320: The signal sending module 110 sets up the CRS signal when the interface verification module 120 starts sending the first excitation message and drops the CRS signal when it finishes sending the first excitation message, and sets up the COL signal at the corresponding position.

[0105] The COL signal is set at one of the following positions: before the CRS signal is set, between the position where the CRS signal is set and the position where it falls, and after the position where the CRS signal falls.

[0106] Steps S310 and S320 are executed in parallel.

[0107] S330: The message comparison module 130 compares the first excitation message with the received message of the chip's MAC layer half-duplex interface to verify and test the message receiving function of the chip's MAC layer half-duplex interface.

[0108] Specifically, if the COL signal falls before the CRS signal rises or falls after the CRS signal, and the contents of the first excitation message and the received message of the chip's MAC layer half-duplex interface are the same, then the verification is successful; if the COL signal is located between the CRS signal rise and fall positions, the comparison results continue.

[0109] The following is combined Figure 4 and Figure 5 This invention introduces a second embodiment of a verification method for a chip MAC layer half-duplex interface.

[0110] A second embodiment of a verification method for a chip MAC layer half-duplex interface uses a second embodiment of a verification device for a chip MAC layer half-duplex interface to verify the chip MAC layer half-duplex interface, and has all the advantages of the second embodiment of a verification device for a chip MAC layer half-duplex interface.

[0111] Figure 4 The present invention illustrates a verification method for a chip MAC layer half-duplex interface, specifically a flowchart for verifying the receiving function of the chip MAC layer half-duplex interface. The method verifies the message receiving function of the chip MAC layer half-duplex interface by sending a first excitation message to the chip MAC layer half-duplex interface, including steps S410 to S430.

[0112] S410: The interface verification module 220 starts sending the first stimulus message to the chip's MAC layer half-duplex interface until the message is sent, and collects the received messages of the chip's MAC layer half-duplex interface.

[0113] S420: The signal sending module 210 sets up the CRS signal when the interface verification module 220 starts sending the first excitation message and drops the CRS signal when it finishes sending the first excitation message, and sets up the COL signal at the corresponding position.

[0114] The COL signal is set at one of the following positions: before the CRS signal is set, between the position where the CRS signal is set and the position where it falls, and after the position where the CRS signal falls.

[0115] Steps S410 and S420 are executed in parallel.

[0116] S430: The message comparison module 230 compares the first stimulus message with the message received through the chip's MAC layer half-duplex interface to verify the message receiving function of the chip's MAC layer half-duplex interface.

[0117] Figure 5 The present invention illustrates a verification method for a chip MAC layer half-duplex interface, specifically a flowchart for verifying the transmission function of the chip MAC layer half-duplex interface. The method verifies the message transmission function of the chip MAC layer half-duplex interface by sending a second excitation message to the generation unit of the chip MAC layer half-duplex interface, including steps S510 to S560.

[0118] S510: The interface verification module 220 starts sending the second stimulus message to the chip MAC layer half-duplex interface until the sending is completed, and collects the received messages of the chip MAC layer half-duplex interface.

[0119] S520: When the signal transmitting module 210 detects a message sent by the half-duplex interface of the chip's MAC layer, it sets up the CRS signal and sets up the COL signal at the corresponding position.

[0120] The COL signal is set at one of the following locations: before the start of the second stimulus message, between the start of the second stimulus message and the set position, between the set position and the end of the second stimulus message, and after the end of the second stimulus message, wherein the set position is obtained according to the 802.3 protocol.

[0121] Steps S510 and S520 are executed in parallel.

[0122] S530: Message comparison module 230 determines the timing relationship between the CRS signal and the COL signal.

[0123] Determining the timing relationship between the CRS signal and the COL signal is equivalent to determining the timing relationship between the second excitation message and the COL signal.

[0124] Specifically, when the COL signal falls before the start position of the second excitation message or the COL signal starts after the end position of the second excitation message, step S540 is executed; when the COL signal starts between the start position of the second excitation message and the set position, step S550 is executed; and when the COL signal starts between the set position and the end position of the second excitation message, step S560 is executed.

[0125] S540: The message comparison module 230 compares the second stimulus message with the message sent by the chip's MAC layer half-duplex interface to verify and test the message sending function of the chip's MAC layer half-duplex interface.

[0126] S550: The message comparison module 230 compares the second stimulus message with the last transmitted message of the chip MAC layer half-duplex interface, and confirms that the previous transmitted message was a discarded message.

[0127] S560: Message comparison module 230 loses sending messages from the MAC layer half-duplex interface of the chip.

[0128] This invention also provides a computing device, which will be described below in conjunction with... Figure 6 Detailed introduction.

[0129] The computing device 600 includes a processor 610, a memory 620, a communication interface 630, and a bus 640.

[0130] It should be understood that the communication interface 630 in the computing device 600 shown in the figure can be used to communicate with other devices.

[0131] The processor 610 can be connected to the memory 620. The memory 620 can be used to store the program code and data. Therefore, the memory 620 can be a storage unit inside the processor 610, an external storage unit independent of the processor 610, or a component that includes both the storage unit inside the processor 610 and the external storage unit independent of the processor 610.

[0132] Optionally, the computing device 600 may also include a bus 640. The memory 620 and communication interface 630 can be connected to the processor 610 via the bus 640. The bus 640 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus 640 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one line is used in this figure, but this does not mean that there is only one bus or one type of bus.

[0133] It should be understood that in this embodiment of the invention, the processor 610 may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor. Alternatively, the processor 610 may employ one or more integrated circuits to execute relevant programs to implement the technical solutions provided in this embodiment of the invention.

[0134] The memory 620 may include read-only memory and random access memory, and provides instructions and data to the processor 610. A portion of the processor 610 may also include non-volatile random access memory. For example, the processor 610 may also store device type information.

[0135] When the computing device 600 is running, the processor 610 executes computer execution instructions stored in the memory 620 to perform the operation steps of each method embodiment.

[0136] It should be understood that the computing device 600 according to the embodiments of the present invention can correspond to the corresponding subject in executing the methods according to the various embodiments of the present invention, and the above and other operations and / or functions of each module in the computing device 600 are respectively for implementing the corresponding processes of the methods of this embodiment. For the sake of brevity, they will not be described in detail here.

[0137] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0138] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0139] In the embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0140] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0141] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0142] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0143] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is used to perform the operation steps of the various method embodiments.

[0144] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0145] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0146] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including, but not limited to, wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0147] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as SystemVerilog, Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0148] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, all of which fall within the scope of protection of the present invention.

Claims

1. A verification device for a chip MAC layer half-duplex interface, characterized in that, For verifying the message reception function of the interface by sending a first stimulus message to the interface, including: The signal transmission module is used to start setting up the CRS signal when the first excitation message is sent and to drop the CRS signal when the first excitation message is sent, and to actively set up the COL signal at any of the following positions: before the CRS signal is set up, between the position where the CRS signal is set up and the position where it drops, and after the position where the CRS signal drops. The interface verification module is used to send a first stimulus message to the interface until the transmission is completed, and to collect the received messages of the interface; wherein, the first stimulus message is continuously sent to the interface during the CRS signal activation period; The message comparison module is used to compare the first stimulus message and the received message to verify and test the message receiving function. Specifically, when the COL signal falls before the CRS signal starts to rise or the COL signal rises after the CRS signal falls, if the content of the received message and the first stimulus message are consistent, the message receiving function of the interface is verified to be successful. When the COL signal is between the CRS signal rise and fall positions, the first stimulus message and the received message are continuously compared.

2. The apparatus according to claim 1, characterized in that, It is also used to verify the message sending function of the interface by sending a second stimulus message to the sending unit of the interface. The signal transmitting module is also used to actively activate the COL signal at any of the following locations: before the start of the second excitation message, between the start of the second excitation message and the set position, between the set position and the end of the second excitation message, and after the end of the second excitation message, wherein the set position is obtained according to the 802.3 protocol; The interface verification module is also used to send a second stimulus message to the sending unit of the interface, so that the interface sends messages outward, and to collect all the messages sent by the interface; The message comparison module is also used to compare the second incentive message and the sent message to verify and test the message sending function.

3. The apparatus according to claim 2, characterized in that, When the COL signal is set between the start position of the second excitation message and the set position... When comparing the second incentive message and the sent message, the message comparison module is specifically used to compare whether the second incentive message is consistent with the last sent message, and also to verify whether the previous sent message was a discarded message.

4. The apparatus according to claim 2, characterized in that, When the COL signal is set between the start position of the second excitation message and the set position, the set position of the COL signal includes each byte between the start position of the second excitation message and the set position, and the duration is 1 clock cycle.

5. The apparatus according to claim 2, characterized in that, When the COL signal is set between the set position and the end position of the second excitation message, the message comparison module compares the second excitation message and the sent message, specifically to confirm whether the sent message is a discarded message.

6. The apparatus according to claim 2, characterized in that, When the COL signal is set between the set position and the end position of the second excitation message, the set position of the COL signal includes: a position randomly selected from the set position to the end position of the second excitation message by a set number of bytes.

7. The apparatus according to claim 1, characterized in that, The device is built based on a UVM environment.

8. A verification method for a chip MAC layer half-duplex interface, characterized in that, Verifying the message receiving function of the interface by sending a first stimulus message to the interface includes: Send a first stimulus message to the interface until the message is sent, and collect the received messages of the interface. The CRS signal is set up when the first stimulus message is sent and dropped when the first stimulus message is dropped, and the COL signal is actively set up at any of the following positions: before the CRS signal is set up, between the position where the CRS signal is set up and the position where the CRS signal is dropped, and after the position where the CRS signal is dropped; wherein, the first stimulus message is continuously sent to the interface during the period when the CRS signal is set up. The message receiving function is verified by comparing the first stimulus message and the received message. Specifically, when the COL signal falls before the CRS signal starts to rise or the COL signal rises after the CRS signal falls, the content of the received message is consistent with the first stimulus message, and the message receiving function of the interface is verified. When the COL signal is between the CRS signal rise and fall positions, the first stimulus message and the received message are continuously compared.

9. A computing device, characterized in that, include, bus; A communication interface, which is connected to the bus; At least one processor is connected to the bus; as well as At least one memory connected to the bus and storing program instructions that, when executed by the at least one processor, cause the at least one processor to perform the method of claim 8.

10. A computer-readable storage medium, characterized in that, It stores program instructions that, when executed by a computer, cause the computer to perform the method of claim 8.

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