Image sensor pixel and image sensor

Abstract

The present application provides a pixel of an image sensor and an image sensor, which can provide intensity information and flight time information of incident light. The pixel may include a photoelectric conversion circuit and a composite measurement circuit. The photoelectric conversion circuit can be used to generate a first current based on the incident light incident on the pixel. The composite measurement circuit is coupled to the photoelectric conversion circuit. The pixel can have a first operating mode and a second operating mode. The composite measurement circuit can generate a first pulse signal based on the first current when the pixel operates in the first operating mode, and the first pulse signal represents the intensity information of the incident light. When the pixel operates in the second operating mode, multiple sampling signals are received, and multiple second pulse signals are generated based on the first current and the multiple sampling signals; the multiple second pulse signals are used to represent the phase offset between the phase of the incident light and the set phase, and the phase offset can be used to determine the distance between the pixel and the target object.

Description

Technical Field

[0001] The present application relates to image sensor technology, and in particular to a pixel of an image sensor and an image sensor. Background Art

[0002] As the application scenarios of image sensors increase, the types of image sensors are also increasing. When the light irradiated on the object is incident on the image sensor, each pixel in the image sensor can convert the incident light into the pixel into a corresponding electrical signal. The processor can generate an image of the object or determine the change of the object through the electrical signals provided by each pixel in the image sensor.

[0003] Different types of image sensors have different processes for converting incident light into electrical signals. For example, a grayscale image sensor converts incident light into electrical signals that represent the light intensity information of the incident light. The processor can use the light intensity information to generate an image of the object. A dynamic vision image sensor converts incident light into electrical signals that represent the change in the light intensity of the incident light. The processor can use the change in light intensity to update the image. Grayscale image sensors and dynamic vision image sensors are generally referred to as two-dimensional image sensors, and the intensity information of the incident light and the change in the light intensity of the incident light generated respectively are called two-dimensional information.

[0004] The time-of-flight image sensor converts the incident light into an electrical signal to represent the time-of-flight information of the incident light, and the incident light is the light reflected by the active light source from the object. The processor can use the time-of-flight information to determine the distance between the object and the active light source, that is, to determine the depth between the object and the active light source. Therefore, the time-of-flight image sensor is usually called a three-dimensional image sensor, and the time-of-flight information of the incident light generated is called three-dimensional information.

[0005] In some new application scenarios of image sensors, multiple types of image sensors are usually required. For example, in an autonomous driving scenario, the vehicle needs to accurately detect the conditions of surrounding objects. Generally, the vehicle emits an active light source, which is reflected after encountering the detected object. The vehicle needs to process the light reflected into the image sensor to generate two-dimensional information or three-dimensional information, so as to generate a two-dimensional image or a three-dimensional image of the object. Therefore, multiple types of image sensors need to be set up in the vehicle, which has a high cost, and the process of matching the information generated by the pixels of different types of image sensors is relatively complicated. Summary of the invention

[0006] In view of this, the present application provides a pixel of an image sensor and an image sensor, which can provide intensity information and flight time information of incident light.

[0007] In a first aspect, the pixel of the image sensor provided in the embodiment of the present application may include a photoelectric conversion circuit and a composite measurement circuit. The photoelectric conversion circuit may be used to generate a first current based on the incident light incident on the pixel. The composite measurement circuit is coupled to the photoelectric conversion circuit. The pixel may have multiple operating modes, such as a first operating mode and a second operating mode. When the pixel is in the first operating mode, it may provide the intensity information of the incident light. When the pixel is in the second operating mode, it may provide the flight time information of the incident light. When the pixel is operating in the first operating mode, the composite measurement circuit may generate a first pulse signal based on the first current, and the first pulse signal represents the intensity information of the incident light. When the pixel is operating in the second operating mode, it receives a plurality of sampling signals, and generates a plurality of second pulse signals based on the first current and the plurality of sampling signals; wherein the plurality of sampling signals correspond to the plurality of second pulse signals one by one, and the plurality of second pulse signals are used to represent the phase offset between the phase of the incident light and the set phase, and the incident light is the light of the set phase incident on the target object and reflected. The set phase may be the phase of the active light. The phase shift between the phase of the incident light and the set phase is the flight time information of the incident light, which can be used to determine the distance between the pixel and the target object.

[0008] In the embodiment of the present application, the composite measurement circuit uses pulsed data output when the pixel is in different working modes. This saves the processing of analog physical quantities in the peripheral circuit. The back-end circuit, such as the image signal processor, can directly process the first pulse signal or the second pulse signal in a digital signal processing manner. In addition, the composite measurement circuit has multiple functions and can provide the intensity information of the incident light and the flight time information, thereby reducing the chip area.

[0009] In a possible design, the composite measurement circuit includes a configuration signal receiving unit, an integration unit, a comparison unit, and a delay sampling unit. The first end of the configuration signal receiving unit is coupled to the photoelectric conversion circuit; the second end of the configuration signal receiving unit is coupled to the first end of the integration unit and to the input end of the comparison unit.

[0010] The configuration signal receiving unit can output the first current to the integration unit in the first working mode; in the second working mode, the configuration signal receiving unit can receive the multiple sampling signals and periodically output the first current to the integration unit based on the signal periods of the multiple sampling signals. The second end of the integration unit is coupled to the first level, and the integration unit can be used to integrate the first current to obtain a measurement voltage and provide the measurement voltage to the comparison unit.

[0011] The input end of the comparison unit is coupled with the first end of the integration unit and can be used to: compare the measurement voltage with a preset reference voltage, and send the comparison result signal to the delay sampling unit, wherein, when the measurement voltage is less than the reference level, the level of the comparison result signal is a second level, and when the measurement voltage is greater than or equal to the reference level, the level of the comparison result signal is a third level, and the second level is greater than the third level; the delay sampling unit is coupled with the output end of the comparison unit; the delay sampling unit is used to: sample the comparison result signal to generate the first pulse signal or the multiple second pulse signals.

[0012] In a possible design, the configuration signal receiving unit includes a first switch and a second switch. The first end of the first switch is coupled to a third power supply level, the second end of the first switch is coupled to the photoelectric conversion circuit, the second end of the first switch is coupled to the first end of the second switch, the second end of the second switch is coupled to the first end of the integration unit, and the third power supply level is less than the second power supply level; wherein, when the first switch is in an open state and the second switch is in an on state, the first current is transmitted to the integration unit; when the first switch is in an on state and the second switch is in an open state, the first current is transmitted to the third power supply level.

[0013] In one possible design, the integration unit includes a first capacitor; a first electrode of the first capacitor is coupled to the photoelectric conversion circuit through the second switch, and a second electrode of the first capacitor is coupled to the first level.

[0014] In one possible design, the comparison unit includes a comparator. The first input terminal of the comparator is coupled to the first terminal of the integration unit for receiving the measurement voltage. The second input terminal of the comparator is coupled to the reference voltage. The output terminal of the comparator is coupled to the delayed sampling unit for outputting the comparison result signal. The initial voltage of the first electrode of the first capacitor can be the same as the level of the ground, and the level of the comparison result signal output by the comparator is the second level.

[0015] In one example, in the first working mode, the control end of the first switch receives a first drive signal, and the first drive signal is a fixed level signal, which is used to drive the first switch to be in an open circuit state. The control end of the second switch receives a second drive signal, and the second drive signal is a fixed level signal, which is used to drive the second switch to be in an on state. Thus, the first current generated by the photodiode can be transmitted to the first pole of the first capacitor via the second switch. When the first pole of the first capacitor is connected to the cathode of the photodiode, the first capacitor integrates the first current, and the voltage at the first pole of the first capacitor increases. When the voltage at the first pole of the first capacitor increases to the reference voltage, the level of the comparison result signal output by the comparator is a third level. After a delay time, the voltage at the first pole of the first capacitor is reset to the initial level, so that the first capacitor can start a new integration process. At this time, the level of the comparison result signal output by the comparator becomes the second level.

[0016] In the embodiment of the present application, the comparator outputs a low level which can be regarded as the comparator generating a reset valid level. During an integration process of the first capacitor, the voltage at the first pole of the first capacitor increases from the initial voltage to the reference level, and the comparator outputs a low level. After the voltage at the first pole of the first capacitor is reset to the initial voltage, the comparator outputs a high level, and thus the comparator generates a pulse. In the first working mode, the number of pulses in the first pulse signal output by the comparator within a fixed time, that is, the frequency of the first pulse signal output by the comparator, can characterize the intensity information of the incident light. The image signal processor can use the frequency of the first pulse signal output by the comparator to encode the intensity information of the incident light.

[0017] In another example, in the second working mode, the control end of the first switch receives a third drive signal; the third drive signal is a periodic signal, and the first switch is used to control the first switch to alternate between an on state and an off state according to the period of the third drive signal. The control end of the second switch receives the multiple sampling signals; wherein any sampling signal is a periodic signal, and the second switch is used to control the second switch to alternate between an on state and an off state according to the period of each sampling signal. Wherein, when the second switch is in the on state, the first switch is in the off state, and if the photoelectric conversion circuit outputs the first current, the first current can be transmitted to the first pole of the first capacitor. When the first switch is in the on state, the second switch is in the off state, and if the photoelectric conversion circuit outputs the first current, the first current can be transmitted to the third power supply level. In some scenarios, the third drive signal and the sampling signal can be a pair of anti-phase clock signals. The frequency of the sampling signal is the same as the frequency of the optical fiber of the set phase.

[0018] The control end of the second switch receives the multiple sampling signals in a time-sharing manner, and the comparator can output the second pulse signal corresponding to each sampling signal in a time-sharing manner. The multiple sampling signals have different phases. When the control end of the second switch receives a sampling signal with a phase of the first phase, the comparator outputs a second pulse signal corresponding to the first phase. Within a preset number of cycles, the total number of pulses in the second pulse signal corresponding to the first phase represents the integral value corresponding to the first phase. The integral value corresponding to the phase of each sampling signal can be used to determine the phase offset between the phase of the incident light and the set phase.

[0019] In one possible design, the delayed sampling unit includes a D latch and a NOR gate circuit; the data input end of the D latch is coupled to the output end of the comparator for receiving the comparison result signal; the timing control input end of the D latch is used to receive a first clock signal; the Q output end of the D latch is coupled to the first input end of the NOR circuit for outputting a signal to the NOR circuit; the second input end of the NOR gate circuit is used to receive the first clock signal; the output end of the NOR gate circuit is coupled to an image signal processor for outputting the first pulse signal or the second pulse signal.

[0020] In a possible design, the composite measurement circuit further includes a reset switch. The first end of the reset switch is grounded, and the second end is coupled to the first end of the integration unit. The control end of the reset switch is coupled to the delay sampling unit for receiving the first pulse signal. During a period when the level of the first pulse signal is a fourth level, the reset switch is in an open circuit state; during a period when the level of the first pulse signal is a fifth level, the reset switch is in an on state, so that the voltage at the first end of the integration unit is a reset voltage, such as a ground level. The fourth level is greater than the fifth level.

[0021] In a possible design, the composite measurement circuit further includes a readout unit. The readout unit is coupled to the delayed sampling unit and to an image signal processor. The readout unit is used to receive a storage signal provided by the image signal processor and cache the first pulse signal or the second pulse signal according to the storage signal. The readout unit can receive a scan signal provided by the image signal processor and output the cached signal to the image signal processor according to the scan signal.

[0022] In a possible design, the readout unit includes a third switch, a fourth switch and an RS latch. The first end of the third switch is coupled to the image signal processor; the second end of the third switch is coupled to the first pole of the fourth switch; the control end of the third switch is used to receive the scan signal provided by the image signal processor, wherein the scan signal is used to drive the third switch to be in a conducting state. The second pole of the fourth switch is grounded, and the control end of the fourth switch is coupled to the Q output end of the RS latch; the reset end of the RS latch is coupled to the image signal processor, and is used to receive the storage signal or the reset signal provided by the image signal processor; the set end of the RS latch is coupled to the output end of the delay sampling unit, and is used to receive the first pulse signal, and the level at the Q output end of the RS latch is the same as the level of the first pulse signal, or receive the second pulse signal, and the level at the Q output end of the RS latch is the same as the level of the second pulse signal.

[0023] In a possible design, the pixel further includes a dynamic visual measurement circuit; the dynamic visual measurement circuit is coupled to the photoelectric conversion circuit and to an image signal processor. The dynamic visual measurement circuit can generate an indication level signal based on the first current, and send the indication level signal to the image signal processor, wherein the indication level signal represents information on changes in light intensity of the incident light.

[0024] The pixel provided in the embodiment of the present application can provide the intensity information of the incident light, the light intensity change information of the incident light and the flight time information of the incident light. The pixel has multiple functions, which is conducive to the image sensor serving more application scenarios.

[0025] In one possible design, the pixel further includes a current mirror circuit. The composite measurement circuit is coupled to the photoelectric conversion circuit via the current mirror circuit. The current mirror circuit can be used to provide the composite measurement circuit with the first current generated by the photoelectric conversion circuit. In such a design, the first current is multiplexed and provided to the dynamic vision measurement circuit and the composite measurement circuit, so that the two circuits can work synchronously. In addition, the isolation between the dynamic vision circuit and the composite measurement circuit is increased, and the mutual influence between the composite measurement circuit and the dynamic vision measurement circuit is reduced.

[0026] In one possible design, the photoelectric conversion circuit includes a photodiode, wherein an anode of the photodiode is coupled to a first power supply level, and a cathode of the photodiode is coupled to the composite measurement circuit and to a second power supply level, wherein the second power supply level is greater than the first power supply level.

[0027] In one possible design, the voltage of the first power supply level is less than zero, which can increase the current gain of the photodiode, so that the pixel can work normally in a darker environment. In some application scenarios, by selecting materials with different absorption wavelengths as photodiodes, the pixel can process incident light of various wavelengths.

[0028] In a second aspect, an embodiment of the present application further provides an image sensor, which may include an array of multiple pixels, wherein at least one pixel is a pixel of any possible design as in the first aspect.

[0029] In a possible design, the image sensor may further include an image signal processor. The image signal processor is coupled to the composite measurement circuit. The image signal processor may control a target pixel to be in a first operating mode, wherein the target pixel is any one of the at least one pixel; receive a first pulse signal, and determine intensity information of incident light incident on the target pixel according to a frequency of the first pulse signal.

[0030] In one possible design, the image signal processor is also used to: control the target pixel to be in a second operating mode, and send multiple sampling signals corresponding to the multiple phases to the target pixel in sequence according to the preset multiple phases, wherein the multiple phases correspond one-to-one to the multiple sampling signals; receive multiple second pulse signals, and the multiple sampling signals correspond one-to-one to the multiple second pulse signals; determine the phase offset between the phase of the incident light incident on the target pixel and the set phase according to each second pulse signal in the multiple second pulse signals, wherein the incident light is the light of the set phase incident on the target object and reflected.

[0031] In one possible design, the image signal processor can determine the number corresponding to each second pulse signal, wherein the number corresponding to each second pulse signal is the number of rising edges in each second pulse signal within a preset time length; based on the number corresponding to the multiple second pulse signals, determine the phase offset; and based on the phase offset, determine the distance between the target pixel and the target object.

[0032] The technical effects that can be achieved in the above-mentioned second aspect can refer to the description of the technical effects that can be achieved in the above-mentioned first aspect and any possible design in the first aspect, and the repetitions will not be discussed here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram showing the structure of a pixel;

[0034] Figure 2 A schematic diagram showing a specific structure of a pixel;

[0035] Figure 3 A schematic diagram showing a specific structure of a composite measurement circuit in a pixel;

[0036] Figure 4 A specific structural schematic diagram of a comparator is shown;

[0037] Figure 5 A specific structural schematic diagram of a D latch is shown;

[0038] Figure 6 A schematic diagram showing a sampling signal according to an exemplary embodiment is shown;

[0039] Figure 7 A specific structural schematic diagram of an RS latch is shown;

[0040] Figure 8 A schematic diagram showing the structure of another pixel;

[0041] Fig. 9 A structural schematic diagram of a dynamic vision measurement circuit is shown;

[0042] Fig.10 A specific structural schematic diagram of a dynamic vision measurement circuit is shown;

[0043] Fig.11 A schematic diagram showing the specific structure of a response circuit in a dynamic vision measurement circuit;

[0044] Fig.12 A specific structural schematic diagram of a pixel circuit is shown;

[0045] Fig.13 A schematic structural diagram of an image sensor is shown. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The specific operating method in the method embodiment can also be applied to the device embodiment or the system embodiment. It should be noted that in the description of the present application, "at least one" refers to one or more, wherein multiple refers to two or more. In view of this, "multiple" can also be understood as "at least two" in the embodiment of the present application. "And / or" describes the association relationship of the associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the related objects before and after are in an "or" relationship. In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0047] It should be pointed out that in the embodiments of the present application, "coupling" can be understood as electrical connection, and the coupling of two electrical components can be direct or indirect coupling between the two electrical components. For example, the connection between A and B can be direct coupling between A and B, or indirect coupling between A and B through one or more other electrical components, such as A and B coupling, or A and C direct coupling, C and B direct coupling, and A and B are coupled through C. In some scenarios, "coupling" can also be understood as connection. In short, the coupling between A and B enables the transmission of electrical energy between A and B.

[0048] It should be noted that the switch tube and the switch in the embodiment of the present application can be one or more of various types of switch tubes such as relays, metal oxide semiconductor field effect transistors (metal oxide semiconductor field effect transistors, MOSFET), bipolar junction transistors (bipolar junction transistors, BJT), insulated gate bipolar transistors (insulated gate bipolar transistors, IGBT), etc., and the embodiment of the present application will not list them one by one. Each switch tube can include a first electrode (or a first end), a second electrode (or a second end) and a control electrode (or a control end), wherein the control electrode is used to control the conduction or disconnection of the switch tube. When the switch tube is turned on, current can be transmitted between the first electrode and the second electrode of the switch tube, and when the switch tube is disconnected, current cannot be transmitted between the first electrode and the second electrode of the switch tube. Taking MOSFET as an example, the control electrode of the switch tube is the gate, the first electrode of the switch tube can be the source of the switch tube, the second electrode can be the drain of the switch tube, or the first electrode can be the drain of the switch tube, and the second electrode can be the source of the switch tube.

[0049] In some cases, the switch tube is turned on when driven by a high level, and the switch tube is disconnected when driven by a low level. In other cases, the switch tube is turned on when driven by a low level, and is disconnected when driven by a low level. The embodiment of the present application does not impose too many restrictions on this. The following is an introduction to the example that the switch tube is turned on when driven by a high level and is disconnected when driven by a low level. It should be understood that the high level and the low level are relative concepts, and the level (voltage value) of the high level is greater than the level of the low level. In digital circuits, 1 is usually used to represent the high level and 0 is used to represent the low level. For different components in the circuit, the level of the high level can be the same or different. For the convenience of introduction, in the embodiment of the present application, the high level can be 1.8V and the low level can be 0V.

[0050] The following is an introduction to the pixel (or pixel circuit) of the image sensor provided by the present application in conjunction with the accompanying drawings. Figure 1 , an embodiment of the present application provides a pixel of an image sensor, which can be coupled to an image signal processor. The pixel may include a photoelectric conversion circuit and a composite measurement circuit. The pixel can be used to convert light incident on the pixel into a corresponding electrical signal. The composite measurement circuit can be coupled to the photoelectric conversion circuit. The photoelectric conversion circuit can generate a first current based on incident light incident on the pixel. Optionally, the first current can also be called a photocurrent, that is, the corresponding current converted by the photoelectric conversion circuit from the incident light.

[0051] The pixel provided in the embodiment of the present application has multiple operating modes, which correspond to the multiple operating modes of the composite measurement circuit. In other words, the composite measurement circuit in the pixel provided in the embodiment of the present application has multiple operating modes to realize the multiple functions of the pixel. Optionally, the composite measurement circuit can switch the operating mode under the drive of the image signal processor. The composite measurement circuit can receive the photocurrent from the photoelectric conversion circuit, and then can detect the two-dimensional information (such as the intensity information of the incident light) or the three-dimensional information (such as the flight time information of the incident light) of the incident light based on the photocurrent.

[0052] For example, when the pixel is in the first working mode, the composite measurement current is used to detect the intensity information of the incident light. When the pixel is in the second working mode, the composite measurement circuit can be used to detect the flight time information of the incident light. The working process of the composite measurement circuit in different working modes of the pixel is introduced below.

[0053] The composite measurement circuit can generate a first pulse signal based on the first current when the pixel operates in the first operating mode, and the first pulse signal represents the intensity information of the incident light, so that the pixel can detect two-dimensional information of the incident light. For example, the image signal processor can control the composite measurement circuit to operate in the first operating mode. The image signal processor can send a first operating mode control signal to the composite measurement circuit. The composite measurement circuit can generate a first pulse signal based on the first current in response to the first operating mode control signal.

[0054] The composite measurement circuit can receive multiple sampling signals when the pixel operates in the second working mode, and generate multiple second pulse signals based on the first current and the multiple sampling signals. The multiple sampling signals correspond to the multiple second pulse signals one by one, and the multiple second pulse signals are used to characterize the phase offset between the phase of the incident light and the set phase, and the incident light is the light of the set phase incident on the target object and reflected. Thereby, the pixel detects the three-dimensional information of the incident light. In the embodiment of the present application, the three-dimensional information (that is, the time of flight information) of the composite measurement current detecting the incident light can be the phase offset between the phase of the incident light and the phase of the active light source. For example, the image signal processor can send a second working mode control signal to the composite measurement circuit, and the second working mode control signal can include multiple sampling signals, wherein the multiple sampling signals are periodic signals, and the phases of the multiple sampling signals are different. The image signal processor can send sampling signals to the composite measurement circuit in sequence, and the composite measurement circuit can respond to each received sampling signal, and generate a second pulse signal corresponding to the sampling signal based on the first current and the received sampling signal. The second pulse signal corresponding to each sampling signal generated by the composite measurement circuit can characterize the phase offset between the phase of the incident light and the set phase (such as the phase of the active light source). The image sensor is used in the detection of three-dimensional information scenes. The light emitted by the active light source is reflected by the object to be measured and then incident on the pixel of the image sensor. The frequency of the active light source is pre-configured, and the image signal processor can obtain the frequency of the active light source in advance.

[0055] The following is a brief introduction to the process by which the image signal processor can use the phase offset to determine the distance between the pixel and the object to be measured. Take the sine wave modulated active light source as an example. The active light source can be recorded as r(t) = coswt. Where w is the phase set above. The incident light is the light from the active light source that is reflected by the target object and is delayed. The incident light can be recorded as in, is the phase shift between the incident light and the active light source.

[0056] In one implementation, the image signal processor may determine the distance corresponding to the detected phase offset based on a preset relationship between the phase offset and the distance. The relationship may be expressed as: Where c is the speed of light and fmod is the frequency of the active light source.

[0057] In another embodiment, the image signal processor may determine the distance corresponding to the detected phase offset based on a preset relationship between the phase offset and the distance. The relationship is expressed as: Where c is the speed of light, fmod is the frequency of the active light source, and k is the refractive index.

[0058] In combination with the pixel structure, multiple working modes of the pixel are described in detail below. In one embodiment, the photoelectric conversion circuit may include a photodiode (PD). The photodiode (PD) may be set between a first power supply level and a second power supply level, and the second power supply level is greater than the first power supply level. In a possible embodiment, see Figure 2 , the cathode of the photodiode (PD) is coupled to the second power supply level (VDD1). The anode of the photodiode (PD) is coupled to the first power supply level (VSS), and the cathode of the photodiode (PD) is coupled to the composite measurement circuit. Optionally, the second power supply level (VDD1) may be 3.3V. The first power supply level (VSS) may be less than zero, that is, less than the ground level. Such a design can improve the current gain of the photoelectric conversion circuit.

[0059] In one embodiment, see also Figure 2 The composite measurement circuit may include a configuration signal receiving unit, an integration unit, a comparison unit, and a delay sampling unit. The first end of the configuration signal receiving unit is coupled to a photoelectric conversion circuit, such as a cathode of the photodiode (PD). The second end of the configuration signal receiving unit is coupled to the first end of the integration unit and to the input end of the comparison unit.

[0060] When the pixel is in the first operating mode, the configuration signal receiving unit can receive the first operating mode control signal to conduct the photoelectric conversion circuit and the integration unit, so that the configuration signal receiving unit receives the first current and outputs the first current to the integration unit.

[0061] When the pixel is in the second operating mode, the configuration signal unit can receive each sampling signal and, based on the signal period of the sampling signal, periodically connect the photoelectric conversion circuit and the integration unit, so that the configuration signal receiving unit periodically outputs the first current to the integration unit.

[0062] like Figure 2 As shown, the first end of the integration unit is coupled to the second end of the configuration signal receiving unit, the first end of the integration unit is coupled to the comparison unit, and the second end of the integration unit is coupled to the first level (VQ). The first level (VQ) may be a fixed voltage. Optionally, the first level (VQ) may be a ground level, or the second end of the integration unit may be grounded. The integration unit may receive the first current output by the configuration signal receiving unit. The integration unit may be used to integrate the received first current to obtain a measurement voltage, and provide the measurement voltage to the comparison unit. As shown Figure 2The node VD is shown in FIG. The node VD may be any point between the second end of the configuration signal receiving unit and the comparison unit. The integration unit integrates the first current to change the voltage at the node VD, and the voltage at the node VD is the aforementioned measurement voltage.

[0063] like Figure 2 As shown, the input end of the comparison unit can be coupled to the first end of the integration unit, and the output end of the comparison unit can be coupled to the delay sampling unit. The comparison unit can receive the measurement voltage, compare the measurement voltage with a preset reference voltage, and output (send) the comparison result signal to the delay sampling unit. The comparison unit can output the comparison result signal at a second level when the measurement voltage is less than the reference level. When the measurement voltage is greater than or equal to the reference level, the level of the comparison result signal is a third level, wherein the second level is greater than the third level.

[0064] The comparison result signal output by the comparison unit is an analog signal, and the signal output by the comparison unit is recorded as a first analog signal for easy distinction. From the above introduction, it can be seen that the level of the first analog signal in the period when the measured voltage is less than the reference voltage is the second level, and the level in the period when the measured voltage is greater than or equal to the reference voltage is the third level.

[0065] The delayed sampling unit is coupled to the output end of the comparison unit, and the delayed sampling unit is coupled to the image signal processor. The delayed sampling unit can perform delayed sampling processing on the signal output by the comparison unit to generate the first pulse signal or the second pulse signal. The delayed sampling unit can receive a first clock signal (clk) provided by the image signal processor, and sample the signal output by the comparison unit based on the first clock signal (clk). The delayed sampling unit can convert an analog signal into a digital signal, and the delayed sampling unit outputs a pulse within a given period. Such a design can meet the time requirements of the image signal processor.

[0066] When the pixel works in the first working mode, the delayed sampling unit samples the signal output by the comparison unit based on the first clock signal (clk), and the pulse signal obtained is the aforementioned first pulse signal. When the pixel works in the second working mode, the delayed sampling unit samples the signal output by the comparison unit based on the first clock signal (clk), and the pulse signal obtained is the aforementioned second pulse signal.

[0067] For a possible implementation, see Figure 3, the configuration signal receiving unit may include a first switch (Q1) and a second switch (Q2). The first end of the first switch (Q1) is coupled to the third power supply level (DR), the second end of the first switch (Q1) is coupled to the anode of the photodiode (PD), and the second end of the first switch (Q1) is coupled to the first end of the second switch (Q2). The control end of the first switch (Q1) is coupled to the image signal processor. The second end of the second switch (Q2) is coupled to the first end of the integration unit. The control end of the second switch (Q2) is coupled to the image signal processor.

[0068] In one embodiment, see Figure 3 As shown, the integration unit may include an integration device. In some examples, the integration unit may include a first capacitor (CD). The first pole of the first capacitor (CD) is coupled to the photoelectric conversion circuit, and the second pole of the first circuit (CD) is grounded. For example, the first pole of the first capacitor (CD) is coupled to the anode of the photodiode (PD) through the second switch (Q2). When the second switch (Q2) is in an on state, the anode of the photodiode (PD) and the first pole of the first capacitor (CD) can be connected. When the second switch (Q2) is in an off state, the anode of the photodiode (PD) and the first pole of the first capacitor (CD) can be disconnected. The first pole of the first capacitor (CD) can be implemented as the first end of the integration unit, and the second pole of the first capacitor (CD) can be implemented as the second end of the integration unit.

[0069] In one embodiment, see Figure 3 As shown, the comparison unit includes a first comparator. The first input terminal of the first comparator is coupled to the first terminal of the integration unit, the second input terminal of the first comparator receives a reference level (VREF), and the output terminal of the first comparator is used to output the first analog signal. The first comparator can be any comparator that can realize the function of the above-mentioned comparison unit. Figure 4 According to an exemplary embodiment, a circuit structure diagram of a first comparator is shown, wherein the voltage of a power supply level VDD of the first comparator may be 1.8V. Figure 4 The Vin terminal shown in the figure may be an input terminal of the first comparator and may be coupled to a first electrode of the first capacitor (CD). The Vref terminal is coupled to a reference level. The Vb terminal is coupled to a fixed voltage. The Vcomp terminal is an output terminal of the first comparator.

[0070] In one possible implementation, see Figure 3As shown, the delayed sampling unit may include a D latch and a NOR gate circuit. In the embodiment of the present application, the D latch may be any type of D latch. The D latch usually has a data input terminal (D), a timing control input terminal (EN), and a Q output terminal. Among them, when EN is a high level, the level of the Q output terminal changes with the level of the data input terminal (D); when the timing control input terminal (EN) is a low level, the level of the Q output terminal does not change the output state. Figure 5 A circuit structure diagram of a D latch is shown as an example.

[0071] The data input terminal (D) of the D latch is coupled to the output terminal of the first comparator for receiving the first analog signal. The timing control input terminal (EN) of the D latch is coupled to the image signal processor for receiving the first clock signal (clk). The NOR gate circuit is used to perform NOR processing on two input signals and output the processed signal. The NOR processing performed by the NOR gate circuit is introduced below. If both input signals are low level, the NOR gate circuit outputs a high level. If both input signals are high level (or the two input signals are high level and low level respectively), the NOR gate circuit outputs a low level.

[0072] The first input end of the NOR circuit is coupled to the Q output end of the D latch, and is used to output a signal to the NOR circuit. The second input end of the NOR gate circuit is coupled to the image signal processor, and is used to receive the first clock signal (clk). The NOR gate circuit can generate a pulse signal after performing NOR processing on the signal output from the Q output end of the D latch and the first clock signal (clk). The output end of the NOR gate circuit can be coupled to the image signal processor to output a pulse signal. Wherein, when the pixel is in the first working mode, the NOR gate circuit outputs the first pulse signal. When the pixel is in the second working mode, the NOR gate circuit outputs the second pulse signal.

[0073] Combine the following Figure 3The specific circuit structure of the pixel shown in the figure introduces the working process of the composite measurement circuit of the pixel in the first working mode. The image signal processor can send a first working mode control signal to the composite measurement circuit, and the first working mode control signal can include a first drive signal and a second drive signal. In the configuration signal receiving unit, the control end of the first switch (Q1) is used to receive the first drive signal, and the control end of the second switch (Q2) is used to receive the second drive signal. Among them, the first drive signal and the second drive signal are both fixed level signals. The first drive signal can drive the first switch (Q1) to be in an open state, and the second drive signal can drive the second switch (Q2) to be in an on state. Thereby, the first current (I) generated by the photodiode (PD) can be transmitted to the first pole of the first capacitor (CD) via the second switch (Q2).

[0074] The configuration signal receiving unit can keep the photoelectric conversion circuit connected to the integration unit under the control of the first drive signal and the second drive signal, so that the first current can be continuously input into the integration unit. The first capacitor (CD) can be an integrating capacitor. When the first electrode of the first capacitor (CD) is connected to the cathode of the photodiode (PD), the first capacitor (CD) integrates the first current (I), and the voltage (VFD) at the node VD changes. For convenience of introduction, the node VD is recorded as an integration node. The first capacitor (CD) integrates the first current (I), which is actually the first current (I) charging the first capacitor (CD).

[0075] The initial voltage of the integration node can be the same as the level of the ground, and the level of the comparison result signal output by the first comparator is the second level. When the configuration signal receiving unit outputs the first current to the integration unit, the first capacitor (CD) integrates the first current. When the first capacitor (CD) integrates the first current, the voltage (VFD) at the integration node increases. When the level at the integration node increases to the reference voltage, the level of the comparison result signal output by the first comparator is the third level. After a delay time, the voltage (VFD) at the integration node is reset to the initial level, so that the first capacitor (CD) starts a new integration process. At this time, the level of the comparison result signal output by the first comparator becomes the second level. In the embodiment of the present application, the first comparator outputs a low level, which can be regarded as the first comparator generating a reset valid level. It can be seen that in an integration process of the first capacitor (CD), the voltage (VFD) at the integration node increases from the initial voltage to the reference level, the first comparator outputs a low level, and after the voltage (VFD) at the integration node is reset to the initial voltage, the first comparator outputs a high level, so that the first comparator generates a pulse. The number of pulses output by the first comparator within a fixed time is the frequency of the pulses output by the first comparator. The frequency of the pulses output by the first comparator can represent the intensity information of the incident light. The image signal processor can encode the intensity information of the incident light using the pulse frequency output by the first comparator. Since the composite measurement circuit outputs a first pulse signal in the first working mode, the grayscale data has only 1 bit.

[0076] In the pixel provided in the embodiment of the present application, the greater the intensity of the incident light, the greater the first current generated, and the shorter the integration time of the first capacitor (CD) between the initial level and the reference level. Then the frequency at which the first comparator generates a reset valid level (that is, generates a pulse) within a certain period of time is higher. The image signal processor can count the number of valid reset levels output by the first comparator within a fixed time. This number can characterize the light intensity information of the incident light, that is, the intensity information of the incident light. This method of detecting the intensity of light in the frequency domain can also be called grayscale pulse imaging technology.

[0077] Combine the following Figure 3The specific circuit structure of the pixel shown in the figure is introduced for the working process of the composite measurement circuit in the second working mode. The image signal processor can send a second working mode control signal to the composite measurement circuit, and the second working mode control signal can include a third driving signal and a fourth driving signal. In the configuration signal receiving unit, the control terminal of the first switch (Q1) is used to receive the third driving signal, and the control terminal of the second switch (Q2) is used to receive the fourth driving signal. The third driving signal is used to drive the first switch (Q1), and the fourth driving signal is used to drive the second switch (Q2). Among them, both the third driving signal and the fourth driving signal are periodic signals. When the second switch (Q2) is in the on state, the first switch (Q1) is in the open state, and when the first switch (Q1) is in the on state, the second switch (Q2) is in the open state. In some examples, the third driving signal and the fourth driving signal can be a pair of inverted clock signals.

[0078] Both the third driving signal and the fourth driving signal provided by the image signal processor to the composite measurement circuit are periodic square wave signals, and the frequency is the same as that of the active light source. Driven by the third driving signal, the first switch (Q1) can be periodically in the on state. Driven by the fourth driving signal, the second switch (Q2) can be periodically in the on state. When the second switch (Q2) is on and the first switch (Q1) is off, the first current (I) is transmitted to the integration node. When the second switch (Q2) is off and the first switch (Q1) is on, the first current is all transmitted to the DR. Driven by the fourth driving signal, the second switch (Q2) alternates between the on state and the off state, having a gating effect. The fourth driving signal can be the aforementioned sampling signal, denoted as g(t). The sampling signal g(t) can drive the second switch (Q2) to alternately be in the on state and the off state. Figure 6 (a) in the figure exemplarily shows the waveform of the sampling signal during the duration corresponding to a period T, where both k0 and T are pre-configured constants. For example, in one period, when -k0 / 2 < t < k0 / 2, if the photoelectric conversion circuit generates the first current, the second switch (Q2) can transmit the first current to the first capacitor (CD). And at other times within one period T, if the photoelectric conversion circuit generates the first current, the second switch (Q2) will not transmit the first current to the first capacitor (CD). It should be noted that Figure 6 the sampling signal g(t) shown in (a) in the figure is used to illustrate the gating effect of the second switch (Q2) under the control of the fourth driving signal, and it is not a specific limitation on the sampling signal. In the actual application scenario, the sampling signal is a periodic signal, and in each period, the moment when the level in the sampling signal changes from low level to high level (referred to as the phase of the sampling signal in this application) is adjustable.

[0079] like Figure 6 As shown in (b), the light reflected by the target object after the active light signal is incident on the pixel. The light signal incident on the pixel is recorded as the incident light signal. The frequency of the incident light signal does not change relative to the active light signal, and is the same as the frequency of the active light signal. The phase and amplitude of the incident light signal may change, and may be different from the phase and amplitude of the active light signal. The fourth drive signal is a control signal for driving the second switch (Q2), and the high level period in the fourth drive signal is the period when the second switch (Q2) is in the on state. The low level period in the fourth drive signal is the period when the second switch (Q2) is in the off state. The second switch (Q2) has a gating effect under the control of the fourth drive signal. The first current (I) can only be transmitted to the first capacitor (CD) when the second switch (Q2) is in the on state, and the first capacitor (CD) is charged, so that photoelectrons are stored at the first capacitor (CD), and the first capacitor (CD) is integrated with the first current. Figure 6 The shaded portion of (b) is the time period corresponding to the first current being transmitted to the first capacitor (CD).

[0080] Within a preset number of cycles (such as cycle T of the fourth drive signal), the first capacitor (CD) integrates the first current in each cycle, and the total number of pulses output by the first comparator represents the integral value of the first current within the corresponding time within a preset number of cycles (such as hundreds of cycles).

[0081] The image signal processor can adjust the phase of the fourth driving signal, that is, the image signal processor can provide the fourth driving signal with multiple phase combinations, for example, four phase combinations, and any two phases of the four phase combinations are orthogonal.

[0082] Among them, the fourth drive signal can be the aforementioned sampling signal. The image signal processor provides a sampling signal to the second switch (Q2) to drive the second switch (Q2) to alternate between an on state and an off state. When the second switch (Q2) is in the on state, the first current is transmitted to the integration capacitor (CD), and when the second switch (Q2) is in the off state, the first current cannot be transmitted to the integration capacitor (CD). Under the control of the sampling signal, the second switch (Q2) is in the on state, so that the integration capacitor integrates the first current. This process can realize the cross-correlation processing of the sampling signal g(t) and the incident light signal s(t), and the processed signal can be represented by C(τ), and its mathematical expression is: k0 is a pre-configured constant.

[0083] The image signal processor provides multiple sampling signals with different phases. Figure 6In (c), the following is an example of multiple sampling signals g0(t), g1(t), g2(t), and g3(t). The phases of g0(t), g1(t), g2(t), and g3(t) can be 0, π, The image signal processor provides each sampling signal to the second switch (Q2) in a time-division manner. Figure 6 As shown in (c) in Figure 2, assuming that the incident light signal is phase Sampling signals of different phases play different gating roles. For example, in a period T, during the shaded portion of the waveform of the sampling signal g0(t), the second switch (Q2) transmits the first current to the first capacitor (CD). The duration of the second switch (Q2) transmitting the first current is During the period of the shaded portion of the waveform of the sampling signal g1(t), the second switch (Q2) transmits the first current to the first capacitor (CD). The duration of the second switch (Q2) transmitting the first current is During the period of the shaded portion of the waveform of the sampling signal g2(t), the second switch (Q2) transmits the first current to the first capacitor (CD). The duration of the second switch (Q2) transmitting the first current is When the sampling signal g3 (t) controls the second switch (Q2), the duration for which the second switch (Q2) transmits the first current is zero.

[0084] exist When the sampling signal is g0(t), the sampling signal is the cross-correlation function value of g0(t) and the incident light signal s(t) When the sampling signal is g1(t), the cross-correlation function value of the sampling signal g1(t) and the incident light signal s(t) is When the sampling signal is g2(t), the cross-correlation function value of the sampling signal g2(t) and the incident light signal s(t) is When the sampling signal is g3(t), the cross-correlation function value of the sampling signal g3(t) and the incident light signal s(t) is

[0085] When the sampling signal g0(t) is input, the second switch (Q2) is periodically in an on state under the control of the sampling signal g0(t), and the first comparator outputs a second pulse signal corresponding to the sampling signal g0(t), wherein, within a preset number of cycles (cycles of the sampling signal), the total number of pulses (the total number of rising edges) in the second pulse signal corresponding to the sampling signal g0(t) represents the cross-correlation function value C0 corresponding to the sampling signal g0(t), which is also the cross-correlation function value C0 corresponding to the phase of the sampling signal g0(t).

[0086] Similarly, when the sampling signal g1(t) is input, the second switch (Q2) is periodically in an on state under the control of the sampling signal g1(t), and the first comparator outputs a second pulse signal corresponding to the sampling signal g1(t), wherein, within a preset number of cycles (cycles of the sampling signal), the total number of pulses (the total number of rising edges) in the second pulse signal corresponding to the sampling signal g1(t) represents the cross-correlation function value C1 corresponding to the sampling signal g1(t), which is also the cross-correlation function value C1 corresponding to the phase of the sampling signal g1(t).

[0087] Similarly, when the sampling signal g2(t) is input, the second switch (Q2) is periodically in an on state under the control of the sampling signal g2(t), and the first comparator outputs a second pulse signal corresponding to the sampling signal g2(t), wherein, within a preset number of cycles (the cycle of the sampling signal), the total number of pulses (the total number of rising edges) in the second pulse signal corresponding to the sampling signal g2(t) represents the cross-correlation function value C2 corresponding to the sampling signal g2(t), which is also the cross-correlation function value C2 corresponding to the phase of the sampling signal g2(t).

[0088] Similarly, when the sampling signal g3(t) is input, the second switch (Q2) is periodically in an on state under the control of the sampling signal g3(t), and the first comparator outputs a second pulse signal corresponding to the sampling signal g3(t), wherein, within a preset number of cycles (cycles of the sampling signal), the total number of pulses (the total number of rising edges) in the second pulse signal corresponding to the sampling signal g3(t) represents the cross-correlation function value C3 corresponding to the sampling signal g3(t), which is also the cross-correlation function value C3 corresponding to the phase of the sampling signal g3(t).

[0089] The image signal processor can determine the cross-correlation function value corresponding to each sampling signal according to the second pulse signal corresponding to each received sampling signal, and determine the phase offset according to the cross-correlation function value corresponding to the sampling signal, wherein:

[0090] Please see again Figure 2 In order to facilitate resetting the voltage at the integration node, the composite measurement circuit may further include a reset switch (MRST), wherein the first end of the reset switch (MRST) is grounded, and the second end is coupled to the first end of the integration unit. The control end of the reset switch (MRST) is connected to the output end of the delay sampling unit. Figure 3, the second end of the reset switch (MRST) can be coupled to the first electrode of the first capacitor (CD), and the control end of the reset switch (MRST) can be coupled to the output end of the NOR gate circuit. The reset switch (MRST) can alternate between the on state and the off state under the control of the pulse signal output by the delay sampling unit. When the reset switch (MRST) is in the on state, the voltage at the first end of the integration unit can be reset to the initial voltage, that is, 0V. In other words, when the reset switch (MRST) is in the on state, the voltage at the integration node (VFD) can be reset to the initial voltage.

[0091] For example, when the D latch samples the falling edge (or negative pulse, i.e., the edge where the high level changes to the low level) of the first analog signal generated by the first comparator at the high level edge (rising edge) of the first clock signal (clk), the output level of the Q output terminal is low. During the low level period of the first clock signal (clk), when the output signal of the Q output terminal is low, the level of the first pulse signal output by the NOR gate circuit is high, which can drive the reset switch (MRST) to be turned on, so that the level at the integration node is reset and restored to the initial level, such as 0V.

[0092] For a possible design, see Figure 2 The composite measurement circuit may further include a readout unit. The readout unit is coupled to the delayed sampling unit and to the image signal processor. The readout unit may cache the signal output by the delayed sampling unit, such as the first pulse signal or the second pulse signal, under the drive of the storage signal (clr=0) provided by the image signal processor. Under the drive of the selection signal (sel) provided by the image signal processor, the cached signal is output to the image signal processor through the output end (out) of the readout unit; or under the drive of the reset signal (clr=1) provided by the image signal processor, the output signal to the image signal processor is reset.

[0093] For some examples, see Figure 3The readout unit may include a third switch (Q3), a fourth switch (Q4) and an RS latch. The first end of the third switch (Q3) may be coupled to the image signal processor as the output end (out) of the readout unit. Or the first end of the third switch (Q3) may be used as the output end (out) of the readout unit. The second end of the third switch (Q3) is coupled to the first pole of the fourth switch (Q4), and the control end of the third switch (Q3) is used to receive the selection signal (sel), and the selection signal is used to drive the third switch (Q3) to be in a conducting state. The second pole of the fourth switch (Q4) is grounded, and the control end of the fourth switch (Q4) is coupled to the Q output end of the RS latch. The reset end (R) of the RS latch is coupled to the image signal processor and can be used to receive the storage signal or the reset signal (clr=1). The set end (S) of the RS latch is coupled to the output end of the NOR gate circuit and is used to receive the first pulse signal or the second pulse signal.

[0094] The RS latch has the function of recording the level. The image signal processor can provide a storage signal to the reset terminal (R) of the RS latch to drive the recording level function of the RS latch. The storage signal can be a fixed level signal, and the level of the storage signal (clr=0) can be a low level (0), so that the RS latch can latch the level of the positive pulse (rising edge) of the signal at the set terminal (S) (that is, the first pulse signal). When the level at the set terminal (S) changes from a low level to a high level, the RS latch latches the level of the set terminal (S), and the level state of the Q output terminal of the RS latch is a high level, and the output high level is maintained.

[0095] The image signal processor can provide a reset signal to the reset terminal (R) of the RS latch to drive the RS latch to reset, so that the initial output of the RS latch is 0. The reset signal can be a fixed level signal, and the level of the reset signal (clr=1) can be a high level (1), so that the output level state of the RS latch is a low level, so that when the image signal processor sends a storage signal to the RS latch, the RS latch can record the level. Figure 7 A circuit diagram of an RS latch is shown according to an exemplary embodiment.

[0096] The control end of the fourth switch (Q4) is coupled to the Q output end of the RS latch. The Q output end of the RS latch outputs a high level, which can drive the fourth switch (Q4) to turn on. The Q output end of the RS latch outputs a low level, which can drive the fourth switch (Q4) to turn off. Therefore, after the RS latch records the high level of the first pulse signal, the fourth switch (Q4) is turned on.

[0097] The image signal processor provides a selection signal (sel) to the third switch (Q3), so that the third switch (Q3) is in a conducting state under the drive of the selection signal (sel), so that the fourth switch (Q4) can be connected to the image signal processor. The fourth switch (Q4) can be coupled to a bus pull-up resistor.

[0098] If the third switch (Q3) is in a conducting state under the drive of the selection signal (sel), when the fourth switch (Q4) is turned on, the first end of the third switch (Q3) (which can also be regarded as the output end of the pixel) has a level output. When the fourth switch (Q4) is disconnected, the first end of the third switch (Q3) has no level output. If the image signal processor does not provide the selection signal (sel) to the third switch (Q3), the third switch (Q3) is in an open circuit state, and the first end of the third switch (Q3) has no level output.

[0099] In the first working mode, the pixel provided by the embodiment of the present application can provide information on light intensity changes. However, when the position of the object being measured or the state of the object changes, the intensity of the light incident on the pixel also changes accordingly. Based on this, in a possible implementation, the pixel provided by the embodiment of the present application can also include a dynamic visual measurement circuit. Please refer to Figure 8 The dynamic vision measurement circuit can be coupled to the photoelectric conversion circuit, and the dynamic vision measurement circuit can provide the image signal processor with information about the change in the light intensity of the incident light based on the first current generated by the photoelectric conversion circuit. The dynamic vision measurement circuit can perform logarithmic compression on the light intensity of the incident light to perceive the change in the object being measured, that is, to perceive the image point with drastic changes.

[0100] Please see again Figure 8 , the embodiment of the present application may also include a current mirror circuit. The composite measurement circuit is coupled to the photoelectric conversion circuit through the current mirror circuit. The current mirror circuit can provide the composite measurement circuit with the current generated by the photoelectric conversion circuit. Such a design can achieve that the first current generated by the photoelectric conversion circuit is used simultaneously by two circuits, namely the composite measurement circuit and the dynamic vision measurement circuit. And the current mirror circuit can increase the isolation between the composite measurement circuit and the dynamic vision measurement circuit, and reduce the influence between the composite measurement circuit and the dynamic vision measurement circuit.

[0101] For a possible implementation, see Fig. 9 The dynamic vision measurement circuit may include a light receiving stage, a driving stage, an amplifying stage, a comparing stage, and a responding circuit. The light receiving stage may convert the first current into a logarithmic domain. For some examples, see Fig.10, the light receiving stage includes a fifth switch (M1), a sixth switch (M2) and a seventh switch (M3). The first end of the fifth switch (M1) is coupled to the cathode of the photodiode, and the second end of the fifth switch (M1) is coupled to the current mirror circuit. The control end of the fifth switch (M1) is coupled to the first end of the sixth switch (M2), and the second end of the sixth switch (M2) is coupled to the fourth power supply level (VDD2). Exemplarily, the voltage of the fourth power supply level (VDD2) can be 1.8V. The control end of the sixth switch (M2) is coupled to a preset fixed level (Vb1). The first end of the seventh switch (M3) is coupled to the control end of the fifth switch (M1), and to the first end of the sixth switch (M2). The second end of the seventh switch (M3) is grounded, and the control end of the seventh switch (M3) is coupled to the cathode of the photodiode (PD). The output end of the light receiving stage, i.e., the first end of the sixth switch (M2), is connected to a virtual ground under the action of negative feedback. The subthreshold region characteristics of the fifth switch (M1) make the voltage (VQ) at the output end of the light receiving stage and the first current I have a logarithmic relationship, such as lnI.

[0102] The driver stage can increase the isolation between the amplifier stage and the light receiving stage, and the driver stage is used to provide the first current in the logarithmic domain to the amplifier stage. For some examples, see Fig.10 The driving stage (also referred to as the source follower stage) may include an eighth switch (M4) and a ninth switch (M5). The first end of the eighth switch (M4) is coupled to the fourth power supply level (VDD2), and the second end of the eighth switch (M4) is coupled to the first end of the ninth switch (M5). The control end of the eighth switch (M4) is coupled to a preset fixed level (Vb3). The second end of the ninth switch (M5) is grounded, and the control end of the ninth switch (M5) is coupled to the control end of the fifth switch (M1).

[0103] The amplifier stage can include a capacitive feedback circuit to amplify a small varying signal. For some examples, see Fig.10 The amplifier stage may include a second capacitor (C1), a third capacitor (C2), a tenth switch (M6), an eleventh switch (M7) and a twelfth switch (M8). The first electrode of the second capacitor (C1) is coupled to the second end of the eighth switch (M4), the second electrode of the second capacitor (C1) is coupled to the first electrode of the third capacitor (C2), the second electrode of the second capacitor (C1) is coupled to the first end of the tenth switch (M6), and the second electrode of the second capacitor (C1) is coupled to the control end of the eleventh switch (M7).

[0104] The second end of the tenth switch (M6) is coupled to the second electrode of the third capacitor (C2), the second end of the tenth switch (M6) is coupled to the first end of the eleventh switch (M7), and the second end of the tenth switch (M6) is coupled to the first end of the twelfth switch (M8). The control end of the tenth switch (M6) is coupled to the image signal processor to receive the amplification control signal (RST_N). The amplification control signal (RST_N) can be provided by the response circuit in the dynamic vision measurement circuit. The second end of the eleventh switch (M7) is coupled to the fourth power supply level (VDD2). The second end of the twelfth switch (M8) is grounded, and the control end of the twelfth switch (M8) receives the fixed level VO.

[0105] The capacitor feedback circuit formed by the second capacitor (C1), the third capacitor (C2), the tenth switch (M6), the eleventh switch (M7) and the twelfth switch (M8) amplifies the changing small signal by C1 / C2 times, and superimposes it on the reset DC bias voltage to change the voltage of the second electrode of the third capacitor (C2). The second electrode of the third capacitor (C2) can also be used as the output end (VC) of the amplifier stage.

[0106] For some examples, see Fig.10 , the comparison stage may include a thirteenth switch (M9), a fourteenth switch (M10), a fifteenth switch (M11) and a sixteenth switch (M12). The first end of the thirteenth switch (M9) is coupled to the second power supply level, the second end of the thirteenth switch (M9) is coupled to the first end of the fourteenth switch (M10), and the control end of the thirteenth switch (M9) is coupled to the second electrode of the third capacitor (C2). The second end of the fourteenth switch (M10) is grounded, and the control end of the fourteenth switch (M10) receives a fixed level VN. Among them, the second end of the thirteenth switch (M9) is the first output end ON of the comparison stage.

[0107] The first end of the fifteenth switch (M11) is coupled to the second power supply level, the second end of the fifteenth switch (M11) is coupled to the first end of the sixteenth switch (M12), and the control end of the fifteenth switch (M11) is coupled to the second electrode of the third capacitor (C2). The second end of the sixteenth switch (M12) is grounded, and the control end of the sixteenth switch (M12) receives a fixed voltage level VP. The second end of the fifteenth switch (M11) is the second output end OFF of the comparison stage.

[0108] Optionally, the eleventh switch (M7), the thirteenth switch (M9), and the fifteenth switch (M11) are PMOS tubes of the same size. The twelfth switch (M8), the fourteenth switch (M10), and the sixteenth switch (M12) are NMOS tubes of the same size. The fixed voltage level VN received by the control end of the fourteenth switch (M10) is greater than the fixed voltage level VO received by the control end of the twelfth switch (M8), and the fixed voltage level VP received by the control end of the sixteenth switch (M12) is less than the fixed voltage level VO received by the control end of the twelfth switch (M8).

[0109] When the amplification control signal (RST_N) is at a low level (0), the tenth switch (M6) is in a conducting state. The level of the output terminal (VC) of the amplifier stage is restored to a preset reset level, at which time the first output terminal ON of the comparison stage outputs a low level (0), and the second output terminal OFF outputs a high level (1).

[0110] When the level of the amplifier stage output terminal (VC) shifts from the reset level to the positive to cancel the current source mismatch caused by the difference between the fixed level VP and the comparison threshold BIAS, the second output terminal OFF outputs a low level (0). When the level of the amplifier stage output terminal (VC) shifts from the reset level to the negative to cancel the current source mismatch caused by the difference between the fixed level VN and the comparison threshold BIAS, the first output terminal ON outputs a high level (1). Based on the preset comparison threshold BIAS, fixed level VP, fixed level VN, and fixed level VO, the above process can be realized.

[0111] The dynamic vision measurement circuit may further include a response circuit, which may receive the level of the first output terminal ON and the second output terminal OFF of the comparison stage, and latch the level of the first output terminal ON and the level of the second output terminal OFF. The response circuit may generate a request signal (REQ) based on the level of the first output terminal ON and the level of the second output terminal OFF of the comparison stage, and the generation of the request signal (REQ) may indicate that a change in light intensity has occurred. For example, when the first output terminal ON of the comparison stage is at a high level (1) and the second output terminal OFF of the comparison stage is at a low level (0), the response circuit may generate the request signal (REQ), and / or, when the first output terminal ON of the comparison stage is at a low level (0), the second output terminal OFF of the comparison stage is at a high level (1), and the second output terminal OFF of the comparison stage is at a low level (0), the response circuit may generate the request signal (REQ).

[0112] When the dynamic vision measurement circuit is in the initial state, the first output terminal ON of the comparison stage outputs a low level (0), and the second output terminal OFF outputs a high level (1). If the first current of the incident light increases, the level of the output terminal (VC) of the amplifier stage decreases, the first output terminal ON of the comparison stage outputs a high level (1), and the second output terminal OFF outputs a high level (1). If the first current of the incident light decreases, the first output terminal ON of the comparison stage outputs a low level (0), and the second output terminal OFF outputs a low level (0).

[0113] The response circuit is coupled to the image signal processor and sends a request signal (REQ) to the image signal processor. When the level of the first output terminal ON of the comparison stage changes from a low level to a high level, the response circuit sends a request signal (REQ) to the image signal processor. And when the level of the second output terminal OFF of the comparator changes from a high level to a low level, the response circuit sends a request signal (REQ) to the image signal processor so that the image signal processor is informed of the light intensity change event. When a dynamic event (such as light intensity change) occurs, the rise or fall of the output level is accelerated.

[0114] In some examples, the response circuit may include logic circuits such as a NAND gate, a NOR gate, and a NOT gate, and adopt a standard CMOS digital push-pull structure to implement the above functions. Fig.11 As shown, the response circuit can receive the level provided by the first output terminal ON of the comparison stage and the level provided by the second output terminal OFF of the comparison stage. The response circuit can receive the response signal (ACK) and the reset dynamic measurement signal (RST) provided by the image signal processor. The reset dynamic measurement signal (RST) can drive the dynamic vision measurement circuit to restore the initial state and wait for the next change event. The tenth switch in the comparison stage of the aforementioned dynamic vision measurement circuit receives the amplification control signal (RST_N), which is the inverted signal of the reset dynamic measurement signal (RST).

[0115] like Fig.11 As shown, the response circuit has multiple output terminals, output terminal CON and output terminal COFF. In the initial state of the response circuit, the level of output terminal CON is low level (0), and the level of output terminal COFF is low level (0). When a dynamic event occurs, if the level of output terminal CON is high level (1) and the level of output terminal COFF is low level (0), it indicates that the light intensity has a positive change (that is, the light intensity increases). If the level of output terminal CON is low level (0) and the level of output terminal COFF is high level (1), it indicates that the light intensity has a negative change (that is, the light intensity decreases). The image signal processor can determine the light intensity change through the level of output terminal CON and output terminal COFF.

[0116] For easy introduction, such as Fig.11As shown, the input terminal of the response circuit receiving the reset dynamic measurement signal (RST) is recorded as the input terminal RST. The input terminal of the response circuit receiving the response signal (ACK) is recorded as the input terminal ACK. The input terminal connected to the first output terminal ON of the comparison stage in the response circuit is recorded as the input terminal ON, and the input terminal connected to the second output terminal OFF of the comparison stage in the response circuit is recorded as the input terminal OFF.

[0117] The response circuit may include multiple switches and multiple inverters. The multiple switches are respectively recorded as switch S1, switch S2, ..., switch S14. The multiple inverters are respectively recorded as inverter NG1, inverter NG2 and inverter NG3. Among them, the first end of switch S1 is coupled to the power supply level, the second end of switch S1 is coupled to the first end of switch S2, and the control end of switch S1 is coupled to the input end RST. The second end of switch S2 is coupled to the input end ON, and is coupled to the first end of switch S3, the control end of switch S2 is coupled to the output end of inverter NG2, and the input end of inverter NG2 is coupled to the input end ON. The second end of switch S3 is grounded, and the control end of switch S3 is coupled to the input end RST. The level at the output end of inverter NG2 is recorded as NON.

[0118] The first end of the switch S4 is coupled to the power supply level, the second end of the switch S4 is coupled to the first end of the switch S5, and is coupled to the input end OFF. The input end of the inverter NG1 is coupled to the input end RST, and the output end of the inverter NG1 is coupled to the control end of the switch S4. The level at the output end of the inverter NG1 is recorded as RST_N. The second end of the switch S5 is coupled to the first end of the switch S6. The input end of the inverter NG3 is coupled to the input end OFF, and the output end of the inverter NG3 is coupled to the control end of the switch S5. The level at the input end of the inverter NG3 is recorded as NOFF. The second end of the switch S6 is grounded, and the control end of the switch S6 is coupled to the output end of the inverter NG1.

[0119] A first end of the switch S7 is coupled to the input terminal ON, a second end of the switch S7 is grounded, and a control end of the switch S7 is coupled to the output end of the inverter NG3. A first end of the switch S8 is coupled to the power supply level, a second end of the switch S8 is coupled to the input terminal OFF, and a control end of the switch S8 is coupled to the output end of the inverter NG2.

[0120] The first end of switch S9 is coupled to the output terminal REQ, the second end of switch S9 is grounded, and the control end of switch S9 is coupled to the input terminal ON. The first end of switch S10 is coupled to the output terminal REQ, the second end of switch S10 is grounded, and the control end of switch S10 is coupled to the output end of inverter NG3.

[0121] The first end of the switch S11 is grounded, the second end of the switch S11 is coupled to the first end of the switch S12, the control end of the switch S11 is coupled to the input end ON, the second end of the switch S12 is coupled to the output end CON, and the control end of the switch S12 is coupled to the input end ACK.

[0122] The first end of switch S13 is grounded, the second end of switch S13 is coupled to the first end of switch S14, the control end of switch S13 is coupled to the output end of inverter NG3, the second end of switch S14 is coupled to the output end COFF, and the control end of switch S14 is coupled to the input end ACK.

[0123] The switches S13 and S14 can be in a conducting state under the driving of the response control signal received by the input terminal ACK, so that the second end of the switch S11 is connected to the output terminal CON, and the second end of the switch S13 is connected to the output terminal COFF. If the level at the input terminal ON can drive the switch S11 to be turned on, the output terminal CON outputs a high level (1). If the level at the input terminal ON cannot drive the switch S11 to be turned on, the output terminal CON outputs a low level (0).

[0124] In a possible implementation, Fig.12 As shown, the current mirror circuit may include a seventeenth switch (M13), an eighteenth switch (M14), a nineteenth switch (M15), a twentieth switch (M16), and a switch MBIAS. The first end of the seventeenth switch (M13) is coupled to the second power supply level (VDD1), the second end of the seventeenth switch (M13) is coupled to the first end of the eighteenth switch (M14), and the control end of the seventeenth switch (M13) is also coupled to the first end of the eighteenth switch (M14). The second end of the eighteenth switch (M14) is coupled to the first end of the switch MBIAS, and the control end of the eighteenth switch (M14) is also coupled to the first end of the switch MBIAS. The second end of the switch MBIAS is coupled to the second end of the fifth switch (M1) in the dynamic vision measurement circuit, and the control end of the switch MBIAS is coupled to the bias level BIAS. The first end of the nineteenth switch (M15) is coupled to the second power supply level (VDD1), the second end of the nineteenth switch (M15) is coupled to the first end of the twentieth switch (M16), and the control end of the nineteenth switch (M15) is coupled to the control end of the seventeenth switch (M13). The second end of the twentieth switch (M16) is coupled to the second end of the first switch in the composite measurement circuit. The control end of the twentieth switch (M16) is coupled to the control end of the eighteenth switch (M14). In such a design, the first current is copied to the composite measurement circuit by using a current mirror circuit. And the switch MBIAS can shield the coupling interference of the service current of the composite measurement circuit to the dynamic vision measurement circuit.

[0125] Based on the pixels provided in any of the above embodiments, the present application also provides an image sensor, which may include a plurality of pixels arranged in an array and an image signal processor. The square in the figure represents the pixels provided in the present application. Fig.13 , the image processor may include a column selection unit. As an example, the image sensor may include n rows and m columns of pixels. The control end of the first switch (Q1) in the configuration signal receiving unit of the pixels in the nth row is coupled to the nth first configuration signal terminal (TXD) of the column selection unit, and the control end of the second switch (Q2) in the configuration signal receiving unit of the pixels in the nth row is coupled to the nth second configuration signal terminal (TX) of the column selection unit. The first configuration signal terminal of the column selection unit is used to provide the aforementioned first drive signal or the third drive signal. The second configuration signal terminal of the column selection unit is used to provide the aforementioned second drive signal or the fourth drive signal. The timing control input end of the D latch in the delay sampling unit of the pixels in the nth row is coupled to the nth clock signal output terminal of the column selection unit. The second input end of the NOR gate circuit in the delay sampling unit of the pixels in the nth row is coupled to the nth clock signal output terminal of the column selection unit. The clock signal output terminal of the column selection unit is used to output the aforementioned first clock signal (clk). The reset end of the RS latch of the readout unit of the pixels in the nth row is coupled to the nth reset signal terminal of the column selection unit. The reset signal terminal of the column selection unit is used to output the aforementioned reset signal (clr).

[0126] The first end of the third switch (Q3) of the readout unit of the pixel in the mth column is coupled to the mth column data bus, and the image signal processor can receive the data output by the pixel in the mth column via the mth column grayscale data bus. The readout signal terminal of the column selection unit is used to output the aforementioned selection signal (sel). The control end of the third switch (Q3) of the readout unit of the pixel in the nth row is coupled to the nth readout signal terminal of the column selection unit. Driven by the readout signal of the column selection unit, the pixels in the nth row output data to the grayscale data bus coupled to the column where each pixel is located.

[0127] From the above introduction, it can be seen that all pixels in the nth row can share five control signals provided by the column selection unit, namely, the selection signal (sel), the reset signal (clr), the first clock signal (clk), the signal (TXD) provided by the first configuration signal terminal, and the signal (TX) provided by the second configuration signal terminal. Among them, the signal (TXD) provided by the first configuration signal terminal and the signal (TX) provided by the second configuration signal terminal can be used to configure the working mode of the composite measurement circuit. After completing an integration process and resetting from the threshold voltage to the initial voltage, the composite measurement circuit will output a pulse, which is sampled multiple times by the first clock signal (clk) and the selection signal (sel) within a fixed period of time. After each sampling, it is cleared to zero with the reset signal (clr). The frequency of the pulse generated by counting can encode the size of the light intensity. Therefore, the grayscale data of the pixel is only one bit, and the column selection unit scans row by row and outputs the pulse data OUT upward.

[0128] Please see again Fig.13 In one possible implementation, each pixel in the image sensor includes a dynamic vision measurement circuit. The image signal processor may further include a row selection unit (also referred to as a dynamic vision measurement synchronization arbitrator). The input terminal RST of the pixels in the nth row is coupled to the nth reset dynamic measurement signal terminal of the row selection unit. The reset dynamic measurement signal terminal of the row selection unit is used to output the aforementioned reset dynamic measurement signal (RET). The input terminal ACK of the pixels in the nth row is coupled to the nth response control signal terminal of the row selection unit. The response control signal terminal of the row selection unit is used to output the aforementioned response control signal (ACK).

[0129] The output terminal REQ of the pixels in the nth row is coupled to the nth time request signal terminal of the row selection unit, and the request signal terminal of the row selection unit is coupled to receive the aforementioned request signal (REQ).

[0130] The output terminal CON of the pixels in the mth column is coupled to the image processor through the first dynamic event data bus, and the output terminal COFF of the pixels in the mth column is coupled to the image processor through the second dynamic event data bus. Driven by the response control signal (ACK), the pixels in the nth row output light intensity change data to the first dynamic event bus and the second dynamic event bus coupled to the column where each pixel is located.

[0131] Assuming that when the pixels in the i-th row generate a light intensity change event, a request signal (REQ) is sent to the row selection unit (arbitrator), and the row selection unit (arbitrator) sends an acknowledgement signal (ACK) to the pixels in the i-th row, so that the pixels in the i-th row transmit two bits of data (the level of the pixel output terminal CON and the level of the output terminal COFF) to the first dynamic event bus and the second dynamic event bus. After a delay time, the row selection unit (arbitrator) sends a reset signal (RST) to the pixels in the i-th row, so that the dynamic vision measurement circuit in the pixels in the i-th row returns to the initial state and waits for the next change time.

[0132] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A pixel of an image sensor, characterized in that: include: a photoelectric conversion circuit for generating a first current based on incident light incident on the pixel; The composite measuring circuit is coupled with the photoelectric conversion circuit to: When the pixel operates in a first operating mode, a first pulse signal is generated based on the first current, wherein the first pulse signal represents the intensity information of the incident light; When the pixel operates in the second operating mode, a plurality of sampling signals are received, and a plurality of second pulse signals are generated based on the first current and the plurality of sampling signals; wherein the plurality of sampling signals correspond to the plurality of second pulse signals one by one, and the plurality of second pulse signals are used to characterize a phase offset between a phase of the incident light and a set phase, and the incident light is light reflected by the light of the set phase incident on a target object; The composite measurement circuit includes a configuration signal receiving unit, an integration unit, a comparison unit, and a delay sampling unit; The first end of the configuration signal receiving unit is coupled to the photoelectric conversion circuit; the second end of the configuration signal receiving unit is coupled to the first end of the integration unit and to the input end of the comparison unit; the configuration signal receiving unit is used to: in the first working mode, output the first current to the integration unit; In the second working mode, the plurality of sampling signals are received, and based on signal periods of the plurality of sampling signals, the first current is periodically output to the integration unit.

2. The pixel according to claim 1, wherein: The photoelectric conversion circuit includes a photodiode; The anode of the photodiode is coupled to a first power supply level; the cathode of the photodiode is coupled to the composite measurement circuit and to a second power supply level; and the second power supply level is greater than the first power supply level.

3. The pixel according to claim 1 or 2, characterized in that The second end of the integration unit is coupled to the first level, and the integration unit is used to integrate the first current to obtain a measurement voltage, and provide the measurement voltage to the comparison unit; The input end of the comparison unit is coupled to the first end of the integration unit, and is used to: compare the measurement voltage with a preset reference voltage, and send a comparison result signal to the delay sampling unit, wherein when the measurement voltage is less than the reference level, the level of the comparison result signal is a second level, and when the measurement voltage is greater than or equal to the reference level, the level of the comparison result signal is a third level, and the second level is greater than the third level; The delayed sampling unit is coupled to the output end of the comparison unit; the delayed sampling unit is used to: perform sampling processing on the comparison result signal to generate the first pulse signal or the multiple second pulse signals.

4. The pixel according to claim 3, characterized in that The configuration signal receiving unit includes a first switch and a second switch; The first end of the first switch is coupled to a third power supply level, the second end of the first switch is coupled to the photoelectric conversion circuit, the second end of the first switch is coupled to the first end of the second switch, the second end of the second switch is coupled to the first end of the integration unit, and the third power supply level is less than the second power supply level; When the first switch is in an open state and the second switch is in an open state, the first current is transmitted to the integration unit; when the first switch is in an open state and the second switch is in an open state, the first current is transmitted to the third power supply level.

5. The pixel according to claim 4, characterized in that In the first working mode, the control end of the first switch receives a first driving signal, where the first driving signal is a fixed level signal and is used to drive the first switch to an open circuit state; The control end of the second switch receives a second driving signal, where the second driving signal is a fixed level signal and is used to drive the second switch to be in a conducting state.

6. The pixel according to claim 4, characterized in that In the second working mode, the control end of the first switch receives a third driving signal; the third driving signal is a periodic signal, and the first switch is used to control the first switch to alternate between an on state and an off state according to the period of the third driving signal; The control end of the second switch receives the plurality of sampling signals; wherein any one of the sampling signals is a periodic signal, and the second switch is used to control the second switch to alternate between an on state and an off state according to the period of each sampling signal; When the second switch is in the on state, the first switch is in the off state, and when the first switch is in the on state, the second switch is in the off state.

7. The pixel according to claim 3, wherein: The integration unit includes a first capacitor; a first electrode of the first capacitor is coupled to the photoelectric conversion circuit through a second switch, and a second electrode of the first capacitor is coupled to the first level.

8. The pixel according to claim 3, wherein: The comparison unit includes a comparator; The first input terminal of the comparator is coupled to the first terminal of the integration unit for receiving the measurement voltage; The second input terminal of the comparator is coupled to the reference voltage; The output end of the comparator is coupled to the delayed sampling unit and is used to output the comparison result signal.

9. The pixel according to claim 3, characterized in that The delayed sampling unit includes a D latch and a NOR gate circuit; The data input terminal of the D latch is coupled to the output terminal of the comparator for receiving the comparison result signal; The timing control input terminal of the D latch is used to receive a first clock signal; The Q output terminal of the D latch is coupled to the first input terminal of the NOR circuit, and is used to output a signal to the NOR circuit; The second input terminal of the NOR gate circuit is used to receive the first clock signal; The output end of the NOR gate circuit is coupled to an image signal processor and is used to output the first pulse signal or the second pulse signal.

10. The pixel according to claim 3, wherein: The composite measurement circuit further includes a reset switch; a first end of the reset switch is grounded, and a second end is coupled to the first end of the integration unit; a control end of the reset switch is coupled to the delay sampling unit for receiving the first pulse signal; During a period when the level of the first pulse signal is at a fourth level, the reset switch is in an off-circuit state; during a period when the level of the first pulse signal is at a fifth level, the reset switch is in an on-state, so that the voltage at the first end of the integration unit is a reset voltage; wherein the fourth level is greater than the fifth level.

11. The pixel according to claim 3, wherein: The composite measurement circuit further includes a readout unit; the readout unit is coupled to the delayed sampling unit and coupled to the image signal processor; The readout unit is used for: receiving a storage signal provided by the image signal processor, and buffering the first pulse signal or the second pulse signal according to the storage signal; A scanning signal provided by the image signal processor is received, and a buffered signal is output to the image signal processor according to the scanning signal.

12. The pixel according to claim 11, wherein: The readout unit includes a third switch, a fourth switch and an RS latch; The first end of the third switch is coupled to the image signal processor; the second end of the third switch is coupled to the first pole of the fourth switch; the control end of the third switch is used to receive the scanning signal provided by the image signal processor, wherein the scanning signal is used to drive the third switch to be in a conducting state; A second electrode of the fourth switch is grounded, and a control terminal of the fourth switch is coupled to a Q output terminal of the RS latch; The reset end of the RS latch is coupled to the image signal processor for receiving the storage signal or the reset signal provided by the image signal processor. The set end of the RS latch is coupled to the output end of the delay sampling unit for receiving the first pulse signal, and the level at the Q output end of the RS latch is the same as the level of the first pulse signal, or receiving the second pulse signal, and the level at the Q output end of the RS latch is the same as the level of the second pulse signal.

13. The pixel according to claim 1, wherein: The pixel further includes a dynamic visual measurement circuit; the dynamic visual measurement circuit is coupled to the photoelectric conversion circuit and to an image signal processor, and is used to: Based on the first current, an indication level signal is generated and sent to the image signal processor, wherein the indication level signal represents light intensity change information of the incident light.

14. The pixel according to claim 13, wherein: The pixel further includes a current mirror circuit; the composite measurement circuit is coupled to the photoelectric conversion circuit via the current mirror circuit; The current mirror circuit is used to provide the first current generated by the photoelectric conversion circuit to the composite measurement circuit.

15. An image sensor, characterized in that: include: An array of multiple pixels, at least one pixel is a pixel as described in any one of claims 1-14.

16. The sensor according to claim 15, characterized in that Also included is an image signal processor; the image signal processor is coupled to the composite measurement circuit; The image signal processor is used for: Controlling a target pixel to be in a first working mode, wherein the target pixel is any one of the at least one pixel; A first pulse signal is received, and intensity information of incident light incident on the target pixel is determined according to the frequency of the first pulse signal.

17. The sensor according to claim 16, characterized in that The image signal processor is further used for: Controlling the target pixel to be in a second working mode, and sending a plurality of sampling signals corresponding to the plurality of phases to the target pixel in sequence according to the plurality of preset phases, wherein the plurality of phases correspond to the plurality of sampling signals one by one; Receiving a plurality of second pulse signals, wherein the plurality of sampling signals correspond one to one to the plurality of second pulse signals; According to each of the plurality of second pulse signals, a phase offset between a phase of incident light incident on the target pixel and a set phase is determined, wherein the incident light is light reflected by the target object when the light of the set phase is incident on the target object.

18. The sensor according to claim 17, characterized in that The image signal processor is specifically used for: Determine the number corresponding to each second pulse signal, wherein the number corresponding to each second pulse signal is the number of rising edges in each second pulse signal within a preset time length; Determining the phase offset based on the number of second pulse signals; The distance between the target pixel and the target object is determined according to the phase offset.

Images