Pixel signal output circuit and image sensor

Abstract

The application discloses a pixel signal output circuit and an image sensor, and belongs to the technical field of image sensing, wherein a pixel signal is output through a pixel circuit; an additional current generation circuit outputs an additional current according to the voltage of the pixel signal when the voltage of the pixel signal is less than a preset voltage; a current mirror circuit mirrors the additional current to output a superimposed current; a switch circuit is connected with a control signal and outputs the superimposed current based on the control signal; a current source superimposes the superimposed current on an initial current of the current source to form a superimposed composite current; and based on the composite current, the pixel circuit accelerates the establishment speed of the pixel signal; due to the superimposed current introduced in the current source, the output voltage of the pixel circuit is rapidly pulled down to accelerate the establishment of the pixel signal, the time required for establishment when the pixel signal changes is reduced, the single-row readout time is shortened, and the overall frame rate is improved.

Description

Technical Field

[0001] This application belongs to the field of image sensing technology, and particularly relates to a pixel signal output circuit and an image sensor. Background Technology

[0002] The current method of pixel signal output involves connecting the row selection transistor in the pixel circuit to the cascaded current source in the column readout circuit to form an effective pixel signal output. After the pixel signal is established, the subsequent circuitry performs analog-to-digital conversion. However, due to the long pixel signal output trace, the capacitive and resistive loads at this node are large, resulting in a longer setup time when the pixel signal changes. This is detrimental to reducing the single-line readout time and improving the overall frame rate. Summary of the Invention

[0003] The purpose of this application is to provide a pixel signal output circuit and an image sensor, which aims to solve the problem that the related pixel signal output circuit cannot shorten the readout time and improve the overall frame rate.

[0004] This application provides a pixel signal output circuit, including:

[0005] Pixel circuit, configured to output pixel signals;

[0006] An additional current generation circuit, connected to the pixel circuit, is configured to output an additional current based on the voltage of the pixel signal when the voltage of the pixel signal is less than a preset voltage.

[0007] A current mirror circuit, connected to the additional current generating circuit, is configured to mirror the additional current to output a superimposed current.

[0008] A switching circuit, connected to the current mirror circuit, is configured to receive a control signal and output the superimposed current based on the control signal;

[0009] A current source, connected to the pixel circuit and the switching circuit, is configured to superimpose the superimposed current onto the initial current of the current source to form a superimposed composite current.

[0010] Based on the composite current, the pixel circuit accelerates the establishment speed of the pixel signal.

[0011] In one embodiment, the current source includes a first field-effect transistor and a second field-effect transistor;

[0012] The drain of the first field-effect transistor is connected to the pixel signal output terminal of the pixel circuit to output the composite current;

[0013] The source of the first field-effect transistor and the drain of the second field-effect transistor are used together as the superimposed current input terminal of the current source and connected to the switching circuit to receive the superimposed current.

[0014] The gate of the first field-effect transistor serves as the first bias voltage input terminal of the current source, and is connected to the first bias voltage; the gate of the second field-effect transistor serves as the second bias voltage input terminal of the current source, and is connected to the second bias voltage.

[0015] The source of the second field-effect transistor is connected to the power supply ground.

[0016] In one embodiment, the additional current generating circuit includes a fifth field-effect transistor;

[0017] The source of the fifth field-effect transistor is connected to the first power supply;

[0018] The gate of the fifth field-effect transistor serves as the pixel signal voltage input terminal of the additional current generation circuit, and is connected to the pixel circuit and the current source to receive the voltage of the pixel signal.

[0019] The drain of the fifth field-effect transistor serves as the additional current output terminal of the additional current generation circuit and is connected to the current mirror circuit to output the additional current.

[0020] In one embodiment, the current mirror circuit includes a third field-effect transistor and a fourth field-effect transistor;

[0021] The drain of the third field-effect transistor serves as the superimposed current output terminal of the current mirror circuit and is connected to the switching circuit to output the superimposed current.

[0022] The drain of the fourth field-effect transistor, the gate of the fourth field-effect transistor, and the gate of the third field-effect transistor together serve as the additional current input terminal of the current mirror circuit, and are connected to the additional current generation circuit to receive the additional current.

[0023] The source of the third field-effect transistor and the source of the fourth field-effect transistor are connected to the power supply ground.

[0024] In one embodiment, the switching circuit includes a sixth field-effect transistor;

[0025] The gate of the sixth field-effect transistor serves as the control signal input terminal of the switching circuit, so as to receive the control signal;

[0026] The source of the sixth field-effect transistor serves as the current input terminal of the switching circuit to connect to the superimposed current.

[0027] The drain of the sixth field-effect transistor serves as the current output terminal of the switching circuit to output the superimposed current.

[0028] In one embodiment, the current mirror circuit includes a seventh field-effect transistor and a first to an nth current mirror field-effect transistor;

[0029] The drain of the first current mirror field-effect transistor to the drain of the nth current mirror field-effect transistor serve as the superimposed current output terminal of the current mirror circuit, and are connected to the switching circuit to output the superimposed current.

[0030] The drain of the seventh field-effect transistor, the gate of the seventh field-effect transistor, and the gates of the first to nth current mirror field-effect transistors together serve as the additional current input terminal of the current mirror circuit, and are connected to the additional current generation circuit to receive the additional current.

[0031] The source of the seventh field-effect transistor, the source of the first current mirror field-effect transistor, and the source of the nth current mirror field-effect transistor are all connected to the power supply ground.

[0032] Where n is a natural number greater than 1, and i is a positive integer less than or equal to n.

[0033] In one embodiment, the switching circuit includes a first switching transistor to an nth switching transistor;

[0034] The gates of the first switch transistor to the gates of the nth switch transistor serve as the control signal input terminals of the switching circuit, so as to receive the control signal;

[0035] The source terminals of the first switch transistor to the nth switch transistor serve as the current input terminals of the switching circuit to connect to the superimposed current.

[0036] The drains of the first switch to the drains of the nth switch serve as the current output terminals of the switching circuit to output the superimposed current.

[0037] In one embodiment, the pixel circuit includes a reset transistor, a transfer transistor, a source follower transistor, a row selection transistor, and a photoelectric conversion element;

[0038] The drain of the reset transistor and the drain of the source follower transistor are connected to the second power supply. The source of the reset transistor, the gate of the source follower transistor, and the source of the transmission transistor are connected to the floating diffusion point. The drain of the transmission transistor is connected to the negative terminal of the photoelectric conversion element. The source of the source follower transistor is connected to the drain of the row selection transistor. The source of the row selection transistor serves as the output terminal of the pixel circuit to output a pixel signal. The gate of the reset transistor is connected to a reset signal. The gate of the row selection transistor is connected to a row selection signal. The gate of the transmission transistor is connected to a transmission control signal. The positive terminal of the photoelectric conversion element is connected to the power supply ground.

[0039] In one embodiment, within one cycle, the on-time of the transmission transistor is t1, the off-time is t2, the on-time of the switching circuit is t3, the off-time is t4, and t1 > t3 > t4 > t2.

[0040] In one embodiment, within one cycle, the on-time of the transmission transistor is t1, the off-time is t2, the on-time of the switching circuit is t3, the off-time is t4, and t1 > t2 ≥ t3 > t4.

[0041] In one embodiment, within one cycle, the on-time of the reset transistor is T1, the off-time is T2, the first on-time of the switching circuit is T3, the first off-time is T4, the on-time of the transmission transistor TX is T5, the off-time is T6, the second on-time of the switching circuit is T7, and the second off-time is T8.

[0042] And T1>T2≥T3>T4>T5>T6≥T7>T8.

[0043] This invention also provides an image sensor, which includes the pixel signal output circuit described above.

[0044] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: the superimposed current introduced in the current source rapidly lowers the output voltage of the pixel circuit to accelerate the establishment of the pixel signal, reduces the establishment time required when the pixel signal changes, shortens the single-line readout time, and improves the overall frame rate. Attached Figure Description

[0045] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of a pixel signal output circuit provided in an embodiment of this application;

[0047] Figure 2 This is an example circuit schematic diagram of a pixel signal output circuit provided in an embodiment of this application;

[0048] Figure 3 Another example circuit schematic diagram of a pixel signal output circuit provided in an embodiment of this application;

[0049] Figure 4 for Figure 2 A timing diagram of a pixel signal output circuit is shown.

[0050] Figure 5 for Figure 3 A timing diagram of a pixel signal output circuit is shown.

[0051] Figure 6 for Figure 2 Another timing diagram of the pixel signal output circuit shown;

[0052] Figure 7 for Figure 3 Another timing diagram of the pixel signal output circuit shown;

[0053] Figure 8 for Figure 2 Another timing diagram of the pixel signal output circuit shown;

[0054] Figure 9 for Figure 3 Another timing diagram of the pixel signal output circuit is shown. Detailed Implementation

[0055] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0056] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0057] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0058] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0059] Figure 1 A schematic diagram of the pixel signal output circuit provided in a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0060] The aforementioned pixel signal output circuit includes a pixel circuit 11, an additional current generation circuit 12, a current mirror circuit 13, a switching circuit 14, and a current source 15.

[0061] Pixel circuit 11 is configured to output pixel signals.

[0062] An additional current generating circuit 12 is connected to the pixel circuit 11 and is configured to output additional current based on the pixel signal voltage when the pixel signal voltage is less than a preset voltage.

[0063] The current mirror circuit 13 is connected to the additional current generation circuit 12 and is configured to mirror the additional current to output a superimposed current.

[0064] The switching circuit 14 is connected to the current mirror circuit 13 and is configured to receive a control signal and output a superimposed current based on the control signal.

[0065] Current source 15, connected to pixel circuit 11 and switching circuit 14, is configured to superimpose current onto the initial current of current source 15 to form a superimposed composite current.

[0066] Based on the composite current, the pixel circuit 11 accelerates the establishment speed of the pixel signal.

[0067] The preset voltage is between 400mV and 800mV. The additional current and the superimposed current are in a multiple relationship. The control signal can be provided by digital circuitry.

[0068] In this embodiment of the invention, by setting an additional current generation circuit, an additional current can be output according to the voltage of the pixel signal and superimposed on the initial current of the current source by a certain multiple, thereby speeding up the establishment speed of the pixel signal, reducing the establishment time required when the pixel signal changes, shortening the single-line readout time and improving the overall frame rate.

[0069] Figure 2 An example circuit structure of the pixel signal output circuit provided in an embodiment of the present invention is shown. Figure 3 Another example circuit structure of the pixel signal output circuit provided in the embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:

[0070] like Figure 2 and Figure 3 As shown, the current source 15 includes a first field-effect transistor M1 and a second field-effect transistor M2.

[0071] The drain of the first field-effect transistor M1 is connected to the pixel signal output terminal of the pixel circuit 11 to output a composite current; the source of the first field-effect transistor M1 and the drain of the second field-effect transistor M2 together serve as the superimposed current input terminal of the current source 15, and are connected to the switching circuit 14 to receive the superimposed current; the gate of the first field-effect transistor M1 serves as the first bias voltage input terminal of the current source 15 to receive the first bias voltage ncasc; the gate of the second field-effect transistor M2 serves as the second bias voltage input terminal of the current source 15 to receive the second bias voltage nbias; the source of the second field-effect transistor M2 is connected to the power supply ground.

[0072] The first bias voltage ncasc and the second bias voltage nbias are constant values ​​during operation, ensuring the stability of the current in the current source 15.

[0073] like Figure 2 and Figure 3 As shown, the additional current generating circuit 12 includes a fifth field-effect transistor M5.

[0074] The source of the fifth field-effect transistor M5 is connected to the first power supply VAA; the gate of the fifth field-effect transistor M5 serves as the pixel signal voltage input terminal of the additional current generation circuit 12, and is connected to the pixel circuit 11 and the current source 15 to receive the pixel signal voltage; the drain of the fifth field-effect transistor M5 serves as the additional current output terminal of the additional current generation circuit 12, and is connected to the current mirror circuit 13 to output additional current.

[0075] In practice, the fifth field-effect transistor M5 can be a PMOS transistor.

[0076] like Figure 2 and Figure 3As shown, the pixel circuit 11 includes a reset transistor RST, a transmission transistor TX, a source follower transistor SF, a row selection transistor RS, and a photoelectric conversion element PD.

[0077] The drain of the reset transistor RST and the drain of the source follower transistor SF are connected to the second power supply PIXVDD. The source of the reset transistor RST, the gate of the source follower transistor SF, and the source of the transmission transistor TX are connected to the floating diffusion point FD. The drain of the transmission transistor TX is connected to the negative terminal of the photoelectric conversion element PD. The source of the source follower transistor SF is connected to the drain of the row selection transistor RS. The source of the row selection transistor RS serves as the output terminal of the pixel circuit 11 to output the pixel signal. The gate of the reset transistor RST is connected to the reset signal rst. The gate of the row selection transistor RS is connected to the row selection signal rowsel. The gate of the transmission transistor TX is connected to the transmission control signal tx. The positive terminal of the photoelectric conversion element PD is connected to the power supply ground.

[0078] This circuit is simple and reliable.

[0079] like Figure 2 As shown, the current mirror circuit 13 includes a third field-effect transistor M3 and a fourth field-effect transistor M4.

[0080] The drain of the third field-effect transistor M3 serves as the superimposed current output terminal of the current mirror circuit 13 and is connected to the switching circuit 14 to output the superimposed current. The drain of the fourth field-effect transistor M4, the gate of the fourth field-effect transistor M4, and the gate of the third field-effect transistor M3 together serve as the additional current input terminal of the current mirror circuit 13 and are connected to the additional current generation circuit 12 to receive additional current. The source of the third field-effect transistor M3 and the source of the fourth field-effect transistor M4 are connected to the power supply ground.

[0081] This circuit is simple and reliable.

[0082] like Figure 2 As shown, the switching circuit 14 includes a sixth field-effect transistor M6.

[0083] The gate of the sixth field-effect transistor M6 serves as the control signal input terminal of the switching circuit 14 to receive the control signal; the source of the sixth field-effect transistor M6 serves as the current input terminal of the switching circuit 14 to receive the superimposed current; and the drain of the sixth field-effect transistor M6 serves as the current output terminal of the switching circuit 14 to output the superimposed current.

[0084] This circuit is simple and reliable.

[0085] like Figure 3 As shown, the current mirror circuit 13 includes a seventh field-effect transistor M7 and a first current mirror field-effect transistor QJ1 to an nth current mirror field-effect transistor QJn.

[0086] The drain of the first current mirror field-effect transistor QJ1 to the drain of the nth current mirror field-effect transistor QJn serve as the superimposed current output terminal of the current mirror circuit 13, and are connected to the switching circuit 14 to output the superimposed current.

[0087] The drain of the seventh field-effect transistor M7, the gate of the seventh field-effect transistor M7, and the gates of the first current mirror field-effect transistor QJ1 to the nth current mirror field-effect transistor QJn together serve as the additional current input terminal of the current mirror circuit 13, and are connected to the additional current generation circuit 12 to receive additional current.

[0088] The source of the seventh field-effect transistor M7, the source of the first current mirror field-effect transistor QJ1, and the source of the nth current mirror field-effect transistor QJn are all connected to the power supply ground.

[0089] Where n is a natural number greater than 1, and i is a positive integer less than or equal to n.

[0090] By connecting multiple current mirrors in parallel, where the width-to-length ratio of the (i+1)th current mirror field-effect transistor QJi+1 is twice that of the ith current mirror field-effect transistor QJi, the superimposed current adjustment in the range of 0 to 31I is achieved, with a minimum step size of I.

[0091] like Figure 3 As shown, the switching circuit 14 includes the first switching transistor Q1 to the nth switching transistor Qn.

[0092] The gate of the first switch Q1 to the gate of the nth switch Qn serve as the control signal input terminals of the switching circuit 14 to receive the control signal; the source of the first switch Q1 to the source of the nth switch Qn serve as the current input terminals of the switching circuit 14 to receive the superimposed current; the drain of the first switch Q1 to the drain of the nth switch Qn serve as the current output terminals of the switching circuit 14 to output the superimposed current.

[0093] By using the first switch Q1 to the nth switch Qn, any one of the multiple current mirrors connected in parallel can be turned on, which improves the flexibility of the pixel signal output circuit to accelerate pixel signal establishment.

[0094] The following is based on the working principle. Figure 2 and Figure 3 Further explanation is provided below:

[0095] First, the control signal rst of the reset transistor RST and the control signal tx of the transmission transistor TX are both set to high level, turning on all transistors and resetting the circuit and photodiode PD.

[0096] The control signal rst of the reset transistor RST and the control signal tx of the transmission transistor TX are set to low level to expose the photodiode PD.

[0097] At the end of the exposure, the control signal tx of the transmission transistor TX is set to high level, the control signal rowsel of the row selection transistor RS is set to high level, and the row selection transistor RS is turned on; the transmission transistor TX transfers electrons to the floating diffusion point FD, and outputs the pixel signal pixout through the row selection transistor RS.

[0098] The first field-effect transistor M1 and the second field-effect transistor M2 constitute a current source 15 that provides current to the pixel circuit 11. When the pixel circuit 11 is selected, the source follower transistor SF in the pixel circuit 11 and the current source 15 constitute a buffer.

[0099] The buffer consists of a source follower transistor SF and a current source 15, with the source follower transistor SF located in the pixel circuit 11. The current source 15 keeps the current flowing through the source follower transistor SF constant, thus keeping the gate-source voltage of the source follower transistor SF constant. The output voltage of the source follower transistor SF follows the small-signal variation of the input voltage of the source follower transistor SF, and the small-signal gain is approximately 1.

[0100] When the voltage of the pixel signal pixout is less than a preset voltage, the fifth field-effect transistor M5 outputs additional current based on the pixel signal voltage. In specific implementations, the source terminal of the fifth field-effect transistor M5 is connected to the first power supply VAA. The voltage of the first power supply VAA needs to be set such that when the pixel signal changes little (i.e., the pixel signal remains at a high level after the transmission transistor Tx is turned on), the fifth field-effect transistor M5 cannot conduct because the gate-source voltage Vgs is below the threshold voltage. This is because the pixel signal has a short setup time due to the small change, and there is no need to speed it up. Introducing additional current into the current source 15 at this time might cause overshoot in the pixel signal, leading to a longer setup time. When the pixel signal changes significantly (i.e., when the pixel signal drops to a lower level), the fifth field-effect transistor M5 conducts and is in the saturation region. The greater the pixel signal change, the greater the current output by the fifth field-effect transistor M5.

[0101] The threshold voltage of the fifth field-effect transistor M5 will change depending on the process, voltage and temperature conditions. The threshold voltage needs to be set to different voltage values ​​according to different process, voltage and temperature conditions.

[0102] exist Figure 2 In this configuration, the third field-effect transistor M3 and the fourth field-effect transistor M4 form a current mirror, mirroring the current output from the fifth field-effect transistor M5 according to a certain ratio, so as to output a superimposed current to the source of the sixth field-effect transistor M6. The gate of the sixth field-effect transistor M6 is connected to a control signal, and the superimposed current is output from the drain of the sixth field-effect transistor M6 based on the control signal.

[0103] exist Figure 3In this process, by controlling the number of active switching transistors Qi, the magnitude of the superimposed current to the original current source 15 is controlled, ultimately controlling the pixel signal establishment speed. By setting the control signals (vc4 to vc0) of each switching transistor, the superimposed current can be adjusted within the range of 0 to 31I, with a minimum step size of I.

[0104] The initial current of current source 15 and the superimposed current from the current mirror are superimposed in current source 15 to form a superimposed composite current. This composite current is also the current through the source follower transistor SF. Since the magnitude of the current through the source follower transistor SF determines the gate-source voltage of the source follower transistor SF, the superimposed current introduced in current source 15 increases the gate-source voltage of the source follower transistor SF. When the voltage of the floating diffusion point FD is the same, the voltage output by the source follower transistor SF is lower. Compared with the case without additional current, the introduction of additional current allows the voltage output by the source follower transistor SF to establish a lower voltage. The voltage drops more per unit time, and the establishment speed is accelerated. Therefore, the pixel circuit 11 accelerates the establishment speed of the pixel signal based on the composite current.

[0105] Subsequently, the control signal vtrl is turned off, ensuring that the stable value of the source follower transistor SF output signal is not affected by the switching circuit 14, the current mirror circuit 13, and the additional current generation circuit 12.

[0106] It should be noted that, Figure 2 The timing of the pixel signal output circuit shown has the following three possibilities.

[0107] In the first case Figure 2 The timing diagram of the pixel signal output circuit shown is as follows: Figure 4 As shown. Within one cycle, the on-time of the transmission transistor TX is t1, and the off-time is t2. The on-time of the switching circuit 14 is t3, and the off-time is t4, where t1 > t3 > t4 > t2. Correspondingly, Figure 3 The timing diagram of the pixel signal output circuit shown is as follows: Figure 5 As shown.

[0108] exist Figure 4 In the process, because the control signal vtrl of the sixth field-effect transistor M6 and the control signal tx of the transmission transistor TX overlap, the additional current is established earlier after the control signal tx of the transmission transistor TX is turned off, thus accelerating the pixel signal establishment speed. Similarly, in Figure 5 In this process, because the control signals of each switch (vc4 to vc0) and the control signal tx of the transmission transistor TX overlap, the additional current is established earlier after the control signal tx of the transmission transistor TX is turned off, which speeds up the pixel signal establishment speed.

[0109] In the second case Figure 2 Another timing sequence of the pixel signal output circuit shown is as follows: Figure 6 As shown. Within one cycle, the on-time of the transmission transistor TX is t1, and the off-time is t2. The on-time of the switching circuit 14 is t3, and the off-time is t4, where t1 > t2 ≥ t3 > t4. Correspondingly, Figure 2 Another timing sequence of the pixel signal output circuit shown is as follows: Figure 7 As shown.

[0110] exist Figure 6 and Figure 7 In this design, the additional current is turned on for a preset time only after the control signal tx of the output transmission transistor TX is transmitted. The effects of charge injection and clock feedthrough are considered for the voltage change of the floating diffusion point FD, which improves the pixel signal establishment speed while taking into account the stability of pixel signal establishment.

[0111] In this context, clock feedthrough refers to the voltage rise or fall of the floating diffusion point FD caused by a transition in the gate voltage of the transmission transistor TX from low to high or from high to low, which is coupled to the floating diffusion point FD through the gate-drain capacitance or the gate-source capacitance.

[0112] In the third case Figure 2 Another timing sequence of the pixel signal output circuit shown is as follows: Figure 8 As shown. Within one cycle, the on-time of the reset transistor RST is T1, the off-time is T2, the first on-time of the switching circuit 14 is T3, the first off-time is T4, the on-time of the transmission transistor TX is T5, the off-time is T6, the second on-time of the switching circuit 14 is T7, and the second off-time is T8; and T1 > T2 ≥ T3 > T4 > T5 > T6 ≥ T7 > T8. Accordingly, Figure 2 Another timing sequence of the pixel signal output circuit shown is as follows: Figure 9 As shown.

[0113] exist Figure 8 and Figure 9 In this design, the additional current is turned on for a preset time only after the control signal tx of the transmission transistor TX, taking into account the effects of charge injection and clock feedthrough on the voltage variation of the floating diffusion point FD. At the same time, the additional current is turned on after the control signal of the reset transistor RST is turned off, taking into account the voltage fluctuation of the floating diffusion point FD, which not only speeds up the establishment of the pixel signal but also further improves the stability of the pixel signal establishment.

[0114] This invention also provides an image sensor, which includes the pixel signal output circuit described above.

[0115] In this embodiment of the invention, a pixel circuit outputs a pixel signal; an additional current generation circuit outputs an additional current based on the pixel signal voltage when the pixel signal voltage is less than a preset voltage; a current mirror circuit mirrors the additional current to output a superimposed current; a switching circuit receives a control signal and outputs the superimposed current based on the control signal; a current source superimposes the superimposed current onto the initial current of the current source to form a superimposed composite current; based on the composite current, the pixel circuit accelerates the establishment speed of the pixel signal; because the superimposed current introduced in the current source rapidly lowers the output voltage of the pixel circuit to accelerate the establishment of the pixel signal, it reduces the establishment time required when the pixel signal changes, shortens the single-line readout time, and improves the overall frame rate.

[0116] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0117] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A pixel signal output circuit, characterized in that, include: Pixel circuit, configured to output pixel signals; An additional current generation circuit, connected to the pixel circuit, is configured to output an additional current based on the voltage of the pixel signal when the voltage of the pixel signal is less than a preset voltage. A current mirror circuit, connected to the additional current generating circuit, is configured to mirror the additional current to output a superimposed current. A switching circuit, connected to the current mirror circuit, is configured to receive a control signal and output the superimposed current based on the control signal; A current source, connected to the pixel circuit and the switching circuit, is configured to superimpose the superimposed current onto the initial current of the current source to form a superimposed composite current. Based on the composite current, the pixel circuit accelerates the establishment speed of the pixel signal.

2. The pixel signal output circuit as described in claim 1, characterized in that, The current source includes a first field-effect transistor and a second field-effect transistor; The drain of the first field-effect transistor is connected to the pixel signal output terminal of the pixel circuit to output the composite current; The source of the first field-effect transistor and the drain of the second field-effect transistor are used together as the superimposed current input terminal of the current source and connected to the switching circuit to receive the superimposed current. The gate of the first field-effect transistor serves as the first bias voltage input terminal of the current source, so as to connect the first bias voltage. The gate of the second field-effect transistor serves as the second bias voltage input terminal of the current source, so as to connect the second bias voltage; The source of the second field-effect transistor is connected to the power supply ground.

3. The pixel signal output circuit as described in claim 1, characterized in that, The additional current generating circuit includes a fifth field-effect transistor; The source of the fifth field-effect transistor is connected to the first power supply; The gate of the fifth field-effect transistor serves as the pixel signal voltage input terminal of the additional current generation circuit, and is connected to the pixel circuit and the current source to receive the voltage of the pixel signal. The drain of the fifth field-effect transistor serves as the additional current output terminal of the additional current generation circuit and is connected to the current mirror circuit to output the additional current.

4. The pixel signal output circuit as described in claim 1, characterized in that, The current mirror circuit includes a third field-effect transistor and a fourth field-effect transistor; The drain of the third field-effect transistor serves as the superimposed current output terminal of the current mirror circuit and is connected to the switching circuit to output the superimposed current. The drain of the fourth field-effect transistor, the gate of the fourth field-effect transistor, and the gate of the third field-effect transistor together serve as the additional current input terminal of the current mirror circuit, and are connected to the additional current generation circuit to receive the additional current. The source of the third field-effect transistor and the source of the fourth field-effect transistor are connected to the power supply ground.

5. The pixel signal output circuit as described in claim 4, characterized in that, The switching circuit includes a sixth field-effect transistor; The gate of the sixth field-effect transistor serves as the control signal input terminal of the switching circuit, so as to receive the control signal; The source of the sixth field-effect transistor serves as the current input terminal of the switching circuit to connect to the superimposed current. The drain of the sixth field-effect transistor serves as the current output terminal of the switching circuit to output the superimposed current.

6. The pixel signal output circuit as described in claim 1, characterized in that, The current mirror circuit includes a seventh field-effect transistor and current mirror field-effect transistors from the first to the nth current mirror field-effect transistors. The drain of the first current mirror field-effect transistor to the drain of the nth current mirror field-effect transistor serve as the superimposed current output terminal of the current mirror circuit, and are connected to the switching circuit to output the superimposed current. The drain of the seventh field-effect transistor, the gate of the seventh field-effect transistor, and the gates of the first to nth current mirror field-effect transistors together serve as the additional current input terminal of the current mirror circuit, and are connected to the additional current generation circuit to receive the additional current. The source of the seventh field-effect transistor, the source of the first current mirror field-effect transistor, and the source of the nth current mirror field-effect transistor are all connected to the power supply ground. Where n is a natural number greater than 1, and i is a positive integer less than or equal to n.

7. The pixel signal output circuit as described in claim 6, characterized in that, The switching circuit includes a first switching transistor to an nth switching transistor; The gates of the first switch transistor to the gates of the nth switch transistor serve as the control signal input terminals of the switching circuit, so as to receive the control signal; The source terminals of the first switch transistor to the nth switch transistor serve as the current input terminals of the switching circuit to connect to the superimposed current. The drains of the first switch to the drains of the nth switch serve as the current output terminals of the switching circuit to output the superimposed current.

8. The pixel signal output circuit as described in claim 1, characterized in that, The pixel circuit includes a reset transistor, a transmission transistor, a source follower transistor, a row selection transistor, and a photoelectric conversion element; The drain of the reset transistor and the drain of the source follower transistor are connected to the second power supply. The source of the reset transistor, the gate of the source follower transistor, and the source of the transmission transistor are connected to the floating diffusion point. The drain of the transmission transistor is connected to the negative terminal of the photoelectric conversion element. The source of the source follower transistor is connected to the drain of the row selection transistor. The source of the row selection transistor serves as the output terminal of the pixel circuit to output a pixel signal. The gate of the reset transistor is connected to a reset signal. The gate of the row selection transistor is connected to a row selection signal. The gate of the transmission transistor is connected to a transmission control signal. The positive terminal of the photoelectric conversion element is connected to the power supply ground.

9. The pixel signal output circuit as described in claim 8, characterized in that, Within one cycle, the on-time of the transmission transistor is t1, the off-time is t2, the on-time of the switching circuit is t3, the off-time is t4, and t1 > t3 > t4 > t2.

10. The pixel signal output circuit as described in claim 8, characterized in that, Within one cycle, the on-time of the transmission transistor is t1, the off-time is t2, the on-time of the switching circuit is t3, the off-time is t4, and t1 > t2 ≥ t3 > t4.

11. The pixel signal output circuit as described in claim 8, characterized in that, Within one cycle, the turn-on time of the reset transistor is T1, the turn-off time is T2, the first turn-on time of the switching circuit is T3, the first turn-off time is T4, the turn-on time of the transmission transistor TX is T5, the turn-off time is T6, the second turn-on time of the switching circuit is T7, and the second turn-off time is T8. And T1>T2≥T3>T4>T5>T6≥T7>T8.

12. An image sensor, characterized in that, The image sensor includes a pixel signal output circuit as described in any one of claims 1 to 11.

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