image sensor

Abstract

The application provides an image sensor, comprising: a pixel array comprising a plurality of pixel units arranged in an array, each pixel unit comprising a photodiode, a transfer transistor, a reset transistor and an amplification transistor; a readout circuit comprising a plurality of column processing units for reading voltage signals from each column of pixel units respectively, each column processing unit comprising an amplification module; wherein the source electrode of the amplification transistor of each column of pixel units is connected to the input end of the amplification module of the corresponding column processing unit, and the drain electrode of the amplification transistor is connected to the output end of the amplification module. The internal structure of the pixel unit of the image sensor of the application is consistent with that of a conventional 3T or 4T pixel, and the process compatibility is good; only by improving the connection mode of the amplification module in the column processing unit, a new amplification mode is realized, higher conversion gain is obtained, and the power consumption caused by the introduction of an additional reference voltage and an additional amplification circuit is avoided.

Description

Technical Field

[0001] This invention relates to an image sensor. Background Technology

[0002] In current CMOS image sensors, 3T or 4T pixel structures are commonly used. Figure 1 (A traditional 4T pixel is shown as an example). The main reason is that the amplifier transistor M3 in the pixel is a source follower (SF) structure, which allows for a large output voltage range and high degree of freedom in the reset voltage. Its conversion gain is approximately inversely proportional to the capacitance of the FD node (gate of transistor M3). To achieve better noise performance in low-light conditions, another existing approach in the industry is to modify the amplifying transistors in the pixel to operate in a common-source amplification structure, namely the so-called capacitor feedback transimpedance amplifier (CTIA) pixel structure (such as...). Figure 2 As shown), its conversion gain is approximately inversely proportional to the capacitance between the gate and drain of transistor M3. .because CTIA pixels can achieve higher conversion gain compared to traditional 4T pixels. However, the main problems with CTIA pixels are their smaller operating range, the need for more precise reset voltage, poor PVT robustness, and susceptibility to output voltage saturation due to charge injection.

[0003] To combine the advantages of the two structures, patent US10277848B2 proposes a hybrid pixel structure that integrates both. By switching the peripheral circuit, the pixel can switch between SF and CTIA modes. However, this requires an additional reference voltage and still cannot solve the inherent problems of CTIA pixels. Patent CN110537366A proposes a differential pixel structure, which can improve the problems of single-ended CTIA pixels to some extent. However, the operation and timing of the differential structure are more complex, and the power consumption is significantly increased, limiting its application. Patent CN107770461 proposes a dual-gain output pixel structure that combines the pixel and the amplifier in the column circuit to achieve signal output in both SF and CTIA modes. However, this structure requires the addition of capacitors, transistors, and additional signal output lines within the pixel, increasing the pixel's complexity. The amplifier in the column circuit also increases the overall power consumption. Summary of the Invention

[0004] The purpose of this invention is to provide an image sensor that can achieve high conversion gain based on traditional 3T or 4T pixel structures through simple structural improvements and low power consumption costs.

[0005] Based on the above considerations, the present invention provides an image sensor, comprising: a pixel array including multiple pixel units arranged in an array, each pixel unit including a photodiode, a transfer transistor, a reset transistor, and an amplifying transistor; and a readout circuit including multiple column processing units that read voltage signals from each column of pixel units, each column processing unit including an amplification module; wherein the source of the amplifying transistor of each column of pixel units is connected to the input terminal of the amplification module of the corresponding column processing unit, and the drain of the amplifying transistor is connected to the output terminal of the amplification module.

[0006] Preferably, the amplification module includes a first capacitor, a second capacitor, and an amplification unit, wherein the source of the amplification transistor is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is connected to the first terminal of the second capacitor and the input terminal of the amplification unit, and the second terminal of the second capacitor and the output terminal of the amplification unit are connected to the drain of the amplification transistor.

[0007] Preferably, the amplification unit comprises a single transistor or multiple transistors.

[0008] Preferably, the amplification unit is a single PMOS transistor, the gate of the PMOS transistor is connected to the second terminal of the first capacitor and the first terminal of the second capacitor, the source of the PMOS transistor is connected to the first power supply voltage, and the drain of the PMOS transistor is connected to the drain of the amplification transistor and the second terminal of the second capacitor.

[0009] Preferably, the second capacitor is the parasitic capacitance of the amplification unit.

[0010] Preferably, the first capacitor and the second capacitor are a capacitor array.

[0011] Preferably, the column processing unit further includes a first switch, which is connected in parallel with the second capacitor.

[0012] Preferably, the column processing unit further includes a second switch, a third switch, and a fourth switch. The source of the amplifying transistor is connected to the first terminal of the first capacitor through the second switch. The second terminal of the second capacitor and the output terminal of the amplifying unit are connected to the drain of the amplifying transistor through the third switch. The drain of the amplifying transistor is connected to the second power supply voltage through the fourth switch. When the fourth switch is closed and the second and third switches are open, the image sensor operates in the first mode, and the column processing unit reads the first voltage signal from the source of the amplifying transistor. When the fourth switch is open and the second and third switches are closed, the image sensor operates in the second mode, and the column processing unit reads the second voltage signal from the drain of the amplifying transistor.

[0013] Preferably, when the image sensor is operating in the second mode, the column processing unit also reads out a third voltage signal from the source of the amplifying transistor.

[0014] Preferably, the amplification module includes an amplification unit, wherein the source of the amplification transistor is connected to the input terminal of the amplification unit, the drain of the amplification transistor is connected to the output terminal of the amplification unit, and the drain of the reset transistor is connected to the drain of the amplification transistor.

[0015] Preferably, the amplification unit comprises a single transistor or multiple transistors.

[0016] Preferably, the amplification unit is a single PMOS transistor, the gate of the PMOS transistor is connected to the source of the amplification transistor, the source of the PMOS transistor is connected to a first power supply voltage, and the drain of the PMOS transistor is connected to the drain of the amplification transistor.

[0017] Preferably, the column processing unit further includes a fifth switch and a sixth switch, the source of the amplifying transistor is connected to the input terminal of the amplifying unit through the fifth switch, and the input terminal of the amplifying unit is also connected to ground voltage through the sixth switch; When the sixth switch is closed and the fifth switch is open, the image sensor operates in the first mode, and the column processing unit reads the first voltage signal from the source of the amplifying transistor. When the sixth switch is open and the fifth switch is closed, the image sensor operates in the second mode, and the column processing unit reads the second voltage signal from the drain of the amplifying transistor.

[0018] Preferably, when the image sensor is operating in the second mode, the column processing unit also reads out a third voltage signal from the source of the amplifying transistor.

[0019] Preferably, the drain of the reset transistor is connected to the drain of the amplification transistor.

[0020] Preferably, the column processing unit further includes a current source, the output of which is connected to the source of an amplifying transistor.

[0021] Preferably, the pixel unit further includes a selection transistor, which is connected between the source of the amplifying transistor and the input terminal of the amplifying module, or between the drain of the amplifying transistor and the output terminal of the amplifying module.

[0022] Compared with existing technologies, the internal structure of the pixel unit of the image sensor of this invention is consistent with that of traditional 3T or 4T pixels, resulting in good process compatibility. The new amplification mode is achieved by improving the connection method of the amplification module in the column processing unit, achieving higher conversion gain without introducing additional reference voltage or power consumption caused by additional amplification circuits. The device structure of the amplification module is located in the readout circuit, and its size can be much larger than the transistor in the pixel, resulting in better process consistency and more flexible adjustment of conversion gain. The conversion gain can be switched between the traditional source follower mode (first mode) and the new amplification mode (second mode) by the control circuit. Attached Figure Description

[0023] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.

[0024] Figure 1 This is a circuit diagram of a 4T pixel structure image sensor in the prior art; Figure 2 This is a circuit diagram of a CTIA pixel structure image sensor in the prior art; Figure 3 This is a schematic diagram of the image sensor system of the present invention; Figure 4 This is a schematic diagram illustrating the principle of the image sensor of the present invention; Figure 5 This is a circuit diagram of an image sensor according to Embodiment 1 of the present invention; Figure 6 for Figure 5 The equivalent circuit diagram of the image sensor operating in the first mode; Figure 7 for Figure 5 The signal timing diagram of the image sensor operating in the first mode; Figure 8 for Figure 5 The equivalent circuit diagram of the image sensor operating in the second mode; Figure 9 for Figure 5 The signal timing diagram of the image sensor operating in the second mode; Figure 10 for Figure 5 The image sensor's conversion gain curves in two modes; Figure 11 for Figure 5 A circuit diagram illustrating one application of an image sensor; Figure 12 for Figure 5 A circuit diagram of another application of the image sensor; Figure 13 for Figure 5 A circuit diagram illustrating another application of the image sensor; Figure 14 This is a circuit diagram of an image sensor according to Embodiment 2 of the present invention; Figure 15 for Figure 14 The equivalent circuit diagram of the image sensor operating in the second mode.

[0025] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation

[0026] To address the problems in the prior art, the present invention provides an image sensor that can achieve high conversion gain based on a traditional 3T or 4T pixel structure through simple structural improvements and lower power consumption costs.

[0027] In the following detailed description of preferred embodiments, reference will be made to the accompanying drawings, which form part of this invention. The accompanying drawings illustrate specific embodiments by way of example that enable the implementation of the invention. The exemplary embodiments are not intended to be exhaustive of all embodiments according to the invention. It will be understood that other embodiments may be utilized, and structural or logical modifications may be made, without departing from the scope of the invention. Therefore, the following detailed description is not restrictive, and the scope of the invention is defined by the appended claims.

[0028] The following detailed description is based on specific embodiments.

[0029] like Figure 3 , Figure 4 As shown, the image sensor of the present invention includes a pixel array 100 and a readout circuit 200 located around the pixel array 100.

[0030] The pixel array 100 includes multiple pixel units 101 arranged in an array. Each pixel unit 101 includes a photodiode PD and multiple pixel transistors, namely a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The photodiode PD is used to perform photoelectric conversion on the incident light to obtain the corresponding charge. The transfer transistor M1 is used to transfer the charge accumulated in the photodiode PD to the floating diffusion region FD. The reset transistor M2 is used to reset the potential of the floating diffusion region FD. The amplification transistor M3 is used to convert the charge in the floating diffusion region FD into a corresponding voltage signal. The selection transistor M4 is used to output the voltage signal to the column processing unit of the readout circuit. The connection method of each transistor is existing technology and will not be described in detail.

[0031] The readout circuit 200 includes a plurality of column processing units 201, each column processing unit 201 corresponding to one or more columns of pixel units 101 in the pixel array 100, and is used to read the output voltage signal from the corresponding column of pixel units 101. Figure 4 Showing a pixel unit P in the Mth column of pixels <n>(The specific circuit of the corresponding column processing unit M is taken as an example). Each column processing unit 201 includes an amplification module 202. The source of the amplification transistor M3 of each column pixel unit 101 is connected to the input terminal of the amplification module 202 of the corresponding column processing unit 201, and the drain of the amplification transistor M3 of each column pixel unit 101 is connected to the output terminal of the amplification module 202 of the corresponding column processing unit 201. In addition, the column processing unit 201 also includes a current source CS, and the output terminal of the current source CS is connected to the source of the amplification transistor M3.

[0032] The specific structure of the amplification module 202 is described in detail below with reference to specific embodiments.

[0033] Example 1 like Figure 5 As shown, the amplification module 202 includes a first capacitor C. C Second capacitor C FB Amplification unit 203, the source of amplification transistor M3 is connected to the first capacitor C. C First terminal, first capacitor C C The second terminal is connected to the second capacitor C. FB The first terminal and the input terminal of the amplification unit 203, the second capacitor C FB The second terminal and the output terminal of the amplification unit 203 are connected to the drain of the amplification transistor M3.

[0034] Based on the above structure, the column processing unit 201 can read the voltage signal V from the drain of the amplifying transistor M3. HG The first capacitor C in the amplification module 202 C Second capacitor C FB The transconductance Gm of the amplification unit 203 and the load provide the floating diffusion region FD to the output node V. HG This results in a higher conversion gain than the traditional source follower mode, and due to the first capacitor C C Second capacitor C FB Both the amplification unit 203 and the amplification unit are located in the peripheral circuit. Their size can be much larger than that of the transistor M3 inside the pixel. Compared with the traditional CTIA pixel structure, the process consistency is better and the conversion gain can be adjusted more flexibly.

[0035] In such Figure 5 In the preferred embodiment shown, the amplification unit 203 is a single PMOS transistor M5, and the gate of the PMOS transistor M5 is connected to the first capacitor C. C The second terminal and the second capacitor C FB At the first terminal, the source of PMOS transistor M5 is connected to the first power supply voltage VDD1, and the drain of PMOS transistor M5 is connected to the drain of amplifier transistor M3 and the second capacitor C. FB The second terminal. By using a PMOS transistor M5 as the amplification unit 203, it has advantages such as simple structure, low noise, and large voltage margin. Those skilled in the art will understand that in other embodiments not shown, a single NMOS transistor or multiple transistors may also be used as the amplification unit 203.

[0036] In addition, the second capacitor C FB It can be the parasitic capacitance of the amplification unit 203, or it can be the same as the first capacitor C. C Similarly, it is an independent capacitor component. The first capacitor C C Second capacitor C FB It can be a fixed capacitor or a variable capacitor array, thereby changing the first capacitor C C Second capacitor C FB The gain of the amplifier module 202 is adjusted proportionally to allow for flexible adjustment of the conversion gain.

[0037] Preferably, the column processing unit 201 further includes a second capacitor C. FB The first switch S1 connected in parallel is used to perform a self-clearing operation on the amplification module 202.

[0038] Further preferably, the column processing unit 201 further includes a second switch S2, a third switch S3, and a fourth switch S4, and the source of the amplifying transistor M3 is connected to the first capacitor C through the second switch S2. C First terminal, second capacitor C FB The second terminal and the output terminal of the amplification unit 203 are connected to the drain of the amplification transistor M3 through the third switch S3, and the drain of the amplification transistor M3 is connected to the second power supply voltage VDD2 through the fourth switch S4.

[0039] Therefore, when the fourth switch S4 is closed and the second switch S2 and the third switch S3 are open, the equivalent circuit of the image sensor operating in the first mode is as follows: Figure 6 As shown, the signal timing is as follows Figure 7 As shown, in this mode, the column processing unit reads the first voltage signal V from the source of the amplifying transistor M3. SF (like Figure 10 V1 in the model is equivalent to the traditional source follower mode, which has a lower conversion gain.

[0040] When the fourth switch S4 is open, and the second switch S2 and the third switch S3 are closed, the image sensor operates in the equivalent circuit of the second mode as follows: Figure 8 As shown, the signal timing is as follows Figure 9 As shown, in this mode, the column processing unit reads the second voltage signal V from the drain of the amplifying transistor M3. HG (like Figure 10 (V2 in the image sensor) has a higher conversion gain. Of course, when the image sensor is operating in the second mode, the column processing unit can also simultaneously read the third voltage signal V from the source of the amplifying transistor M3. SF (like Figure 10 (V3 in the original text), therefore, when the image sensor of the present invention operates in the second mode, it can simultaneously generate both high and low conversion gain outputs, so as to select and apply them as needed.

[0041] Figure 11 for Figure 4 In one embodiment, the amplification module 202 is directly connected to the analog-to-digital converter 204; Figure 12 for Figure 4 In another application of the embodiment, the amplification module 202 is connected to the analog-to-digital converter 204 after passing through the column amplifier 205; Figure 13 for Figure 4 In another application of the embodiment, the amplification module 202 is connected to two sampling circuits 206 and 207 respectively.

[0042] Example 2 In another preferred embodiment of the image sensor of the present invention, the first capacitor C in the amplification module 202 can also be... C Second capacitor C FB The term "abbreviation" means that only the amplification unit 203 is used as the amplification module, with the source of the amplification transistor M3 connected to the input terminal of the amplification unit 203 and the drain of the amplification transistor M3 connected to the output terminal of the amplification unit 203.

[0043] The specific structure is as follows: Figure 14 As shown, the amplification unit 203 is preferably a single PMOS transistor M5, the gate of which is connected to the source of the amplification transistor M3, the source of which is connected to the first power supply voltage VDD1, and the drain of which is connected to the drain of the amplification transistor M3. However, in other embodiments not shown, a single NMOS transistor or multiple transistors may also be used as the amplification unit 203.

[0044] It should be noted that when the amplification module 202 adopts this structure that omits capacitors, it is necessary to match the connection method of the drain of the reset transistor M2 in the pixel unit 101 to the drain of the amplification transistor M3 (different from the connection of the drain of the reset transistor M2 to the third power supply voltage VDD3 in Embodiment 1) so as to achieve self-clearing through the pixel unit.

[0045] Further preferably, the column processing unit 201 further includes a fifth switch S5 and a sixth switch S6. The source of the amplifying transistor M3 is connected to the gate of the PMOS transistor M5 (i.e., the input terminal of the amplifying unit) through the fifth switch S5, and the gate of the PMOS transistor M5 is also connected to the ground voltage through the sixth switch S6.

[0046] Therefore, when the sixth switch S6 is closed and the fifth switch S5 is open, the PMOS transistor M5 is turned on as a switch, the image sensor operates in the first mode, and the column processing unit reads the first voltage signal V from the source of the amplifying transistor M3. SF This is equivalent to the traditional source follower mode, with a lower conversion gain.

[0047] When the sixth switch S6 is open and the fifth switch S5 is closed, the equivalent circuit is as follows: Figure 15 As shown, the PMOS transistor M5 serves as an amplification unit, the image sensor operates in the second mode, and the column processing unit reads the second voltage signal V from the drain of the amplification transistor M3. HG The conversion gain is relatively high. Of course, when the image sensor is operating in the second mode, the column processing unit can also simultaneously read the third voltage signal V from the source of the amplifying transistor M3. SF Therefore, when the image sensor of the present invention operates in the second mode, it can simultaneously generate both high and low conversion gain outputs, so that they can be selected and applied as needed.

[0048] Those skilled in the art will understand that Figure 14 The illustrated embodiments can also be applied to similar... Figure 11 , Figure 12 , Figure 13 The applications shown will not be elaborated upon here.

[0049] Furthermore, in the 4T pixel structure shown in the aforementioned embodiment, the selection transistor M4 is connected between the source of the amplifying transistor M3 and the input terminal of the amplification module 202. In other 4T pixel structures not shown, the selection transistor M4 can also be connected between the drain of the amplifying transistor M3 and the output terminal of the amplification module 202. Of course, in the 3T pixel structure, the selection transistor M4 can be omitted.

[0050] In summary, the internal structure of the pixel unit of the image sensor of the present invention is consistent with that of traditional 3T or 4T pixels, resulting in good process compatibility. The new amplification mode is achieved by improving the connection method of the amplification module in the column processing unit, achieving higher conversion gain without introducing additional reference voltage or power consumption caused by additional amplification circuits. The device structure of the amplification module is located in the readout circuit, and its size can be much larger than the transistors in the pixel, resulting in better process consistency and more flexible adjustment of conversion gain. The conversion gain can be switched between the traditional source follower mode (first mode) and the new amplification mode (second mode) by the control circuit.

[0051] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is evident that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.< / n>

Claims

1. An image sensor, characterized in that, include: A pixel array includes multiple pixel units arranged in an array, each pixel unit including a photodiode, a transfer transistor, a reset transistor, and an amplification transistor; The readout circuit includes multiple column processing units that read voltage signals from each column of pixel units, each column processing unit including an amplification module; the column processing unit also includes a current source, the output of which is connected to the source of an amplification transistor. In this configuration, the source of the amplifying transistor in each column of pixel units is connected to the input terminal of the amplifying module of the corresponding column processing unit, and the drain of the amplifying transistor is connected to the output terminal of the amplifying module, so that the conversion gain of the voltage signal at the drain of the amplifying transistor is higher than the conversion gain of the voltage signal at the source of the amplifying transistor.

2. The image sensor as described in claim 1, characterized in that, The amplification module includes a first capacitor, a second capacitor, and an amplification unit. The source of the amplification transistor is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is connected to the first terminal of the second capacitor and the input terminal of the amplification unit, and the second terminal of the second capacitor and the output terminal of the amplification unit are connected to the drain of the amplification transistor.

3. The image sensor as described in claim 2, characterized in that, The amplification unit includes a single transistor or multiple transistors.

4. The image sensor as described in claim 3, characterized in that, The amplification unit is a single PMOS transistor. The gate of the PMOS transistor is connected to the second terminal of the first capacitor and the first terminal of the second capacitor. The source of the PMOS transistor is connected to the first power supply voltage. The drain of the PMOS transistor is connected to the drain of the amplification transistor and the second terminal of the second capacitor.

5. The image sensor as described in claim 2, characterized in that, The second capacitor is the parasitic capacitance of the amplification unit.

6. The image sensor as described in claim 2, characterized in that, The first capacitor and the second capacitor are a capacitor array.

7. The image sensor as described in claim 2, characterized in that, The column processing unit also includes a first switch, which is connected in parallel with a second capacitor.

8. The image sensor as described in claim 2, characterized in that, The column processing unit further includes a second switch, a third switch, and a fourth switch. The source of the amplifying transistor is connected to the first terminal of the first capacitor through the second switch. The second terminal of the second capacitor and the output terminal of the amplifying unit are connected to the drain of the amplifying transistor through the third switch. The drain of the amplifying transistor is connected to the second power supply voltage through the fourth switch. When the fourth switch is closed and the second and third switches are open, the image sensor operates in the first mode, and the column processing unit reads the first voltage signal from the source of the amplifying transistor. When the fourth switch is open and the second and third switches are closed, the image sensor operates in the second mode, and the column processing unit reads the second voltage signal from the drain of the amplifying transistor.

9. The image sensor as claimed in claim 8, characterized in that, When the image sensor is operating in the second mode, the column processing unit also reads out a third voltage signal from the source of the amplifying transistor.

10. The image sensor as claimed in claim 1, characterized in that, The amplification module includes an amplification unit, wherein the source of the amplification transistor is connected to the input terminal of the amplification unit, and the drain of the amplification transistor is connected to the output terminal of the amplification unit.

11. The image sensor as claimed in claim 10, characterized in that, The amplification unit includes a single transistor or multiple transistors.

12. The image sensor as claimed in claim 11, characterized in that, The amplification unit is a single PMOS transistor. The gate of the PMOS transistor is connected to the source of the amplification transistor, the source of the PMOS transistor is connected to the first power supply voltage, and the drain of the PMOS transistor is connected to the drain of the amplification transistor.

13. The image sensor as claimed in claim 10, characterized in that, The column processing unit also includes a fifth switch and a sixth switch. The source of the amplifying transistor is connected to the input terminal of the amplifying unit through the fifth switch, and the input terminal of the amplifying unit is also connected to the ground voltage through the sixth switch. When the sixth switch is closed and the fifth switch is open, the image sensor operates in the first mode, and the column processing unit reads the first voltage signal from the source of the amplifying transistor. When the sixth switch is open and the fifth switch is closed, the image sensor operates in the second mode, and the column processing unit reads the second voltage signal from the drain of the amplifying transistor.

14. The image sensor as claimed in claim 13, characterized in that, When the image sensor is operating in the second mode, the column processing unit also reads out a third voltage signal from the source of the amplifying transistor.

15. The image sensor as claimed in claim 10, characterized in that, The drain of the reset transistor is connected to the drain of the amplification transistor.

16. The image sensor as claimed in claim 1, characterized in that, The pixel unit further includes a selection transistor, which is connected between the source of the amplifying transistor and the input terminal of the amplifying module, or between the drain of the amplifying transistor and the output terminal of the amplifying module.

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