Method for forming SRAM device, and mask layout

Abstract

A method for forming an SRAM device and a mask layout, the method comprising: providing a substrate including a memory cell region including two sub-cell regions, each sub-cell region including a pass transistor region and a pull-down transistor region adjacent along a first direction, a pull-up transistor region adjacent the pull-down transistor region along a second direction, the substrate having gate structures formed thereon with first source / drain doping layers and second source / drain doping layers formed on both sides of the gate structures; forming a first partition layer on a dielectric layer between the second source / drain doping layers at an interface between adjacent pull-up transistor regions, the first partition layer extending over the gate structures of the pull-up transistor regions; forming a first interconnect opening in the pull-up transistor region that exposes the second source / drain doping layers, the first interconnect opening of the pull-up transistor region extending to a top of a gate structure of another pull-up transistor region and exposing a corresponding gate structure, adjacent first interconnect openings in the memory cell region being isolated by the first partition layer. The present application improves process efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming an SRAM device and a mask layout. Background Technology

[0002] With the gradual development of semiconductor process technology, semiconductor process nodes are continuously decreasing in size, following Moore's Law. To adapt to the shrinking process nodes and the increasing integration of semiconductor devices, the critical dimensions of metal-oxide-semiconductor (MOS) devices are also shrinking, and the spacing of interconnect structures is also decreasing to even smaller dimensions. Correspondingly, the manufacturing process of semiconductor devices is also constantly being improved to meet people's requirements for device performance.

[0003] Currently, in the fabrication of interconnect structures for MOS devices, a cut technique is typically used to sever the strip-shaped interconnect structure. The severed interconnect structure corresponds to different transistors, which can improve the transistor integration density. Furthermore, when multiple interconnect structures are arranged in a row along the extension direction, the cut technique can precisely reduce the spacing (Cut CD) between the disconnected interconnect structures after cutting. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming an SRAM device and a mask layout, which saves process costs and improves process efficiency.

[0005] To address the aforementioned problems, this invention provides a method for forming an SRAM device, comprising: providing a substrate including a memory cell region, the memory cell region including two centrally symmetrical sub-cell regions, the sub-cell region including a transmission gate transistor region and a pull-down transistor region adjacent to each other along a first direction, and a pull-up transistor region adjacent to the transmission gate transistor region and the pull-down transistor region along a second direction, the pull-up transistor regions being disposed adjacently, a gate structure extending along the second direction and arranged along the first direction being formed on the substrate of the memory cell region, a first source / drain doped layer and a second source / drain doped layer being formed in the substrate on both sides of the gate structure, the second source / drain doped layers of the pull-down transistor region and the pull-up transistor region being located on the same side of the gate structure, and the second source / drain doped layers of the pull-down transistor region and the pull-up transistor region being closer to the first source / drain doped layer than the first source / drain doped layer. Near the transmission gate transistor region, a dielectric layer covering the gate structure, the second source / drain doped layer, and the first source / drain doped layer is formed on the substrate, with the second direction perpendicular to the first direction; at the boundary of adjacent pull-up transistor regions, a first isolation layer is formed on the dielectric layer between the second source / drain doped layers, and the first isolation layer extends along the first direction to above the gate structure of the pull-up transistor region; in the dielectric layer at the top of the second source / drain doped layer of any of the adjacent pull-up transistor regions, a first interconnect opening exposing the second source / drain doped layer is formed, and the first interconnect opening extends to the top of the gate structure of another adjacent pull-up transistor region and exposes the corresponding gate structure; adjacent first interconnect openings in the memory cell region are isolated by the first isolation layer; a shared plug is formed in the first interconnect opening.

[0006] Accordingly, embodiments of the present invention also provide a mask layout, including: a memory cell region, the memory cell region including two centrally symmetrical sub-cell regions, the sub-cell regions including a transmission gate transistor region and a pull-down transistor region adjacent along a first direction, and a pull-up transistor region adjacent to the transmission gate transistor region and the pull-down transistor region along a second direction, the pull-up transistor regions being disposed adjacently, the first direction being perpendicular to the second direction; a first layout layer, including a gate pattern, extending along the second direction in the memory cell region and arranged along the first direction; a second layout layer, including a first source / drain doped pattern and a second source / drain doped pattern located on both sides of the gate pattern, the second source / drain doped patterns of the pull-down transistor region and the pull-up transistor region being located on the same side of the gate pattern, and the pull-down transistor region... The second source / drain doped layer of the pull-up transistor region is closer to the transmission gate transistor region than the first source / drain doped layer; the third layer includes a first partition pattern located at the boundary of adjacent pull-up transistor regions and between the second source / drain doped patterns, the first partition pattern also extending along a first direction to above the gate pattern of the pull-up transistor region; the fourth layer includes a shared plug pattern, the shared plug pattern including a sub-opening pattern located above the second source / drain doped pattern of any pull-up transistor region, and a transition opening pattern located between and connected to the sub-opening patterns of adjacent pull-up transistor regions, the sub-opening pattern also extending to above the gate pattern of another pull-up transistor region, the connected sub-opening pattern and transition opening pattern constituting the shared plug pattern.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the formation method provided by the embodiments of the present invention, in any pull-up transistor region, a first interconnect opening exposing the second source / drain doped layer is formed in the dielectric layer on top of the second source / drain doped layer. The first interconnect opening of the pull-up transistor region also extends to the top of the gate structure of another pull-up transistor region and exposes the corresponding gate structure. Adjacent first interconnect openings in the memory cell region are isolated by a first isolation layer. In the embodiment of the present invention, in the step of forming the first interconnect opening, adjacent first interconnect openings in the memory cell region are separated by the formed first isolation layer, which is beneficial to increase the process window for forming the first interconnect opening. Moreover, in the same step, adjacent first interconnect openings can be formed simultaneously using a single photomask to form a shared plug in the pull-up transistor region, thereby saving process costs and improving process efficiency. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the structure of an SRAM device;

[0010] Figures 2 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming an SRAM device according to the present invention;

[0011] Figure 19 This is the mask plate of the present invention. Figure 1 A schematic diagram of an embodiment. Detailed Implementation

[0012] Currently, the manufacturing costs of SRAM devices need to be reduced, and their manufacturing efficiency needs to be improved. This paper analyzes the reasons why the manufacturing costs and efficiency of an SRAM device need to be reduced and improved.

[0013] Figure 1 This is a schematic diagram of the structure of an SRAM device.

[0014] refer to Figure 1 , Figure 1 This is a top view of an SRAM device. The SRAM device includes a memory cell region 10S, which includes two centrally symmetrical sub-cell regions 10C. Each sub-cell region 10C includes sub-cell regions along a first direction (e.g., ...). Figure 1 The transmission gate transistor region 10G and pull-down transistor region 10D adjacent to each other in the X direction, and along the second direction (such as...) Figure 1 A pull-up transistor region 10U is adjacent to the transmission gate transistor region 10G and the pull-down transistor region 10D in the Y direction. The pull-up transistor regions 10U are arranged adjacent to each other. A gate structure 20 extending in the second direction and arranged in the first direction is formed on the substrate of the memory cell region 10S. A first source / drain doped layer 14 and a second source / drain doped layer 13 are formed in the substrates on both sides of the gate structure 20, respectively. The second source / drain doped layers 13 of the pull-down transistor region 10D and the pull-up transistor region 10U are located on the same side of the gate structure 20, and the second source / drain doped layers 13 of the pull-down transistor region 10D and the pull-up transistor region 10U are relatively smaller than the first source / drain doped layers. The heterogeneous layer 14 is closer to the transmission gate transistor region 10G. A dielectric layer covering the gate structure 20, the second source / drain doped layer 13, and the first source / drain doped layer 14 is also formed on the substrate. In any pull-up transistor region 10U, a shared plug 61 electrically connected to the second source / drain doped layer 13 is formed in the dielectric layer on top of the second source / drain doped layer 13. The shared plug 61 of the pull-up transistor region 10U also extends to the top of the gate structure 20 of another pull-up transistor region 10U and is electrically connected to the corresponding gate structure 20. Adjacent shared plugs 61 in the memory cell region 10S are isolated by the dielectric layer. The second direction is perpendicular to the first direction.

[0015] Specifically, the transmission gate transistor region 10G is used to form the transmission gate transistor, the pull-down transistor region 10D is used to form the pull-down transistor, and the pull-up transistor region 10U is used to form the pull-up transistor. The transmission gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.

[0016] In the memory cell region 10S, adjacent shared plugs 61 are located in adjacent pull-up transistor regions 10U. The spacing between adjacent shared plugs 61 is small, so two photomasks are needed to form two adjacent shared plugs 61 respectively, which can easily increase the process cost and reduce the process efficiency.

[0017] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming an SRAM device, comprising: providing a substrate including a memory cell region, the memory cell region including two centrally symmetrical sub-cell regions, the sub-cell region including a transmission gate transistor region and a pull-down transistor region adjacent to each other along a first direction, and a pull-up transistor region adjacent to the transmission gate transistor region and the pull-down transistor region along a second direction, the pull-up transistor regions being disposed adjacently, a gate structure extending along the second direction and arranged along the first direction being formed on the substrate of the memory cell region, a first source / drain doped layer and a second source / drain doped layer being formed in the substrate on both sides of the gate structure, the second source / drain doped layers of the pull-down transistor region and the pull-up transistor region being located on the same side of the gate structure, and the second source / drain doped layers of the pull-down transistor region and the pull-up transistor region being relatively... The first source / drain doped layer is closer to the transmission gate transistor region. A dielectric layer covering the gate structure, the second source / drain doped layer, and the first source / drain doped layer is also formed on the substrate, with the second direction perpendicular to the first direction. At the junction of adjacent pull-up transistor regions, a first isolation layer is formed on the dielectric layer between the second source / drain doped layers. The first isolation layer also extends along the first direction to above the gate structure of the pull-up transistor region. In any pull-up transistor region, a first interconnect opening exposing the second source / drain doped layer is formed in the dielectric layer at the top of the second source / drain doped layer. The first interconnect opening of the pull-up transistor region also extends to the top of the gate structure of another pull-up transistor region and exposes the corresponding gate structure. Adjacent first interconnect openings in the memory cell region are isolated by the first isolation layer. A shared plug is formed in the first interconnect opening.

[0018] Accordingly, embodiments of the present invention also provide a mask layout, including: a memory cell region, the memory cell region including two centrally symmetrical sub-cell regions, the sub-cell regions including a transmission gate transistor region and a pull-down transistor region adjacent along a first direction, and a pull-up transistor region adjacent to the transmission gate transistor region and the pull-down transistor region along a second direction, the pull-up transistor regions being disposed adjacently, the first direction being perpendicular to the second direction; a first layout layer, including a gate pattern, extending along the second direction in the memory cell region and arranged along the first direction; a second layout layer, including a first source / drain doped pattern and a second source / drain doped pattern located on both sides of the gate pattern, the second source / drain doped patterns of the pull-down transistor region and the pull-up transistor region being located on the same side of the gate pattern, and the pull-down transistor region... The second source / drain doped layer of the pull-up transistor region is closer to the transmission gate transistor region than the first source / drain doped layer; the third layer includes a first partition pattern located at the boundary of adjacent pull-up transistor regions and between the second source / drain doped patterns, the first partition pattern also extending along a first direction to above the gate pattern of the pull-up transistor region; the fourth layer includes a shared plug pattern, the shared plug pattern including a sub-opening pattern located above the second source / drain doped pattern of any pull-up transistor region, and a transition opening pattern located between and connected to the sub-opening patterns of adjacent pull-up transistor regions, the sub-opening pattern also extending to above the gate pattern of another pull-up transistor region, the connected sub-opening pattern and transition opening pattern constituting the shared plug pattern.

[0019] In the formation method provided by the embodiments of the present invention, in any pull-up transistor region, a first interconnect opening exposing the second source / drain doped layer is formed in the dielectric layer on top of the second source / drain doped layer. The first interconnect opening of the pull-up transistor region also extends to the top of the gate structure of another pull-up transistor region and exposes the corresponding gate structure. Adjacent first interconnect openings in the memory cell region are isolated by a first isolation layer. In the embodiment of the present invention, in the step of forming the first interconnect opening, adjacent first interconnect openings are separated by the already formed first isolation layer, which is beneficial to increase the process window for forming the first interconnect opening. Moreover, in the same step, adjacent first interconnect openings can be formed simultaneously using a single photomask to form a shared plug in the pull-up transistor region, thereby saving process costs and improving process efficiency.

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] Figures 2 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming an SRAM device according to the present invention.

[0022] Reference Figures 2 to 5 ,in, Figure 2 This is a top view of an SRAM device. Figure 3 for Figure 2 A top view of the fins and gate structure in any memory cell region. Figure 4 for Figure 2 Cross-sectional view based on the AA direction, Figure 5 for Figure 2 A cross-sectional view based on the BB direction is provided, including a base 100, comprising a storage cell region 100S, the storage cell region 100S comprising two centrally symmetrical sub-cell regions 100C, the sub-cell regions 100C comprising along a first direction (e.g., ... Figure 2 (As shown in the X direction) adjacent transmission gate transistor region 100G and pull-down transistor region 100D, and along the second direction (as shown in the X direction) Figure 2 (As shown in the Y direction) A pull-up transistor region 100U is adjacent to the transmission gate transistor region 100G and the pull-down transistor region 100D. The pull-up transistor regions 100U are arranged adjacent to each other. A gate structure 200 extending in the second direction and arranged in the first direction is formed on the substrate 100 of the memory cell region 100S. A first source / drain doped layer 140 and a second source / drain doped layer 130 are formed in the substrate 100 on both sides of the gate structure 200, respectively. The second source / drain doped layer 130 of the pull-down transistor region 100D and the pull-up transistor region 100U are located on the same side of the gate structure 200, and the second source / drain doped layer 130 of the pull-down transistor region 100D and the pull-up transistor region 100U is closer to the transmission gate transistor region 100G than the first source / drain doped layer 140. A dielectric layer 320 covering the gate structure 200, the second source / drain doped layer 130 and the first source / drain doped layer 140 is also formed on the substrate 100. The second direction is perpendicular to the first direction.

[0023] In this embodiment, the SRAM device includes memory cell regions 100S. Specifically, there are multiple memory cell regions 100S, and adjacent memory cell regions 100S are mirror-distributed in a first direction.

[0024] In this embodiment, in the SRAM device, multiple memory cell regions 100S are arranged in a matrix along a first direction and a second direction. As an example, Figure 2 Six memory cell regions 100S are shown, but the number of memory cell regions 100S contained in an SRAM device is not limited to six.

[0025] Accordingly, the memory cell region 100S includes a transmission gate transistor region 100G, a pull-down transistor region 100D, and a pull-up transistor region 100U. Specifically, the transmission gate transistor region 100G is used to form transmission gate transistors, the pull-down transistor region 100D is used to form pull-down transistors, and the pull-up transistor region 100U is used to form pull-up transistors. The transmission gate transistors and pull-down transistors are both N-type transistors, and the pull-up transistors are P-type transistors.

[0026] In this embodiment, the storage cell area 100S includes two centrally symmetrical sub-cell areas 100C. Each of the two sub-cell areas 100C includes a transmission gate transistor area 100G, a pull-down transistor area 100D, and a pull-up transistor area 100U.

[0027] Specifically, the transmission gate transistor region 100G and the pull-down transistor region 100D are arranged adjacent to each other in the first direction, and the transmission gate transistor region 100G and the pull-down transistor region 100D are arranged adjacent to the pull-up transistor region 100U in the second direction.

[0028] In this embodiment, along the first direction, the fins 110 of the pull-up transistors 100U in adjacent memory cell regions 100S are disconnected from each other. Therefore, in the pull-up transistor transmission region 100U, the end of the fin 110 located on the side of the transmission gate transistor region 100G is recessed relative to the end of the fin 110 in the transmission gate transistor region 100G, effectively preventing the fins 110 in the pull-up transistors 100U in adjacent memory cell regions 100S from contacting each other in the first direction.

[0029] Substrate 100 provides the basis for the fabrication process of SRAM devices.

[0030] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0031] In this embodiment, the SRAM device is taken as a fin field-effect transistor.

[0032] In this embodiment, a fin portion 110 extending in the second direction and arranged in parallel in the first direction is also formed on the substrate 100, and the gate structure 200 spans the fin portion 110 and covers part of the sidewall and part of the top of the fin portion 100.

[0033] Fin 110 is used to provide a channel for the transistor.

[0034] In this embodiment, the material of the fin 110 is the same as the material of the substrate 100, which is silicon. In other embodiments, the material of the fin can also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin can also be different from the material of the substrate.

[0035] In this embodiment, the substrate also includes an isolation layer 120, which covers part of the sidewall of the fin 110. The isolation layer 120 is used to achieve insulation between different devices. For example, in CMOS manufacturing process, an isolation layer 120 is usually formed between NMOS transistors and PMOS transistors.

[0036] In this embodiment, the material of the isolation layer 120 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

[0037] The gate structure 200 is used to control the opening and closing of the transistor channel.

[0038] In this embodiment, the gate structure 200 includes a gate dielectric layer along a portion of the sidewall and a portion of the top of the covering fin 100, and a gate electrode layer located on the gate dielectric layer.

[0039] In this embodiment, the gate structure 200 is a metal gate structure.

[0040] Accordingly, the gate electrode layer includes a work function layer and an electrode layer located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the gate structure.

[0041] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0042] The first source / drain doped layer 130 and the second source / drain doped layer 140 are used as the source or drain region of a fin field-effect transistor. Specifically, the doping type of the first source / drain doped layer 130 and the second source / drain doped layer 140 is the same as the channel conductivity type of the corresponding transistor.

[0043] In this embodiment, the dielectric layer includes a first dielectric layer 310 covering the sidewalls of the gate structure 200 and a second dielectric layer 320 located on the first dielectric layer 310.

[0044] The first dielectric layer 310 serves to isolate adjacent devices and also provides a process basis for forming the gate structure 200.

[0045] The second dielectric layer 320 provides a process basis for the subsequent formation of shared plugs and source-drain plugs. The second dielectric layer 320 also serves to isolate adjacent plugs.

[0046] The dielectric layer is made of insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0047] Continue to refer to Figures 2 to 5At the junction of adjacent pull-up transistor regions 100U, a first isolation layer 410 is formed on the dielectric layer between the second source and drain doped layers 130. The first isolation layer 410 also extends along the first direction above the gate structure 200 of the pull-up transistor region 100U.

[0048] The first isolation layer 410 is used to divide the first interconnect opening located on both sides of the adjacent pull-up transistor regions 100U when the first interconnect opening is subsequently formed in the dielectric layer 410.

[0049] In this embodiment, the material of the first isolation layer 410 has an etching selectivity ratio with the material of the dielectric layer. Therefore, in the subsequent step of forming the first interconnect opening in the dielectric layer, it is beneficial to reduce the damage to the first isolation layer 410, thereby helping to achieve a better isolation effect of the first isolation layer 410 on the first interconnect opening of the adjacent pull-up transistor regions 100U on both sides, and thus helping to ensure the performance of the semiconductor structure.

[0050] It should be noted that the etching selectivity ratio between the dielectric layer material and the first isolation layer 410 material should not be too small. If the etching selectivity ratio between the dielectric layer material and the first isolation layer 410 material is too small, the first isolation layer 410 is easily damaged during the subsequent step of forming the first interconnect opening in the dielectric layer. This makes it difficult to achieve a good isolation effect of the first isolation layer 410 on the first interconnect openings of the adjacent pull-up transistor regions 100U on both sides, affecting the performance of the semiconductor structure. Therefore, in this embodiment, the etching selectivity ratio between the dielectric layer material and the first isolation layer 410 material is greater than or equal to 3:1.

[0051] In this embodiment, the material of the first partition layer 410 includes tungsten, titanium nitride, or amorphous silicon.

[0052] In this embodiment, during the step of forming the first isolation layer 410, a second isolation layer 420 is also formed on the dielectric layer between two adjacent first source / drain doped layers 140 at the junction of adjacent memory cell regions 100S along the first direction, and the second isolation layer 420 extends along the second direction.

[0053] The second partition layer 420 is used to divide the first interconnect opening located on both sides of the adjacent memory cell area 100S when the first interconnect opening is subsequently formed in the dielectric layer.

[0054] Accordingly, in this embodiment, the material of the second partition layer 420 has an etching selectivity ratio with the material of the dielectric layer, and the material of the second partition layer 420 includes tungsten, titanium nitride or amorphous silicon.

[0055] In this embodiment, to simplify the process, the first partition layer 410 and the second partition layer 420 are made of the same material.

[0056] Reference Figures 6 to 14 In the dielectric layer on top of the second source / drain doped layer 130 of any adjacent pull-up transistor region 100U, a first interconnect opening 330 is formed to expose the second source / drain doped layer 130. The first interconnect opening 330 of the pull-up transistor region 100U also extends to the top of the gate structure 200 of the other adjacent pull-up transistor region 100U and exposes the corresponding gate structure 200. The adjacent first interconnect openings 330 in the memory cell region 100S are isolated by the first isolation layer 410.

[0057] In this embodiment, in the step of forming the first interconnect opening 330, adjacent first interconnect openings 330 are separated by the already formed first partition layer 410, which helps to increase the process window for forming the first interconnect opening 330. Moreover, in the same step, adjacent first interconnect openings 330 can be formed simultaneously using a single photomask to form the shared plug in the pull-up transistor region 100U, thereby helping to save process costs and improve process efficiency.

[0058] The first interconnection opening 330 is used to provide space for the subsequent formation of a shared plug.

[0059] In this embodiment, a dry etching process is used to etch the dielectric layer to form the first interconnect opening 330.

[0060] Dry etching is anisotropic, thus minimizing damage to the second source / drain doped layer 130 and gate structure 200 exposed by the first interconnect opening 330. Furthermore, dry etching offers greater directional etching, enabling highly accurate pattern transformation and improving the sidewall morphology quality and dimensional accuracy of the first interconnect opening 330. The dry etching process is an anisotropic dry etching process.

[0061] In this embodiment, at the junction of adjacent memory cell regions 100S along the first direction, a second isolation layer 420 is formed on the dielectric layer between two adjacent first source / drain doped layers 140. Correspondingly, in the step of forming the first interconnect opening 330, the first interconnect opening 330 of adjacent memory cell regions 100S along the first direction is isolated by the second isolation layer 420.

[0062] In this embodiment, the first interconnect opening 330 of the adjacent memory cell area 100S along the first direction is isolated by the second partition layer 420, which is beneficial to further increase the process window for forming the first interconnect opening 330. Moreover, in the same step, the first interconnect opening 330 of the adjacent memory cell area 100S along the first direction can be formed simultaneously using a single photomask, thereby further saving process costs and improving process efficiency.

[0063] Specifically, in conjunction with reference Figures 6 to 15 The steps for forming the first interconnect opening 330 are described in detail.

[0064] Reference Figures 6 to 9 , Figure 6 This is a top view of an SRAM device. Figure 7 for Figure 6 Cross-sectional view based on the AA direction, Figure 8 This is a top view of an SRAM device. Figure 9 for Figure 8 A mask layer 400 is formed based on a cross-sectional view along the BB direction, covering the first isolation layer 410 and the dielectric layer.

[0065] The mask layer 400 is used as an etching mask as an etching medium layer. For example, the material of the mask layer 400 includes a planarization material.

[0066] Specifically, an etching mask layer 500 is formed on the mask layer 400. The etching mask layer 500 is subjected to a first patterning process to form a first patterned opening exposing the top of the mask layer 400. The first patterned opening includes a first patterned sub-opening 510 located above the second source / drain doped layer 130 of any pull-up transistor region 100U, and a patterned transition opening 520 located between and connected to the first patterned sub-openings 510 of adjacent pull-up transistor regions 100U. The first patterned sub-opening 510 also extends above the gate structure 200 of another pull-up transistor region 100U. The first patterned sub-opening 510 and the patterned transition opening 520, which are connected, constitute the first patterned opening; the etched mask layer 500 is subjected to a second patterning process to form a second patterned opening that exposes the top of the mask layer 400. The second patterned opening includes a second patterned sub-opening 530 located on one side of the gate structure 200, above the second source / drain doped layer 130 of the pull-down transistor region 100D and the pull-up transistor region 100U. The second patterned sub-opening 530 extends along the second direction across the second source / drain doped layer 130 of the memory cell region 100S. The second patterned opening is connected to the first patterned opening.

[0067] The first and second patterned openings are used as mask openings of the patterned mask layer 400. The first patterned sub-openings 510 of adjacent memory cell regions 100S along the first direction are all connected, so that the first and second patterned openings can be formed using a single photomask, saving process costs and improving process efficiency.

[0068] It should be noted that the order in which the first and second graphical openings are formed is not limited.

[0069] Reference Figures 10 to 12 , Figure 10This is a top view of an SRAM device. Figure 11 for Figure 10 Cross-sectional view based on the AA direction, Figure 12 for Figure 10 Based on the cross-sectional view along the BB direction, a patterned mask layer 400 is formed to create a mask opening. The mask opening includes a sub-opening 430 located above the second source / drain doped layer 130 of any pull-up transistor region 100U, and a transition opening 440 located between and connected to the sub-openings 430 of adjacent pull-up transistor regions 100U. The sub-openings 430 also extend above the gate structure 200 of another pull-up transistor region 100U.

[0070] It should be noted that, for the sake of clarity of the illustration, Figure 10 The image only shows the mask openings of the mask layer 400 in three adjacent memory cell regions 100S on one side.

[0071] The mask opening is used as a mask opening to form the first interconnect opening 330. The transition opening 440, which is located between the sub-openings 430 of the adjacent pull-up transistor regions 100U and is connected to the sub-openings 430, exposes part of the top of the first isolation layer 410. When the mask opening etches the dielectric layer, the first isolation layer 410 can divide the first interconnect openings 330 of the adjacent pull-up transistor regions 100U on both sides of the first isolation layer 410.

[0072] In this embodiment, during the step of patterning the mask layer 400, the sub-openings 430 of adjacent memory cell regions 100S along the first direction are connected.

[0073] If the sub-openings 430 of adjacent memory cell regions 100S along the first direction are connected, then all the sub-openings 430 of adjacent memory cell regions 100S along the first direction are connected, thereby enabling the use of a single photomask to form a mask opening, saving process costs and improving process efficiency.

[0074] In this embodiment, the sub-openings 430 of adjacent memory cell regions 100S along the first direction are connected and expose part of the top of the second partition layer 420. When the mask opening etches the dielectric layer, the second partition layer 420 can divide the first interconnect openings 330 of adjacent memory cell regions 100S on both sides of the second partition layer 420.

[0075] In this embodiment, the sub-opening 430 serves as the first sub-opening 430. The step of patterning the mask layer 400 further includes: in the sub-cell region 100C, on the side of the gate structure 200, forming a second sub-opening 450 above the second source / drain doped layer 130 of the pull-down transistor region 100D and the pull-up transistor region 100U. The second sub-opening 450 extends along the second direction across the second source / drain doped layer 130 of the memory cell region 100S. The second sub-opening 450 is connected to the transition opening 440. The second sub-opening 450 is used as an etching opening for forming the second interconnect opening.

[0076] Reference Figures 13 to 15 , Figure 13 This is a top view of an SRAM device. Figure 14 for Figure 13 Cross-sectional view based on the AA direction, Figure 15 for Figure 13 Based on the cross-sectional view along the BB direction, the dielectric layer is etched along the mask opening to form the first interconnect opening 330.

[0077] In this embodiment, the first isolation layer 410 and the dielectric layer have an etching selectivity ratio, so that in the step of etching the dielectric layer along the mask opening to form the first interconnect opening 330, the first isolation layer 410 can be retained while etching the dielectric layer, so that the first isolation layer 410 can divide the first interconnect opening 330 located on both sides of the first isolation layer 410 adjacent pull-up transistor regions 100U.

[0078] In this embodiment, the second partition layer 420 and the dielectric layer have an etching selectivity ratio, so that in the step of etching the dielectric layer along the mask opening to form the first interconnect opening 330, the second partition layer 420 can be retained while etching the dielectric layer, so that the second partition layer 420 can divide the first interconnect opening 330 located on both sides of the second partition layer 420 adjacent memory cell regions 100S.

[0079] In this embodiment, after the first interconnect opening 330 is formed, the mask layer 400 is removed to prepare for the subsequent formation of a shared plug in the first interconnect opening 330.

[0080] In this embodiment, a wet etching process is used to remove the mask layer 400.

[0081] Wet etching has the characteristics of isotropic etching, which is beneficial for removing the mask layer 400 cleanly. Moreover, wet etching has a relatively low cost and simple operation steps, and can achieve a large etching selectivity, which helps to reduce damage to other film layers during the removal of the mask layer 400.

[0082] In this embodiment, after removing the mask layer 400, the method further includes removing the first partition layer 410 and the second partition layer 420 to prepare for the subsequent formation of a shared plug.

[0083] Wet etching has the characteristics of isotropic etching, which is beneficial for removing the first isolation layer 410 and the second isolation layer 420 cleanly. Moreover, wet etching has relatively low cost and simple operation steps, and can achieve a large etching selectivity, which helps to reduce damage to other film layers during the removal of the first isolation layer 410 and the second isolation layer 420.

[0084] In this embodiment, before the shared plug is subsequently formed in the first interconnect opening 330, the method further includes: forming a second interconnect opening 450 in the sub-cell region 100C in the dielectric layer on one side of the gate structure 200, which simultaneously exposes the pull-down transistor region 100D and the pull-up transistor region 100U, and the adjacent second interconnect openings 450 in the second direction are isolated by the first isolation layer 410.

[0085] The second interconnect opening 450 is used to provide space for the subsequent formation of the source-drain plug.

[0086] Adjacent second interconnect openings 450 in the second direction are isolated by a first partition layer 410. Adjacent first interconnect openings 330 in the storage cell area 100S also utilize the first partition layer 410 for isolation. The first partition layer 410 enables the formation of the first interconnect opening 330 to utilize the existing first partition layer 410, which helps to save process costs and improve process efficiency. Moreover, since the formation of the first interconnect opening 330 and the second interconnect opening 450 both utilize the first partition layer 410, the first interconnect opening 330 and the second interconnect opening 450 can be formed in the same step, which improves process efficiency.

[0087] In this embodiment, the first interconnection opening 330 and the second interconnection opening 350 are formed in the same step, which simplifies the process flow and improves the process efficiency.

[0088] Reference Figures 16 to 18 , Figure 16 This is a top view of an SRAM device. Figure 17 for Figure 16 Cross-sectional view based on the AA direction, Figure 18 for Figure 16 Based on the cross-sectional view along the BB direction, a shared plug 610 is formed in the first interconnection opening 330.

[0089] It should be noted that, for the sake of clarity of the illustration, Figure 16 The dielectric layer is not shown. Figure 16 Two types of fillers are also used to illustrate interconnect plugs and source / drain plugs.

[0090] In any pull-up transistor region 100U, the first interconnect opening 330 exposes the second source / drain doped layer 130, and the first interconnect opening 330 also extends to expose the gate structure 200 in another pull-up transistor region 100U. Therefore, the shared plug 610 is electrically connected to the second source / drain doped layer 130 of the pull-up transistor region 100U in any sub-cell region 100C, and the gate structure 200 of the pull-up transistor region 100U in another sub-cell region 100C.

[0091] In the memory cell region 100S, the pull-up transistor and pull-down transistor in any sub-cell region 100C constitute a first inverter, and the pull-up transistor and pull-down transistor in another sub-cell region 100C constitute a second inverter. The input terminal of the first inverter and the output terminal of the second inverter are connected to form a latch, and the input terminal of the second inverter and the output terminal of the first inverter are connected to form a latch. That is, the gate structure 200 of the pull-up transistor region 100U in any sub-cell region 100C and the first source / drain doped layer 130 of the pull-up transistor region 100U in another sub-cell region 100C are electrically connected through a shared plug 610, and the gate structure 200 of the pull-up transistor region 100U in another sub-cell region 100C and the second source / drain doped layer 130 of the pull-up transistor region 100U in any sub-cell region 100C are electrically connected through a shared plug 610.

[0092] In this embodiment, the shared plug 610 is made of tungsten. In other embodiments, the shared plug may also be made of cobalt or ruthenium.

[0093] In this embodiment, after forming the second interconnect opening 450, the method further includes forming a source / drain plug 620 in the second interconnect opening 450.

[0094] In subcell region 100C, the second interconnect opening 450 exposes the second source / drain doped layers 130 of pull-down transistor region 100D and pull-up transistor region 100U. Therefore, the source / drain plug 620 is electrically connected to the second source / drain doped layers 130 of pull-down transistor region 100D and pull-up transistor region 100U.

[0095] By using the source-drain plug 620, the source and second source-drain doped layers 130 of the pull-up transistor and pull-down transistor in any sub-cell region 100C are electrically connected, thereby forming a first inverter and a second inverter.

[0096] In this embodiment, the shared plug 610 is in contact with the source / drain plug 620, so that the shared plug 610 and the source / drain plug 620 can share the same plug post and be electrically connected to the second source / drain doped layer 130, and be formed in the same process, simplifying the process steps and improving the process efficiency.

[0097] In other embodiments, the shared plug may also be isolated from the source / drain plug, and the shared plug and the source / drain plug are electrically connected to the second source / drain doped layer, respectively.

[0098] In this embodiment, the source / drain plug 620 is made of tungsten. In other embodiments, the source / drain plug may also be made of cobalt or ruthenium.

[0099] In this embodiment, a shared plug 610 is formed in the first interconnect opening 330 and a source / drain plug 620 is formed in the second interconnect opening 450 in the same step, which simplifies the process steps and improves the process efficiency.

[0100] Figure 19 This is the mask plate of the present invention. Figure 1 A schematic diagram of an embodiment.

[0101] refer to Figure 19 The mask layout includes a storage cell region 101S, which includes two centrally symmetrical sub-cell regions 101C. Sub-cell regions 101C include areas along a first direction (e.g., ...). Figure 18 (As shown in the X direction) Adjacent transmission gate transistor region 101G and pull-down transistor region 101D, and along the second direction (as shown in the X direction) Figure 18 (As shown in the Y direction) A pull-up transistor region 101U is adjacent to the transmission gate transistor region 101G and the pull-down transistor region 101D. The pull-up transistor regions 101U are arranged adjacently, with the first direction perpendicular to the second direction; A first layer includes a gate pattern 201, which extends along the second direction and is arranged along the first direction in the memory cell region 101S; A second layer includes a first source / drain doped pattern 141 and a second source / drain doped pattern 131 located on both sides of the gate pattern 201. The second source / drain doped patterns 131 of the pull-down transistor region 101D and the pull-up transistor region 101U are located on the same side of the gate pattern 201, and the second source / drain doped layers 131 of the pull-down transistor region 101D and the pull-up transistor region 101U are closer to the transmission gate transistor region 101G than the first source / drain doped layer 141; A third layer The first partition pattern 411 is located at the boundary of adjacent pull-up transistor regions 101U and between the second source-drain doped patterns 131. The first partition pattern 411 also extends along the first direction to above the gate pattern 201 of the pull-up transistor region 101U. The fourth layer includes a shared plug pattern 611. The shared plug pattern 611 includes a sub-opening pattern 641 located above the second source-drain doped pattern 131 of any pull-up transistor region 101U, and a transition opening pattern 631 located between and connected to the sub-opening patterns 641 of adjacent pull-up transistor regions 101U. The sub-opening pattern 641 also extends to above the gate pattern 201 of another pull-up transistor region 101U. The connected sub-opening pattern 641 and the transition opening pattern 631 constitute the shared plug pattern 611.

[0102] In this embodiment, the mask layout is used to form an SRAM device, which includes memory cell regions 101S. Specifically, there are multiple memory cell regions 101S, and adjacent memory cell regions 101S are mirror-distributed in a first direction.

[0103] Specifically, in an SRAM device, multiple memory cell regions 101S are arranged in a matrix along a first direction and a second direction. As an example, Figure 19 Six memory cell regions 102S are shown, but the number of memory cell regions 101S contained in an SRAM device is not limited to six.

[0104] Accordingly, the memory cell region 101S includes a transmission gate transistor region 101G, a pull-down transistor region 101D, and a pull-up transistor region 101U. Specifically, the transmission gate transistor region 101G is used to form transmission gate transistors, the pull-down transistor region 101D is used to form pull-down transistors, and the pull-up transistor region 101U is used to form pull-up transistors. The transmission gate transistors and pull-down transistors are both N-type transistors, and the pull-up transistors are P-type transistors.

[0105] In this embodiment, the storage cell region 101S includes two centrally symmetrical sub-cell regions 101C. Each of the two sub-cell regions 101C includes a transmission gate transistor region 101G, a pull-down transistor region 101D, and a pull-up transistor region 101U.

[0106] Specifically, the transmission gate transistor region 101G and the pull-down transistor region 101D are arranged adjacent to each other in the first direction, and the transmission gate transistor region 101G and the pull-down transistor region 101D are arranged adjacent to the pull-up transistor region 101U in the second direction.

[0107] In this embodiment, the mask layout further includes a fifth layer, which includes a fin pattern 111, which extends along a first direction and is arranged in parallel along a second direction.

[0108] Fin pattern 111 is used to form fins, which are used to provide channels for transistors.

[0109] In this embodiment, along the first direction, the fins of the pull-up transistors 101U in adjacent memory cell regions 101S are disconnected from each other. Therefore, in the pull-up transistor transmission region 101U, the end of the fin pattern 111 located on the side of the transmission gate transistor region 101G is recessed relative to the end of the fin pattern 111 in the transmission gate transistor region 101G, effectively preventing the fins of the pull-up transistors 101U in adjacent memory cell regions 101S from contacting each other in the first direction.

[0110] The gate pattern 201 is used to form a gate structure, which is used to control the opening and closing of the transistor channel.

[0111] In this embodiment, the first layer is located above the fifth layer, so in the semiconductor process, the gate structure is formed after the fins are formed.

[0112] In semiconductor manufacturing, the gate structure spans the fins in the region and covers part of the top and sidewalls of the fins. Therefore, the gate pattern 201 is orthogonal to the fin pattern 111 in the region. Specifically, when there are multiple fin patterns 111 in the region, one gate pattern 201 is orthogonal to multiple fin patterns 111.

[0113] The first source / drain doped pattern 141 is used to form the first source / drain doped layer, and the second source / drain doped pattern 131 is used to form the second source / drain doped layer.

[0114] In this embodiment, the second layer is located above the first layer. Therefore, in the semiconductor process, the first source / drain doped layer and the second source / drain doped layer are formed first, and then the gate structure is formed.

[0115] The first partition pattern 411 is used to form a first partition layer, which is used to divide the sub-opening patterns 641 of the adjacent pull-up transistor regions 101U located on both sides of the first partition layer.

[0116] In this embodiment, the third layer is located above the first layer. Therefore, in the semiconductor process, after the gate structure is formed, the first barrier layer is formed.

[0117] In this embodiment, the third layer also includes a second partition pattern 421, which is located at the junction of adjacent memory cell regions 101S along the first direction and between two adjacent first source / drain doped patterns 141. The second partition pattern 421 extends along the second direction.

[0118] The second partition pattern 421 is used to form a second partition layer, which is used to divide the sub-opening patterns 641 of adjacent storage cell areas 101S located on both sides of the second partition layer.

[0119] The shared plug pattern 611 is used to form a shared plug. Specifically, the shared plug pattern 611 is used to form a first interconnect opening. In any pull-up transistor region 101U, a first interconnect opening is formed to expose the second source / drain doped layer. The first interconnect opening of the pull-up transistor region 101U also extends to the top of the gate structure of another pull-up transistor region 101U and exposes the corresponding gate structure. Adjacent first interconnect openings in the memory cell region 101S are isolated by a first isolation layer. Accordingly, the shared plug is electrically connected to the second source / drain doped layer of the pull-up transistor region 101U in any sub-cell region 101C and the gate structure of the pull-up transistor region 101U in another sub-cell region 101C.

[0120] In this embodiment, the fourth layer is located above the third layer. Therefore, in the semiconductor process, the first partition layer is formed first, and then the shared plug is formed.

[0121] In this embodiment, in the fourth layer, the sub-opening patterns 641 of adjacent storage cell areas 101S along the first direction are connected.

[0122] When the sub-opening patterns 641 of adjacent memory cell regions 101S along the first direction are connected to form the first interconnection opening, the second partition layer can divide the first interconnection opening of adjacent memory cell regions 101S located on both sides of the second partition layer.

[0123] In this embodiment of the invention, adjacent first interconnect openings are separated by a first partition layer that has already been formed, which helps to increase the process window for forming the first interconnect openings. Thus, in the same step, an adjacent first interconnect opening can be formed simultaneously using a single photomask to form a shared plug in the pull-up transistor region 101U, thereby helping to save process costs and improve process efficiency.

[0124] In this embodiment, the mask layout further includes a sixth layer, including a source / drain plug pattern 621, located on one side of the gate pattern 201 and above the second source / drain doped pattern 131 of the pull-down transistor region 101D and the pull-up transistor region 101U. The source / drain plug pattern 621 extends along the second direction across the second source / drain doped pattern 131 of the memory cell region 101S.

[0125] The first partition layer is also used to divide the source and drain plug patterns 621 of the adjacent sub-unit regions 101C located on both sides of the first partition layer.

[0126] Source-drain plug pattern 621 is used to form source-drain plugs, which are electrically connected to the second source-drain doped layers of pull-down transistor region 101D and pull-up transistor region 101U.

[0127] In this embodiment, the shared plug pattern 611 is in contact with the source / drain plug pattern 621, so that the shared plug and the source / drain plug can share the same plug post and be electrically connected to the second source / drain doped layer, and be formed in the same process, simplifying the process steps and improving the process efficiency.

[0128] In other embodiments, the shared plug pattern may also be isolated from the source / drain plug pattern, and the shared plug and the source / drain plug are electrically connected to the second source / drain doped layer, respectively.

[0129] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming an SRAM device, characterized in that, include: A substrate is provided, including a memory cell region. The memory cell region includes a transmission gate transistor region and a pull-down transistor region adjacent to each other along a first direction, and a pull-up transistor region adjacent to the transmission gate transistor region and the pull-down transistor region along a second direction. The pull-up transistor regions are arranged adjacent to each other. A gate structure extending along the second direction and arranged along the first direction is formed on the substrate of the memory cell region. A first source / drain doped layer and a second source / drain doped layer are formed in the substrate on both sides of the gate structure, respectively. The second source / drain doped layers of the pull-down transistor region and the pull-up transistor region are located on the same side of the gate structure, and the second source / drain doped layers of the pull-down transistor region and the pull-up transistor region are closer to the transmission gate transistor region than the first source / drain doped layer. A dielectric layer covering the gate structure, the second source / drain doped layer and the first source / drain doped layer is also formed on the substrate. The second direction is perpendicular to the first direction. At the junction of adjacent pull-up transistor regions, a first isolation layer is formed on the dielectric layer between the second source and drain doped layers, and the first isolation layer also extends along the first direction to above the gate structure of the pull-up transistor region. In the dielectric layer at the top of the second source / drain doped layer of any of the adjacent pull-up transistor regions, a first interconnect opening is formed to expose the second source / drain doped layer. The first interconnect opening also extends to the top of the gate structure of the other adjacent pull-up transistor region and exposes the corresponding gate structure. Adjacent first interconnect openings in the memory cell region are isolated by the first isolation layer. A shared plug is formed in the first interconnection opening.

2. The method for forming an SRAM device as described in claim 1, characterized in that, The number of storage cell areas is multiple, and adjacent storage cell areas are mirror-distributed in the first direction; The method further includes: forming a second isolation layer on a dielectric layer between two adjacent first source / drain doped layers at the boundary of adjacent memory cell regions along the first direction, wherein the second isolation layer extends along the second direction to form the first interconnect opening, wherein the first interconnect opening of the adjacent memory cell regions along the first direction is isolated by the second isolation layer.

3. The method for forming an SRAM device as described in claim 1, characterized in that, Before forming the shared plug in the first interconnect opening, the method further includes: forming a second interconnect opening in a dielectric layer on one side of the gate structure, which simultaneously exposes the pull-down transistor region and the pull-up transistor region, wherein adjacent second interconnect openings in the second direction are isolated by the first isolation layer.

4. The method for forming an SRAM device as described in claim 3, characterized in that, The first interconnect opening and the second interconnect opening are formed in the same step.

5. The method for forming an SRAM device as described in claim 3, characterized in that, The method further includes forming a source / drain plug in the second interconnect opening.

6. The method for forming an SRAM device as described in claim 5, characterized in that, The shared plug and the source / drain plug are formed in the same step.

7. The method for forming an SRAM device as described in claim 1, characterized in that, The step of forming the first interconnect opening includes: forming a mask layer covering the first isolation layer and the dielectric layer; The mask layer is patterned to form a mask opening, the mask opening including a sub-opening located above the second source / drain doped layer of any of the pull-up transistor regions, and a transition opening located between and connected to the sub-openings of adjacent pull-up transistor regions, the sub-openings also extending above the gate structure of the other pull-up transistor region; The dielectric layer is etched along the opening of the mask to form the first interconnect opening.

8. The method for forming an SRAM device as described in claim 7, characterized in that, The number of storage cell areas is multiple, and adjacent storage cell areas are mirror-distributed in the first direction; The method further includes: forming a second isolation layer on a dielectric layer between two adjacent first source / drain doped layers at the boundary of adjacent memory cell regions along the first direction, the second isolation layer extending along the second direction and communicating with sub-openings of the adjacent memory cell regions along the first direction.

9. The method for forming an SRAM device as described in claim 1, characterized in that, The material of the first partition layer includes tungsten, titanium nitride, or amorphous silicon.

10. The method for forming an SRAM device as described in claim 1, characterized in that, The material of the dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

11. The method for forming an SRAM device as described in claim 1, characterized in that, The dielectric layer is etched using a dry etching process to form the first interconnect opening.

12. A photomask layout, characterized in that, include: The storage cell area includes a transmission gate transistor area and a pull-down transistor area adjacent to each other along a first direction, and a pull-up transistor area adjacent to the transmission gate transistor area and the pull-down transistor area along a second direction. The pull-up transistor areas are arranged adjacent to each other, and the first direction is perpendicular to the second direction. The first layer includes a gate pattern that extends along the second direction and is arranged along the first direction in the memory cell region; The second layer includes a first source-drain doped pattern and a second source-drain doped pattern located on both sides of the gate pattern. The second source-drain doped patterns of the pull-down transistor region and the pull-up transistor region are located on the same side of the gate pattern, and the second source-drain doped layers of the pull-down transistor region and the pull-up transistor region are closer to the transmission gate transistor region than the first source-drain doped layer. The third layer includes a first partition pattern located at the boundary of adjacent pull-up transistor regions and between the second source / drain doped patterns. The first partition pattern also extends along the first direction above the gate pattern of the pull-up transistor region. The fourth layer includes a shared plug pattern, which includes a sub-aperture pattern located above the second source / drain doped pattern of any of the pull-up transistor regions, and a transitional opening pattern located between and connected to the sub-aperture patterns of adjacent pull-up transistor regions. The sub-aperture pattern also extends above the gate pattern of another pull-up transistor region, and the connected sub-aperture pattern and transitional opening pattern constitute the shared plug pattern.

13. The mask layout as described in claim 12, characterized in that, The number of storage cell areas is multiple, and adjacent storage cell areas are mirror-distributed in the first direction; The third layer also includes a second partition pattern located at the boundary of adjacent memory cell regions along the first direction and between two adjacent first source / drain doped patterns, the second partition pattern extending along the second direction.

14. The mask layout as described in claim 13, characterized in that, In the fourth layer, the sub-opening patterns of adjacent storage cell areas along the first direction are connected.

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