A capacitance-charged drive circuit and method for suppressing oscillation of a hysteretic comparator

Abstract

The application discloses a capacitor charging type drive circuit and method for inhibiting oscillation of a hysteresis comparator, and is characterized in that the circuit comprises a drive unit and a charging time control unit; wherein the drive unit drives a switch tube M1 to be turned on or turned off based on an output voltage of the hysteresis comparator, so as to control charging and discharging states of the capacitor and charging states of a load in a later stage; and the charging time control unit is connected with the drive unit and is used for controlling the switch tube M1 to keep a turned-on state in a delay time when the output level of the hysteresis comparator is low. The circuit has simple structure, few components, and is less limited in parameter selection of a preset delay time and a reference voltage, and has good circuit output effect.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a capacitor-charged drive circuit and method for suppressing hysteresis comparator oscillations. Background Technology

[0002] Currently, in order to suppress excessive discharge, drive circuits typically incorporate over-discharge protection units when supplying power to downstream loads. These units quickly shut down the drive transistors used for discharge in the event of potential over-discharge. Generally, existing over-discharge protection units employ hysteresis comparators to compare the magnitude of the drive voltage and provide protection when the drive voltage is excessive.

[0003] However, hysteresis comparators typically use two different reference voltages simultaneously to switch between high and low levels. It's important to note that if the difference between the two reference voltages is too large, the circuit may be difficult to apply to low-voltage chips or integrated circuits, or it may fail to adequately power the drive capacitor in the drive circuit. Conversely, if the difference between the two reference voltages is too small, when the load is high and the output current of the drive transistor is large, the hysteresis comparator is likely to experience frequent state switching between the two reference voltages, or even oscillate.

[0004] When the circuit oscillates, the actual charging time within the same period is shorter than the expected charging time. This makes it difficult for the drive capacitor in the circuit to charge to the amount specified in the circuit design. When the capacitor is undercharged, it may not be able to fully drive the downstream load during its actual discharge process.

[0005] To address this issue, background technology document CN212381445U provides an LED driver circuit that uses an enable signal generation module connected to the output of a mode control module. When the LED driver circuit operates in normal driving mode, it is controlled by an LED switching control signal. When the LED driver circuit operates in over-discharge protection mode, it shuts down the drive control module to stop power supply. However, this circuit requires careful consideration of the values ​​of the three reference voltages and involves the use of operational amplifiers, charge pumps, and other components, resulting in a complex circuit structure and limited application scenarios.

[0006] To address the above problems, this invention provides a novel capacitor-charged drive circuit for suppressing hysteresis comparator oscillations. Summary of the Invention

[0007] To address the shortcomings of existing technologies, the present invention aims to provide a capacitor-charged drive circuit that suppresses hysteresis comparator oscillations by adding a charging time control unit, thereby extending the conduction of the switching transistor and the charging of the drive capacitor based on a preset delay time.

[0008] The present invention adopts the following technical solution.

[0009] The first aspect of the present invention relates to a capacitor charging drive circuit for suppressing hysteresis comparator oscillation, wherein the circuit includes a drive unit and a charging time control unit; the drive unit drives the switch M1 to turn on or off based on the output voltage of the hysteresis comparator, thereby controlling the charging and discharging state of the capacitor and the charging state of the downstream load; the charging time control unit is connected to the drive unit and is used to control the switch M1 to remain on during a delay time when the output level of the hysteresis comparator is low.

[0010] Preferably, the charging time control unit includes an OR gate, a delay unit, a NOT gate, and an AND gate; wherein, the first input terminal of the OR gate is connected to the output terminal of the hysteresis comparator, and the output terminal is respectively connected to the input terminal of the delay unit, the first input terminal of the AND gate, and the gate of the switching transistor M1; the output terminal of the delay unit is connected to the second input terminal of the AND gate after passing through the NOT gate, and the output terminal of the AND gate is connected to the second input terminal of the OR gate.

[0011] Preferably, the driving unit includes the hysteresis comparator, the switching transistor M1, the driving resistor R, and the driving capacitor C; wherein, the first positive input terminal of the hysteresis comparator is connected to the first reference voltage Vref1, the second positive input terminal is connected to the second reference voltage Vref2, and the negative input terminal is connected to the source of the switching transistor M1 and one end of the driving resistor R; the drain of the switching transistor M1 is connected to the power supply, the other end of the driving resistor R serves as the load output terminal, and is grounded after passing through the driving capacitor C.

[0012] Preferably, the first reference voltage Vref1 is greater than the second reference voltage Vref2; and when the output voltage of the hysteresis comparator is low, the reference voltage of the hysteresis comparator is the first reference voltage Vref1, and when the output voltage is high, the reference voltage of the hysteresis comparator is the second reference voltage Vref2.

[0013] Preferably, when the circuit is powered on, the driving capacitor C is in a charging state before the voltage at the negative input terminal of the hysteresis comparator gradually rises to the first reference voltage Vref1; the output voltage of the hysteresis comparator is in a high-level state.

[0014] Preferably, when the voltage at the negative input terminal of the hysteresis comparator rises to the first reference voltage Vref1, the output voltage of the hysteresis comparator switches to a low level, and the driving capacitor continues to charge during the delay period after the output of the hysteresis comparator switches to a low level; when the delay period ends, the switching transistor M1 is turned off, and the driving capacitor switches to a discharging state.

[0015] Preferably, when the driving capacitor is in a discharging state, the switch M1 is turned off before the voltage at the negative input terminal of the hysteresis comparator gradually decreases to the second reference voltage Vref2; when the voltage at the negative input terminal of the hysteresis comparator decreases to the second reference voltage Vref2, the output voltage of the hysteresis comparator switches to a high level, and the switch M1 is immediately turned on.

[0016] Preferably, the preset delay time of the delay unit is determined based on the charging speed of the driving capacitor.

[0017] Preferably, the preset delay time Where C is the capacitance of the driving capacitor, and I is the drain-source current when the switching transistor M1 is turned on.

[0018] A second aspect of the present invention relates to a capacitor-charged driving method for suppressing hysteresis comparator oscillation, the method being implemented based on a capacitor-charged driving circuit for suppressing hysteresis comparator oscillation as described in the first aspect of the present invention.

[0019] The beneficial effects of this invention are that, compared with the prior art, the capacitor-charging drive circuit for suppressing hysteresis comparator oscillation in this invention can suppress the oscillation of the hysteresis comparator by adding a charging time control unit and extending the conduction of the switching transistor and the charging of the drive capacitor based on a preset delay time, thereby ensuring the stable power supply of the drive circuit to the downstream load. This invention has a simple circuit structure, fewer components, fewer restrictions on the selection of preset delay time and reference voltage parameters, and good circuit output performance. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a capacitor-charged driving circuit in the prior art of this invention;

[0021] Figure 2 This is a schematic diagram of a capacitor-charged drive circuit for suppressing hysteresis comparator oscillation according to the present invention. Detailed Implementation

[0022] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0023] Figure 1 This is a schematic diagram of a capacitor-charged drive circuit in the prior art of this invention. Figure 1 As shown, in the driving circuits commonly used in the prior art, a hysteresis comparator is added to protect against over-discharge. This hysteresis comparator is usually located at the output terminal of the driving switch M1, and in this invention, it is the source of M1. After receiving the output voltage of M1, it compares it with a reference voltage to generate a feedback signal to drive the gate of the switch M1 to turn on or off.

[0024] In addition, to ensure stable power supply to the downstream load, a driving resistor R and a driving capacitor C are added in this invention. The driving resistor R and driving capacitor C are connected in series, with one end connected to the output terminal of the switching transistor and the other end grounded. When the capacitor is charging, the downstream load's power supply is interrupted; when the capacitor is discharging, the downstream load receives power from the capacitor.

[0025] Analyzing the operation of this circuit, when the chip is powered on, the voltage at B in the circuit is 0. At this time, the voltage at the output terminal D of the hysteresis comparator is at a high level, thereby turning on the switching transistor M1, so that the charging current I charges the capacitor C through the resistor, and the voltage value of the upper plate of the capacitor C gradually increases.

[0026] When the voltage at point B gradually increases to the first reference voltage Vref1, the output voltage of the hysteresis comparator flips from a high level to a low level. At this time, the switch M1 is turned off, and there is no current flowing through point B and the drive resistor R, so there is no voltage drop across the drive resistor R. Then, as the drive capacitor C gradually discharges, the voltage at point B gradually decreases. When the voltage at point B gradually decreases to the second reference voltage Vref2, the output signal of the hysteresis comparator flips again, changing from a low level to a high level. This causes the switch M1 to turn on again, and the drive capacitor recharges.

[0027] Once the circuit reaches a stable state, the voltage at point B will fluctuate between the first reference voltage Vref1 and the second reference voltage Vref2. Therefore, if the voltage difference between the two reference voltages Vref1 and Vref2 is small, the switching transistor M1 will continuously and rapidly switch between the on and off states, making it difficult for the MOSFET to maintain a stable operating state, and even causing oscillation.

[0028] In existing technologies, to prevent circuit oscillation, the switching time of the switching transistor M1 between its on and off states is typically extended by increasing the difference between the two reference voltages. However, the effectiveness of this approach is limited. For example, when this drive circuit is applied to a low-voltage chip, the power supply voltage itself is low; therefore, the difference between the first and second reference voltages cannot be increased beyond the power supply voltage. On the other hand, to ensure that the drive capacitor can be fully charged and kept in a state that does not over-discharge, the lower reference voltage cannot be too low.

[0029] To address this problem, the present invention provides a novel capacitor-charged drive circuit for suppressing hysteresis comparator oscillations.

[0030] Figure 2 This is a schematic diagram of a capacitor-charged drive circuit for suppressing hysteresis comparator oscillation according to the present invention. Figure 2As shown, a capacitor charging drive circuit for suppressing hysteresis comparator oscillation is disclosed. The circuit includes a drive unit and a charging time control unit. The drive unit drives the switch M1 to turn on or off based on the output voltage of the hysteresis comparator, thereby controlling the charging and discharging state of the capacitor and the charging state of the downstream load. The charging time control unit is connected to the drive unit and is used to control the switch M1 to remain on during the delay time when the output level of the hysteresis comparator is low.

[0031] The circuit design concept in this invention is to keep the switching transistor in the on state for a certain preset delay time after the output level of the hysteresis comparator switches from a high level to a low level. In this way, the circuit of this invention increases the on-time of the switching transistor and reduces the off-time of the switching transistor to a certain extent. In other words, it prolongs the charging time of the driving capacitor and reduces the time that the driving capacitor supplies power to the subsequent load.

[0032] Preferably, the charging time control unit includes an OR gate, a delay unit, a NOT gate, and an AND gate; wherein, the first input terminal of the OR gate is connected to the output terminal of the hysteresis comparator, and the output terminal is respectively connected to the input terminal of the delay unit, the first input terminal of the AND gate, and the gate of the switching transistor M1; the output terminal of the delay unit is connected to the second input terminal of the AND gate after passing through the NOT gate, and the output terminal of the AND gate is connected to the second input terminal of the OR gate.

[0033] The charging time control unit in this invention is essentially a logic control circuit used to delay the transition of the gate voltage of the switching transistor M1 when the output of the hysteresis comparator changes from high to low within a certain delay time. Furthermore, this logic control circuit can maintain the original circuit's control logic during other time periods, allowing the output voltage of the hysteresis comparator to control the on or off state of the switching transistor.

[0034] Preferably, the driving unit includes a hysteresis comparator, a switching transistor M1, a driving resistor R, and a driving capacitor C; wherein, the first positive input terminal of the hysteresis comparator is connected to a first reference voltage Vref1, the second positive input terminal is connected to a second reference voltage Vref2, and the negative input terminal is connected to the source of the switching transistor M1 and one end of the driving resistor R; the drain of the switching transistor M1 is connected to the power supply, the other end of the driving resistor R serves as the load output terminal, and is grounded after passing through the driving capacitor C.

[0035] In the second aspect of this invention, the connection method of the hysteresis comparator, the switching transistor, and the driving resistor and capacitor is similar to that in the prior art, and can be used to prevent excessive discharge of the circuit.

[0036] Preferably, the first reference voltage Vref1 is greater than the second reference voltage Vref2; and when the output voltage of the hysteresis comparator is low, the reference voltage of the hysteresis comparator is the first reference voltage Vref1, and when the output voltage is high, the reference voltage of the hysteresis comparator is the second reference voltage Vref2.

[0037] In this invention, the first reference voltage can be set to be higher than the second reference voltage. In this way, when the voltage at the negative input terminal of the hysteresis comparator gradually rises to a level higher than the first reference voltage, its output terminal will change from high to low. Conversely, when the voltage at the negative input terminal gradually decreases to a level lower than the second reference voltage, its output terminal will change from low to high.

[0038] Preferably, when the circuit is powered on, the driving capacitor C is in a charging state before the voltage at the negative input terminal of the hysteresis comparator gradually rises to the first reference voltage Vref1; the output voltage of the hysteresis comparator is in a high-level state.

[0039] In this invention, when the circuit is powered on, the voltage at the negative input terminal of the hysteresis comparator gradually increases from zero. Before the output voltage of the hysteresis comparator gradually rises and triggers a reversal of its output voltage state, the output voltage of the hysteresis comparator remains at a high level.

[0040] At this point, since the output of the delay unit is initially at a low level, the first input of the AND gate is at a high level, thus causing the OR gate output to be at a high level. The high-level OR gate output voltage will continue until the preset delay of the delay unit ends. The circuit will maintain this state until the voltage at point B in the circuit rises to equal the first reference voltage Vref1. At this time, the voltage drop across the resistor is I*R, and the voltage across the upper plate of the capacitor is V. b -I*R.

[0041] Preferably, when the voltage at the negative input terminal of the hysteresis comparator rises to the first reference voltage Vref1, the output voltage of the hysteresis comparator switches to a low level, and the driving capacitor continues to charge during the delay period after the output of the hysteresis comparator switches to a low level; when the delay period ends, the switching transistor M1 is turned off, and the driving capacitor switches to a discharging state.

[0042] Specifically, after a preset delay, the output of the delay unit flips, causing the voltage at point H in the circuit to change from high to low. If the voltage at point B has not yet risen to the first reference voltage Vref1, the voltage at point D, the output of the hysteresis comparator, will not flip and will remain high. However, if the voltage at point B has risen to the first reference voltage Vref1, causing the voltage at point D to drop, the voltage at point E will change along with the output voltage of the AND gate. At this point, since the delay time has passed, point F will rise along with the high level of point E, causing point H to become low. This makes the output of the AND gate also low, and the voltage at point E causes the switch M1 to turn off.

[0043] Preferably, when the driving capacitor is in the discharging state, the switch M1 is turned off before the voltage at the negative input terminal of the hysteresis comparator gradually decreases to the second reference voltage Vref2; when the voltage at the negative input terminal of the hysteresis comparator decreases to the second reference voltage Vref2, the output voltage of the hysteresis comparator switches to a high level, and the switch M1 is immediately turned on.

[0044] As the switching transistor M1 turns off, the drive capacitor begins to discharge and supply power to the subsequent load. In this situation, the voltage at point B gradually decreases. Until the voltage at point B drops to Vref2, point D will remain at a low level, causing the state of point E to be influenced by the feedback from point Q. Since the voltage at point E is always low, point Q also remains at a low level.

[0045] When the voltage at point B in the circuit has dropped to Vref2, the voltage at point D will rise, which will cause the voltage at point E to rise, and the switching transistor will turn on again. At this time, the voltage at point E is controlled by point D and is not affected by the delay unit in the circuit.

[0046] Preferably, the preset delay time of the delay unit is determined based on the charging speed of the driving capacitor.

[0047] In this invention, the preset delay time of the delay unit can be determined in advance based on the charging speed of the driving capacitor, so that the capacitor is fully charged during the delay period, and the capacitor discharge can provide sufficient power to the downstream load during the non-charging period.

[0048] Preferably, the preset delay time Where C is the capacitance of the driving capacitor, and I is the drain-source current when the switching transistor M1 is turned on.

[0049] In this invention, the preset delay time should not be greater than the time it takes for the voltage at point B to rise or fall from one reference voltage to another, as long as it ensures that no oscillation occurs in the circuit.

[0050] A second aspect of the present invention relates to a capacitor-charged driving method for suppressing hysteresis comparator oscillation, the method being implemented based on a capacitor-charged driving circuit for suppressing hysteresis comparator oscillation as described in the first aspect of the present invention.

[0051] The beneficial effects of this invention are that, compared with the prior art, the capacitor-charging drive circuit for suppressing hysteresis comparator oscillation in this invention can suppress the oscillation of the hysteresis comparator by adding a charging time control unit and extending the conduction of the switching transistor and the charging of the drive capacitor based on a preset delay time, thereby ensuring the stable power supply of the drive circuit to the downstream load. This invention has a simple circuit structure, fewer components, fewer restrictions on the selection of preset delay time and reference voltage parameters, and good circuit output performance.

[0052] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A capacitor-charged drive circuit for suppressing hysteresis comparator oscillation, characterized in that: The circuit includes a drive unit and a charging time control unit; wherein... The driving unit drives the switching transistor M1 to turn on or off based on the output voltage of the hysteresis comparator, thereby controlling the charging and discharging state of the capacitor and the charging state of the downstream load. The charging time control unit is connected to the drive unit and is used to control the switch M1 to remain in the conducting state during the delay time when the output level of the hysteresis comparator is low. The charging time control unit includes an OR gate, a delay unit, a NOT gate, and an AND gate; the first input of the OR gate is connected to the output of the hysteresis comparator, and the output is connected to the input of the delay unit, the first input of the AND gate, and the gate of the switching transistor M1, respectively; the output of the delay unit is connected to the second input of the AND gate after passing through the NOT gate, and the output of the AND gate is connected to the second input of the OR gate. When the voltage at the negative input terminal of the hysteresis comparator rises to the first reference voltage Vref1, the output voltage of the hysteresis comparator switches to a low level, and the driving capacitor C continues to charge during the delay period after the output of the hysteresis comparator switches to a low level; when the delay period ends, the switching transistor M1 is turned off, and the driving capacitor C switches to a discharging state.

2. The capacitor-charged drive circuit for suppressing hysteresis comparator oscillation as described in claim 1, characterized in that: The driving unit includes the hysteresis comparator, the switching transistor M1, the driving resistor R, and the driving capacitor C; The first positive input terminal of the hysteresis comparator is connected to the first reference voltage Vref1, the second positive input terminal is connected to the second reference voltage Vref2, and the negative input terminal is connected to the source of the switching transistor M1 and one end of the driving resistor R. The drain of the switching transistor M1 is connected to the power supply, and the other end of the driving resistor R serves as the load output terminal, and is grounded after passing through the driving capacitor C.

3. The capacitor-charged drive circuit for suppressing hysteresis comparator oscillation as described in claim 2, characterized in that: The first reference voltage Vref1 is greater than the second reference voltage Vref2; and, When the output voltage of the hysteresis comparator is low, the reference voltage of the hysteresis comparator is the first reference voltage Vref1; when the output voltage is high, the reference voltage of the hysteresis comparator is the second reference voltage Vref2.

4. The capacitor-charged drive circuit for suppressing hysteresis comparator oscillation as described in claim 3, characterized in that: When the circuit is powered on, the driving capacitor C is in a charging state before the voltage at the negative input terminal of the hysteresis comparator gradually rises to the first reference voltage Vref1. The output voltage of the hysteresis comparator is in a high-level state.

5. The capacitor-charged drive circuit for suppressing hysteresis comparator oscillation as described in claim 1, characterized in that: When the driving capacitor C is in a discharging state, the voltage at the negative input terminal of the hysteresis comparator gradually decreases to the second reference voltage Vref2 before the switching transistor M1 is turned off. When the voltage at the negative input terminal of the hysteresis comparator drops to the second reference voltage Vref2, the output voltage of the hysteresis comparator switches to a high level, and the switching transistor M1 immediately turns on.

6. A capacitor-charged drive circuit for suppressing hysteresis comparator oscillation as described in claim 5, characterized in that: The preset delay time of the delay unit is determined based on the charging speed of the driving capacitor C.

7. A capacitor-charged drive circuit for suppressing hysteresis comparator oscillation as described in claim 6, characterized in that: The preset delay time ; in, The capacitance of the driving capacitor is... This is the drain-source current when the switching transistor M1 is turned on.

8. A capacitor-charged driving method for suppressing hysteresis comparator oscillation, characterized in that: The method is implemented based on a capacitor-charged drive circuit for suppressing hysteresis comparator oscillation as described in any one of claims 1-7.

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