Introducing and detecting a stop condition for errors in a single UART

Abstract

A universal asynchronous receiver / transmitter includes a transmit register including information to be transmitted, a receive register including received information, a frame error check circuit that evaluates contents of the receive register for a frame error, and a control logic. The control logic routes contents of the transmit register to the receive register. During transmission of the contents of the transmit register to the receive register through a reprogrammable pin, the control logic modifies a bit inversion register to produce modified contents to be provided to the receive register. The modified contents cause a frame error. The control logic determines whether the frame error check circuit detects the frame error.

Description

[0001] priority

[0002] This application claims priority to Indian Application No. 202111044129, filed on September 29, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This application relates to electronic communications, and more specifically to introducing and detecting faulty stop conditions in a single universal asynchronous receiver / transmitter (UART). Background Technology

[0004] UART is used to implement various communication protocols between electronic devices. UART can be used for serial communication. Data transmission via UART can be framed by start and stop bits to facilitate timing between UARTs on different devices.

[0005] Various errors can occur during data transmission between UARTs. These errors can arise from noise in, for example, the transmitting device, the transmission medium, or the receiving device, or from a misconfiguration of one of these components. One such error may include a faulty stop condition error. A faulty stop condition error can cause a frame error. For example, two UARTs communicating at different baud rates may result in a frame error.

[0006] The inventors of the examples of this disclosure have discovered that testing UART circuits, devices, and modules often involves two or more such UART circuits, devices, or modules. Data is generated by one such UART and received by other such UARTs. Such errors, such as frame errors or stop condition errors, can be artificially created to test the correctness of operation. However, by using a separate UART circuit, device, or module (which may then reside on a microcontroller or system separate from the original UART circuit, device, or module), the inventors of the examples of this disclosure have discovered that this reliance on another UART circuit, device, or module can lead to additional errors. Such additional errors can include positive or negative misidentification results generated by the error testing capabilities of the test UART. For example, data can be sent from a transmitting UART to a receiving UART. Test mechanisms in the transmitting UART can introduce frame errors, for example, by sending erroneous frames with data transmitted at a mismatched baud rate. However, if, for example, noise causes an error inversion when the frame is received and processed by the receiving UART, the error may not be detected. In the testing or verification of a UART, there may be instances where frame error checking does not work correctly, even if such frame error checking works correctly. Furthermore, it may be unclear whether the frame error check of the transmitting UART is not working correctly or the frame error check of the receiving UART is not working correctly, or whether there is noise in the transmitting UART, the transmission medium, or the receiving UART.

[0007] In another example, an interrupt signal can be sent from the UART's transmitter pin to the receive pin in a loopback configuration to generate a framing error. However, in such examples, additional data bytes may be sent along with the interrupt signal to cause a framing error. Framing error handling can be performed using an Interrupt Service Routine (ISR). Interrupt signal handling can also be performed using an ISR. These can also inadvertently introduce additional errors due to failures in these processing systems.

[0008] In yet another example, the receiver pin on the microcontroller can be driven low to introduce a frame error. However, the timing for driving the receiver pin low to sufficiently induce a frame error can vary depending on the baud rate used by the UART under test. This can add additional complexity, making the technique for introducing frame errors adaptable to different baud rates that various UARTs might use. The inventors of the examples disclosed herein have found that the examples of this disclosure solve one or more of these problems. Attached Figure Description

[0009] Figure 1 This is an illustration of an exemplary system for introducing and detecting stop condition errors in UART transmissions, based on examples of this disclosure.

[0010] Figure 2 This is a timing diagram illustrating, according to an example of this disclosure, the introduction of a stop condition error into a UART transmission using a bit reversal of the transmit register.

[0011] Figure 3 This is an illustration of a method for introducing and detecting stop condition errors in UART transmission, based on an example of this disclosure. Detailed Implementation

[0012] Figure 1 This is an illustration of an exemplary system 100 for introducing and detecting framing errors in a single UART, according to examples of this disclosure. Framing errors can be introduced, for example, by introducing a stop condition error. A stop condition error may include, for example, introducing a stop bit error. Communication between UARTs can be performed using frames. Each frame may have a start condition and a stop condition, indicating the start and end of the frame. A stop condition can be implemented by expected values ​​in a sequence of frames. A given UART can detect a framing error when it does not see a stop bit at the expected time during frame transmission. Since the start bit is used to identify the start of an input character or frame, the timing of the start bit can be used as a reference for the remaining bits, and therefore as a reference when the stop bit is expected. If the data line is not in the expected state (such as logic high) when the stop bit is expected, a given UART can determine a framing error, taking into account the amount of data set by the UART and the number of parity bits.

[0013] System 100 can be implemented in any suitable environment, such as in a controller, microcontroller, die, integrated circuit, system-on-a-chip, application-specific integrated circuit, field-programmable gate array, computer, mobile device, or any other suitable electronic device. Figure 1 In the example, system 100 can be implemented by a microcontroller.

[0014] System 100 may include a UART 116. The UART 116 may be implemented by instructions for execution by a processor, analog circuitry, digital circuitry, control logic units, digital logic circuitry programmed via a hardware description language, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), or any suitable combination thereof, whether in a single device or distributed across several devices. System 100 may include more instances of the UART 116 than shown. However, a single such UART 116 may be configured to introduce and detect stop bit errors. In the case of multiple instances of the UART 116, each of the multiple instances of the UART 116 may introduce and detect stop bit errors.

[0015] System 100 may include any suitable external ports, such as TX port 130 and RX port 118, for providing communication to and from UART 116. Such ports 130 and 118 may be implemented by any suitable electrical connection. In various examples, ports 130 and 118 may be external connections to the die, board, chip, or other package of UART 116. Ports 130 and 118 may be configured to provide communication between UART 116 and other instances of UART on other devices.

[0016] System 100 may include any other suitable types and numbers of components. For example, system 100 may include a processor 102 communicatively coupled to memory 104. Memory 104 may include instructions that, when loaded and executed by processor 102, can implement software executed by system 100. System 100 may include a system bus 106. System bus 106 may be configured to provide communication between processor 102 and other parts of system 100, such as UART 116.

[0017] In one example, UART 116 may be a peripheral device of the microcontroller of system 100. Such a peripheral device may perform tasks on behalf of processor 102 and system 100. The task may be initiated by a command, user input, software, or other operation of processor 102. Once initiated, such a task may be performed by the peripheral device independently of processor 102. Therefore, processor 102 may offload tasks to such peripheral devices. When the task is completed, or according to other suitable criteria in which processor 102 or the software executing thereon takes further action, the peripheral device may, for example, generate an interrupt to processor 102. Other possible peripheral devices for system 100 may include, for example, counter 108, digital-to-analog converter 110, analog-to-digital converter 112, or I2C communication circuitry 114.

[0018] The UART 116 may include a control logic unit 140. The control logic unit 140 may be implemented by analog circuitry, digital circuitry, instructions for execution by a processor, or any suitable combination thereof. The control logic unit 140 may be configured to direct and control the operation of the UART 116 to introduce frame errors or stop bit errors, as described in this disclosure.

[0019] UART 116 may include receive registers such as RXREG 126. RXREG 126 may be configured to store one or more information bits (including the actual data to be received, frame information, or error information (such as parity bits)) received at UART 116, such as information bits received via RX port 118. Data received on RX port 118 may typically be received from another instance of the UART, or, if configured for loopback, from UART 116. Data in RXREG 126 may be read and used by any suitable part of system 100, such as control logic unit 140.

[0020] UART 116 may include transmit registers, such as TXREG 128. TXREG 128 may be configured to store one or more information bits to be transmitted by UART 116 via, for example, TX port 130, including the actual data to be transmitted, frame information, or error information (such as parity bits). Data to be stored in TXREG 128 and transmitted via TX port 130 may be generated by any suitable part of system 100 (such as by control logic unit 140, software executing on processor 102, or another peripheral device of system 100).

[0021] The UART 116 may include transmission circuitry 152 and error and event detection circuitry 150. Circuitry 150 and 152 may be implemented using instructions for execution by a processor, analog circuitry, digital circuitry, control logic units, digital logic circuitry programmed via a hardware description language, an ASIC, an FPGA, a PLD, or any suitable combination thereof, whether in a single device or distributed across several devices. Error and event detection circuitry 150 may be configured to detect errors in received frames. Transmission circuitry 152 may be configured to cause the transmission of the contents of TXREG 128 and may be configured to add start and stop bits during transmission.

[0022] In one example, UART 116 can be configured to introduce frame errors using resources available within UART 116. In another example, UART 116 can be configured to introduce frame errors without using additional instances of UART.

[0023] UART 116 may include or be configured to use any suitable loopback or feedback mechanism to bind the outputs of TX port 130 and RX port 118 together, or to bind the outputs of TXREG 128 and RXREG 126 together.

[0024] In one example, UART 116 may include or have access to one or more virtual remapped pins. For simplicity, this document describes a single virtual remapped pin; it should be understood that more than one virtual remapped pin may be provided. Such virtual remapped pins may be configured to provide connectivity between or within a given peripheral device of system 100, such as UART 116. Virtual remapped pins may be implemented, for example, by an interchangeable structure within UART 116 or between UART 116 and other elements of system 100. In one example, virtual remapped pins may be implemented by a software-controlled interconnect matrix. The matrix may be implemented entirely within UART 116 or within UART 116 and a larger system (such as a microcontroller) in which UART 116 resides. Virtual remapped pins may be programmable via control logic unit 140. Control logic unit 140 may then make programmable calls to other parts of the system to configure the virtual remapped pins. This virtual remapped pin can be programmable to electrically bind (i.e., connect) two ports of the UART 116 or System 100. The virtual remapped pin can be used to bind, for example, the TX port and RX port or register together, or to bind the RX port or register to a known signal. For example, the UART 116 may include a remapped pin RP 120. RP 120 is shown external to the UART 116 as if these were physical pins for demonstration purposes. Furthermore, Figure 1 Two representations of the remapped pin RP 120 are shown for readability. A single instance of the remapped pin RP 120 is shown as a separate instance to illustrate the equivalent routing of signals to and from the remapped pin, although these are single instances. Control logic 130 can be configured to route two or more signals to the same remapped pin. This can have the effect of connecting two or more signals. This can occur within UART 116 or System 100. Signal routing via the remapped pin RP 120 can be programmatically performed by control logic 130 by assigning and reassigning the remapped pin RP 120. However, for illustrative purposes, the ability of control logic 130 to route signals via the remapped pin RP 120 can be shown as switch 124.

[0025] In another example, UART 116 can utilize an external loopback connection using ports 130 and 118. The output of TX port 130 can be connected to RX port 118. This can be selectively enabled or disabled using any suitable circuitry, such as via switch 138. Switch 138 can be controlled, for example, by control logic unit 140.

[0026] Data frames to be sent to TX port 130 or RP 120 can be stored in TXREG 128. This data frame can be configured according to any suitable transmission scheme for the UART design. It can include any suitable basic data, parity information, start conditions, or stop conditions. For example, a stop bit within the frame or any other suitable stop signal or information can be used. In another example, the stop bit can be in the tenth position within the frame, after the start bit and eight data bits. In another example, the stop bit can be expected to be a logic high value.

[0027] The examples shown in this disclosure can follow this scheme. In other examples, the stop bit may be expected to be a logic low value or may appear at other expected locations within a given frame.

[0028] Frame information (such as stop conditions) can be set or checked by any suitable part of UART 116. For example, UART 116 may include frame error checking circuitry 136. Frame error checking circuitry 136 can be implemented by instructions for execution by a processor, analog circuitry, digital circuitry, control logic units, digital logic circuitry programmed via a hardware description language, ASIC, FPGA, PLD, or any suitable combination thereof, whether in a single device or distributed across several devices. Furthermore, frame error checking circuitry 136 can be configured to check the contents of RXREG 126 and assess whether a frame error has occurred. As discussed above, such frame errors can occur when stop conditions (such as the correct value of the stop bit) are not observed. Frame error checking circuitry 136 can be implemented in part by event and error detection circuitry 150, and vice versa.

[0029] The frame error checking circuit 136 can be configured to evaluate the contents of RXREG 126 and determine whether a frame error has occurred when it is received. A frame error is determined when the contents of RXREG 126 do not include a stop bit or stop condition at the expected position. If a frame error has occurred, UART 116 can take any appropriate corrective action. If no frame error has occurred, UART 116 can continue processing the information in RXREG 126.

[0030] Control logic unit 140 can be configured to switch UART 116 between test mode and normal mode. Test mode can be used based on any suitable criteria. For example, test mode can be performed when system 100 starts up, periodically, as part of a larger diagnostic test, or as required by the user or system software.

[0031] During normal operation, where the frame error checking capability of UART 116 is not tested, the output of TXRED 128 may not be routed back to RXREG 126 via RP 120, TX port 130, or RX port 118. Switch 138 can, for example, disconnect the loopback path between TX port 130 and RX port 118. Control logic unit 140 can be configured to route (not shown) the content of TXREG 128 to TX port 130. Data can be sent from TX port 130 to other entities (not shown) connected to TX port 130. Furthermore, control logic unit 140 can be configured to route content from RX port 118 (not shown) to RXREG 126. Frame error checking circuitry 136 can check for possible frame errors in the data received in RXREG 126. If no frame error is detected, the received data can be processed. If a frame error is detected, any appropriate corrective action can be taken. These may include, for example, requesting the sender of the information (such as another UART) to resend the data, or notifying the user or a software entity of system 100.

[0032] During test mode, where the frame error checking capability of the UART 116 under test is being tested, control logic unit 140 can connect the output of TXREG 128 to an input of UART 116. In one example, control logic unit 140 can connect the output of TXREG 128 to RP 120, which can be connected to an input of UART 116 for input to RXREG 126. In another example, control logic unit 140 can connect the output of TXREG 128 to TX port 130 via switch 138, and connect TX port 130 to RX port 118.

[0033] During test mode, control logic unit 140 can be configured to cause a frame error in a frame sent from TXREG 128 and routed to RXREG 126. In one example, control logic unit 140 can be configured to cause a frame error in a frame when a frame is sent from TXREG 128. The frame error can be caused by a manually generated incorrect stop condition or stop bit. In another example, control logic unit 140 can be configured to cause a frame error in a frame when a frame is received at RXREG 126. Control logic unit 140 can be configured to cause a frame error in a frame in any suitable manner. In various examples, control logic unit 140 can be configured to change a bit inversion register to cause a frame error in the transmitted frame. The bit inversion register can be used to cause a manually generated incorrect stop condition or stop bit. In various examples, control logic unit 140 can be configured to introduce an incorrect stop bit in a frame to cause a frame error. In various examples, control logic unit 140 can be configured to introduce an incorrect stop bit in a frame to cause a frame error by changing a bit inversion register.

[0034] Bit reversal can include changing the state of a bit to its opposite state, or evaluating a bit based on its opposite state. A bit reversal register defines whether the contents of a given register are to be transmitted or interpreted using bit reversal. Although called a register, a bit reversal register can be implemented in any suitable manner, such as by a single bit, and with any suitable control logic unit. In one example, UART 116 may include or be communicatively coupled to a bit reversal register for data transmission. Bit reversal registers can define out-of-phase transmission or interpretation for any suitable number and type of registers. For example, TXREG 126 may be transmitted or interpreted using bit reversal by the TXINV register or control signal 134.

[0035] In various examples, control logic unit 140 selectively sets the TX INV register or control signal 134 to induce a frame error. A frame error can be caused by an incorrect stop bit. Control logic unit 140 can be configured to selectively set the TX INV register or control signal 134 to induce an error in the stop bit of a given frame, thereby causing a frame error. In one example, control logic unit 140 can be configured to selectively change the value of the TX INV register or control signal 134 to induce a stop bit error. In various examples, control logic unit 140 can be configured to selectively change the value of the TX INV register or control signal 134 during frame transmission to induce a stop bit error. In various examples, control logic unit 140 can be configured to selectively change the value of the TX INV register or control signal 134 during frame transmission and after the start bit or start condition to induce a stop bit error. In various examples, control logic unit 140 can be configured to selectively change the value of the TX INV register or control signal 134 during frame transmission to induce a stop bit error. In various examples, control logic unit 140 may be configured to selectively change the value of the TX INV register or control signal 134 during frame transmission, after the start bit or start condition, and before the end of the frame (covering when a stop bit is expected) to induce a stop bit error.

[0036] Upon receiving a frame, at the expected stop bit time, the frame error checking circuit 136 checks the contents of RXREG 126 to determine if the stop bit is logic one. A logic one is expected in normal, correct transmission. To induce a frame error due to a stop bit error, control logic unit 140 can be configured to selectively change or cause a change in the value of the TX INV register or control signal 134 during frame transmission in test mode. The changed value of the TX INV register or control signal 134 can be configured to artificially cause the stop bit to be logic zero. As discussed above, this can be performed in test mode to test the error checking capability of the UART 116. A logic zero at the expected stop bit time causes the frame error checking circuit 136 to generate a frame error.

[0037] In various implementations, a logic zero value can be expected at the time of the stop bit.

[0038] UART 116 can be implemented as part of, for example, functional safety diagnostic software, where the purpose of the diagnostics is to test the functionality of modules including hardware error detection mechanisms available in the device. This software diagnostics for UART is used by application software running in the automotive ECU to verify whether the frame error check mechanism in the UART is functioning correctly. Testing of UART 116 can be performed without relying on other UARTs.

[0039] Figure 2 This is a timing diagram illustrating the introduction of a stop condition error into a UART transmission, based on an example of this disclosure. For simplicity, propagation delays between different parts of the system are omitted, and the transmission is shown as instantaneous. Figure 2 The data shown may reflect the contents of TXREG 128, which may be generated by, for example, control logic unit 140 or any other suitable part of system 100. Figure 2 The traces shown are the contents of TXREG 128, the TXINV register or control signal 134, the output of TXREG 128 (denoted as TX) to RXREG 126 as an output from UART 116 or within UART 116 (which may include transmissions via RP 120 or TX 130), the input from TXREG 128 to RXREG 126 (denoted as RX) as an input from UART 116 or within UART 116 (which may include transmissions via RP 120 or TX 130), and the contents of RXREG 126.

[0040] The Y-axis can be defined by any suitable time increment. For example, microseconds... Figure 2 As shown in the image.

[0041] exist Figure 2 In the example, a data frame including start condition, data bit 00011100, parity bit 1, and stop bit 1 can be sent. This frame can be loaded into a TXREG 128.

[0042] At 2 microseconds, frame transmission can begin from TXREG 128. The TX INV register or control signal 134 can be cleared or otherwise set so that bit inversion is not used and the start condition is affected. Start conditions (such as the start bit) can be transmitted. The expected and received values ​​at RXREG 126 can be the logic low level of the start bit at 2 microseconds.

[0043] At 4 microseconds, frame data transmission can begin. Depending on the transmission protocol and frame data length definition, frame data can be transmitted for any suitable time duration. For example, eight bits of data can be transmitted. For frame error testing purposes, this can be ignored. Figure 2 The example shown contains data values ​​within that time frame, but these values ​​can be manipulated for other tests, such as parity tests.

[0044] The value of the bit inversion register can be changed at any point during frame data transmission, after the transmission of the start bit and before the transmission of the stop bit.

[0045] exist Figure 2In this process, the TX INV register or control signal 134 can be changed between 2 microseconds and 4 microseconds, causing bit inversion to be applied to the data sent from TXREG 128. The TX INV register or control signal 134 can be reset between 22 microseconds and 24 microseconds.

[0046] As a result, at 22 microseconds, the data value received at RXREG 126 may be a logic low level instead of a logic high level. This could be a stop bit error and potentially cause a frame error. The frame error check circuit 136 observes this situation and may generate a frame error. The control logic unit 140 can evaluate whether the frame error check circuit 136 correctly generates a frame error in response to a man-made stop bit error, and if not, take any appropriate corrective action.

[0047] After a stop bit error occurs, the value of the bit inversion register can be toggled again so that its value is the same as the value at 3 microseconds. Therefore, the UART 116 may not interpret consecutive logic low levels on the received value of TXREG 128 as an interrupt signal.

[0048] Figure 3 This is an illustration of an exemplary method 300 for introducing and detecting frame errors in a UART (i.e., in a single UART), according to an example of this disclosure.

[0049] Method 300 can be executed by any suitable mechanism, such as Figures 1 to 3 The system, and particularly the control logic unit 140 and frame error checking circuit 136. Method 300 may include... Figure 3 The steps may be more or fewer. Furthermore, the steps of method 300 may be repeated, omitted, skipped, executed in a different order, executed in parallel, or executed recursively.

[0050] At position 305, the UART can be initialized.

[0051] At point 310, it can be determined whether the UART is operated in normal mode or test mode. The decision to enter test mode can be made by the UART user on demand, periodically, at startup, or on any other suitable basis. If the UART is operated in normal mode, method 300 can proceed to 315. Otherwise, if the UART is operated in test mode, method 300 can proceed to 330.

[0052] At position 315, data can be transferred from one UART to another, or data can be received from another UART at a UART. Data to be transferred can be stored in TXREG. Received data can be stored in RXREG. Received data can be examined to locate the expected stop bit.

[0053] At point 320, it can be determined whether a stop bit error exists. If not, method 300 can return to 310. If yes, method 30 can proceed to 325.

[0054] At 325, any appropriate corrective action can be taken for a stop bit error, such as generating an error signal, generating an alarm, or requesting a retransmission of the frame by the transmitting UART. Method 300 can return to 310.

[0055] At 330, the contents of TXREG can be sent to RXREG. The contents can be sent via a remapped pin, which can be mapped between TXREG and RXREG so that the output of TXREG will propagate to RXREG, or via a set switch 138. A countdown can begin until the appropriate time is reached for a set control signal or an invert register (such as TXINV 134). A control signal can be set and sent before the stop bit of TXREG is sent. The control signal inverts the contents sent between TXREG and RXREG, which may include the stop bit. An inverted stop bit value can cause a stop bit error, and more specifically, a frame error.

[0056] At 335, it can be determined whether to set and send a control signal or invert the register. If so, method 300 can proceed to 340. Otherwise, method 300 can repeat 335 for one or more additional clock cycles.

[0057] At position 340, the system can wait until the stop bit propagates to RXREG.

[0058] At position 345, it can be determined whether the expected stop bit has been received. If so, method 300 can proceed to position 355. Otherwise, method 300 can proceed to position 350.

[0059] At point 350, it can be determined that the frame error checking circuitry executing 345 is malfunctioning. Any appropriate corrective action can be performed, such as issuing an alarm to the user of the UART. Method 300 can then return to 310.

[0060] At point 355, it can be confirmed that the frame error checking circuitry executing 350 is functioning correctly. Method 300 can then return to 310.

[0061] Embodiments of this disclosure may include an apparatus. The apparatus may include a transmit register containing information to be transmitted by a UART. The apparatus may include a receive register containing information received by the UART. The apparatus may include a bit-inverting register or control signal configured to invert transmitted or received information. The apparatus may include frame error checking circuitry configured to evaluate the contents of the receive register for frame errors. The apparatus may include control logic configured to route the contents of the transmit register to the receive register. The control logic may be implemented by instructions for execution by a processor, analog circuitry, digital circuitry, control logic, digital logic circuitry programmed via a hardware description language, an ASIC, an FPGA, a PLD, or any suitable combination thereof, whether in a single device or distributed across several devices. The control logic may be configured to modify the bit-inverting register or issue a bit-inverting signal such that the modified content is provided to the receive register. The modified content may be configured to cause a frame error. The control logic may be configured to determine whether the frame error checking circuitry has detected a frame error.

[0062] In combination with any of the above embodiments, the control logic unit can be configured to determine the presence of a frame error from the detection of an erroneous stop bit. The erroneous stop bit can be introduced by a bit inversion register or a bit inversion signal. The bit inversion register or bit inversion signal can be processed by the transmission circuitry. Frame errors can be detected by error and event handling circuitry or frame error checking circuitry. These circuits can be implemented by instructions for execution by a processor, analog circuitry, digital circuitry, control logic unit, digital logic circuitry programmed via a hardware description language, ASIC, FPGA, PLD, or any suitable combination thereof, whether in a single device or distributed across several devices.

[0063] In combination with any of the above embodiments, the bit inversion register or bit inversion signal can be an inverted bit or a signal used to invert the transmission of the contents of the transmit register.

[0064] In combination with any of the above implementation schemes, the bit inversion register or bit inversion signal can be an inverted bit used to invert the reception of the contents of the receive register.

[0065] In combination with any of the above implementation schemes, the control logic unit can be used to modify the bit inversion register or issue a bit inversion signal after receiving the start bit of a frame at the receive register.

[0066] In combination with any of the above embodiments, the control logic unit can be used to modify the bit inversion register or issue a bit inversion signal before the stop bit of the expected frame at the receive register.

[0067] In combination with any of the above embodiments, the control logic unit can be used to modify the bit inversion register or issue a bit inversion signal to cause a stop bit error, which causes a frame error.

[0068] In combination with any of the above embodiments, the control logic unit may be used to modify the bit inversion register or issue a bit inversion signal to cause a stop bit error by inverting the expected value at the receive register at the time when the expected stop bit is expected.

[0069] Although examples have been described above, this disclosure may have other variations and examples without departing from the substance and scope of these examples.

Claims

1. An apparatus comprising: Transmit register, which includes information to be transmitted by a Universal Asynchronous Receiver / Transmitter (UART); A receive register, the receive register including information received by the UART; A frame error checking circuit, wherein the frame error checking circuit evaluates the contents of the receive register in response to frame errors; and Control logic component, the control logic component: The contents of the transmit register are routed to the receive register; Modifying the bit-inverting register or issuing a bit-inverting signal to provide the modified content to the receive register, the modification causing a frame error, the bit-inverting register or bit-inverting signal causing the transmitted or received information to be inverted; and Determine whether the frame error verification circuit has detected the frame error.

2. The apparatus of claim 1, wherein the bit-inverting register is a bit-inverting bit for reversing the transmission of the contents of the transmit register.

3. The apparatus according to any one of claims 1 to 2, wherein the bit-inverting register is a bit-inverting bit for inverting the reception of the contents of the receive register.

4. The apparatus according to any one of claims 1 to 3, wherein the control logic component modifies the bit inversion register after receiving the start bit of the frame at the receive register.

5. The apparatus according to any one of claims 1 to 4, wherein the control logic component modifies the bit inversion register before anticipating the stop bit of the frame at the receive register.

6. The apparatus according to any one of claims 1 to 5, wherein the control logic component modifies the bit inversion register to cause a stop bit error, the stop bit error causing the frame error.

7. The apparatus of claim 6, wherein the control logic component modifies the bit inversion register to cause the stop bit error by inverting the expected value at the receive register at the time when the stop bit is expected.

8. A method comprising, in a universal asynchronous receiver / transmitter (UART), said UART: The contents of the transmit register are routed to the receive register, the transmit register containing information to be transmitted by the UART, and the receive register containing information to be received by the UART; Modify the bit inversion register or issue a bit inversion signal to provide the modified content to the receive register, the modified content causing a frame error, the bit inversion register or bit inversion signal causing the transmitted or received information to be inverted; And a frame error checking circuit, which evaluates the contents of the receive register in response to frame errors; as well as Determine whether the frame error verification circuit has detected the frame error.

9. The method of claim 8, wherein the bit-inverting register or bit-inverting signal is a bit-inverting bit for inverting the transmission of the contents of the transmit register, and such that modifying the contents includes inverting the contents of the transmit register.

10. The method according to any one of claims 8 to 9, wherein the bit-inverting register or bit-inverting signal is a bit-inverting bit for inverting the reception of the contents of the receive register, and such that modifying the contents includes inverting the contents of the receive register.

11. The method according to any one of claims 8 to 10, comprising modifying the bit inversion register or issuing the bit inversion signal after receiving the start bit of the frame at the receive register.

12. The method according to any one of claims 8 to 11, comprising modifying the bit inversion register or issuing the bit inversion signal before anticipating the stop bit of the frame at the receive register.

13. The method according to any one of claims 8 to 12, comprising modifying the bit inversion register or issuing the bit inversion signal to cause a stop bit error, the stop bit error causing the frame error.

14. The method of claim 13, further comprising modifying the bit inversion register or issuing the bit inversion signal to cause the stop bit error by inverting the expected value at the receive register at the time when the stop bit is expected.

15. A microcontroller, comprising: Universal Asynchronous Receiver / Transmitter (UART) A transmit register, the transmit register including information to be transmitted by the UART; A receive register, the receive register including information received by the UART; A frame error checking circuit, wherein the frame error checking circuit evaluates the contents of the receive register in response to frame errors; and Control logic component, the control logic component: The contents of the transmit register are routed to the receive register; Modifying the bit-inverting register or issuing a bit-inverting signal to provide the modified content to the receive register, the modification causing a frame error, the bit-inverting register or bit-inverting signal causing the transmitted or received information to be inverted; and Determine whether the frame error verification circuit has detected the frame error.

16. The microcontroller of claim 15, wherein the bit-inverting register or bit-inverting signal is a bit-inverting bit for reversing the transmission of the contents of the transmit register.

17. The microcontroller according to any one of claims 15 to 16, wherein the bit-inverting register or bit-inverting signal is a bit-inverting bit for inverting the reception of the contents of the receive register.

18. The microcontroller according to any one of claims 15 to 17, wherein the control logic component modifies the bit inversion register or issues the bit inversion signal after receiving the start bit of the frame at the receive register.

19. The microcontroller according to any one of claims 15 to 18, wherein the control logic component modifies the bit inversion register or issues the bit inversion signal before the stop bit of the frame is anticipated at the receive register.

20. The microcontroller according to any one of claims 15 to 19, wherein the control logic unit modifies the bit inversion register or issues the bit inversion signal to cause a stop bit error, the stop bit error causing the frame error.

21. The microcontroller of claim 20, wherein the control logic unit modifies the bit inversion register or issues the bit inversion signal to cause the stop bit error by inverting the expected value at the receive register at the time when the stop bit is expected.

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