Display drive circuit and display device

Abstract

Provided are a display driving circuit and a display device, which belong to the technical field of display. In the display driving circuit, a push-pull circuit is coupled with an internal circuit, a first external power supply terminal, a second external power supply terminal and a target node, and can control the on-off of the first external power supply terminal and the second external power supply terminal and the target node in response to a target control signal transmitted by the internal circuit. A switching circuit is coupled with the target node and an I / O interface of the display driving circuit, and can transmit the potential of the target node to the I / O interface of the display driving circuit, i.e. the first power signal transmitted by the first external power supply terminal to the target node or the second power signal transmitted by the second external power supply terminal to the target node is further output to the I / O interface. In this way, by flexibly setting the target control signal, the first power signal and the second power signal, signals of multiple different potentials can be transmitted to the I / O interface, and the compatibility of the I / O interface is improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display driving circuit and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display devices are widely used in the display field due to their advantages such as self-illumination, small thickness, light weight and high luminous efficiency.

[0003] In related technologies, OLED display devices generally include: an application processor (AP), a flash integrated circuit (Flash IC), and a display driver integrated circuit (DDIC). Both the AP and the Flash IC are coupled to the input / output (I / O) interfaces of the DDIC for communication. Furthermore, the operating voltage of the AP is typically approximately 1.2V, and the operating voltage of the Flash IC is typically approximately 1.8V.

[0004] However, the operating voltage of each I / O interface in the current DDIC is fixed. For example, the operating voltage of the I / O interface in the DDIC is 1.2V or 1.8V, which results in poor compatibility of the I / O interface. Summary of the Invention

[0005] This disclosure provides a display driver circuit and display device, which can solve the problem of poor compatibility of DDIC I / O interfaces in related technologies. The technical solution is as follows:

[0006] On the one hand, a display driving circuit is provided, the display driving circuit including: an input / output I / O interface, internal circuitry, a push-pull circuit, and a switching circuit;

[0007] The internal circuit is coupled to the push-pull circuit, and the internal circuit is used to transmit target control signals to the push-pull circuit;

[0008] The push-pull circuit is also coupled to a first external power supply terminal, a second external power supply terminal, and a target node, respectively. The push-pull circuit is used to respond to the target control signal to control the connection and disconnection between the first external power supply terminal and the target node, and to control the connection and disconnection between the second external power supply terminal and the target node.

[0009] The switching circuit is coupled to the first control terminal, the I / O interface and the target node respectively. The switching circuit is used to transmit the potential of the target node to the I / O interface in response to the first control signal provided by the first control terminal.

[0010] Wherein, the potential of the first power signal provided by the first external power supply terminal is greater than the potential of the second power signal provided by the second external power supply terminal.

[0011] Optionally, the push-pull circuit includes: a first switch sub-circuit and a second switch sub-circuit;

[0012] The first switch sub-circuit is coupled to the internal circuit, the first external power supply terminal and the target node respectively. The first switch sub-circuit is used to control the on / off state of the first external power supply terminal and the target node in response to the target control signal provided by the internal circuit.

[0013] The second switch sub-circuit is coupled to the internal circuit, the second external power supply terminal and the target node respectively. The second switch sub-circuit is used to control the connection and disconnection between the second external power supply terminal and the target node in response to the target control signal provided by the internal circuit.

[0014] Optionally, the first switching sub-circuit includes a first transistor; the second switching sub-circuit includes a second transistor, and the first transistor and the second transistor are of different types.

[0015] The gate of the first transistor is coupled to the internal circuit, the first terminal of the first transistor is coupled to the first external power supply terminal, and the second terminal of the first transistor is coupled to the target node.

[0016] The gate of the second transistor is coupled to the internal circuit, the first terminal of the second transistor is coupled to the second external power supply terminal, and the second terminal of the second transistor is coupled to the target node.

[0017] Optionally, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0018] Optionally, the switching circuit includes a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are of different types;

[0019] The gates of the third transistor and the fourth transistor are both coupled to the first control terminal, the first terminals of the third transistor and the fourth transistor are both coupled to the target node, and the second terminals of the third transistor and the fourth transistor are both coupled to the I / O interface.

[0020] Optionally, the third transistor is a P-type transistor, and the fourth transistor is an N-type transistor.

[0021] Optionally, the display driving circuit further includes: an electrostatic discharge circuit;

[0022] The electrostatic discharge circuit is coupled to the first external power supply terminal, the second external power supply terminal, and the I / O interface, respectively. The electrostatic discharge circuit is used to release the static electricity generated at the I / O interface based on the first power signal and the second power signal.

[0023] Optionally, the electrostatic discharge circuit includes a fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor are of different types;

[0024] The gate and first terminal of the fifth transistor are both coupled to the first external power supply terminal, and the second terminal of the fifth transistor is coupled to the I / O interface;

[0025] The gate and first terminal of the sixth transistor are both coupled to the second external power supply terminal, and the second terminal of the sixth transistor is coupled to the I / O interface.

[0026] Optionally, the fifth transistor is a P-type transistor, and the sixth transistor is an N-type transistor.

[0027] Optionally, the display driving circuit further includes a current-limiting resistor connected in series between the switching circuit and the I / O interface, the current-limiting resistor being used to limit the potential transmitted to the I / O interface for current protection.

[0028] Optionally, the display driving circuit further includes: a Schottky trigger and a protection circuit;

[0029] The Schottky trigger is coupled to the internal circuit and the I / O interface respectively. The Schottky trigger is used to receive the analog power signal provided by the I / O interface, convert the analog power signal into a digital power signal, and then transmit it to the internal circuit.

[0030] The protection circuit is coupled to the I / O interface, the first external power supply terminal, the second external power supply terminal, and the second control terminal respectively. The protection circuit is used to stabilize the potential at the I / O interface in response to the second control signal provided by the second control terminal, based on the first power signal and the second power signal.

[0031] The internal circuitry is also coupled to the I / O interface and is also used to receive analog power signals provided by the I / O interface.

[0032] Optionally, the protection circuit includes: a pull-up resistor, a pull-down resistor, a first switch, and a second switch;

[0033] The control terminal of the first switch is coupled to the second control terminal, the first terminal of the first switch is coupled to the first external power supply terminal, and the second terminal of the first switch is coupled to the first terminal of the pull-up resistor.

[0034] The control terminal of the second switch is coupled to the second control terminal, the first terminal of the second switch is coupled to the second external power supply terminal, and the second terminal of the second switch is coupled to the first terminal of the pull-down resistor.

[0035] The second end of both the pull-up resistor and the pull-down resistor are coupled to the I / O interface.

[0036] Optionally, the potential of the first power supply signal is 1.2 volts or 1.8V, and the potential of the second power supply signal is 0.

[0037] On the other hand, a display device is provided, the display device comprising: an application processor, a storage circuit, a power management integrated circuit, and a display driving circuit as described above;

[0038] The application processor, the storage circuit, and the power management integrated circuit are all coupled to the I / O interface of the display driver circuit, and the I / O interfaces coupled to the application processor, the storage circuit, and the power management integrated circuit are different.

[0039] The application processor communicates bidirectionally with the display driver circuit, the storage circuit communicates bidirectionally with the display driver circuit, and the display driver circuit provides power supply signals to the power management integrated circuit.

[0040] Optionally, the display device includes an organic light-emitting diode (OLED) display device.

[0041] In summary, the beneficial effects of the technical solutions provided by the embodiments of this disclosure can at least include:

[0042] A display driving circuit and a display device are provided. The display driving circuit includes an internal circuit, a push-pull circuit, and a switching circuit. The push-pull circuit is coupled to the internal circuit, a first external power supply terminal, a second external power supply terminal, and a target node, and is capable of controlling the on / off state of the first and second external power supply terminals with respect to the target node in response to a target control signal transmitted by the internal circuit. The switching circuit is coupled to the target node and the I / O interface of the display driving circuit, and is capable of transmitting the potential of the target node to the I / O interface of the display driving circuit, that is, further outputting a first power signal transmitted from the first external power supply terminal to the target node or a second power signal transmitted from the second external power supply terminal to the target node to the I / O interface. Thus, by flexibly setting the target control signal, the first power signal, and the second power signal, multiple signals with different potentials can be transmitted to the I / O interface, improving the compatibility of the I / O interface. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the structure of a display driving circuit provided in an embodiment of this disclosure;

[0045] Figure 2 This is a schematic diagram of another display driving circuit provided in an embodiment of this disclosure;

[0046] Figure 3 This is a schematic diagram of another display driving circuit provided in an embodiment of the present disclosure;

[0047] Figure 4 This is a schematic diagram of another display driving circuit provided in an embodiment of the present disclosure;

[0048] Figure 5 This is a schematic diagram of another display driving circuit provided in an embodiment of the present disclosure;

[0049] Figure 6 This is a schematic diagram illustrating the working principle of a push-pull circuit provided in an embodiment of this disclosure;

[0050] Figure 7 This is a schematic diagram illustrating the working principle of a switching circuit provided in an embodiment of this disclosure;

[0051] Figure 8 This is a schematic diagram of the structure of an electrostatic discharge circuit provided in an embodiment of this disclosure;

[0052] Figure 9 This is a schematic diagram of another display driving circuit provided in an embodiment of the present disclosure;

[0053] Figure 10 This is a schematic diagram of another display driving circuit provided in an embodiment of the present disclosure;

[0054] Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0056] Display devices generally include: an application processor (AP), a flash memory integrated circuit (Flash IC), a display driver integrated circuit (DDIC), and a power management integrated circuit (Power Management IC). The DDIC's logic circuits typically operate at a supply voltage between 1.65V and 1.95V, with a typical value of 1.8V. Furthermore, with the rapid advancement of manufacturing processes (FAB), the AP's process technology has progressed from 7 nanometers (nm) to 5nm. Consequently, the voltage of the communication signals between the AP and the DDIC has decreased from 1.8 volts (V) to 1.2V. For example, each I / O interface of the DDIC can be controlled by the 1.2V voltage provided by the AP. However, due to current cost and process considerations, Flash ICs and PMICs do not require a 5nm process. Therefore, the communication voltage between the Flash IC / PMIC and the DDIC generally remains at 1.8V. Furthermore, currently, the voltage output from the DDIC's I / O interface to other circuits is generally referenced to 1.8V, and the voltage input from other circuits to the DDIC is directly transmitted to the DDIC via the I / O interface. The overall circuit architecture of the DDIC is simple, but its communication stability is relatively poor.

[0057] Based on this, the present disclosure provides a new DDIC, whose various I / O interfaces are compatible with dual voltage transmission of 1.2V and 1.8V, as well as low voltage transmission of 0V. It can better adapt to the improved capabilities of FAB processes and meet the communication requirements of application processors (APs) manufactured using 5nm process technology, with high output multiplexing efficiency.

[0058] Figure 1 This is a schematic diagram of a display driving circuit provided in an embodiment of this disclosure. For example... Figure 1As shown, the display driver circuit includes: an input / output I / O interface, an internal circuit 01, a push-pull circuit 02, and a switching circuit 03.

[0059] The internal circuit 01 is coupled to the push-pull circuit 02. The internal circuit 01 is used to transmit the target control signal to the push-pull circuit 02.

[0060] Optionally, the internal circuit 01 may include multiple components such as analog circuits, digital circuits, and instruction registers. In this embodiment, the circuit capable of providing the target control signal is referred to as the internal circuit 01, and the target control signal is referred to as the internal signal provided by the display driving circuit 01. The internal circuit 01 can transmit various target control signals of different potentials to the push-pull circuit 02 to flexibly control the operation of the push-pull circuit 02. Based on this, the target control signal can also be referred to as an enable signal.

[0061] For example, the instruction register in internal circuit 01 can pre-store register instructions, which can carry the target control signal to be generated. When internal circuit 01 receives the register instruction, it can generate the target control signal at the corresponding potential based on the content of the instruction and transmit the target control signal to push-pull circuit 02. For example, internal circuit 01 can generate a target control signal at a first potential or a target control signal at a second potential.

[0062] The push-pull circuit 02 is also coupled to the first external power supply terminal VDDI, the second external power supply terminal VSSI, and the target node N0, respectively. The push-pull circuit 02 is used to control the on / off state of the first external power supply terminal VDDI and the target node N0 in response to the target control signal, and to control the on / off state of the second external power supply terminal VSSI and the target node N0.

[0063] For example, push-pull circuit 02 can control the first external power supply terminal VDDI to conduct with the target node N0 and control the second external power supply terminal VSSI to discouple from the target node N0 when the target control signal potential is a first potential. At this time, the first power signal provided by the first external power supply terminal VDDI can be transmitted to the target node N0, meaning the signal written to the target node N0 at this time can be the first power signal. Similarly, push-pull circuit 02 can control the first external power supply terminal VDDI to discouple from the target node N0 and control the second external power supply terminal VSSI to conduct with the target node N0 when the target control signal potential is a second potential. At this time, the second power signal provided by the second external power supply terminal VSSI can be transmitted to the target node N0, meaning the signal written to the target node N0 at this time can be the second power signal. Thus, the purpose of writing either a first power signal or a second power signal to the target node N0 is achieved.

[0064] Switching circuit 03 is coupled to the first control terminal Con1, the I / O interface, and the target node N0. Switching circuit 03 is used to transmit the potential of target node N0 to the I / O interface in response to the first control signal provided by the first control terminal Con1.

[0065] For example, the switching circuit 03 can control the target node N0 to be connected to the I / O interface when the potential of the first control signal provided by the first control terminal Con1 is either a first potential or a second potential, so that the signal written to the target node N0 can be further transmitted to the I / O interface. That is, the first power signal or the second power signal is output to the I / O interface. This I / O interface can also be coupled to other devices (e.g., application processor AP), and the power signal transmitted to the I / O interface can be used by the display driver circuit to communicate with the other device. Based on this, Figure 1 The circuits shown can be divided into the output section of the display driver circuit. Furthermore, Figure 1 The first potential of the first control signal is marked as AVDD_int, and the second potential of the first control signal is marked as GND. The following embodiments are similar and will not be described again.

[0066] By configuring this switch circuit 03, direct coupling between the I / O interface and the push-pull circuit 02 can be avoided. This prevents large potential signals received at the I / O interface from impacting the push-pull circuit 02, thus protecting it. Simultaneously, it also prevents damage to the I / O interface caused by a malfunction in the push-pull circuit 02 outputting a large potential signal, thereby protecting the I / O interface.

[0067] Optionally, in this embodiment, the first potential can be a high potential, and the second potential can be a low potential. Furthermore, the potential of the first power signal provided by the first external power supply terminal VDDI can be greater than the potential of the second power signal provided by the second external power supply terminal VSSI. For example, the potential of the first power signal can be greater than 0, and the potential of the second power signal can be 0. In this way, the purpose of outputting different potentials, such as 0 or greater than 0, to the I / O interface is achieved.

[0068] It should be noted that both the first external power supply terminal VDDI and the second external power supply terminal VSSI can be external power supply terminals independent of the display driver circuit. That is, the first and second power signals can be external signals, not internal signals of the display driver circuit. In other words, the power signal output to the I / O interface can be provided by an external power supply, and the signal generated by the internal circuit 01 of the display driver circuit serves only as an enable signal. Therefore, different potential selections for the I / O interface can be achieved by flexibly setting the potentials of the first and second power signals. For example, the potential of the first power signal can be 1.2V or 1.8V, and the potential of the second power signal can be 0V.

[0069] In summary, this disclosure provides a display driving circuit comprising an internal circuit, a push-pull circuit, and a switching circuit. The push-pull circuit is coupled to the internal circuit, a first external power supply terminal, a second external power supply terminal, and a target node, and is capable of controlling the connection and disconnection of the first and second external power supply terminals with respect to the target node in response to a target control signal transmitted by the internal circuit. The switching circuit is coupled to both the target node and the I / O interface of the display driving circuit, and is capable of transmitting the potential of the target node to the I / O interface of the display driving circuit, specifically, transmitting a first power signal from the first external power supply terminal to the target node or a second power signal from the second external power supply terminal to the target node, and further outputting it to the I / O interface. Thus, by flexibly setting the target control signal, the first power signal, and the second power signal, multiple signals with different potentials can be transmitted to the I / O interface, improving the compatibility of the I / O interface.

[0070] Figure 2 This is a schematic diagram of another display driving circuit provided in an embodiment of this disclosure. For example... Figure 2 As shown, the push-pull circuit 02 included in the display driving circuit may include: a first switch sub-circuit 021 and a second switch sub-circuit 022.

[0071] The first switch sub-circuit 021 can be coupled to the internal circuit 01, the first external power supply terminal VDDI, and the target node N0, respectively. The first switch sub-circuit 021 can be used to control the on / off state of the first external power supply terminal VDDI and the target node N0 in response to the target control signal provided by the internal circuit 01.

[0072] For example, the first switch sub-circuit 021 can control the first external power supply terminal VDDI to conduct with the target node N0 when the target control signal is at a first potential, so that the first power signal is transmitted to the target node N0 and further output to the I / O interface via the switch circuit 03. Also, the first switch sub-circuit 021 can control the first external power supply terminal VDDI to disconnect from the target node N0 when the target control signal is at a second potential.

[0073] The second switch sub-circuit 022 can be coupled to the internal circuit 01, the second external power supply terminal VSSI, and the target node N0, respectively. The second switch sub-circuit 022 can be used to control the on / off state of the second external power supply terminal VSSI and the target node N0 in response to the target control signal provided by the internal circuit 01.

[0074] For example, the second switch sub-circuit 022 can control the second external power supply terminal VSSI to conduct with the target node N0 when the target control signal is at the second potential, so that the second power signal is transmitted to the target node N0 and further output to the I / O interface via the switch circuit 03. Also, the second switch sub-circuit 022 can control the first external power supply terminal VDDI to disconnect from the target node N0 when the target control signal is at the first potential.

[0075] Figure 3 This is a schematic diagram of another display driving circuit provided in an embodiment of this disclosure. For example... Figure 3 As shown, the display driving circuit described in this embodiment may further include an electrostatic discharge (ESD) circuit 04.

[0076] The electrostatic discharge circuit 04 can be coupled to the first external power supply terminal VDDI, the second external power supply terminal VSSI, and the I / O interface, respectively. The electrostatic discharge circuit 04 can be used to release static electricity generated at the I / O interface based on the first and second power signals, thereby protecting the I / O interface.

[0077] Figure 4 This is a schematic diagram of another display driving circuit provided in an embodiment of this disclosure. For example... Figure 4As shown, the display driving circuit may further include a current-limiting resistor R0 connected in series between the switching circuit 03 and the I / O interface. This current-limiting resistor R0 can be used to limit the current transmitted to the I / O interface.

[0078] Figure 5 This is a schematic diagram of another display driving circuit provided in an embodiment of this disclosure. For example... Figure 5 As shown, in the push-pull circuit 02 provided in this embodiment, the first switching sub-circuit 021 may include a first transistor T1. The second switching sub-circuit 022 may include a second transistor T2.

[0079] The gate T1 of the first transistor can be coupled to the internal circuit O1, the first terminal of the first transistor T1 can be coupled to the first external power supply terminal VDDI, and the second terminal of the first transistor T1 can be coupled to the target node N0.

[0080] The gate of the second transistor T2 can be coupled to the internal circuit 01, the first terminal of the second transistor T2 can be coupled to the second external power supply terminal VSSI, and the second terminal of the second transistor T2 can be coupled to the target node N0.

[0081] Furthermore, the first transistor T1 and the second transistor T2 are of different types. For example, refer to... Figure 5 and Figure 6 As shown in the schematic diagram of the push-pull circuit 02, in this embodiment, the first transistor T1 coupled to the first external power supply terminal VDDI can be an N-type transistor, and the second transistor T2 coupled to the second external power supply terminal VSSI can be a P-type transistor. Based on this, combined with... Figure 6 It can be seen that the push-pull circuit 02 includes a first working mode and a second working mode.

[0082] In the first operating mode, the internal circuit 01 can transmit a high-potential target control signal to the push-pull circuit 02. At this time, the first transistor T1 is turned on, and the second transistor T2 is turned off. Correspondingly, the first external power supply terminal VDDI is coupled to the target node N0 through the turned-on first transistor T1. Furthermore, the second external power supply terminal VSSI is disconnected from the target node N0. Figure 6 (Represented by dashed lines in the middle). Furthermore, the first power signal provided by the first external power supply terminal VDDI can be transmitted to the target node N0 via the first transistor T1, and then further output to the I / O interface via the switching circuit 03.

[0083] In the second operating mode, the internal circuit 01 can transmit the potential of the target control signal at a low potential to the push-pull circuit 02. At this time, the first transistor T1 is turned off, and the second transistor T2 is turned on. Correspondingly, the first external power supply terminal VDDI is disconnected from the target node N0. Figure 6 (Represented by dashed lines in the diagram). The second external power supply terminal VSSI is coupled to the target node N0 via the activated second transistor T2. Furthermore, the second power signal provided by the second external power supply terminal VSSI can be transmitted to the target node N0 via the second transistor T2, and then further output to the I / O interface via the switching circuit O3.

[0084] It should be noted that, Figure 6 The target node N0 and switching circuit 03 are not shown. Of course, in some embodiments, the first transistor T1 can also be a P-type transistor, and correspondingly, the second transistor T2 can be an N-type transistor. Based on this, when the target control signal potential is low, the first transistor T1 can be turned on, and the second transistor T2 can be turned off. The first power signal provided by the first external power supply terminal VDDI is output to the I / O interface via the turned-on first transistor T1 and switching circuit 03. And, when the target control signal potential is high, the first transistor T1 can be turned off, and the second transistor T2 can be turned on. The second power signal provided by the second external power supply terminal VSSI is output to the I / O interface via the turned-on second transistor T1 and switching circuit 03.

[0085] Continue to refer to Figure 5 As can be seen, the switching circuit 03 provided in this embodiment may include a third transistor T3 and a fourth transistor T4.

[0086] Specifically, the gates of the third transistor T3 and the fourth transistor T4 can both be coupled to the first control terminal Con1, meaning they can both receive the first control signal AVDD_int at the first potential and the second control signal GND at the second potential. The first terminals of both the third transistor T3 and the fourth transistor T4 can be coupled to the target node N0. The second terminals of both the third transistor T3 and the fourth transistor T4 can be coupled to the I / O interface.

[0087] Furthermore, the third transistor T3 and the fourth transistor T4 are of different types. For example, refer to... Figure 5 and Figure 7 As shown in the schematic diagram of the working principle of the switching circuit 03, in this embodiment, the third transistor T3 can be a P-type transistor, and the fourth transistor T4 can be an N-type transistor. Based on this, combined with... Figure 7 It can be seen that the switching circuit 03 includes a (1) working mode and a (2) working mode.

[0088] In the first operating mode (1), the potential of the first control signal provided by the first control terminal Con1 can be the first potential AVDD_int. At this time, the third transistor T3 is turned off. Figure 7 (Indicated by dashed lines), the fourth transistor T4 is turned on. Correspondingly, the target node N0 is connected to the I / O interface via the fourth transistor T4. Furthermore, the data written to the target node N0 is further output to the I / O interface via the fourth transistor T4. At this time, the signal written to the target node N0 is a first power supply signal with a potential of 1.2V / 1.8V. That is, combined with... Figure 6 In this embodiment of the disclosure, the potential of the first control signal and the potential of the target control signal transmitted by the internal circuit 01 can be simultaneously at the first potential, so that the first power supply signal can be reliably output to the I / O interface through the fourth transistor T4, and the low potential of the I / O interface is pulled up to 1.2V / 1.8V.

[0089] In the second operating mode, the potential of the second control signal provided by the first control terminal Con1 can be the second potential GND. At this time, the third transistor T3 is turned on, and the fourth transistor T4 is turned off. Figure 7 (Represented by dashed lines). Accordingly, the target node N0 is connected to the I / O interface via the third transistor T3. Furthermore, the data written to the target node N0 is further output to the I / O interface via the third transistor T3. At this time, the signal written to the target node N0 is a second power supply signal with a potential of 0V. That is, combined with... Figure 6 In this embodiment of the disclosure, the potential of the first control signal and the potential of the target control signal transmitted by the internal circuit 01 can be simultaneously at the second potential, so that the second power supply signal can be reliably output to the I / O interface through the third transistor T3, pulling the high potential of the I / O interface down to a low potential, such as 0V.

[0090] Based on the above explanation of the working principle of switch circuit 03, it can be seen that by setting up a parallel structure including N-type transistors and P-type transistors, the potential of the I / O interface can be reliably pulled low or high. Figure 6 When both push-pull circuit 02 and switch circuit 03 are in the first (1) working mode, it can be considered as the normal working mode of outputting to the I / O interface. When both push-pull circuit 02 and switch circuit 03 are in the second (2) working mode, it can be considered as the working mode of pulling the potential of the I / O interface low to form a low-level output, which is suitable for more scenarios.

[0091] Of course, in some embodiments, the third transistor T3 can also be an N-type transistor, and correspondingly, the fourth transistor T4 can be a P-type transistor. Based on this, when the potential of the first control signal is the first potential AVDD_int, the third transistor T3 can be turned on, and the fourth transistor T4 can be turned off, allowing the target node N0 to connect to the I / O interface through the third transistor T3. Furthermore, when the potential of the first control signal is the second potential GND, the third transistor T3 can be turned off, and the fourth transistor T4 can be turned on, allowing the target node N0 to connect to the I / O interface through the fourth transistor T4.

[0092] Continue to refer to Figure 5 It can be seen that the electrostatic discharge circuit 04 described in this embodiment may include: a fifth transistor T5 and a sixth transistor T6.

[0093] The gate and first terminal of the fifth transistor T5 can both be coupled to the first external power supply terminal VDDI, and the second terminal of the fifth transistor T5 can be coupled to the I / O interface.

[0094] The gate and first terminal of the sixth transistor T6 can both be coupled to the second external power supply terminal VSSI, and the second terminal of the sixth transistor T6 can be coupled to the I / O interface.

[0095] Based on this, the fifth transistor T5 can reliably release the static electricity generated at the I / O interface based on the first power signal provided by the first external power supply terminal VDDI. The sixth transistor T6 can reliably release the static electricity generated at the I / O interface based on the second power signal provided by the second external power supply terminal VSSI, thereby further protecting the I / O interface.

[0096] Furthermore, the fifth transistor T5 and the sixth transistor T6 can be of different types. For example, refer to... Figure 5 and Figure 8 As shown in the schematic diagram of an electrostatic discharge circuit, in this embodiment, the fifth transistor T5 can be a P-type transistor and the sixth transistor T6 can be an N-type transistor.

[0097] Currently, diodes are commonly used to discharge static electricity generated at I / O interfaces. However, due to the relatively large voltage drop of diodes (typically between 0.5V and 1.2V), the static discharge effect is poor. Transistors, on the other hand, typically have a voltage drop between 0.3V and 0.6V, which is much smaller. Therefore, this embodiment uses N-type and P-type transistors instead of ordinary diodes, which facilitates the discharge of static electricity generated at the I / O interface and improves the electrostatic discharge protection performance of the ESD circuit.

[0098] Figure 9 This is a schematic diagram of another display driving circuit provided in an embodiment of this disclosure. For example... Figure 9As shown, the display driving circuit described in this embodiment may further include: a Schottky trigger 05 and a protection circuit 06.

[0099] The Schottky flip-flop 05 can be coupled to both the internal circuit 01 and the I / O interface. The Schottky flip-flop 05 can receive analog power signals (referred to as analog signals) provided by the I / O interface, convert the analog power signals into digital power signals (referred to as digital signals), and then transmit them to the internal circuit 01.

[0100] For example, the Schottky trigger 05 can convert signals from the I / O interface to 0 and 1. For instance, it can convert a 1.2V power supply signal from an analog signal to a digital signal "1" and input it to the internal circuit 01 to drive the devices within it. Similarly, it can convert a 0V power supply signal from an analog signal to a digital signal "0" and input it to the internal circuit 01 to drive the devices within it.

[0101] Furthermore, refer to Figure 9 It can also be seen that the internal circuit 01 described in this embodiment can be directly coupled to the I / O interface. Furthermore, the internal circuit 01 can also be used to receive analog power signals provided by the I / O interface. That is, the internal circuit 01 can also directly receive analog signals input from the I / O interface (e.g., 1.2V or 0V power signals).

[0102] Based on this Figure 9 The Schottky trigger 05 and protection circuit 06 shown can be divided into the input section of the display driver circuit. It should be noted that the signals input from the I / O interface to the internal circuit 01 can come from other external devices coupled to the display driver circuit, such as the application processor (AP). Furthermore, the internal circuit 01 of the input section and the internal circuit 01 of the output section can be the same internal circuit 01.

[0103] The protection circuit 06 can be coupled to the I / O interface, the first external power supply terminal VDDI, the second external power supply terminal VSSI, and the second control terminal Con2, respectively. The protection circuit 06 can be used to stabilize the potential of the I / O interface based on the first power supply signal and the second power supply signal in response to the second control signal provided by the second control terminal Con2.

[0104] For example, when the potential of the second control signal provided by the second control terminal Con2 is the first potential, the protection circuit 06 can adjust the potential at the I / O interface based on the first power supply signal and the second power supply signal to stabilize the potential of the I / O interface. Furthermore, the protection circuit 06 can stop operating when the potential of the second control signal is the second potential.

[0105] exist Figure 5Based on the circuit structure shown, Figure 10 A schematic diagram of another display driver circuit is shown. For example... Figure 10 As shown, the protection circuit 06 described in this embodiment may include: a pull-up resistor R1, a pull-down resistor R2, a first switch K1, and a second switch K2.

[0106] Among them, the control terminal of the first switch K1 can be connected to the second control terminal Con2. Figure 10 (Not shown) Coupling, the first end of the first switch K1 can be coupled to the first external power supply terminal VDDI, and the second end of the first switch K1 can be coupled to the first end of the pull-up resistor R1.

[0107] The control terminal of the second switch K2 can be connected to the second control terminal Con2 ( Figure 10 (Not shown) Coupling, the first end of the second switch K2 can be coupled to the second external power supply terminal VSSI, and the second end of the second switch K2 can be coupled to the first end of the pull-down resistor R2.

[0108] The second end of pull-up resistor R1 and the second end of pull-down resistor R2 can both be coupled to the I / O interface.

[0109] Based on this, it can be seen that when the potential of the second control signal provided by the second control terminal Con2 is the first potential, both the first switch K1 and the second switch K2 are closed. The first external power supply terminal VDDI and the second external power supply terminal VSSI are both connected to the I / O interface. That is, the first external power supply terminal VDDI, the pull-up resistor R1, the second external power supply terminal VSSI, the pull-down resistor R2, and the I / O interface form a circuit. At this time, under the action of the pull-up resistor R1 and the pull-down resistor R2, the potential at the I / O interface can tend to stabilize. When the potential of the second control signal is the second potential, the first switch K1 and the second switch K2 are open. The first external power supply terminal VDDI and the second external power supply terminal VSSI are both disconnected from the I / O interface.

[0110] It should be noted that when the I / O interface is in a floating state, the potential of the second control signal can be set to the first potential to effectively stabilize the level of the I / O interface in the floating state.

[0111] It should also be noted that the first control terminal Con1 and the second control terminal Con2 can also be coupled to the internal circuit 01 and receive the first control signal and the second control signal respectively provided by the internal circuit 01. Furthermore, the display driver circuit generally includes multiple I / O interfaces, each of which can be coupled to, for example... Figure 10 The circuit structure shown improves the compatibility of each I / O interface.

[0112] In summary, this disclosure provides a display driving circuit comprising an internal circuit, a push-pull circuit, and a switching circuit. The push-pull circuit is coupled to the internal circuit, a first external power supply terminal, a second external power supply terminal, and a target node, and is capable of controlling the connection and disconnection of the first and second external power supply terminals with respect to the target node in response to a target control signal transmitted by the internal circuit. The switching circuit is coupled to both the target node and the I / O interface of the display driving circuit, and is capable of transmitting the potential of the target node to the I / O interface of the display driving circuit, specifically, transmitting a first power signal from the first external power supply terminal to the target node or a second power signal from the second external power supply terminal to the target node, and further outputting it to the I / O interface. Thus, by flexibly setting the target control signal, the first power signal, and the second power signal, multiple signals with different potentials can be transmitted to the I / O interface, improving the compatibility of the I / O interface.

[0113] Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Figure 11 As shown, the display device may include: an application processor (AP), a flash memory IC, a power management integrated circuit (PMIC), and a display driver IC as shown in any of the above figures.

[0114] The application processor (AP), flash memory IC, and power management integrated circuit (PMIC) can all be coupled to the I / O interface of the display driver IC (DDIC), and the I / O interfaces coupled to the AP, flash memory IC, and PMIC can be different. Furthermore, the AP and DDIC can communicate bidirectionally, as can the flash memory IC, and the DDIC can provide power signals to the PMIC.

[0115] Optional, see reference Figure 11 It can also be seen that, due to manufacturing process limitations, the communication voltage between the application processor (AP) and the display driver circuit (DDIC) can be 1.2V. The voltage between the flash memory IC and the display driver circuit (DDIC) can be 1.8V. Furthermore, the display driver circuit (DDIC) can provide a 1.8V power supply signal to the power management integrated circuit (PMIC).

[0116] Optionally, the display device described in the embodiments of this disclosure can be any product or component with display function, such as an OLED display device, a mobile phone, a tablet computer, a flexible display device, a television, and a monitor.

[0117] The terminology used in the embodiments of this disclosure is for illustrative purposes only and is not intended to limit the scope of this disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should be understood in their ordinary sense by one of ordinary skill in the art to which this disclosure pertains.

[0118] For example, the words “first,” “second,” or “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0119] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0120] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0121] Terms like "up," "down," "left," or "right" are used only to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connection" or "coupled" refers to an electrical connection.

[0122] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0123] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A display driving circuit, characterized in that, The display driving circuit includes: an input / output I / O interface, an internal circuit (01), a push-pull circuit (02), and a switching circuit (03); The internal circuit (01) is coupled to the push-pull circuit (02), and the internal circuit (01) is used to transmit the target control signal to the push-pull circuit (02); The push-pull circuit (02) is also coupled to the first external power supply terminal (VDDI), the second external power supply terminal (VSSI), and the target node (N0) respectively. The push-pull circuit (02) is used to control the connection and disconnection between the first external power supply terminal (VDDI) and the target node (N0) in response to the target control signal, and to control the connection and disconnection between the second external power supply terminal (VSSI) and the target node (N0). The switching circuit (03) is coupled to the first control terminal (Con1), the I / O interface and the target node (N0) respectively. The switching circuit (03) is used to transmit the potential of the target node (N0) to the I / O interface in response to the first control signal provided by the first control terminal (Con1). Wherein, the potential of the first power signal provided by the first external power supply terminal (VDDI) is greater than the potential of the second power signal provided by the second external power supply terminal (VSSI), and the potential of the first power signal is 1.2 volts or 1.8 volts, and the potential of the second power signal is 0, so that the I / O interface is compatible with dual voltage transmission of 1.2 volts and 1.8 volts, and is also compatible with transmission of 0 volts.

2. The display driving circuit according to claim 1, characterized in that, The push-pull circuit (02) includes: a first switch sub-circuit (021) and a second switch sub-circuit (022); The first switch sub-circuit (021) is coupled to the internal circuit (01), the first external power supply terminal (VDDI) and the target node (N0) respectively. The first switch sub-circuit (021) is used to control the on / off state of the first external power supply terminal (VDDI) and the target node (N0) in response to the target control signal provided by the internal circuit (01). The second switch sub-circuit (022) is coupled to the internal circuit (01), the second external power supply terminal (VSSI) and the target node (N0) respectively. The second switch sub-circuit (022) is used to control the on / off state of the second external power supply terminal (VSSI) and the target node (N0) in response to the target control signal provided by the internal circuit (01).

3. The display driving circuit according to claim 2, characterized in that, The first switching sub-circuit (021) includes a first transistor (T1); the second switching sub-circuit (021) includes a second transistor (T2), and the first transistor (T1) and the second transistor (T2) are of different types; The gate (T1) of the first transistor is coupled to the internal circuit (01), the first terminal of the first transistor (T1) is coupled to the first external power supply terminal (VDDI), and the second terminal of the first transistor (T1) is coupled to the target node (N0). The gate of the second transistor (T2) is coupled to the internal circuit (01), the first terminal of the second transistor (T2) is coupled to the second external power supply terminal (VSSI), and the second terminal of the second transistor (T2) is coupled to the target node (N0).

4. The display driving circuit according to claim 3, characterized in that, The first transistor (T1) is a P-type transistor, and the second transistor (T2) is an N-type transistor.

5. The display driving circuit according to any one of claims 1 to 4, characterized in that, The switching circuit (03) includes a third transistor (T3) and a fourth transistor (T4), wherein the third transistor (T3) and the fourth transistor (T4) are of different types; The gates of the third transistor (T3) and the fourth transistor (T4) are both coupled to the first control terminal (Con1). The first terminals of the third transistor (T3) and the fourth transistor (T4) are both coupled to the target node (N0). The second terminals of the third transistor (T3) and the fourth transistor (T4) are both coupled to the I / O interface.

6. The display driving circuit according to claim 5, characterized in that, The third transistor (T3) is a P-type transistor, and the fourth transistor (T4) is an N-type transistor.

7. The display driving circuit according to any one of claims 1 to 4, characterized in that, The display driving circuit also includes: an electrostatic discharge circuit (04); The electrostatic discharge circuit (04) is coupled to the first external power supply terminal (VDDI), the second external power supply terminal (VSSI) and the I / O interface respectively. The electrostatic discharge circuit (04) is used to release the static electricity generated at the I / O interface based on the first power signal and the second power signal.

8. The display driving circuit according to claim 7, characterized in that, The electrostatic discharge circuit (04) includes a fifth transistor (T5) and a sixth transistor (T6), wherein the fifth transistor (T5) and the sixth transistor (T6) are of different types; The gate and first terminal of the fifth transistor (T5) are both coupled to the first external power supply terminal (VDDI), and the second terminal of the fifth transistor (T5) is coupled to the I / O interface; The gate and first terminal of the sixth transistor (T6) are both coupled to the second external power supply terminal (VSSI), and the second terminal of the sixth transistor (T6) is coupled to the I / O interface.

9. The display driving circuit according to claim 8, characterized in that, The fifth transistor (T5) is a P-type transistor, and the sixth transistor (T6) is an N-type transistor.

10. The display driving circuit according to any one of claims 1 to 4, characterized in that, The display driving circuit further includes a current-limiting resistor (R0) connected in series between the switching circuit (03) and the I / O interface. The current-limiting resistor (R0) is used to limit the potential transmitted to the I / O interface.

11. The display driving circuit according to any one of claims 1 to 4, characterized in that, The display driving circuit also includes: a Schottky trigger (05) and a protection circuit (06); The Schottky trigger (05) is coupled to the internal circuit (01) and the I / O interface respectively. The Schottky trigger (05) is used to receive the analog power signal provided by the I / O interface, convert the analog power signal into a digital power signal, and then transmit it to the internal circuit (01). The protection circuit (06) is coupled to the I / O interface, the first external power supply terminal (VDDI), the second external power supply terminal (VSSI), and the second control terminal (Con2) respectively. The protection circuit (06) is used to stabilize the potential at the I / O interface in response to the second control signal provided by the second control terminal (Con2) based on the first power signal and the second power signal. The internal circuit (01) is also coupled to the I / O interface, and the internal circuit (01) is also used to receive the analog power signal provided by the I / O interface.

12. The display driving circuit according to claim 11, characterized in that, The protection circuit (06) includes: a pull-up resistor (R1), a pull-down resistor (R2), a first switch (K1), and a second switch (K2); The control terminal of the first switch (K1) is coupled to the second control terminal (Con2), the first terminal of the first switch (K1) is coupled to the first external power supply terminal (VDDI), and the second terminal of the first switch (K1) is coupled to the first terminal of the pull-up resistor (R1). The control terminal of the second switch (K2) is coupled to the second control terminal (Con2), the first terminal of the second switch (K2) is coupled to the second external power supply terminal (VSSI), and the second terminal of the second switch (K2) is coupled to the first terminal of the pull-down resistor (R2). The second end of both the pull-up resistor (R1) and the pull-down resistor (R2) is coupled to the I / O interface.

13. A display device, characterized in that, The display device includes: an application processor, a storage circuit, a power management integrated circuit, and a display driving circuit as described in any one of claims 1 to 12; The application processor, the storage circuit, and the power management integrated circuit are all coupled to the I / O interface of the display driver circuit, and the I / O interfaces coupled to the application processor, the storage circuit, and the power management integrated circuit are different. The application processor communicates bidirectionally with the display driver circuit, the storage circuit communicates bidirectionally with the display driver circuit, and the display driver circuit provides power supply signals to the power management integrated circuit.

14. The display device according to claim 13, characterized in that, The display device includes an organic light-emitting diode (OLED) display device.

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