A method for improving the power supply rejection ratio of a linear voltage regulator

Abstract

The application discloses a chip design technical field and a method for improving power supply rejection capability of a linear voltage regulator, which comprises the following steps: step one, a double-loop feedback structure is used, the double-loop feedback structure comprises a high-speed loop and a low-speed loop, the high-speed loop is used for improving LDO transient response speed through a high-speed low-gain fast loop circuit, and the low-speed loop is used for improving overall loop gain through a low-speed high-gain slow loop circuit; step two, an auxiliary LDO is added at a node of LDO circuit structure power supply rejection; step three, a dynamic current impedance modulation technology is added; and step four, an NMOS transistor is used to make a folded cascode amplifier structure of an input pair to accurately amplify errors of reference voltage and feedback voltage, the method has extremely high power supply rejection ratio at low frequency, has good power supply rejection capability at high frequency, provides clean and ripple-free internal power supply for different load modules, and plays a good isolation role between power supply and noise sensitive modules.

Description

Technical Field

[0001] This invention belongs to the field of chip design technology, specifically a method for improving the power supply rejection capability of a linear voltage regulator. Background Technology

[0002] Wireless Power Management Units (WPMUs) are power supply systems for electronic devices and are widely used in various fields. With the continuous development of on-chip integration technology, the functions and applications implemented by System-on-Chip (SoC) are becoming increasingly complex. Common wearable and implantable biomedical electronic devices, such as heart rate and blood pressure monitors, gastrointestinal capsule endoscopes, pacemakers, and deep brain stimulators, have brought great convenience to people's daily lives and health. The LDO, a core module in the WPMU, faces a major challenge in terms of power supply rejection ratio (PSRR). The LDO should have better PSRR capabilities in the high-frequency range to provide a clean, ripple-free input voltage to noise-sensitive modules.

[0003] When the input power of the WPMU is between 50μW and 100μW, the input voltage is too low and DC-DC boosting is required. The internal switching frequency in the high-frequency range of 1MHz to 100MHz will have power supply ripple, which will cause the regulator to have poor power supply rejection capability and weaken the isolation between the power supply and noise-sensitive modules. Summary of the Invention

[0004] To address the problem of poor power supply rejection in voltage regulators, which weakens the isolation between power supplies and noise-sensitive modules, the present invention provides a method for improving the power supply rejection capability of linear voltage regulators.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows: A method for improving the power supply rejection capability of a linear regulator includes the following steps:

[0006] Step 1: Use a dual-loop feedback structure, which includes a high-speed loop and a low-speed loop. The high-speed loop is used to improve the transient response speed of the LDO through a high-speed, low-gain fast loop circuit, and the low-speed loop is used to improve the overall loop gain through a low-speed, high-gain slow loop circuit.

[0007] Step 2: Add an auxiliary LDO at the power supply rejection node of the LDO circuit structure to enhance the power supply rejection ratio in the high frequency range;

[0008] Step 3: Add dynamic current impedance modulation technology to keep the magnitude of the main pole impedance dynamically stable, improve the phase margin, and ensure loop stability.

[0009] Step 4: Using an NMOS transistor as the input pair, a folded cascode amplifier structure is used to accurately amplify the reference voltage and feedback voltage.

[0010] The above scheme achieves the following beneficial effects: 1. It keeps the magnitude of the main pole impedance dynamically stable, improves the phase margin, and ensures loop stability; 2. It gives the LDO an extremely high low-frequency power supply rejection ratio.

[0011] 2. Compared to using PMOS as the input pair transistor, it reduces the impact of power supply noise on the amplifier.

[0012] 3. This invention proposes a method to improve the power supply rejection capability of a linear regulator across the entire frequency spectrum under low voltage conditions. As the core regulator in a WPMU, it has an extremely high power supply rejection ratio at low frequencies and good power supply rejection capability at high frequencies. It provides a clean, ripple-free internal power supply for different load modules and provides good isolation between the power supply and noise-sensitive modules.

[0013] Furthermore, step one includes the following steps:

[0014] S1.1, For the output node V of LOOP1 OUT It employs on-chip integrated capacitors to maintain the dominant pole position at V. OUT This achieves the purpose of effectively filtering high-frequency power supply noise.

[0015] S1.2 For LOOP2, the dominant pole position should be maintained at Vmir, so that the amplifier output node V EA Pushed to a high frequency of MHz, ensuring the stability of the LOOP2 loop, increasing gain, and further enhancing power supply rejection capability.

[0016] Beneficial effects: Using a dual feedback loop to adjust the output voltage aims to ensure a fast circuit response while maintaining a very high power supply rejection ratio (PSR), thus improving the poor suppression capability caused by power supply rejection spikes.

[0017] Furthermore, in step two, the three-input auxiliary LDO further filters the noise of the input power supply voltage, providing a clean and ripple-free Vmir voltage internally, thus improving the power supply rejection spike that occurs at 10MHz.

[0018] Furthermore, the dynamic current impedance modulation technique in step three is used to dynamically adjust the impedance of the first-stage output node of the amplifier according to the load current.

[0019] Beneficial effects: The performance requirements for loop phase margin are extremely high without using large external load capacitors, so the amplifier's PVT characteristics are very critical. At the same time, due to the high power supply rejection ratio, the amplifier needs to maintain a high gain. However, increasing the loop gain will lead to a huge challenge to loop stability, and its stability capability will be greatly reduced. In order to ensure the amplifier's phase margin and loop stability, a dynamic current impedance modulation technique is proposed here, which dynamically adjusts the impedance of the first stage output node of the amplifier according to the load current.

[0020] Furthermore, in step four, the NMOS is used as a folded cascode amplifier with input pair transistors.

[0021] Beneficial effects: 1. The error amplifier uses a folded cascode amplifier with NMOS input transistors, which significantly enhances the gain compared to a five-transistor amplifier structure. Simultaneously, using NMOS input transistors reduces the impact of power supply voltage on the circuit. In circuits requiring extremely high power supply rejection ratios, it offers a stronger advantage in power supply rejection compared to circuits using PMOS input transistors. The second stage of the error amplifier adds a PMOS transistor layer compared to the traditional folded cascode structure. The main purpose here is to filter the power supply by adding MOS transistors, reducing the impact of power supply noise on the amplifier output.

[0022] 2. This invention enhances three key factors: low-frequency gain, transient response capability, and loop phase margin. Firstly, the dual-loop structure, used here as a fast-loop, low-gain voltage-flipping follower loop, enables rapid response to load changes, improving transient response capability. Secondly, utilizing the noise ripple filtering characteristics of the internal three-input auxiliary LDO, nodes sensitive to power supply rejection ratio (PSRR) are effectively filtered, improving the PSRR across the entire frequency range. Finally, a folded cascode amplifier with NMOS input pairs amplifies the error between the reference and feedback voltages, increasing loop gain and reducing Vo. DD The effect of power supply noise on the first stage output of the amplifier. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the overall structure of the present invention;

[0024] Figure 2 This is a schematic diagram of the small signal model of the present invention;

[0025] Figure 3 This is a schematic diagram of the source voltage follower enhanced small-signal model of the present invention;

[0026] Figure 4 This is a schematic diagram of the three-input auxiliary LDO of the present invention;

[0027] Figure 5These are the power supply rejection ratio simulation results of the assisted LDO and the conventional LDO according to the present invention;

[0028] Figure 6 This is a schematic block diagram of the dynamic current comparison circuit structure of the present invention;

[0029] Figure 7 This invention S d1 S d2 Simulation results of high and low level signals under different load currents;

[0030] Figure 8 The simulation results of the overall loop gain and phase margin of this invention are obtained by using dynamic current impedance modulation technology within the range of input voltage 1.2V, output voltage 1V, and load current 20mA.

[0031] Figure 9 This is a schematic diagram of the circuit structure of the present invention;

[0032] Figure 10 These are the simulation results of the loop wave characteristics of this invention;

[0033] Figure 11 This is the simulation result of the power supply rejection ratio when the low voltage is 1.2V and the output voltage is 1V according to the present invention.

[0034] Figure 12 This is the simulation verification result of the power supply ripple suppression ratio under transient conditions of the present invention;

[0035] Figure 13 This is a comparison of the transient response simulation results of a conventional LDO and a low-voltage high power supply rejection ratio voltage-flipping follower LDO.

[0036] Figure 14 These are simulation results of the LDO linear adjustment rate applied using the present invention;

[0037] Figure 15 These are simulation results of LDO load regulation applied using the present invention;

[0038] Figure 16 This is a simulation result showing the change in efficiency corresponding to the change in LDO output current using the present invention. Detailed Implementation

[0039] The following detailed description illustrates the specific implementation method:

[0040] The basic implementation examples are as follows: Figure 1 As shown: A method for improving the power supply rejection capability of a linear regulator.

[0041] Example 1

[0042] like Figures 1-16As shown, this embodiment provides a method for improving the power supply rejection capability of a linear regulator across the entire frequency spectrum under low-voltage conditions. The steps are as follows:

[0043] Step 1, such as Figure 1 The diagram shows a dual-loop feedback structure. On the one hand, the high-speed, low-gain fast loop improves the transient response speed of the LDO. On the other hand, the low-speed, high-gain slow loop improves the overall loop gain, giving the LDO an extremely high low-frequency power supply rejection ratio.

[0044] Step one includes the following steps:

[0045] S1.1 To evaluate the characteristics of different loop transfer functions of the LDO, such as Figure 2 The small-signal model of the designed low-voltage, high-power supply rejection ratio (PSRR) voltage-flipping follower LDO is analyzed. The transfer function formulas for different loops are derived by disconnecting the first-stage amplifier output and the input node of the source voltage follower enhancement. Through theoretical analysis of the formulas, key factors of the transfer function for different loops are identified, and the performance of the actual circuit is improved, ultimately achieving the low-voltage, high-frequency PSRR performance of the LDO. Where g... mi This indicates the transconductance of different transistors. R i C i r oi These represent the parasitic resistance, parasitic capacitance, and internal resistance of the MOS transistor in each section, respectively. A ea This represents the DC gain of the error amplifier. A mg =g m20 (r o20 ||r o21 ) and A pass =g mp (r op ||R L () represents the DC gain of the M8 and M9 common-gate amplifiers and the power transistor M, respectively. pass DC gain.

[0046] First, the loop transfer function of LOOP1 is derived. Figure 2 It can be seen that the changes in the input and output of loop LOOP1 are respectively caused by V loop1 and V e This indicates that due to the LDO feedback loop, V OUT The change is equal to V loop1 The change. To perfect the derivation of the transfer function of LOOP1, we need to start with small-signal analysis from the source voltage follower enhancement structure to obtain v. g The formula for small signals. For example... Figure 3 The figure shows the small-signal model of the source voltage follower enhancement circuit. According to Kirchhoff's current law, its transfer function is:

[0047]

[0048] Where g m15 / c g =p g 1 / c2(r o15 ||r o16 ) = p2, 1 / c1(r o17 ||r o18 The pole positions are determined by z1, z2, p1, and p2, respectively. Therefore, the principle of pole-zero cancellation can be used to eliminate z1, z2, p1, and p2. By simplifying the transfer function of the voltage follower enhancement circuit, we can finally obtain the information about v. g The expression:

[0049]

[0050] v g Substituting this into the low-voltage, high-frequency power supply rejection ratio (LDO) small-signal model, complete the LOOP1 loop input node v. e The derivation is as follows. In loop LOOP1, the focus is mainly on the pole p. out p e p g The analysis shows that its location is determined by the impedance of the node. Additionally, due to the use of on-chip integrated capacitors, the LOOP1 loop will... out We analyze it as if it were the principal pole. Finally, we can obtain v. e The node voltage change and the LOOP1 transfer function are as follows:

[0051]

[0052]

[0053] S1.2 Complete the derivation of the transfer function of LOOP2 loop. Through small-signal model analysis, complete the output node voltage v of LOOP2 loop. ea Formula derivation yields:

[0054]

[0055]

[0056] Substituting the above formula into the LOOP2 transfer function, we get:

[0057]

[0058] The transfer formula shows that the main pole positions of LOOP2 and LOOP1 are different, mainly due to the internal 15pF integrated capacitor C. mir As impedance enhancement, V mirAs the dominant pole, it also makes the output pole p of the error amplifier... ea As a secondary point, dynamic impedance modulation technology is used to push it to a high frequency above MHz, ensuring that the loop has high gain while maintaining ultra-strong stability, and finally realizing that the LDO has good power supply rejection ratio at high frequency, ensuring the stable operation of low-voltage high power supply rejection ratio voltage-flip follower LDO.

[0059] Therefore, the design of dual feedback loops LOOP1 and LOOP2 enables the loop to have high gain and ultra-high stability. Ultimately, this achieves good power supply rejection capability for the LDO across the entire frequency spectrum.

[0060] Step 2: Add auxiliary LDOs at nodes where power supply rejection is more sensitive in the LDO circuit structure to enhance the power supply rejection ratio in the high-frequency range;

[0061] To improve the DC accuracy and enhance power supply rejection of voltage-flipping follower LDOs, a three-input error amplifier structure (such as...) is used. Figure 4 As shown, a new feedback loop is added to compare the difference between the reference voltage and the output voltage, ultimately increasing the output voltage V. OUT The voltage accuracy. Because theoretically V OUT and V REF The voltage values ​​are closer. Assuming the W:L ratio of the three input transistors is N:1:N-1, making N = 4, and the ratio is 4:3:1, we can deduce V. OUT for:

[0062]

[0063] V MIR =V OUT +ΔV

[0064] Where A EA The DC gain of the error amplifier (including V) SET The voltage gain (the voltage produced by the voltage), ΔV is V OUT and V MIR The difference arises due to the effects of PVT and load current variations. Ideally, the error amplifier gain A... EA Infinity, A EA >>1 Therefore, we can obtain:

[0065]

[0066]

[0067] From the formula, we can obtain that when the ratio is 4:1:3, V REF Compared to V MIR Closer to V OUTWhen N is infinitely large, we can obtain:

[0068]

[0069] From the above formula, we can see that the larger N is, the greater V is. MIR The closer to V REA Similarly, the formula is derived through small-signal simulation of the circuit:

[0070]

[0071] From the formula, we can see that the larger N is, the larger V is. OUT / V IN A smaller ratio corresponds to a lower logarithm of PSR, indicating higher power supply rejection capability. Ultimately, this achieves both fast transient response and higher power supply rejection capability in the assisted LDO. The simulation results of power supply rejection ratios for assisted LDO and traditional LDO structures are compared (e.g.,...). Figure 5 As shown, while traditional LDOs have a strong advantage at low frequencies, their power supply rejection ratio (PSR) is very poor in the high-frequency range above 1MHz, with the PSR peak even reaching over 0dB at 10MHz. In contrast, a flip-type voltage follower LDO with a three-input error amplifier structure exhibits excellent PSR performance across the entire frequency range, generally maintaining around -40dB, and at least -14dB at the highest PSR peak. Therefore, a three-input error amplifier voltage flip-type follower LDO was ultimately chosen as the internal auxiliary LDO circuit structure to achieve efficient power supply rejection across the entire frequency range.

[0072] Step 3: Propose dynamic current impedance modulation technology to keep the magnitude of the main pole impedance dynamically stable, improve the phase margin, and ensure loop stability.

[0073] Based on the characteristics of a MOS transistor current-controlled voltage source and the principle of a hysteresis comparator, by controlling M... d9 M d13 Transistor and inverter circuits generate S based on changes in the output current. d1 and S d2 Two different control signals (e.g.) Figure 6 (As shown). The dashed line in the figure represents the amplifier output node V. EA The dynamic current impedance modulation module at the location generates S through the dynamic current comparison structure. d1 and S d2 Control the switch to close and open, and adjust node V according to the magnitude of the output current. EA The impedance at this point is adjusted to ensure that the point remains at a high frequency, thereby reducing the impact on the dominant pole and improving loop stability.

[0074] By analyzing Sd1 S d2 Simulation results of high and low level signals under different load currents (e.g.) Figure 7 (As shown). In actual circuit design, M d4 and M PASS The transistor's W / L ratio is 1:3000, therefore I1 = I OUT / 3000, I8 = I7 = I OUT / 12000, when I OUT When = 0, I7 <I3+I4,V a V b High level S d1 S d1 To ensure p is low level ea It has sufficient frequency and remains at a high frequency position, while p can be obtained from the formula. ea Size by g mea and C c The ratio is determined by this, therefore the internal compensation capacitor Cc = C1. When I OUT When I7 > I3 + I4, that is, I OUT >1.5mA, S d1 S is a high level. d2 Still at low level, internal compensation capacitor C c =C1+C2. When I OUT If you continue to increase it, g will appear. mea In the worst-case scenario, to ensure loop stability while ensuring p ea At a high frequency position, S d1 and S d2 When the voltage is high, all switches are in the closed state, and the internal compensation capacitor C... c =C1+C2+C3.

[0075]

[0076] Figure 8 The overall loop gain and phase margin scan results were obtained using dynamic current impedance modulation technology within an input voltage of 1.2V, an output voltage of 1V, and a load current of 20mA. The results show that the LDO with dynamic current impedance modulation achieves a gain of at least 78dB in Bode's simulation, while maintaining a phase margin above 83° after compensation, meeting the LDO stability requirements. This demonstrates an LDO loop characteristic with ultra-high gain and high stability, ultimately ensuring the LDO has a superior power supply rejection ratio.

[0077] Step 4: The folded cascode amplifier structure using NMOS transistors as input pairs provides precise error amplification of the reference voltage and feedback voltage, reducing the impact of power supply noise on the amplifier compared to using PMOS transistors as input pairs.

[0078] The overall circuit of a low-voltage, high-power supply rejection ratio (PSRR) voltage-flip follower LDO mainly consists of: an error amplifier, dynamic current impedance modulation, an inverting stage, and a voltage-flip follower (such as...). Figure 9 (As shown). The error amplifier uses a folded cascode amplifier with NMOS input transistors, which significantly enhances the gain compared to a five-transistor amplifier. At the same time, using NMOS input transistors reduces the impact of power supply voltage on the circuit. In circuits with extremely high power supply rejection ratio requirements, it has a stronger advantage in power supply rejection compared to circuits with PMOS input transistors.

[0079] Compared to the traditional folded cascode structure, the second stage of the error amplifier adds a PMOS transistor layer. The main purpose here is to filter the power supply by adding MOS transistors, reducing the impact of the power supply voltage on V. EA The influence of the error amplifier output node V EA Controlling NOMS transistor M 13 The gate is configured so that one output point is directly grounded. Through the above series of transistor connection methods that enhance power supply rejection capability, the V0 will be reduced to the maximum extent. DD The ripple effect was mitigated. Ultimately, a folded cascode amplifier circuit structure with high-frequency power supply rejection ratio was achieved.

[0080] The inverting stage mainly consists of transistor M 11 -M 13 The purpose of this structure is to ensure V EA Point and V OUT In-phase transition, first V EA Through M 13 The common-source amplifier is inverted, and then passed through M... 20 The common-gate amplifier is inverted again, and finally outputs to V. OUT At the node, after two inversions, V is ensured EA and V OUT The changes remain in phase. When the output voltage encounters load current or input voltage fluctuations, it can quickly adjust to changes in V. EA The point voltage is adjusted, and finally through M 20 Transistor, making V OUT Stabilized at reference voltage V REF Nearby, ensure output voltage V OUT Precision.

[0081] Meanwhile, the transconductance can be further increased through the inverting stage, which ultimately enhances the loop gain. Since the low-frequency power rejection ratio is closely related to the loop gain, the increase in loop gain can further improve the low-frequency power rejection ratio, enabling the LDO to have good power rejection capability in the low-frequency range.

[0082] The last stage of a low-voltage, high-power supply rejection ratio (PSRR) voltage-flip follower LDO is a basic voltage-flip follower circuit, consisting of M... 14 -M 21 Transistor configuration. Where M... 14 -M 16 This is a source voltage follower enhancement circuit, mainly through M 20 Transistor drain current control M 15 Common-source amplifier, for M Pass The gate of the power transistor is adjusted to achieve voltage regulation. Compared with the voltage flip follower circuit that directly feeds back to the gate of the power transistor, the transconductance of loop LOOP1 is enhanced, thereby improving the DC gain.

[0083] M 19 It is a self-response switch, by M 17 and M 18 Transistor control primarily addresses voltage spikes in the gate voltage caused by sudden changes in external factors, controlled by M. 19 The transistor performs a rapid self-response discharge to reduce the influence of external factors on the gate voltage of the power transistor. 20 -M 21 It is a common-gate amplifier, mainly through the V of LOOP2. SET Voltage control M 20 Transistor gate, for auxiliary M Pass The output voltage of the power transistor is adjusted to improve output voltage accuracy. Simultaneously, the common-gate amplifier is a major component of the loop gain in LOOP1, therefore requiring a very large input voltage M. 21 The transistor's width-to-length ratio is increased to improve transconductance and enhance the loop gain of LOOP1. Ultimately, while ensuring good gain, a voltage flip-follower circuit is used to achieve a fast transient response to the output voltage.

[0084] Example 2

[0085] The difference between this embodiment and the above embodiments is that: Figure 10 Simulation results for the LDO loop gain and phase margin show that with an input voltage of 1.2V and an output voltage of 1V, the loop gain is 80dB, the phase margin is 84.86°, and the unity-gain frequency is 100kHz. Simulation results demonstrate that the proposed auxiliary amplifier transconductance enhancement compensation and high-speed transconductance buffer structure can help the LDO achieve the required gain and phase in high-voltage or low-voltage modes, enabling the amplifier to accurately amplify V. FB and V REF This reduces errors and enhances the overall linearity and load regulation performance of the LDO. Furthermore, the power rejection ratio in the low-frequency range can also be effectively improved.

[0086] Power supply rejection ratio (PSRR) is the most critical performance indicator of a low-voltage, high PRR voltage-flipping follower LDO. It reflects the LDO's ability to suppress power ripple caused by input power supply voltage noise. The stronger the PRR, the cleaner the LDO's output voltage, ultimately supplying power to the noise-sensitive load module.

[0087] Simulation results of power supply rejection ratio at low voltage 1.2V and output voltage 1V (e.g.) Figure 11 The results (shown in the image) illustrate the PSR simulation results for load currents of 100μA, 1mA, 10mA, and 20mA. The optimal results at frequencies of 100Hz, 100kHz, 1MHz, 10MHz, and 100MHz are -90dB, -40dB, -22dB, -42dB, and -50dB, respectively. Within the load current range of 0–20mA, the peak PSR consistently remains below 0dB, with a maximum of -2dB. Therefore, the simulation results demonstrate a power supply rejection ratio (PSR) of at least -85dB in the low-frequency range of 0–100Hz and at least -15dB in the high-frequency range of 1MHz–100MHz with a 1mA load current. This ultimately achieves excellent PSR performance for the LDO across the entire frequency spectrum.

[0088] Simulation verification results of power supply ripple rejection ratio under transient conditions (e.g.) Figure 12 The simulation (shown) is a transient verification of the power supply rejection ratio (PSRR) under AC conditions. This simulation verifies the high-frequency PSRR power supply ripple rejection under a load current of 100μA, an input voltage frequency of 10MHz, and a swing of 10mV. The simulation results show that when the input swing is 10mV, the output swing is 80μV. The PSRR ripple rejection ratio can be calculated to be -42dB using the formula, which is consistent with the power supply rejection ratio corresponding to 10MHz under AC conditions. This ultimately verifies the high power supply rejection ratio performance of the low-voltage, high-PSRR voltage-flip follower LDO.

[0089] Under the same external conditions, the transient response simulation results of a traditional LDO and a low-voltage high power supply rejection ratio voltage-flipping follower LDO are compared (e.g.) Figure 13 (As shown in the figure). When the load current abruptly changes from 0 to 20mA with a rise / fall delay of 100ns, the simulation results of the conventional LDO (dashed line) show overshoot voltages of 149mV and 198mV at the output voltage, with recovery times of 5.4μs and 5.5μs, respectively. However, the simulation results of the solid line, which employs a method to improve the full-spectrum power rejection capability of the low-dropout linear regulator, show overshoot voltages of 98mV and 25mV, with recovery times of 741ns and 900ns, respectively.

[0090] Simulation results show that the response speed of the voltage-flipping follower LDO is significantly higher than that of the LDO using a traditional resistive feedback network. Therefore, this invention uses a voltage-flipping follower LDO as the basic structure to improve the overall design, achieving a high-speed transient response capability for the LDO.

[0091] Figure 14-15 Simulation results for line regulation and load regulation are shown. When the input voltage changes from 1.1V to 1.6V, the output voltage changes by 85μV, with a line regulation of 0.17μV / mV. When the output current changes from 0 to 20mA, the output voltage changes by 2.8μV, with a load regulation of 0.14μV / mA.

[0092] Simulation results of LDO output current changes corresponding to efficiency changes (e.g.) Figure 16 As shown in the figure, when the output current changes from 2mA to 8mA, the efficiency changes from 90% to 95%. From the efficiency formula, we can see that I... Q The lower the quiescent current, the more efficient the LDO of this invention, and the lower its power consumption. This ultimately ensures the low-voltage, low-power performance of the LDO.

[0093] This paper proposes a method to improve the power supply rejection ratio (PSRR) of a linear regulator across the entire frequency spectrum under low-voltage conditions. This method not only achieves ultra-high and low-frequency gain, improves PSRR performance, and enhances the filtering ability of input power supply noise, but also maintains good PSRR performance in the high-frequency range through the combined use of three-input auxiliary LDOs. Furthermore, dynamic current impedance modulation technology is introduced at critical poles to enhance the LDO loop phase margin and ensure LDO loop stability.

[0094] LDO: Low Dropout Linear Regulator.

[0095] FVF: Flip Voltage Follower.

[0096] WPMU: Wireless Power Management Unit.

[0097] PSR: Power Supply Voltage Rejection Ratio.

[0098] LDR: Load Regulation Rate.

[0099] LNR: Linear adjustment rate.

[0100] In summary, this invention discloses a method for improving the power supply rejection capability of a linear regulator across the entire frequency spectrum under low voltage conditions, which is mainly used to improve various performance indicators of analog low-dropout regulators.

[0101] The power supply rejection ratio enhancement method disclosed in this invention consists of four parts: dual-loop high-gain high-speed feedback, three-input auxiliary LDO, dynamic current impedance modulation, and high-gain error amplifier.

[0102] The dual-loop high-gain high-speed feedback proposed in this invention can maintain high loop gain while providing a fast transient response. This method greatly improves the transient response capability of LDO, resulting in fast recovery and high accuracy.

[0103] The three-input auxiliary LDO proposed in this invention can greatly reduce the impact of input power supply noise on the LDO loop by filtering the noise of the power supply noise sensitive node voltage, eliminating power supply rejection ratio spikes in the high-frequency range, and enabling the LDO to have power supply rejection capability in the full spectrum range.

[0104] The dynamic current impedance modulation proposed in this invention has strong applicability and high sensitivity. It can effectively control the switch according to the load current, change the impedance of key poles, improve the loop phase margin, and ensure the overall stability of LDO.

[0105] The high-gain error amplifier proposed in this invention has high gain and high stability, and can effectively reduce the impact of power supply noise on the amplifier output, giving the LDO extremely high low-frequency gain.

[0106] This invention targets three key LDO metrics: power supply rejection ratio, low-frequency gain, and loop phase margin. It can improve parameters that measure the static performance of an LDO, such as PSR, LNR, and LDR. Secondly, the dual-loop high-speed, high-gain technology enhances the dynamic performance of the LDO, giving it a fast transient response capability.

[0107] The above descriptions are merely embodiments of the present invention. Commonly known structures and characteristics are not described in detail here. Those skilled in the art are aware of all common technical knowledge in the field prior to the application date or priority date, are aware of all existing technologies in that field, and have the ability to apply conventional experimental methods prior to that date. Those skilled in the art can, under the guidance of this application, improve and implement this solution in combination with their own capabilities. Some typical known structures or methods should not be obstacles for those skilled in the art to implement this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of the present invention. These should also be considered within the scope of protection of the present invention, and will not affect the effectiveness of the implementation of the present invention or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A method for improving the power supply rejection capability of a linear regulator, characterized in that: Includes the following steps: Step 1: Use a dual-loop feedback structure, which includes a high-speed loop (LOOP1) and a low-speed loop (LOOP2). LOOP2 is the main low-speed, high-gain error feedback loop, comprising a two-input main error amplifier, a dynamic current impedance modulation module, an inverting stage composed of PMOS transistors M11 and M12 and NMOS transistor M13, an auxiliary LDO containing a three-input auxiliary error amplifier, an on-chip integrated capacitor Cmir, a common-gate amplifier composed of PMOS transistor M20, a source voltage follower enhancement circuit with a transconductance of gm15, and a PMOS power transistor. ; The inverting stage consists of PMOS transistors M11 and M12 and an NMOS transistor M13, with the source of M13 grounded. The gate of M13 is connected to the output nodes of the two input main error amplifiers and also to the dynamic current impedance modulation module. The node voltage is marked as follows. The drain and gate of M12 are connected, and the drain of M13 is connected to it. The node voltage is marked as follows. The source of M12 and the drain of M11, and the on-chip integrated capacitors. One end of the circuit is connected to the non-inverting input of the three-input auxiliary error amplifier of the auxiliary LDO. The source of M12 is the dominant pole inside the LOOP2 loop, and the node voltage is marked as... , The other end is grounded, the inverting input of the three-input auxiliary error amplifier is connected to the reference voltage, and the output of the three-input auxiliary error amplifier is connected to the gate of M11. M11 and Source terminal ; The dynamic current impedance modulation module consists of resistor R1, capacitors C1 to C3, and switches S1, S2, and S3. Switch S1 is connected in series with R1 and C1, forming the first impedance modulation branch; switch S2 is connected in series with C2, and the control signal for S2 is... This forms the second impedance modulation branch; switch S3 is connected in series with C3, and the control signal for S3 is... This forms the third impedance modulation branch; the three impedance modulation branches are connected in parallel, with one end grounded and the other end connected to the output node of the two-input main error amplifier, i.e., the node where the node voltage VEA is located. The non-inverting input terminals of the two-input main error amplifier are connected to the output voltage. The inverting input terminal is connected to the reference voltage; The common-gate amplifier constructed by M20 has its source connected to... The drain of M20 is connected to one end of the output load resistor RL and capacitor CL, while the other end of resistor RL and capacitor CL is grounded. The source of M20 is the voltage output node of the regulator, and the source of M20 is also the main pole inside the LOOP1 loop. The node voltage is marked as follows. The voltage at the node where the drain of M20 is located is The drain of M20 is connected to the input of the source voltage follower enhancement circuit with a transconductance of gm15. The drain of M20 is the loop probe node of LOOP1. During loop analysis, the analysis is disconnected from the drain of M20. The gate of M20 is connected to the gate of M12. The output node of the source voltage follower enhancement circuit is connected to the gate of the PMOS power transistor MPass, and the voltage is marked as follows. ; LOOP1 is a high-speed, low-gain secondary loop, consisting of a common-gate amplifier composed of a PMOS transistor M20, a source voltage follower enhancement circuit with a transconductance of gm15, and a PMOS power transistor MPass; the main pole of LOOP1 is the voltage output node of the regulator. High-speed loop LOOP1 is used to improve the transient response speed of the LDO through a high-speed, low-gain fast loop circuit, while low-speed loop LOOP2 is used to improve the overall loop gain through a low-speed, high-gain slow loop circuit. The small-signal model of the designed low-voltage, high-power-resistance ratio voltage-flipping follower LDO is analyzed. Loop transfer function: In the formula, ; This is the input voltage for loop LOOP1. The intrinsic gain of the principal pole of LOOP1. It is a complex frequency; , , These represent the poles at the voltage output node of the voltage regulator, the probe point node of the LOOP1 loop, and the output node of the common-gate amplifier, respectively. Loop transfer function: In the formula, This represents the DC gain of the two-input main error amplifier; for The main pole inside the loop; This indicates the output node of the two-input main error amplifier; From the transfer formula, we can obtain and The location of the dominant pole is different, by utilizing an internal size of 15pF To enhance impedance, increase back, Will become The dominant pole; simultaneously causing the output poles of both input error amplifiers to be... As a secondary pole, it is pushed to a high frequency above MHz by introducing a dynamic current impedance modulation module to ensure that the loop has high gain while maintaining ultra-strong stability. Ultimately, the LDO has a good power supply rejection ratio under high frequency power supply ripple conditions, ensuring stable operation of the LDO. Step Two, in The main pole inside the loop, i.e. Add an auxiliary LDO at the node where the voltage is located, and As an input to an auxiliary LDO, it enhances the power supply rejection ratio in the high-frequency range; The auxiliary LDO is used by The three-input error amplifier structure in the loop compares the reference voltage and The voltage difference is reduced. The error between the voltage and the reference voltage ultimately increases the output voltage. Voltage accuracy; Step 3: Based on the dynamic current impedance modulation module, so that... The impedance of the main pole inside the loop remains dynamically stable, improving the phase margin and ensuring loop stability; Based on the characteristics of a MOS transistor current-controlled voltage source and the principle of a hysteresis comparator, by controlling a dynamic current comparator circuit and an inverter circuit, a voltage source is generated according to the change in output current. and Two different control signals; and These are used to control the output nodes of the two input main error amplifiers respectively. The second and third impedance modulation branches of the dynamic current impedance modulation module at the location are generated by the dynamic current comparison structure. and The control switch is closed and opened, and the output node of the error amplifier is adjusted according to the magnitude of the output current. The impedance at this point is adjusted to ensure that the point is always at a high frequency, thereby reducing the impact on the dominant pole and improving loop stability. Step 4: Use a folded cascode amplifier structure with NMOS transistors as input pairs as a two-input main error amplifier to accurately amplify the reference voltage and feedback voltage. The two-input main error amplifier adopts a folded common-source common-gate amplifier structure with NMOS as the input transistor pair. Compared with the traditional five-transistor amplifier structure, the gain is enhanced. At the same time, using NMOS as the input transistor pair reduces the impact of power supply voltage on the circuit. In circuits with extremely high power supply rejection ratio requirements, it has a stronger advantage in power supply rejection performance compared with circuits using PMOS as the input transistor pair.

2. The method for improving the power supply rejection capability of a linear regulator according to claim 1, characterized in that: Step one includes the following steps: S1.

1. For the output node VOUT of LOOP1, an on-chip integrated capacitor is used to keep the main pole position at VOUT, thereby achieving the purpose of effectively filtering high-frequency power supply noise. S1.

2. For LOOP2, the dominant pole position should be maintained at Vmir, so that the amplifier output node VEA is pushed to a high frequency MHz, ensuring the stability of LOOP2 loop, improving gain, and further enhancing power supply rejection capability.

3. The method for improving the power supply rejection capability of a linear regulator according to claim 1, characterized in that: In step two, the three-input auxiliary LDO further filters the noise of the input power supply voltage, providing a clean and ripple-free Vmir voltage internally, thus improving the power supply rejection spike that occurs at 10MHz.

4. The method for improving the power supply rejection capability of a linear regulator according to claim 1, characterized in that: In step three, the dynamic current impedance modulation technique is used to dynamically adjust the impedance of the first-stage output node of the amplifier according to the load current.

5. The method for improving the power supply rejection capability of a linear regulator according to claim 1, characterized in that: In step four, NMOS is used as the input pair transistor in a folded cascode amplifier.

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