A wafer surface defect detection method, device and system

Abstract

The present disclosure discloses a wafer surface defect detection method, device and system, which belongs to the technical field of semiconductor manufacturing, and comprises the following steps: acquiring a plurality of wafer images to be detected; for each wafer image to be detected, acquiring a plurality of first connected domains of surface defects in each wafer image to be detected; obtaining a corresponding second connected domain by performing morphological dilation on each first connected domain; forming a defect area to be detected according to the first connected domain corresponding to the second connected domain; and identifying the defect category based on the defect area to be detected. According to the relationship between the connected domains of the surface defects before and after the inflation in the wafer surface image to be detected, the final defect area to be detected is determined; and based on the finally determined defect area to be detected, the defect category is identified, the multiple connected domains belonging to one defect can be combined and identified, the calculation error of the feature value caused by the inflation operation can be avoided, and the defect identification accuracy is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method, apparatus and system for detecting defects on the surface of a wafer. Background Technology

[0002] In the semiconductor field, single-crystal silicon rods are fabricated using the Czochralski method, and then subjected to a series of industrial processes, including slicing, to produce single-crystal silicon wafers, hereinafter referred to as wafers. During wafer transportation or production, defects such as edge chipping, scratches, and chemical contamination caused by friction, scratches, impacts, or chemical immersion are among the most common defects on the wafer surface. If wafers containing these defects are not effectively detected and proceed to subsequent processes, they can easily cause fragmentation problems during the polishing process, leading to polishing equipment malfunctions, downtime, equipment damage, and significant economic losses.

[0003] Therefore, evaluating various defects on wafers is a crucial step, including edge chipping, scratches, graininess, chemical contamination, and missing parts. Manual inspection has significant limitations. First, manual judgment consumes substantial human resources. Second, it is subjective, and the inspector's condition can influence the results. Finally, the precision of the human eye cannot match that of a camera, leading to some missed defects. Therefore, an accurate, stable, and efficient method is needed to address wafer surface defect detection, improve quality control, and provide direction and suggestions for improvement in upstream processes. Summary of the Invention

[0004] In view of this, the present disclosure aims to provide a method, apparatus and system for detecting wafer surface defects; capable of accurately identifying wafer surface defects.

[0005] The technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, this disclosure provides a method for detecting defects on the surface of a wafer, comprising:

[0007] Acquire multiple images of the wafer to be tested;

[0008] For each wafer image to be tested, multiple first connected domains of surface defects in each wafer image to be tested are obtained;

[0009] The corresponding second connected component is obtained by morphologically expanding each first connected component.

[0010] The defect region to be tested is formed based on the first connected region corresponding to the second connected region;

[0011] The defect category is identified based on the defect area to be tested.

[0012] In some examples, obtaining the corresponding second connected component by morphologically dilating each first connected component includes:

[0013] Morphological dilation is performed on each first connected component to obtain the corresponding dilated first connected component.

[0014] When any expanded first connected component is not connected to other expanded first connected components or has overlapping pixels, the any expanded first connected component is determined to be the second connected component corresponding to the any unexpanded first connected component.

[0015] When any expanded first connected component is connected to or has overlapping pixels with other expanded first connected components, the expanded first connected component and other expanded first connected components connected to or have overlapping pixels with the expanded first connected component are merged to obtain a merged connected component; wherein, the merged connected component is a second connected component corresponding to the first connected component before expansion.

[0016] In some examples, forming the defect region to be tested based on the first connected component corresponding to the second connected component includes:

[0017] When a single second connected component corresponds to a single first connected component, the single first connected component is considered as a defect region to be tested.

[0018] When a single second connected component corresponds to at least two first connected components, the at least two first connected components are considered as a defect region to be tested.

[0019] Secondly, this disclosure provides a wafer surface defect detection device, including an image acquisition section, a first extraction section, a second extraction section, a determination section, and an identification section, wherein...

[0020] The image acquisition section is configured to acquire multiple images of the wafer under test.

[0021] The first extraction part is configured to: for each wafer image to be tested, obtain multiple first connected domains of surface defects in each wafer image to be tested;

[0022] The second extraction part is configured to: obtain the corresponding second connected component by performing morphological dilation on each first connected component;

[0023] The determining part is configured to: form the defect region to be tested based on the first connected region corresponding to the second connected region;

[0024] The identification component is configured to identify the defect category based on the defect area to be tested.

[0025] Thirdly, this disclosure provides a computer storage medium that stores a wafer surface defect detection program, which, when executed by at least one processor, implements the wafer surface defect detection method and steps described in the first aspect.

[0026] Fourthly, this disclosure provides a wafer surface defect detection system, the system comprising:

[0027] The first linear array camera is configured to be located above the edge of the wafer under test and to acquire an image of the wafer under test by scanning the wafer one or more times.

[0028] The first light source is configured to illuminate the edge portion of the upper surface of the wafer under test when the first linear array camera acquires an image of the first wafer under test.

[0029] The second linear array camera is configured to be located below the edge of the wafer under test and to acquire images of the second wafer under test by scanning the wafer under test once or multiple times.

[0030] The second light source is configured to illuminate the edge portion of the lower surface of the wafer under test when the second linear scan camera acquires an image of the second wafer under test.

[0031] The third linear array camera is configured to be located diagonally above the edge of the wafer under test, and to acquire the upper side surface of the wafer under test by scanning the wafer under test once or multiple times to obtain the third image of the wafer under test.

[0032] The fourth linear array camera is configured to be located diagonally below the edge of the wafer under test, and to acquire the image of the fourth wafer under test by scanning the wafer under test once or multiple times.

[0033] The third light source is configured as a C-type light source, which illuminates the side portion of the wafer under test when the third linear array camera acquires the image of the third wafer under test and / or the fourth linear array camera acquires the image of the fourth wafer under test.

[0034] The support component is configured to support and rotate the wafer under test when acquiring an image of the wafer under test.

[0035] A computing device is configured to, when executed, implement the method and steps for detecting wafer surface defects as described in the first aspect.

[0036] This disclosure provides a method, apparatus, and system for detecting surface defects; the final defect region to be tested is determined based on the relationship between the connected regions of surface defects before and after expansion in the surface of the wafer image; the defect category is identified based on the finally determined defect region to be tested, which can merge and identify multiple connected regions belonging to one defect, avoid feature value calculation errors caused by expansion operation, and improve the defect identification accuracy. Attached Figure Description

[0037] Figure 1 This is a schematic diagram illustrating the implementation environment of a wafer surface defect detection method provided in this disclosure;

[0038] Figure 2 This is a schematic diagram of a wafer surface defect detection method provided in this disclosure;

[0039] Figure 3 This is a schematic diagram of a wafer side view provided in this disclosure;

[0040] Figure 4 This disclosure provides a schematic diagram of a wafer edge defect detection system;

[0041] Figure 5 This disclosure provides a schematic diagram of a wafer edge image acquired through acquisition;

[0042] Figure 6 This disclosure provides a schematic diagram of the first connected region of a wafer under test;

[0043] Figure 7 This disclosure provides a schematic diagram of the second connected region of a wafer under test;

[0044] Figure 8 This disclosure provides a schematic diagram of the defect region to be tested on a wafer under test;

[0045] Figure 9 This is a schematic diagram of a defect category identification process for a wafer under test provided in this disclosure;

[0046] Figure 10 This is a schematic diagram of a defect category determination process provided in this disclosure;

[0047] Figure 11 This is a schematic diagram of a wafer surface defect detection device provided in this disclosure;

[0048] Figure 12 This is a schematic diagram of a wafer quality assessment method provided in this disclosure. Detailed Implementation

[0049] The terms "first" and "second" in this disclosure are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0050] The terms "upper," "lower," "left," and "right" used in the embodiments of the invention indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0051] To more clearly illustrate the technical solutions in this disclosure or the prior art, the technical solutions in this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0052] See Figure 1 This illustration shows a schematic diagram of the implementation environment for the wafer surface defect detection method provided in this disclosure. Figure 1 In this process, the wafer W to be tested is placed flat on the support component 40, and the light source 20 emits a light beam towards the wafer W. The scanning camera 10 collects the reflected or scattered light rays passing through the surface of the wafer W, generates an image of the wafer W, and transmits it to the computing device 30. The computing device 30 can execute the technical solution of this disclosure based on the received wafer image, thereby identifying the surface defect type of the wafer.

[0053] It should be noted that, Figure 1 The implementation environment shown is for illustrative purposes only and is not intended to limit the scope of the invention. It is understood that those skilled in the art can acquire surface images of the wafer W under test through other methods or systems, which will not be elaborated upon in this disclosure.

[0054] See Figure 2 This disclosure illustrates a method for detecting wafer surface defects, which can be performed by... Figure 1 The computing device 30 shown executes the method, which may include:

[0055] S201: Acquire multiple images of the wafers to be tested;

[0056] When using optical methods to detect defects on the surface of a wafer, a light source emits detection light rays that illuminate the wafer surface at a specific angle outside the wafer. A scanning camera then detects the detection light rays scattered or reflected by the defects at that specific angle to acquire an image of the wafer surface under test.

[0057] Optionally, the scanning camera can be an area scan camera or a line scan camera.

[0058] Optionally, the image of the wafer under test can be an image of the entire wafer simultaneously acquired by one or more scanning cameras; or an image of different areas of the wafer simultaneously acquired by multiple scanning cameras to obtain multiple images of different areas of the wafer under test; or an image of different areas of the wafer acquired by multiple scanning cameras and then stitched together to form a complete image of the wafer under test; or an image of the wafer under test can be obtained by a single scanning camera scanning the wafer multiple times to acquire images of different areas of the wafer under test; or an image of partial areas of the wafer under test can be obtained by a single scanning camera scanning multiple times and then stitched together to obtain a complete image of the wafer under test.

[0059] Optionally, when scanning the surface of the wafer under test with a scanning camera, it can be done by fixing the scanning camera and moving the wafer under test, or by moving the scanning camera and fixing the wafer under test.

[0060] Optionally, the image of the wafer under test obtained by the scanning camera can be either a front image or a back image. The scanning camera scanning the front of the wafer and the scanning camera scanning the back can be the same set of cameras, or multiple sets of cameras can be used to complete the scanning. When acquiring front and back images of the wafer under test using the same set of cameras, this can be achieved by adjusting the positions of the camera and the light source while fixing the position of the wafer under test, or by fixing the positions of the scanning camera and the light source while adjusting the orientation of the wafer under test, or by simultaneously adjusting the scanning camera, the light source, and the wafer under test.

[0061] Edge chipping and cracking defects on wafer edges can even lead to fragmentation during subsequent production processes, damaging production equipment. Furthermore, edge chipping and cracking defects can tend to spread into the wafer interior, severely impacting the manufacturing process. Therefore, edge defects on wafers have become an essential inspection item.

[0062] Optionally, during the relative movement of the line scan camera and the wafer under test along the edge direction of the wafer under test, multiple edge images of the wafer under test are obtained by scanning multiple times with one line scan camera or by scanning different regions of the edge of the wafer under test simultaneously with multiple line scan cameras, which serve as multiple wafer under test images.

[0063] It should be noted that in some examples, a linear scan camera is mounted on one side of the wafer. As the wafer rotates one revolution, the camera acquires a long, strip-shaped optical image of the wafer's edge. Because the wafer's side surface is curved, the image cannot be fully focused, resulting in blurry areas and hindering accurate defect detection and classification. In some examples, when acquiring the edge image of the wafer under test, this disclosure divides the edge structure of the wafer into four near-planar parts, and focuses and scans each of the four planes separately to obtain a clear image. For example... Figure 3 In the schematic diagram of the side surface of the wafer under test shown, the surface of the wafer W is divided into four parts: upper surface, lower surface, upper side surface, and lower side surface. The surface in contact with the support member 40 is the lower surface of the wafer W, and the other surface opposite the lower surface is the upper surface. Figure 3 In the process, the width of the edge region on the upper and lower surfaces of the wafer under test W can be adjusted according to actual needs. The side surface of the wafer is a curved surface. To facilitate the focusing of the scanning camera, the curved side surface of the wafer under test is divided into two near-planar parts: the upper side surface and the lower side surface. The upper side surface and the lower side surface are scanned separately to obtain the side surface image of the wafer.

[0064] Optionally, multiple edge images of the wafer under test can be obtained by scanning different regions of the edge of the wafer under test multiple times using a single line scan camera or by scanning multiple line scan cameras simultaneously. This includes scanning the upper surface edge of the wafer under test to obtain a first edge image, scanning the lower surface edge of the wafer under test to obtain a second edge image, scanning the upper side surface of the wafer under test to obtain a third edge image, and scanning the lower side surface of the wafer under test to obtain a fourth edge image.

[0065] Specifically, in some examples, such as Figure 4 In the schematic diagram of a wafer edge defect detection system shown, a support component 40 rotates the wafer W under test one revolution, and four line scan cameras acquire complete images of the edge region of the wafer W under test. The first line scan camera 101 acquires the edge of the upper surface of the wafer W under test to obtain the first image of the wafer under test; the second line scan camera 102 acquires the edge of the lower surface of the wafer under test to obtain the second image of the wafer under test; the third line scan camera 103 acquires the upper side portion of the wafer under test to obtain the third image of the wafer under test; and the fourth line scan camera 104 acquires the lower side portion of the wafer under test to obtain the fourth image of the wafer under test.

[0066] By dividing the surface of the edge portion of the wafer W under test into four near-planar parts and acquiring images of the edge portion of the wafer W under test, the imaging blurring problem caused by the curved side surface is solved, the imaging quality of the wafer surface under test is improved, and thus the accuracy of identifying defects on the wafer surface under test is improved.

[0067] S202: For each wafer image to be tested, obtain multiple first connected domains of surface defects in each wafer image to be tested;

[0068] The acquired images of the wafer under test include images of the wafer region (the target area) and images of the background region formed by the surrounding environment. For example... Figure 5 The diagram shows a captured wafer edge image. The captured image of the wafer W under test includes a wafer region image and a background region image. It should be noted that a wafer notch is a small notch cut into the edge of the wafer to facilitate accurate positioning of the wafer or to identify the wafer. The boundary between the wafer region image and the background region image is not always perfectly aligned. Figure 5 The image shown approximates a straight line. Understandably, in a test wafer image containing wafer grooves, the boundary between the wafer region image and the background region image is a regular, concave arc curve towards the wafer region.

[0069] Optionally, for each wafer image under test, multiple first connected regions of surface defects in each wafer image under test are obtained, including:

[0070] For each wafer image to be tested, extract the region of interest.

[0071] Remove the background portion from the region of interest image to obtain a first wafer region image;

[0072] Identify and remove the wafer recess portion in the wafer region image to obtain the final wafer region image;

[0073] Multiple first connected domains of surface defects are obtained based on the final wafer region image.

[0074] It should be noted that in some scenarios, where defect detection is only performed on the wafer edge region, the acquired wafer region image will include not only the wafer edge region requiring defect detection, but also some non-edge regions that do not require defect detection. By cropping the region of interest (ROI), the image processing area can be reduced, removing unnecessary wafer regions and most of the background region, thus reducing the amount of data to be processed. For each wafer image under test, the cropped ROI image can include the wafer region of interest and some remaining background regions. Cropping the ROI reduces the amount of data required for subsequent processing, improving detection efficiency. Further removing background and wafer notch images from the ROI can further reduce the amount of data processed, preventing interference with defect identification in subsequent defect detection and improving the accuracy and efficiency of defect identification.

[0075] For each edge image of the wafer under test, the step of cropping the region of interest image for each wafer under test includes:

[0076] For each edge image of the wafer to be tested, a coordinate system is established with the direction of the relative motion as the vertical axis;

[0077] For each edge image of the wafer to be tested, a vertical grayscale projection function is constructed;

[0078] Based on the first derivative of the vertical grayscale projection function, the region of interest image is selected in the edge image of each wafer to be tested.

[0079] In detail, the image of the wafer under test acquired by the linear scan camera through relative motion along the edge of the wafer under test is as follows: Figure 5 As shown, in the horizontal axis direction, the edge of the wafer under test has a clear boundary with the background region. Understandably, the vertical grayscale function along the horizontal axis changes significantly at the boundary. For example, with... Figure 5 A Cartesian coordinate system is established using the bottom-left pixel of the image as the origin. The horizontal axis is the X-axis, and the vertical axis is the Y-axis. A vertical grayscale projection function is constructed by calculating the average grayscale value of the pixels in the vertical direction of the wafer image matrix, with the X-axis pixel index as the variable. The vertical grayscale projection function for the wafer image is shown in the following equation:

[0080]

[0081] in, c Represents the column coordinates of the image of the wafer under test. r This represents the row coordinates of the image of the wafer under test. Indicates the first c Liede r OK, n This represents the total number of rows of pixels in the image of the wafer under test. Indicates the first r Line number c The pixel grayscale value of the column.

[0082] The X-axis pixel position corresponding to the boundary between the wafer region and the background region is determined by calculating the extremum of the first derivative of the vertical grayscale projection function. However, in the actual acquired image of the wafer edge under test, the boundary between the wafer region and the background region is not strictly a straight line or perpendicular to the X-axis. This disclosure expands the position determined by the first derivative of the vertical grayscale projection function according to certain rules or requirements to obtain the region of interest.

[0083] Optionally, a region of interest image is selected from each edge image of the wafer under test based on the first derivative of the vertical grayscale projection function, including:

[0084] The column corresponding to the extreme value of the first derivative of the vertical grayscale projection function is taken as the central axis;

[0085] The column reached by the central axis extending a first width along the positive direction of the horizontal axis is the first column;

[0086] The column reached by extending the central axis to a second width along the negative direction of the horizontal axis is the second column;

[0087] The region between the first column and the second column in each edge image of the wafer under test is the region of interest image.

[0088] In detail, the second width, extending to the left with the column corresponding to the extreme value of the first derivative of the vertical grayscale projection function as the central axis, should take into account the width of the wafer notch. The first width, extending to the right, should be designed to encompass all wafer regions. Optionally, the values ​​of the first and second widths, referencing the first derivative of the vertical grayscale projection function, can be set according to actual requirements. For example, if the requirement is to detect all surface defects on the wafer under test, the second width can be set to include all wafer regions. Figure 5 In the image of the wafer edge shown, the entire left side represents the wafer region. The second width can be left unset; that is, the leftmost column of the image from the central axis to the wafer edge is the region of interest. If the requirement is only to detect defects in the edge region, the second width can be set to at least cover the width of the wafer notch. The first and second widths can also be set to be equal. By selecting the region of interest, the scope of image processing is reduced, the amount of data processed is decreased, and data processing efficiency is improved.

[0089] It should be noted that the extracted region of interest image will still contain some background image. Generally, threshold segmentation is used to segment the wafer region image and the background region image.

[0090] Optionally, removing the background portion from the region of interest image to obtain a first wafer region image includes:

[0091] The region of interest (ROI) image is binarized to obtain a binary image of the ROI.

[0092] Morphological opening and morphological closing operations are performed on the wafer portion in the binary image of the region of interest to obtain the first wafer region;

[0093] The image of the first wafer region in each edge image of the wafer to be tested is the first wafer region image.

[0094] It should be noted that the first wafer region, obtained by binarizing the region of interest image and performing morphological opening and closing operations, can filter out some small spots and fill in negligible holes and wafer groove areas. The image obtained by cropping the first wafer region from the original image of the wafer under test, based on the extent of the first wafer region, is the first wafer region image. During the process of obtaining the first wafer region image, morphological opening and closing operations are used to fill in wafer groove areas or parts of wafer groove areas.

[0095] Further, identifying and removing wafer recesses from the first wafer region image to obtain a final wafer region image includes:

[0096] By binarizing the image of the first wafer region, the wafer groove region is identified;

[0097] The final wafer region is obtained by subtracting the wafer recess region from the first wafer region.

[0098] The portion of each wafer image to be tested located within the final wafer region is the final wafer region image.

[0099] It should be noted that the grooves on a wafer have regular shapes, specific locations, and specific sizes. Based on the specific shape characteristics of the grooves, the morphological features of connected components in the binarized image of the first wafer region are analyzed to identify the wafer groove regions. The wafer groove regions are then subtracted from the first wafer region to obtain the final wafer region; the portion of each wafer image under test located within the final wafer region constitutes the final wafer region image. By removing the wafer grooves from the final wafer region image, the misclassification of wafer grooves as wafer surface defects is avoided when identifying defects based on the final wafer region, further improving the accuracy of wafer surface defect identification.

[0100] Optionally, multiple first connected domains of surface defects are obtained based on the final wafer region image, including:

[0101] For the final wafer region image, multiple first connected domains of surface defects are obtained by combining grayscale thresholding and edge detection.

[0102] Optionally, for the final wafer region image, multiple first connected components of surface defects are obtained by combining grayscale thresholding and edge detection, including:

[0103] The final wafer region image is binarized based on a grayscale threshold to obtain the first defect pixel;

[0104] The gradient image is obtained from the final wafer region image based on the edge detection operator, and the second defect pixel is obtained by filtering according to the gradient threshold.

[0105] Multiple first connected components are obtained based on the first defective pixel and the second defective pixel.

[0106] It should be noted that this disclosure uses a combination of grayscale thresholding and edge detection to filter defective pixels in the final wafer region image. Connectivity analysis is performed on the defective pixels to obtain multiple first connected components, and defect identification is performed based on these multiple first connected components. Based on the difference between the grayscale values ​​of pixels in the defective portion of the wafer surface and those in the normal portion, a reasonable grayscale threshold is set to binarize the final wafer region image, obtaining the first defective pixels. The acquisition of the first defective pixels can be achieved by setting a single grayscale threshold or by setting multiple grayscale thresholds and filtering the final wafer region image multiple times. For example, for defects with grayscale values ​​greater than those in the normal region, a first grayscale threshold is set, and pixels greater than the first grayscale threshold are the first defective pixels acquired in the first iteration. For defects with grayscale values ​​less than those in the normal region, a second grayscale threshold is set, and pixels less than the second grayscale threshold are the first defective pixels acquired in the second iteration. The two first defective pixels are then merged to form the first defective pixel. The grayscale threshold can also be set as an interval grayscale threshold using two grayscale values ​​to filter defective pixels.

[0107] Filtering defective pixels based on grayscale thresholds can lead to the omission of some defective pixels in detailed areas. This disclosure improves the accuracy of defective pixel filtering by processing the final wafer region image using an edge detection operator. The gradient image of the wafer region image is obtained based on the edge detection operator, and a second defective pixel is filtered out by setting a gradient threshold. The first and second defective pixels are then merged into a single defective pixel.

[0108] Specifically, the final wafer region image can be processed using the Sobel edge detector. The horizontal convolution template in the Sobel edge detection operator is... The vertical convolution template is .

[0109] It should be noted that the defect pixels obtained from the final wafer region image screening can be analyzed using connected component analysis to obtain one or more first connected components. Optionally, connected component analysis includes labeling the defect pixels using 4-neighborhoods or 8-neighborhoods. For example, as shown... Figure 6In the schematic diagram of the first connected region of the wafer under test shown, the region within boundary 60 is the final wafer region. The final wafer region within boundary 60 is divided into three first connected regions: the region within boundary 601, the region within boundary 602, and the region within boundary 603. For ease of description, the region within boundary 601 is called first connected region 601, the region within boundary 602 is called first connected region 602, and the region within boundary 603 is called first connected region 603.

[0110] S203: Morphologically expand each of the first connected components to obtain the corresponding second connected components;

[0111] Morphological dilation is based on the expansion of white or black regions in a binary image using a structuring element. It is generally used to fill holes, disconnected patterns, or smooth the edges of patterns. Due to image acquisition errors or errors in subsequent image processing, acquired images of the wafer under test may segment a defect into multiple connected components. This disclosure uses a dilation operation to identify multiple connected components belonging to a single defect, improving the accuracy of defect identification. The effectiveness of the dilation operation depends on the shape and size of the structuring element used.

[0112] Optionally, this disclosure uses a circle with radius R as the structuring element to perform a morphological expansion operation on each first connected region.

[0113] Optionally, a corresponding second connected component can be obtained by morphologically expanding each first connected component, including:

[0114] Morphological dilation is performed on each first connected component to obtain the corresponding dilated first connected component.

[0115] When any expanded first connected component is not connected to other expanded first connected components or has overlapping pixels, the any expanded first connected component is determined to be the second connected component corresponding to the any unexpanded first connected component.

[0116] When any expanded first connected component is connected to or has overlapping pixels with other expanded first connected components, the expanded first connected component and other expanded first connected components connected to or have overlapping pixels with the expanded first connected component are merged to obtain a merged connected component; wherein, the merged connected component is a second connected component corresponding to the first connected component before expansion.

[0117] For example, Figure 6In the schematic diagram of the first connected regions of the wafer under test, the first connected regions 601 and 602 are relatively close, and these two first connected regions may be images of two parts of the same defect. Combining the first connected regions 601 and 602 for defect identification yields higher accuracy. Since there are no other connected regions around the first connected region 603, defect identification is performed solely on the first connected region 603.

[0118] like Figure 7 In the schematic diagram of the second connected region of the wafer under test shown, the first connected region 601 expands to form the expanded first connected region 601, the first connected region 602 expands to form the expanded first connected region 602, and the first connected region 603 expands to form the expanded first connected region 603.

[0119] For the dilated first connected component 601, other dilated first connected components include dilated first connected components 602 and 603. Dilated first connected components 601 and 602 have partial pixel overlap. Dilated first connected components 601 and 602 merge to form... Figure 7 The second connected component 701 is the first connected component 601. The second connected component corresponding to the first connected component 601 is the second connected component 701. Similarly, the second connected component corresponding to the first connected component 602 is the second connected component 701. For the dilated first connected component 603, other dilated first connected components include the dilated first connected components 601 and 602. The dilated first connected component 603 is not connected to other dilated first connected components, and there are no overlapping pixels. The region of the dilated first connected component 603 is formed. Figure 7 The second connected component is 702. The second connected component corresponding to the first connected component 603 is the second connected component 702.

[0120] S204: The defect region to be tested is formed based on the first connected region corresponding to the second connected region.

[0121] The defect region to be tested is formed based on the first connected component corresponding to the second connected component, including:

[0122] When a single second connected component corresponds to a single first connected component, the single first connected component is considered as a defect region to be tested.

[0123] When a single second connected component corresponds to at least two first connected components, the at least two first connected components are considered as a defect region to be tested.

[0124] For example, such as Figure 8 In the schematic diagram of the defect region of the wafer under test shown, the connected region A-1 corresponds to Figure 6The first connected component is 601, and the connected component A-2 corresponds to... Figure 6 The first connected component 602 is formed after the expansion of the first connected components 601 and 602. Figure 7 The second connected component 701 in the diagram corresponds to... Figure 6 The first connected component 601 and the first connected component 602 are two connected components. Based on the relationship between the dilated connected components, connected component A-1 and connected component A-2 belong to two parts of a test defect region A. A-1 and A-2 in the test defect region A are not adjacent and have no overlapping pixel regions. Connected component B corresponds to... Figure 6 The first connected component 603. Because the first connected component 603 expands, it forms... Figure 7 The second connected component 702 corresponds to a first connected component 603. According to... Figure 6 The first connected region 603 forms a defect region B to be tested. The range of the defect region B to be tested is the same as the range of the first connected region 603.

[0125] It should be noted that, Figure 6 , Figure 7 and Figure 8 The descriptions “60”, “601”, “602”, “603”, “701”, “702”, “A”, “B”, “A-1”, and “A-2” in the examples are not intended to limit this disclosure. The shape of the connected domain or defective region can be arbitrary. Without departing from the scope of the technical solution of this disclosure, many possible variations and modifications can be made to the technical solution of this disclosure using the above-disclosed technical content, or equivalent embodiments with equivalent changes can be modified.

[0126] Optionally, in some examples, forming the defect region to be tested based on the first connected component corresponding to the second connected component includes:

[0127] Set a corresponding first tag in each of the plurality of first connected components;

[0128] Set the corresponding second tag for the second connected component;

[0129] When a single second connected component corresponds to a single first connected component, the single first connected component is considered as a defect region to be tested, including:

[0130] When a single second connected component corresponds to a single first connected component, the first label in the single first connected component is updated to the second label of the corresponding single second connected component, and the single first connected component after updating the label is determined as the corresponding defect region to be tested.

[0131] When a single second connected component corresponds to at least two first connected components, the at least two first connected components are considered as a defect region to be tested, including:

[0132] When a single second connected component corresponds to at least two first connected components, the first labels of the at least two first connected components are updated to the second labels of the corresponding single second connected component, and the at least two first connected components after updating the labels are determined as the corresponding defect regions to be tested.

[0133] It should be noted that in the above embodiments, the defect region to be tested is formed based on the first connected component corresponding to the second connected component by setting a marker. For example, for Figure 6 The first connected components shown are labeled 601, 602, and 603, respectively. After the dilation operation, as shown... Figure 7 As shown, the connected region consisting of the first connected region 601, the first connected region 602, and the pixels of the corresponding dilated region is labeled 701. The connected region consisting of the first connected region 603 and the corresponding dilated region is labeled 702. The labels of the first connected regions are updated to the labels of the second connected regions, that is, the label of the first connected region 601 is changed to label 701, the label of the first connected region 602 is changed to label 701, and the label of the first connected region 603 is updated to 702. After the labels of the first connected regions are updated to the labels of the second connected regions, the defect region to be tested is formed. Within the defect region to be tested, the defect region labeled 701 includes... Figure 8 The connected regions A-1 and A-2 are shown. The range of A-1 is the same as the range of the first connected region 601, and the range of A-2 is the same as the range of the first connected region 602. The defect region to be tested, marked 702, is the same as the range of connected region 603 within the first connected region.

[0134] S205: Identify the defect category based on the defect area to be tested.

[0135] Common defect types in wafers, such as edge chipping, scratches, and cracks, all exhibit specific morphological characteristics on the wafer surface. These morphological characteristics can be characterized using feature values ​​in an image. The feature values ​​for each defect region can include its area, aspect ratio, roundness, average grayscale value, length, width, orientation angle, minimum bounding rectangle fill rate, and minimum bounding circle fill rate.

[0136] If eigenvalue calculation is performed based on the second connected component, there is a problem of inaccurate eigenvalue calculation. For example, Figure 7In the second connected component shown, the second connected component 701 includes the first connected component 601 within the solid border and the expanded portion between the dashed border and the solid border. The grayscale value of the expanded portion is determined according to certain rules. When calculating the grayscale mean feature value of the second connected component 701, the introduction of the grayscale value of the expanded portion introduces a certain error into the calculation of the grayscale mean. Understandably, the calculation of other feature values ​​also involves errors.

[0137] This disclosure determines the final defect region to be tested based on the relationship between the connected regions of surface defects before and after expansion in the surface of the wafer image to be tested; based on the finally determined defect region to be tested, the defect category is identified, and multiple connected regions belonging to a single defect can be merged and identified, which can avoid feature value calculation errors caused by expansion operations and improve the defect identification accuracy.

[0138] Each defect region to be tested can contain multiple connected components. The defect category is identified for each region. When a defect region contains multiple connected components, feature calculations are performed by combining these components to identify the defect category. For example, Figure 8 In the schematic diagram of the defect area to be tested shown, the average gray value of the defect area to be tested, marked as A, is the average gray value of the pixels within the two connected domains A-1 and A-2, and the length of the defect area is the total length of A-1 and A-2, etc.

[0139] When determining the defect category based on the features of the defect region, this disclosure defines a series of features and feature value ranges that can determine the defect category as the defect category identification rules. For example, the morphological features of edge chipping defects in an image have corresponding feature value ranges such as area range, gray-level average range, defect aspect ratio range, and roundness range. These specific features and feature value ranges form the edge chipping defect identification rules. Similarly, the morphological features of scratch defects and crack defects also have corresponding feature value ranges such as area range, gray-level average range, defect aspect ratio range, and roundness range in an image, forming scratch defect identification rules and crack defect identification rules, respectively.

[0140] When identifying the defect category for a test defect area, in the example above, if the area, mean gray level, aspect ratio, and roundness of the test defect area all fall within the area range, mean gray level range, aspect ratio range, and roundness range corresponding to edge chipping defects, respectively, then the defect within the test defect area is confirmed as an edge chipping defect. If at least one of the feature values ​​of the test defect area's area, mean gray level, aspect ratio, and roundness does not fall within the corresponding area range, mean gray level range, aspect ratio range, and roundness range corresponding to edge chipping defects, then the defect within the test defect area is confirmed as not being an edge chipping defect.

[0141] like Figure 10The flowchart illustrating the defect category determination process uses edge chipping defects as an example. The area range of an edge chipping defect is defined by its upper and lower limits. Similarly, the grayscale mean range is defined by its upper and lower limits, as are its aspect ratio and roundness. The area, grayscale mean, aspect ratio, and roundness of the defect region are determined sequentially. If any of these features falls outside the range of edge chipping defect feature values, the determination of the edge chipping defect category ends.

[0142] Understandably, the aforementioned feature values ​​of the defect area to be tested can also be compared with the feature value ranges corresponding to the scratch defect identification rules and crack defect identification rules, respectively. If the aforementioned feature values ​​of the defect area to be tested fall within the feature value range corresponding to the scratch defect identification rules or crack defect identification rules, then the defect in the defect area to be tested is confirmed to be a scratch defect or a crack defect. Otherwise, it is confirmed that it is not a scratch or a crack.

[0143] Optionally, identifying the defect category based on the defect area to be tested includes:

[0144] For each defect area to be tested, the following judgments are made:

[0145] When the area, aspect ratio, roundness, and average gray value of each test defect region are all within the area, aspect ratio, roundness, and average gray value range corresponding to edge chipping defects, the defect category of each test defect region is determined to be an edge chipping defect.

[0146] When the area, aspect ratio, roundness, and average gray value of each test defect region are all within the area, aspect ratio, roundness, and average gray value range corresponding to crack defects, the defect category of each test defect region is determined to be a crack defect.

[0147] When the area, aspect ratio, roundness, and average grayscale value of each test defect region are all within the range of area, aspect ratio, roundness, and average grayscale value corresponding to scratch defects, the defect category of each test defect region is determined to be a scratch defect.

[0148] Optionally, when identifying defect categories for each defect region within the defect area to be tested, the categories can be identified sequentially based on their degree of influence. For example, ... Figure 9In the flowchart illustrating the defect category identification process, the order of defect category identification is as follows: chipped edge defects, crack defects, and scratch defects. Specifically, the process determines whether the current defect area to be tested is a chipped edge defect according to the chipped edge defect identification rules. If it is determined to be a chipped edge defect, the defect category identification process for the current defect area ends. If it cannot be confirmed as a chipped edge defect, the process continues to identify crack defects and scratch defects according to the corresponding defect identification rules.

[0149] Based on the same inventive concept as the aforementioned technical solution, see [link to inventive concept]. Figure 11 This disclosure illustrates a wafer surface defect detection device 110, comprising: an image acquisition unit 1101, a first extraction unit 1102, a second extraction unit 1103, a determination unit 1104, and an identification unit 1105; wherein,

[0150] The image acquisition section 1101 is configured to acquire multiple images of the wafer under test.

[0151] The first extraction part 1102 is configured to: for each wafer image to be tested, obtain multiple first connected regions of surface defects in each wafer image to be tested;

[0152] The second extraction part 1103 is configured to: obtain the corresponding second connected component by performing morphological dilation on each first connected component;

[0153] The determining part 1104 is configured to: form a defect region to be tested based on the first connected region corresponding to the second connected region;

[0154] The identification section 1105 is configured to identify the defect category based on the defect area to be tested.

[0155] It should be noted that for the specific implementation of the functions configured in each "part" of the above-mentioned device, please refer to the aforementioned... Figure 2 The implementation methods and examples of the corresponding steps in the wafer surface defect detection method shown are not described in detail here.

[0156] Based on the same concept as the aforementioned technical solution, this disclosure also provides a wafer quality assessment method, which, after the aforementioned wafer surface defect detection method, further includes: assessing the quality of the wafer under test based on the defect category.

[0157] Optionally, assessing the quality of the wafer under test based on the defect category includes:

[0158] If the number of defects in the wafer under test is greater than 0, and the defect category of the defect region under test includes edge chipping and / or crack defects, then the quality of the wafer under test is marked as failing.

[0159] Otherwise, the quality of the wafer under test is marked as passed.

[0160] In detail, such as Figure 12 In the schematic diagram of the wafer quality assessment method, after the wafer under test is inspected for defects using a wafer surface defect detection method, the number of identified defects is counted. If the number of defects is 0, the wafer under test is marked as passing. If the number of defects is greater than 0, it is determined whether the identified defect category includes edge chipping and / or cracking defects. If edge chipping and / or cracking defects are present, the wafer under test is marked as failing. If neither edge chipping nor cracking defects are present, the wafer under test is marked as passing.

[0161] Based on the same concept as the above technical solutions, this disclosure also provides a wafer surface defect detection system, such as... Figure 4 As shown, the system includes:

[0162] The first linear array camera 101 is configured to be located above the edge of the wafer under test and to acquire an image of the wafer under test by scanning the wafer under test once or multiple times.

[0163] The first light source 201 is configured to illuminate the edge portion of the upper surface of the wafer under test when the first linear array camera acquires the image of the first wafer under test.

[0164] The second linear array camera 102 is configured to be located below the edge of the wafer under test and to acquire images of the second wafer under test by scanning the wafer under test once or multiple times.

[0165] The second light source 202 is configured to illuminate the edge portion of the lower surface of the wafer under test when the second linear scan camera acquires an image of the second wafer under test.

[0166] The third linear array camera 103 is configured to be located obliquely above the edge of the wafer under test, and to acquire the upper side surface of the wafer under test by scanning the wafer under test once or multiple times to obtain a third image of the wafer under test.

[0167] The fourth linear array camera 104 is configured to be located diagonally below the edge of the wafer under test, and to acquire the lower side surface of the wafer under test by scanning the wafer under test once or multiple times to obtain the fourth image of the wafer under test.

[0168] The third light source 203 is configured as a C-type light source, which illuminates the side portion of the wafer under test when the third linear array camera acquires the image of the third wafer under test and / or the fourth linear array camera acquires the image of the fourth wafer under test;

[0169] The support component 40 is configured to support and rotate the wafer under test when acquiring an image of the wafer under test.

[0170] Computing device 30, configured to implement at runtime Figure 2 The method and steps for detecting defects on the wafer surface are shown.

[0171] In some examples, computing device 30 is used to perform the wafer surface defect detection method and steps in the wafer surface defect detection method described above, which will not be repeated here.

[0172] In some examples, computing device 30 can be at least one of devices such as smartphones, smartwatches, desktop computers, laptops, virtual reality terminals, augmented reality terminals, wireless terminals, and laptop computers. Computing device 30 has communication capabilities and can access wired or wireless networks. Computing device 30 can refer to one of multiple terminals; those skilled in the art will understand that the number of such terminals can be more or less. In some examples, computing device 30 can receive wafer images transmitted by scanning camera 20 based on the accessed wired or wireless network. It is understood that computing device 30 undertakes the calculation and processing work after acquiring the wafer image in the technical solution of this disclosure, and this disclosure does not limit this aspect.

[0173] The computing device described in this application may include one or more of the following components: a processor and a memory.

[0174] Optionally, the processor connects various parts of the computing device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in memory, and by calling data stored in memory. Optionally, the processor can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor can integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content displayed on the touch screen; the NPU implements Artificial Intelligence (AI) functions; and the baseband chip handles wireless communication. It is understood that the baseband chip can also be implemented as a separate chip without being integrated into the processor.

[0175] The memory may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory may include non-transitory computer-readable storage medium. The memory may be used to store instructions, programs, code, code sets, or instruction sets. The memory may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch functionality, sound playback functionality, image playback functionality, etc.), instructions for implementing the various method embodiments described below, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0176] In addition, those skilled in the art will understand that the structure of the computing device described above does not constitute a limitation on the computing device. The computing device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements. For example, the computing device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.

[0177] This disclosure provides a computer storage medium storing a method program for detecting wafer surface defects, wherein the method program for detecting wafer surface defects, when executed by at least one processor, implements the steps of the wafer surface defect detection method described above.

[0178] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform the wafer surface defect detection method described in the above embodiments.

[0179] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0180] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0181] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method of detecting defects on a wafer surface, characterized by, The method comprises: obtaining a plurality of wafer images to be tested; for each wafer image to be tested, obtaining a plurality of first connected domains of surface defects in the wafer image to be tested; obtaining a corresponding second connected domain by morphological dilation on each first connected domain; forming a defect area to be tested according to the first connected domain corresponding to the second connected domain; identifying a defect category based on the defect area to be tested; wherein the second connected domain corresponding to each first connected domain is obtained by morphological dilation on each first connected domain, comprising: morphologically dilating each first connected domain to obtain a corresponding dilated first connected domain; when any dilated first connected domain does not connect with other dilated first connected domains or has overlapping pixels, determining that the any dilated first connected domain is a second connected domain corresponding to any first connected domain before dilation; when any dilated first connected domain connects with other dilated first connected domains or has overlapping pixels, merging the any dilated first connected domain and other dilated first connected domains connected with or having overlapping pixels with the any dilated first connected domain to obtain a merged connected domain; wherein the merged connected domain is a second connected domain corresponding to any first connected domain before dilation; the defect area to be tested is formed according to the first connected domain corresponding to the second connected domain, comprising: when a single second connected domain corresponds to a single first connected domain, the single first connected domain is taken as a defect area to be tested; when a single second connected domain corresponds to at least two first connected domains, the at least two first connected domains are taken as a defect area to be tested.

2. The method of claim 1, wherein, the plurality of wafer images to be tested are obtained, comprising: during relative movement of a linear array camera and a wafer to be tested along an edge direction of the wafer to be tested, a plurality of wafer edge images are obtained by multiple scanning of the wafer edge by a linear array camera or simultaneous scanning of different regions of the wafer edge by multiple linear array cameras, as a plurality of wafer images to be tested.

3. The method of claim 2, wherein, for each wafer image to be tested, a plurality of first connected domains of surface defects in the wafer image to be tested are obtained, comprising: for each wafer image to be tested, a region of interest image is intercepted; a background part in the region of interest image is removed to obtain a first wafer region image; a wafer groove part in the first wafer region image is identified and removed to obtain a final wafer region image; a plurality of first connected domains of surface defects are obtained based on the final wafer region image.

4. The method of claim 3, wherein, for each wafer edge image, the region of interest image is intercepted for each wafer image to be tested, comprising: for each wafer edge image, a coordinate system is established with the direction of relative movement as a vertical axis; a vertical gray value projection function is constructed for each wafer edge image; a region of interest image is selected in each wafer edge image based on the first derivative of the vertical gray value projection function.

5. The method of claim 4, wherein, the plurality of first connected domains of surface defects are obtained based on the final wafer region image, comprising: a first defect pixel is obtained by binaryzation processing of the final wafer region image based on a defect threshold value; obtaining a gradient image based on the edge detection operator on the final wafer region image, and obtaining second defect pixels by screening according to a gradient threshold value; obtaining a plurality of first connected domains based on the first defect pixels and the second defect pixels.

6. The method of claim 1, wherein, The method further includes: For each of the defect regions to be detected, the following judgment is performed: When the area, aspect ratio, circularity and mean gray value of each of the defect regions to be detected are within the area range, aspect ratio range, circularity range and mean gray value range corresponding to the edge collapse defect, it is determined that the defect category of each of the defect regions to be detected is the edge collapse defect; When the area, aspect ratio, circularity and mean gray value of each of the defect regions to be detected are within the area range, aspect ratio range, circularity range and mean gray value range corresponding to the crack defect, it is determined that the defect category of each of the defect regions to be detected is the crack defect; When the area, aspect ratio, circularity and mean gray value of each of the defect regions to be detected are within the area range, aspect ratio range, circularity range and mean gray value range corresponding to the scratch defect, it is determined that the defect category of each of the defect regions to be detected is the scratch defect.

7. A device for detecting wafer surface defects, the device comprising an image acquisition part, a first extraction part, a second extraction part, a determination part, and an identification part, wherein: the image acquisition part is configured to acquire a plurality of wafer images to be detected; the first extraction part is configured to, for each of the wafer images to be detected, acquire a plurality of first connected domains of surface defects in the wafer image to be detected; the second extraction part is configured to obtain a corresponding second connected domain by performing morphological dilation on each of the first connected domains; the determination part is configured to form a defect region to be detected according to the first connected domain corresponding to the second connected domain; the identification part is configured to identify a defect category based on the defect region to be detected; the second extraction part is further configured to perform morphological dilation on each of the first connected domains to obtain a corresponding dilated first connected domain; when any dilated first connected domain does not interface with other dilated first connected domains or has overlapping pixels, it is determined that the any dilated first connected domain is a second connected domain corresponding to any undilated first connected domain; when any dilated first connected domain interfaces with other dilated first connected domains or has overlapping pixels, the any dilated first connected domain and other dilated first connected domains that interface with or have overlapping pixels with the any dilated first connected domain are merged to obtain a merged connected domain; wherein the merged connected domain is a second connected domain corresponding to any undilated first connected domain; the determination part is further configured to: when a single second connected domain corresponds to a single first connected domain, the single first connected domain is taken as a defect region to be detected; when a single second connected domain corresponds to at least two first connected domains, the at least two first connected domains are taken as a defect region to be detected.

8. A system for detecting defects on a wafer surface, comprising: The system comprises: The first linear array camera is configured to be located above the edge of the wafer to be measured, and to collect a first wafer image to be measured by scanning the wafer to be measured one or more times. The first light source is configured to irradiate the edge portion of the upper surface of the wafer to be measured when the first linear array camera collects the first wafer image to be measured. The second linear array camera is configured to be located below the edge of the wafer to be measured, and to collect a second wafer image to be measured by scanning the wafer to be measured one or more times. The second light source is configured to irradiate the edge portion of the lower surface of the wafer to be measured when the second linear array camera collects the second wafer image to be measured. The third linear array camera is configured to be located obliquely above the edge of the wafer to be measured, and to collect a third wafer image to be measured by scanning the wafer to be measured one or more times to obtain the upper side of the wafer to be measured. The fourth linear array camera is configured to be located obliquely below the edge of the wafer to be measured, and to collect a fourth wafer image to be measured by scanning the wafer to be measured one or more times to obtain the lower side of the wafer to be measured. The third light source is configured to be a C-shaped light source, and to irradiate the side portion of the wafer to be measured when the third linear array camera collects the third wafer image to be measured and / or the fourth linear array camera collects the fourth wafer image to be measured. The support component is configured to support and rotate the wafer to be measured when collecting the image of the wafer to be measured. The computing device is configured to implement the method and steps of claim 1 to 6 for detecting the wafer surface defects.

Images