A high power factor soft-switching bridgeless Buck-Boost PFC converter and its modulation method

Abstract

This invention discloses a high power factor soft-switching bridgeless Buck-Boost PFC converter and its modulation method. The converter consists of eight switching transistors, an energy transfer inductor, and an output filter capacitor. The circuit structure is simple, combining the high efficiency of a bridgeless power factor correction converter with the wide output voltage range of a four-switch Buck-Boost circuit. Furthermore, this converter enables soft switching with relatively low voltage stress on the switching transistors. Four modulation strategies with varying loss levels are provided. Within one power frequency cycle, as the input voltage and converter operating conditions change, the converter control can switch to the modulation strategy with the lowest converter loss, allowing the converter to operate under optimal modulation.

Description

Technical Field

[0001] This invention relates to power electronic circuit technology, specifically to a high power factor soft-switching bridgeless Buck-Boost PFC converter and its modulation method. Background Technology

[0002] In recent years, in order to reduce harmonic pollution of the power grid by power electronic equipment, some countries and international academic organizations have proposed a series of current harmonic requirements and standards. To meet these requirements and standards, AC input power electronic converters need to employ power factor correction technology to improve the power factor of electrical equipment, thereby reducing the harmonic content of the power grid and ensuring its safe and reliable operation.

[0003] Traditional PFC converters are typically boost-type PFC converters, which have excessively high output voltages. In most cases, a cascaded DC-DC converter is needed to achieve voltage reduction, which increases hardware costs and control complexity. Unlike boost-type PFC converters, four-switch buck-boost PFC converters can achieve a wide voltage output range. They use a diode rectifier bridge on the AC side to rectify the mains frequency sinusoidal AC power into a unidirectional pulsating DC voltage. However, due to the large forward voltage drop of the diodes, when the converter output power is high, the current flowing through the diode rectifier bridge will generate significant conduction losses, affecting the converter efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a high power factor soft-switching bridgeless Buck-Boost PFC converter and its modulation method.

[0005] The technical solution to achieve the purpose of this invention is: a high power factor soft-switching bridgeless Buck-Boost PFC converter, comprising eight switching transistors Q1 to Q8, an energy transfer inductor L, and an output filter capacitor C. oThe source of the first switch Q1 is connected to the drain of the second switch Q2; the drain of the third switch Q3 is connected to the source of the fourth switch Q4; the source of the second switch Q2 is connected to the source of the third switch Q3; the drain of the fifth switch Q5 is connected to the drain of the sixth switch Q6; the source of the fifth switch Q5 is connected to the source of the first switch Q1 and the drain of the second switch Q2; the source of the sixth switch Q6 is connected to the drain of the third switch Q3 and the source of the fourth switch Q4; and the drain of the first switch Q1 is connected to the AC input voltage. One end, defined as end a, connects the drain of the fourth switch Q4 to the AC input voltage. The other end, defined as end b, connects the source of the seventh switch Q7 to the drain of the eighth switch Q8. One end of the energy transfer inductor L connects to the drains of the fifth switch Q5 and the sixth switch Q6, while the other end connects to the source of the seventh switch Q7 and the drain of the eighth switch Q8. The source of the eighth switch Q8 connects to the sources of the second switch Q2 and the third switch Q3. The drain of the seventh switch Q7 is connected to the output filter capacitor C. o The positive terminal of the transistor Q8 is connected to the source of the output filter capacitor C. o The negative end.

[0006] A modulation method for the aforementioned high power factor soft-switching bridgeless Buck-Boost PFC converter is as follows:

[0007] When the AC input voltage v in When the voltage at terminal a of the converter is greater than the voltage at terminal b, the drive signals of the first switch Q1 and the second switch Q2 are complementary and have a dead time. The third switch Q3, the fourth switch Q4 and the fifth switch Q5 are always on, the sixth switch Q6 is always off, and the drive signals of the seventh switch Q7 and the eighth switch Q8 are complementary and have a dead time.

[0008] When the AC input voltage v in When the voltage is less than 0, i.e., when the voltage at terminal a of the converter is less than the voltage at terminal b, the first switch Q1, the second switch Q2, and the sixth switch Q6 are always on, the drive signals of the third switch Q3 and the fourth switch Q4 are complementary and have a dead time, the fifth switch Q5 is always off, and the drive signals of the seventh switch Q7 and the eighth switch Q8 are complementary and have a dead time.

[0009] Compared with the prior art, the significant advantages of this invention are: 1) It eliminates the use of diode rectifier bridge, avoiding conduction losses caused by the forward voltage drop of rectifier diodes and improving the efficiency of the converter; 2) All switching transistors in the converter can achieve zero-voltage turn-on, which can further improve the efficiency of the converter; 3) The DC output voltage of the converter can be higher than or lower than the peak value of the AC input voltage, that is, it realizes the buck-boost output function and is also suitable for applications with a wide range of output voltages. Attached Figure Description

[0010] Figure 1 This is the circuit topology diagram of the high power factor soft-switching bridgeless Buck-Boost PFC converter of the present invention.

[0011] Figure 2 In modulation strategy one (v in >0 and v in >V o The theoretical waveform diagram of the downconverter.

[0012] Figure 3 In modulation strategy one (v in >0 and v in <V o The theoretical waveform diagram of the downconverter.

[0013] Figure 4 In modulation strategy one (v in <0 and -v in >V o The theoretical waveform diagram of the downconverter.

[0014] Figure 5 In modulation strategy one (v in <0 and -v in <V o The theoretical waveform diagram of the downconverter.

[0015] Figure 6 In modulation strategy two (v in The theoretical waveform diagram of the converter under >0).

[0016] Figure 7 In modulation strategy two (v in Theoretical waveform diagram of the converter with <0).

[0017] Figure 8 In modulation strategy three (v in The theoretical waveform diagram of the converter under >0).

[0018] Figure 9 In modulation strategy three (v in Theoretical waveform diagram of the converter with <0).

[0019] Figure 10 In modulation strategy four (v in The theoretical waveform diagram of the converter under >0).

[0020] Figure 11 In modulation strategy four (v in Theoretical waveform diagram of the converter with <0).

[0021] Figure 12 This is a simulation waveform diagram of the input voltage and input current of the converter of the present invention.

[0022] Figure 13 The simulation waveform diagram shows the converter operating in the pseudo-quadrilateral discontinuous conduction mode of modulation strategy one.

[0023] Figure 14 The simulation waveform diagram shows the converter operating in the pseudo-quadrilateral critical conduction mode of modulation strategy 1.

[0024] Figure 15 The simulation waveform diagram shows the converter operating under modulation strategy two.

[0025] Figure 16 The simulation waveform diagram shows the converter operating under modulation strategy three.

[0026] Figure 17 The simulation waveform diagram shows the converter operating under modulation strategy four. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0028] The present invention discloses a topology for a high power factor soft-switching bridgeless Buck-Boost PFC converter as follows: Figure 1 As shown, it includes eight switching transistors Q1 to Q8, an energy transfer inductor L, and an output filter capacitor C. oThe source of the first switch Q1 is connected to the drain of the second switch Q2; the drain of the third switch Q3 is connected to the source of the fourth switch Q4; the source of the second switch Q2 is connected to the source of the third switch Q3; the drain of the fifth switch Q5 is connected to the drain of the sixth switch Q6; the source of the fifth switch Q5 is connected to the source of the first switch Q1 and the drain of the second switch Q2; the source of the sixth switch Q6 is connected to the drain of the third switch Q3 and the source of the fourth switch Q4; and the drain of the first switch Q1 is connected to the AC input voltage. One end, defined as end a, connects the drain of the fourth switch Q4 to the AC input voltage. The other end, defined as end b, connects the source of the seventh switch Q7 to the drain of the eighth switch Q8. One end of the energy transfer inductor L connects to the drains of the fifth switch Q5 and the sixth switch Q6, while the other end connects to the source of the seventh switch Q7 and the drain of the eighth switch Q8. The source of the eighth switch Q8 connects to the sources of the second switch Q2 and the third switch Q3. The drain of the seventh switch Q7 is connected to the output filter capacitor C. o The positive terminal of the transistor Q8 is connected to the source of the output filter capacitor C. o The negative end.

[0029] All switches in the converter consist of a unidirectional switch and a diode connected in reverse parallel. The switch can be a transistor, IGBT, or MOSFET. When the switch is a transistor or IGBT, the source of the switch corresponds to the emitter of the transistor or IGBT, the drain of the switch corresponds to the collector of the transistor or IGBT, the cathode of the diode is connected to the drain of the switch, and the anode of the diode is connected to the source of the switch. When the switch is a MOSFET, the source of the switch corresponds to the source of the MOSFET, the drain of the switch corresponds to the drain of the MOSFET, and the diode is the body diode of the MOSFET.

[0030] A modulation method for a high power factor soft-switching bridgeless Buck-Boost PFC converter is as follows: The on and off states of the switching transistors in the converter during one switching cycle are shown in Table 1. When the AC input voltage v... in When the voltage at terminal a of the converter is greater than the voltage at terminal b, the drive signals of the first switch Q1 and the second switch Q2 are complementary and have a dead time. The third switch Q3, the fourth switch Q4, and the fifth switch Q5 are always on, the sixth switch Q6 is always off, and the drive signals of the seventh switch Q7 and the eighth switch Q8 are complementary and have a dead time. When the AC input voltage v inWhen the voltage is less than 0, i.e., when the voltage at terminal a of the converter is less than the voltage at terminal b, the first switch Q1, the second switch Q2, and the sixth switch Q6 are always on, the drive signals of the third switch Q3 and the fourth switch Q4 are complementary and have a dead time, the fifth switch Q5 is always off, and the drive signals of the seventh switch Q7 and the eighth switch Q8 are complementary and have a dead time.

[0031] Table 1 Switch On / Off States

[0032]

[0033] Define the current in the energy transfer inductor L (or simply inductor current) as |v in The slope of | / L changes over time T1, and the inductor current changes at (|v) in |-V o The slope changes over time T2, and the inductor current changes over time -V. o The time for the slope of / L to change is T3, and the time for the inductor current to remain constant is T4 (T4 = T...). s -T1-T2-T3), dead time length is t dead Define three duty cycle variables D. x D y D z The absolute value of the minimum inductor current required to achieve zero-voltage turn-on of all switching transistors is defined as I. ZVS .

[0034] A modulation method for a high power factor soft-switching bridgeless Buck-Boost PFC converter is provided, offering four modulation strategies: modulation strategy one, modulation strategy two, modulation strategy three, and modulation strategy four.

[0035] (1) When the converter operates under a modulation strategy below;

[0036] Define the start time of a switching cycle as t0, and the time elapsed after t0 is (T1-t) dead The time after the specified time length is t1, and time t1 is t... dead The time after the specified time length is t2, and time t2 is the time elapsed after (T2-t). dead The time after the specified time length is t3, and t3 is the time elapsed after t. dead The time after the specified duration is t4. Time t4 is the time interval (T3-t). dead The time after the specified time length is t5. Time t5 is t... dead The time after the specified duration is t6, and time t6 is the time interval (T4-t). dead The time after the specified time length is t7. Time t7 elapses after t dead The time after the duration is t8;

[0037] (a) When v in When >0,

[0038] D x D y D z The values ​​are respectively the duty cycle of the first switch Q1, the duty cycle of the seventh switch Q7, and the difference between the turn-on time of the seventh switch Q7 and the turn-on time of the first switch Q1 (within one switching cycle, the first switch Q1 turns on first, and the seventh switch Q7 turns on later, i.e., D). z >0) and switching period T s The ratio of D; where D x = (T1+T2) / T s D y = (T2+T3) / T s D z =T1 / T s The converter operates sequentially in the following phases within one switching cycle:

[0039] (1a) Phase 1 of the work:

[0040] Before the start of the switching cycle at time t0, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8 are kept on, while the first switch Q1, the second switch Q2, the sixth switch Q6, and the seventh switch Q7 are kept off. At time t0, the junction capacitance voltage v of the first switch Q1... ds_Q1 When discharged to 0, the junction capacitance voltage v of the second switch Q2... ds_Q2 Charged to v in At this time, the first switch Q1 is turned on, achieving zero-voltage turn-on of the first switch Q1, maintaining the on state of the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8, and maintaining the off state of the second switch Q2, the sixth switch Q6, and the seventh switch Q7. The inductor current i L Linear increase; (1b) Working phase two:

[0041] At time t1, the eighth switch Q8 is turned off, while the first, third, fourth, and fifth switches Q1, Q3, Q4, and Q5 remain on, and the second, sixth, and seventh switches Q2, Q6, and Q7 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is discharged, while the junction capacitance of the eighth switch Q8 is charged; at time t2, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 When discharged to 0, the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged to V o ;

[0042] (1c) Phase Three of Work:

[0043] At time t2, the seventh switch Q7 is turned on, achieving zero-voltage turn-on of the seventh switch Q7. This maintains the on-state of the first switch Q1, third switch Q3, fourth switch Q4, and fifth switch Q5, while maintaining the off-state of the second switch Q2, sixth switch Q6, and eighth switch Q8. During this operating phase, if v in >V o Inductor current i L Linear increase; if v in <V o Inductor current i L Linear decrease;

[0044] (1d) Work Phase Four:

[0045] At time t3, the first switch Q1 is turned off, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7 are kept on, and the second switch Q2, the sixth switch Q6, and the eighth switch Q8 are kept off. The inductor current i L The junction capacitance of the first switching transistor Q1 is charged, while the junction capacitance of the second switching transistor Q2 is discharged; at time t4, the junction capacitance voltage v of the first switching transistor Q1 is... ds_Q1 Charged to v in The junction capacitance voltage v of the second switch Q2 ds_Q2 Discharged to 0;

[0046] (1e) Phase Five:

[0047] At time t4, the second switch Q2 is turned on, achieving zero-voltage turn-on of the second switch Q2. This maintains the on-state of the third switch Q3, fourth switch Q4, fifth switch Q5, and seventh switch Q7, while maintaining the off-state of the first switch Q1, sixth switch Q6, and eighth switch Q8. The inductor current i... L Linear decrease;

[0048] (1f) Work Phase Six:

[0049] At time t5, the seventh switch Q7 is turned off, while the second, third, fourth, and fifth switches Q2, Q3, Q4, and Q5 remain on, and the first, sixth, and eighth switches Q1, Q6, and Q8 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is charged, while the junction capacitance of the eighth switch Q8 is discharged; at time t6, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 Charged to V o The junction capacitance voltage v of the eighth switch Q8ds_Q8 Discharged to 0;

[0050] (1g) Working Phase Seven:

[0051] At time t6, the eighth switch Q8 is turned on, achieving zero-voltage turn-on of the eighth switch Q8. This maintains the on-state of the second, third, fourth, and fifth switches Q2, Q3, Q4, and Q5, while maintaining the off-state of the first, sixth, and seventh switches Q1 and Q6. The inductor current i... L Remain unchanged;

[0052] (1h) Work Phase Eight:

[0053] At time t7, the second switch Q2 is turned off, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8 are kept on, and the first switch Q1, the sixth switch Q6, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitance of the first switching transistor Q1 is discharged, while the junction capacitance of the second switching transistor Q2 is charged; at time t8, the junction capacitance voltage v of the first switching transistor Q1 is... ds_Q1 When discharged to 0, the junction capacitance voltage v of the second switch Q2... ds_Q2 Charged to v in ;

[0054] (ii) When v in When <0,

[0055] D x D y D z The values ​​are respectively the duty cycle of the fourth switch Q4, the duty cycle of the seventh switch Q7, and the difference between the turn-on time of Q7 and the turn-on time of Q4 (within one switching cycle, the fourth switch Q4 turns on first, and the seventh switch Q7 turns on later, i.e., D). z >0) and switching period T s The ratio of D; where D x = (T1+T2) / T s D y = (T2+T3) / T s D z =T1 / T s The converter operates sequentially in the following stages during one switching cycle: (1i) Stage 1:

[0056] Before the start of the switching cycle at time t0, the first switch Q1, the second switch Q2, the sixth switch Q6, and the eighth switch Q8 are kept on, while the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7 are kept off. At time t0, the junction capacitance voltage v of the third switch Q3... ds_Q3 Charged to -v in The junction capacitance voltage v of the fourth switch Q4 ds_Q4 The circuit is discharged to 0; at this time, the fourth switch Q4 is turned on, achieving zero-voltage turn-on of the fourth switch Q4, maintaining the on state of the first switch Q1, the second switch Q2, the sixth switch Q6, and the eighth switch Q8, and maintaining the off state of the third switch Q3, the fifth switch Q5, and the seventh switch Q7. The inductor current i L Linear increase; (1j) Working stage two:

[0057] At time t1, the eighth switch Q8 is turned off, while the first, second, fourth, and sixth switches Q1, Q2, Q4, and Q6 remain on, and the third, fifth, and seventh switches Q3, Q5, and Q7 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is discharged, while the junction capacitance of the eighth switch Q8 is charged; at time t2, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 When discharged to 0, the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged to V o ;

[0058] (1k) Phase Three of Work:

[0059] At time t2, the seventh switch Q7 is turned on, achieving zero-voltage turn-on of the seventh switch Q7. This maintains the on-state of the first switch Q1, second switch Q2, fourth switch Q4, and sixth switch Q6, while maintaining the off-state of the third switch Q3, fifth switch Q5, and eighth switch Q8. During this operating phase, if -v in >V o Inductor current i L Linear increase; if -v in <V o Inductor current i L Linear descent; (1l) Working phase four:

[0060] At time t3, the fourth switch Q4 is turned off, while the first, second, sixth, and seventh switches Q1, Q2, Q6, and Q7 remain on, and the third, fifth, and eighth switches Q3, Q5, and Q8 remain off. The inductor current i LThe junction capacitance of the third switch Q3 is discharged, while the junction capacitance of the fourth switch Q4 is charged; at time t4, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 When discharged to 0, the junction capacitance voltage v of the fourth switch Q4... ds_Q4 Charged to -v in ;

[0061] (1m) Working Phase Five:

[0062] At time t4, the third switch Q3 is turned on, achieving zero-voltage turn-on of the third switch Q3. This maintains the on-state of the first switch Q1, second switch Q2, sixth switch Q6, and seventh switch Q7, while maintaining the off-state of the fourth switch Q4, fifth switch Q5, and eighth switch Q8. The inductor current i L Linear decrease;

[0063] (1n) Phase Six of Work:

[0064] At time t5, the seventh switch Q7 is turned off, while the first, second, third, and sixth switches Q1, Q2, Q3, and Q6 remain on, and the fourth, fifth, and eighth switches Q4, Q5, and Q8 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is charged, while the junction capacitance of the eighth switch Q8 is discharged; at time t6, the junction capacitance voltage v of the seventh switch Q7 is controlled. ds_Q7 Charged to V o The junction capacitance voltage v of the eighth switch Q8 ds_Q8 Discharged to 0;

[0065] (1o) Work Phase Seven:

[0066] At time t6, the eighth switch Q8 is turned on, achieving zero-voltage turn-on of the eighth switch Q8. This maintains the on-state of the first switch Q1, second switch Q2, third switch Q3, and sixth switch Q6, while maintaining the off-state of the fourth switch Q4, fifth switch Q5, and seventh switch Q7. The inductor current i... L Remain unchanged;

[0067] (1p) Work Phase Eight:

[0068] At time t7, the third switch Q3 is turned off, while the first, second, sixth, and eighth switches Q1, Q2, Q6, and Q8 remain on, and the fourth, fifth, and seventh switches Q4, Q5, and Q7 remain off. The inductor current i LThe junction capacitance of the third switch Q3 is charged, while the junction capacitance of the fourth switch Q4 is discharged; at time t8, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 Charged to -v in The junction capacitance voltage v of the fourth switch Q4 ds_Q4 Discharged to 0;

[0069] The main waveforms of the converter operating under the modulation strategy are as follows: Figures 2-5 As shown, where Figure 2 It is v in >0 and v in >V o The main waveform at time, Figure 3 It is v in >0 and v in <V o The main waveform at time, Figure 4 It is v in <0 and -v in >V o The main waveform at time, Figure 5 It is v in <0 and -v in <V o The main waveform at that time.

[0070] v in When >0, there are eight working stages (1a) to (1h) within one switching cycle and v in When <0, the mode in which eight operating stages (1i) to (1p) exist within one switching cycle (i.e., T1>0, T2>0, T3>0, and T4>0) is named the Pseudo Quadrilateral Discontinuous Conduction Mode (PQDCM); v in When >0, there are six operating stages (1a) to (1f) within one switching cycle, and the operating stages (1g) and (1h) do not exist, and v in The mode in which there are six working stages (1i) to (1n) within one switching cycle when <0, and no working stages (1o) and (1p) (i.e., T1>0, T2>0, T3>0 and T4=0) is named Pseudo Quadrilateral Critical Conduction Mode (PQCRM).

[0071] When T4>0, the converter operates in pseudo-quadrilateral discontinuous conduction mode. The sampled output voltage is compared with the voltage reference value. The error signal, after passing through an error compensator, is multiplied by a sinusoidal quantity in phase with the mains frequency input voltage to obtain the reference input current i. inT1, T2, T3, and T4 can be solved according to the following calculation principles:

[0072] 1) The integral of the inductor voltage with respect to time is zero within one switching cycle;

[0073] 2) Control the inductor current i at time t0 L =-I zvs To ensure v in At time >0, the first switching transistor Q1 achieves zero-voltage turn-on and v in When the voltage is less than 0, the fourth switch Q4 achieves zero-voltage turn-on and controls v. in When the current is greater than 0, the average current flowing through the first switching transistor Q1 within one switching cycle is equal to the reference current i of the power frequency AC input current. in and v in When <0, the average current flowing through the fourth switch Q4 within one switching cycle is equal to the reference i of the power frequency AC input current. in ,

[0074] 3) When |v in | <V o At time t3, control the inductor current i L =I zvs To ensure v in At >0, the second switch Q2 achieves zero-voltage turn-on and v in When |v < 0, the third switch Q3 achieves zero-voltage turn-on. in |>V o At time t1, control the inductor current i L =I zvs This is to ensure that the seventh switch Q7 achieves zero-voltage turn-on;

[0075] 4) The sum of T1, T2, T3, and T4 is the switching period T. s .

[0076] When T4 = 0, the converter operates in pseudo-quadrilateral critical conduction mode. The sampled output voltage is compared with the voltage reference value. The error signal, after passing through an error compensator, is multiplied by a sinusoidal quantity in phase with the mains frequency input voltage to obtain the reference input current i. in T1, T2, and T3 can be solved according to the following calculation principles:

[0077] 1) The integral of the inductor voltage with respect to time is zero within one switching cycle;

[0078] 2) Controlling the inductor current i at time t0 L =-I zvs To ensure v in At time >0, the first switching transistor Q1 achieves zero-voltage turn-on and v inWhen the voltage is less than 0, the fourth switch Q4 achieves zero-voltage turn-on and controls v. in When the current is greater than 0, the average current flowing through the first switching transistor Q1 within one switching cycle is equal to the reference current i of the power frequency AC input current. in and v in When <0, the average current flowing through the fourth switch Q4 within one switching cycle is equal to the reference i of the power frequency AC input current. in ;

[0079] 3) The sum of T1, T2, and T3 is the switching period T. s .

[0080] (2) When the converter operates under modulation strategy two;

[0081] The prerequisite for the converter to operate under modulation strategy two is |v in |>V o Inductor current i L With |v in The time for the slope change of | / L is T1=0; the start time of a switching cycle is defined as t0, and the time after t0 is (T2-t dead The time after the specified time length is t1, and time t1 is t... dead The time after the specified time length is t2, and time t2 is (T3-t) dead The time after the specified time length is t3, and t3 is the time elapsed after t. dead The time after the specified duration is t4. Time t4 is the time interval (T4-t). dead The time after the specified time length is t5. Time t5 is t... dead The time after the specified duration is t6;

[0082] (a) When v in When >0,

[0083] D x D y D z The values ​​are respectively the duty cycle of the first switch Q1, the duty cycle of the seventh switch Q7, the time difference between the turn-on time of Q7 and the turn-on time of Q1, and the switching period T. s The ratio of D; where D x =T2 / T s D y = (T2+T3) / T s D z =0; The converter operates sequentially in the following phases within one switching cycle:

[0084] (2a) Phase 1 of the work:

[0085] Before the start of the switching cycle at time t0, the third switch Q3, the fourth switch Q4, and the fifth switch Q5 are kept on, while the first switch Q1, the second switch Q2, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8 are kept off. At time t0, the junction capacitance voltage v of the first switch Q1... ds_Q1 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 When the transistors are discharged to 0 sequentially or simultaneously, the junction capacitance voltage v of the second switching transistor Q2... ds_Q2 and the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged sequentially or simultaneously to v in and V o At this time, the first switch Q1 and the seventh switch Q7 are turned on, achieving zero-voltage turn-on of the first switch Q1 and the seventh switch Q7, maintaining the on state of the third switch Q3, the fourth switch Q4 and the fifth switch Q5, and maintaining the off state of the second switch Q2, the sixth switch Q6 and the eighth switch Q8. The inductor current i L Linear increase;

[0086] (2b) Phase Two of Work:

[0087] At time t1, the first switch Q1 is turned off, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the fifth switch Q7 are kept on, and the second switch Q2, the sixth switch Q6, and the eighth switch Q8 are kept off. The inductor current i L The junction capacitance of the first switching transistor Q1 is charged, while the junction capacitance of the second switching transistor Q2 is discharged; at time t2, the junction capacitance voltage v of the first switching transistor Q1 is... ds_Q1 Charged to v in The junction capacitance voltage v of the second switch Q2 ds_Q2 Discharged to 0;

[0088] (2c) Phase Three:

[0089] At time t2, the second switch Q2 is turned on, achieving zero-voltage turn-on of the second switch Q2; the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7 are maintained on, while the first switch Q1, the sixth switch Q6, and the eighth switch Q8 are maintained off. The inductor current i L Linear decrease;

[0090] (2d) Work Phase Four:

[0091] At time t3, the seventh switch Q7 is turned off, while the second, third, fourth, and fifth switches Q2, Q3, Q4, and Q5 remain on, and the first, sixth, and eighth switches Q1, Q6, and Q8 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is charged, while the junction capacitance of the eighth switch Q8 is discharged; at time t4, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 Charged to V o The junction capacitance voltage v of the eighth switch Q8 ds_Q8 Discharged to 0;

[0092] (2e) Phase Five:

[0093] At time t4, the eighth switch Q8 is turned on, achieving zero-voltage turn-on of the eighth switch Q8. This maintains the on-state of the second, third, fourth, and fifth switches Q2, Q3, Q4, and Q5, while maintaining the off-state of the first, sixth, and seventh switches Q1 and Q6. The inductor current i... L Remain unchanged;

[0094] (2f) Work Phase Six:

[0095] At time t5, the second switch Q2 and the eighth switch Q8 are turned off, the third switch Q3, the fourth switch Q4, and the fifth switch Q5 are kept on, and the first switch Q1, the sixth switch Q6, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitances of the first switch Q1 and the seventh switch Q7 are discharged, while the junction capacitances of the second switch Q2 and the eighth switch Q8 are charged; at time t6, the junction capacitance voltage v of the first switch Q1 is... ds_Q1 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 When the transistors are discharged to 0 sequentially or simultaneously, the junction capacitance voltage v of the second switching transistor Q2... ds_Q2 and the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged sequentially or simultaneously to v in and V o ;

[0096] (ii) When v in When <0,

[0097] D x D y D z The values ​​are respectively the duty cycle of the fourth switch Q4, the duty cycle of the seventh switch Q7, the time difference between the turn-on time of Q7 and the turn-on time of Q4, and the switching period T. s The ratio of D; where D x=T2 / T s D y = (T2+T3) / T s D z =0; The converter operates sequentially in the following phases within one switching cycle:

[0098] (2g) Phase One of the work:

[0099] Before the start of the switching cycle at time t0, the first switch Q1, the second switch Q2, and the sixth switch Q6 are kept on, while the third switch Q3, the fourth switch Q4, the fifth switch Q5, the seventh switch Q7, and the eighth switch Q8 are kept off. At time t0, the junction capacitance voltage v of the third switch Q3... ds_Q3 and the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged to -V sequentially or simultaneously in and V o The junction capacitance voltage v of the fourth switch Q4 ds_Q4 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 The transistors are discharged to 0 sequentially or simultaneously; at this time, the fourth switch Q4 and the seventh switch Q7 are turned on, achieving zero-voltage turn-on of the fourth switch Q4 and the seventh switch Q7, maintaining the on state of the first switch Q1, the second switch Q2, and the sixth switch Q6, and maintaining the off state of the third switch Q3, the fifth switch Q5, and the eighth switch Q8. The inductor current i L Linear increase;

[0100] (2h) Work Phase Two:

[0101] At time t1, the fourth switch Q4 is turned off, the first switch Q1, the second switch Q2, the sixth switch Q6, and the seventh switch Q7 are kept on, and the third switch Q3, the fifth switch Q5, and the eighth switch Q8 are kept off. The inductor current i L The junction capacitance of the third switch Q3 is discharged, while the junction capacitance of the fourth switch Q4 is charged; at time t2, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 When discharged to 0, the junction capacitance voltage v of the fourth switch Q4... ds_Q4 Charged to -v in ;

[0102] (2i) Phase Three:

[0103] At time t2, the third switch Q3 is turned on, achieving zero-voltage turn-on of the third switch Q3. This maintains the on-state of the first switch Q1, second switch Q2, sixth switch Q6, and seventh switch Q7, while maintaining the off-state of the fourth switch Q4, fifth switch Q5, and eighth switch Q8. The inductor current i L Linear decrease;

[0104] (2j) Phase Four:

[0105] At time t3, the seventh switch Q7 is turned off, while the first, second, third, and sixth switches Q1, Q2, Q3, and Q6 remain on, and the fourth, fifth, and eighth switches Q4, Q5, and Q8 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is charged, while the junction capacitance of the eighth switch Q8 is discharged; at time t4, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 Charged to V o The junction capacitance voltage v of the eighth switch Q8 ds_Q8 Discharged to 0;

[0106] (2k) Phase Five of the Work:

[0107] At time t4, the eighth switch Q8 is turned on, achieving zero-voltage turn-on of the eighth switch Q8. This maintains the on-state of the first switch Q1, second switch Q2, third switch Q3, and sixth switch Q6, while maintaining the off-state of the fourth switch Q4, fifth switch Q5, and seventh switch Q7. The inductor current i... L Remain unchanged;

[0108] (2l) Work Phase Six:

[0109] At time t5, the third switch Q3 and the eighth switch Q8 are turned off, the first switch Q1, the second switch Q2, and the sixth switch Q6 are kept on, and the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitances of the third switch Q3 and the eighth switch Q8 are charged, while the junction capacitances of the fourth switch Q4 and the seventh switch Q7 are discharged; at time t6, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 and the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged to -V sequentially or simultaneously in and V o The junction capacitance voltage v of the fourth switch Q4 ds_Q4 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 They are discharged to 0 successively or simultaneously;

[0110] The main waveforms of the converter operating under modulation strategy two are as follows: Figure 6 and Figure 7 As shown, where Figure 6 It is v in The main waveform when >0, Figure 7 It is v in The main waveform when <0.

[0111] The mode in which the converter operates under modulation strategy two is named PseudoTriangle Discontinuous Conduction Mode One (PTDCM1), and the prerequisite for executing modulation strategy two is |v in |>V o When modulation strategy two is executed, the sampled output voltage is compared with the voltage reference value. The error signal is processed by the error compensator, and the output is multiplied by a sinusoidal quantity in phase with the power frequency input voltage to obtain the reference value i of the input current. in T2, T3, and T4 can be solved according to the following calculation principles:

[0112] 1) The integral of the inductor voltage with respect to time is zero within one switching cycle;

[0113] 2) Controlling the inductor current i at time t0 L =-I zvs To ensure v in At time >0, the first switching transistor Q1 achieves zero-voltage turn-on and v in When the voltage is less than 0, the fourth switch Q4 achieves zero voltage and controls v. in When the current is greater than 0, the average current flowing through the first switching transistor Q1 within one switching cycle is equal to the reference current i of the power frequency AC input current. in and v in When <0, the average current flowing through the fourth switch Q4 within one switching cycle is equal to the reference i of the power frequency AC input current. in ;

[0114] 3) The sum of T2, T3, and T4 is the switching period T. s .

[0115] (3) When the converter operates under modulation strategy three;

[0116] Inductor current i L With (|v in |-V o The time for the slope change of ) / L is T2=0; the start time of a switching cycle is defined as t0, and the time after t0 is (T1-t) dead The time after the specified time length is t1, and time t1 is t... deadThe time after the specified time length is t2, and time t2 is (T3-t) dead The time after the specified time length is t3, and t3 is the time elapsed after t. dead The time after the specified duration is t4. Time t4 is the time interval (T4-t). dead The time after the specified time length is t5. Time t5 is t... dead The time after the specified duration is t6;

[0117] (a) When v in When >0,

[0118] D x D y D z The values ​​are respectively the duty cycle of the first switch Q1, the duty cycle of the seventh switch Q7, and the time difference between the turn-on time of Q7 and the turn-on time of Q1 (within one switching cycle, the first switch Q1 turns on first, and the seventh switch Q7 turns on later, i.e., D). z >0) and switching period T s The ratio of D; where D x =T1 / T s D y =T3 / T s D z =T1 / T s The converter operates sequentially in the following phases within one switching cycle:

[0119] (3a) Phase 1 of the work:

[0120] Before the start of the switching cycle at time t0, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8 are kept on, while the first switch Q1, the second switch Q2, the sixth switch Q6, and the seventh switch Q7 are kept off. At time t0, the junction capacitance voltage v of the first switch Q1... ds_Q1 When discharged to 0, the junction capacitance voltage v of the second switch Q2... ds_Q2 Charged to v in At this time, the first switch Q1 is turned on, achieving zero-voltage turn-on of the first switch Q1, maintaining the on state of the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8, and maintaining the off state of the second switch Q2, the sixth switch Q6, and the seventh switch Q7. The inductor current i L Linear increase; (3b) Working stage two:

[0121] At time t1, the first switch Q1 and the eighth switch Q8 are turned off, the third switch Q3, the fourth switch Q4, and the fifth switch Q5 are kept on, and the second switch Q2, the sixth switch Q6, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitances of the first switch Q1 and the eighth switch Q8 are charged, while the junction capacitances of the second switch Q2 and the seventh switch Q7 are discharged; at time t2, the junction capacitance voltage v of the first switch Q1 is... ds_Q1 and the junction capacitance voltage v of the eighth switch ds_Q8 Charged sequentially or simultaneously to v in and V o The junction capacitance voltage v of the second switch Q2 ds_Q2 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 They are discharged to 0 successively or simultaneously;

[0122] (3c) Work Phase Three:

[0123] At time t2, the second switch Q2 and the seventh switch Q7 are turned on, achieving zero-voltage turn-on for the second switch Q2 and the seventh switch Q7. The third switch Q3, the fourth switch Q4, and the fifth switch Q5 are maintained on, while the first switch Q1, the sixth switch Q6, and the eighth switch Q8 are maintained off. The inductor current i... L Linear decrease;

[0124] (3d) Phase Four of the Work:

[0125] At time t3, the seventh switch Q7 is turned off, while the second, third, fourth, and fifth switches Q2, Q3, Q4, and Q5 remain on, and the first, sixth, and eighth switches Q1, Q6, and Q8 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is charged, while the junction capacitance of the eighth switch Q8 is discharged; at time t4, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 Charged to V o The junction capacitance voltage v of the eighth switch Q8 ds_Q8 Discharged to 0;

[0126] (3e) Phase Five:

[0127] At time t4, the eighth switch Q8 is turned on, achieving zero-voltage turn-on of the eighth switch Q8. This maintains the on-state of the second, third, fourth, and fifth switches Q2, Q3, Q4, and Q5, while maintaining the off-state of the first, sixth, and seventh switches Q1 and Q6. The inductor current i... L Remain unchanged;

[0128] (3f) Work Phase Six:

[0129] At time t5, the second switch Q2 is turned off, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8 are kept on, and the first switch Q1, the sixth switch Q6, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitance of the first switching transistor Q1 is discharged, while the junction capacitance of the second switching transistor Q2 is charged; at time t6, the junction capacitance voltage v of the first switching transistor Q1 is... ds_Q1 When discharged to 0, the junction capacitance voltage v of the second switch Q2... ds_Q2 Charged to v in ;

[0130] (ii) When v in When <0,

[0131] D x D y D z The values ​​are respectively the duty cycle of the fourth switch Q4, the duty cycle of the seventh switch Q7, and the time difference between the turn-on time of Q7 and the turn-on time of Q4 (within one switching cycle, the fourth switch Q4 turns on first, and the seventh switch Q7 turns on later, i.e., D). z >0) and switching period T s The ratio of D; where D x =T1 / T s D y =T3 / T s D z =T1 / T s The converter operates sequentially in the following phases within one switching cycle:

[0132] (3g) Phase One of the work:

[0133] Before the start of the switching cycle at time t0, the first switch Q1, the second switch Q2, the sixth switch Q6, and the eighth switch Q8 are kept on, while the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7 are kept off. At time t0, the junction capacitance voltage v of the fourth switch Q4... ds_Q4 When discharged to 0, the junction capacitance voltage v of the third switch Q3... ds_Q3 Charged to -v in At this time, the fourth switch Q4 is turned on, achieving zero-voltage turn-on of the fourth switch Q4, maintaining the on state of the first switch Q1, the second switch Q2, the sixth switch Q6, and the eighth switch Q8, and maintaining the off state of the third switch Q3, the fifth switch Q5, and the seventh switch Q7. The inductor current i LLinear increase; (3h) Working phase two:

[0134] At time t1, the fourth switch Q4 and the eighth switch Q8 are turned off, the first switch Q1, the second switch Q2, and the sixth switch Q6 are kept on, and the third switch Q3, the fifth switch Q5, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitances of the fourth switch Q4 and the eighth switch Q8 are charged, while the junction capacitances of the third switch Q3 and the seventh switch Q7 are discharged; at time t2, the junction capacitance voltage v of the fourth switch Q4 is... ds_Q4 and the junction capacitance voltage v of the eighth switch ds_Q8 Charged to -V sequentially or simultaneously in and V o The junction capacitance voltage v of the third switch Q3 ds_Q3 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 They are discharged to 0 successively or simultaneously;

[0135] (3i) Phase Three of Work:

[0136] At time t2, the third switch Q3 and the seventh switch Q7 are turned on, achieving zero-voltage turn-on for the third switch Q3 and the seventh switch Q7. This maintains the on-state of the first switch Q1, the second switch Q2, and the sixth switch Q6, while maintaining the off-state of the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8. The inductor current i... L Linear decrease;

[0137] (3j) Phase Four of Work:

[0138] At time t3, the seventh switch Q7 is turned off, while the first, second, third, and sixth switches Q1, Q2, Q3, and Q6 remain on, and the fourth, fifth, and eighth switches Q4, Q5, and Q8 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is charged, while the junction capacitance of the eighth switch Q8 is discharged; at time t4, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 Charged to V o The junction capacitance voltage v of the eighth switch Q8 ds_Q8 Discharged to 0;

[0139] (3k) Phase Five of the Work:

[0140] At time t4, the eighth switch Q8 is turned on, achieving zero-voltage turn-on of the eighth switch Q8. This maintains the on-state of the first switch Q1, second switch Q2, third switch Q3, and sixth switch Q6, while maintaining the off-state of the fourth switch Q4, fifth switch Q5, and seventh switch Q7. The inductor current i... L Remain unchanged;

[0141] (3l) Work Phase Six:

[0142] At time t5, the third switch Q3 is turned off, while the first, second, sixth, and eighth switches Q1, Q2, Q6, and Q8 remain on, and the fourth, fifth, and seventh switches Q4, Q5, and Q7 remain off. The inductor current i L The junction capacitance of the third switch Q3 is charged, while the junction capacitance of the fourth switch Q4 is discharged; at time t6, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 Charged to -v in The junction capacitance voltage v of the fourth switch Q4 ds_Q4 Discharged to 0;

[0143] The main waveforms of the converter operating under modulation strategy three are as follows: Figure 8 and Figure 9 As shown, where Figure 8 It is v in The main waveform when >0, Figure 9 It is v in The main waveform when <0.

[0144] The mode in which the converter operates under modulation strategy three is named PseudoTriangle Discontinuous Conduction Mode Two (PTDCM2). When modulation strategy three is executed, the sampled output voltage is compared with the voltage reference value. The error signal is processed by the error compensator, and the output is multiplied by a sinusoidal quantity in phase with the mains frequency input voltage to obtain the reference value i of the input current. in The following calculation principles can be used to solve for T1, T3, and T4:

[0145] 1) The integral of the inductor voltage with respect to time is zero within one switching cycle;

[0146] 2) Controlling the inductor current i at time t0 L =-I zvs To ensure v in At time >0, the first switching transistor Q1 achieves zero-voltage turn-on and v in When the voltage is less than 0, the fourth switch Q4 achieves zero-voltage turn-on and controls v. inWhen the current is greater than 0, the average current flowing through the first switching transistor Q1 is equal to the reference current i of the power frequency AC input current. in and v in When the current is less than 0, the average current flowing through the fourth switch Q4 is equal to the reference current i of the power frequency AC input current. in ;

[0147] 3) The sum of T1, T3, and T4 is the switching period T. s .

[0148] (4) When the converter is operating under modulation strategy four;

[0149] The prerequisite for the converter to operate under modulation strategy four is |v in | <V o Inductor current i L With -V o The time for the slope change of / L is T3 = 0; the start time of a switching cycle is defined as t0, and the time after t0 is (T1 - t dead The time after the specified time length is t1, and time t1 is t... dead The time after the specified time length is t2, and time t2 is the time elapsed after (T2-t). dead The time after the specified time length is t3, and t3 is the time elapsed after t. dead The time after the specified duration is t4. Time t4 is the time interval (T4-t). dead The time after the specified time length is t5. Time t5 is t... dead The time after the specified duration is t6;

[0150] (a) When v in When >0,

[0151] D x D y D z The values ​​are respectively the duty cycle of the first switch Q1, the duty cycle of the seventh switch Q7, and the time difference between the turn-on time of Q7 and the turn-on time of Q1 (within one switching cycle, the first switch Q1 turns on first, and the seventh switch Q7 turns on later, i.e., D). z >0) and switching period T s The ratio of D; where D x = (T1+T2) / T s D y =T2 / T s D z =T1 / T s The converter operates sequentially in the following phases within one switching cycle:

[0152] (4a) Phase 1 of the work:

[0153] Before the start of the switching cycle at time t0, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8 are kept on, while the first switch Q1, the second switch Q2, the sixth switch Q6, and the seventh switch Q7 are kept off. At time t0, the junction capacitance voltage v of the first switch Q1... ds_Q1 When discharged to 0, the junction capacitance voltage v of the second switch Q2... ds_Q2 Charged to v in At this time, the first switch Q1 is turned on, achieving zero-voltage turn-on of the first switch Q1, maintaining the on state of the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8, and maintaining the off state of the second switch Q2, the sixth switch Q6, and the seventh switch Q7. The inductor current i L Linear increase; (4b) Working phase two:

[0154] At time t1, the eighth switch Q8 is turned off, while the first, third, fourth, and fifth switches Q1, Q3, Q4, and Q5 remain on, and the second, sixth, and seventh switches Q2, Q6, and Q7 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is discharged, while the junction capacitance of the eighth switch Q8 is charged; at time t2, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 When discharged to 0, the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged to V o ;

[0155] (4c) Phase Three of Work:

[0156] At time t2, the seventh switch Q7 is turned on, achieving zero-voltage turn-on of the seventh switch Q7. This maintains the on-state of the first switch Q1, third switch Q3, fourth switch Q4, and fifth switch Q5, while maintaining the off-state of the second switch Q2, sixth switch Q6, and eighth switch Q8. The inductor current i L Linear decrease;

[0157] (4d) Work Phase Four:

[0158] At time t3, the first switch Q1 and the seventh switch Q7 are turned off, the third switch Q3, the fourth switch Q4, and the fifth switch Q5 are kept on, and the second switch Q2, the sixth switch Q6, and the eighth switch Q8 are kept off. The inductor current i L The junction capacitances of the first switch Q1 and the seventh switch Q7 are charged, while the junction capacitances of the second switch Q2 and the eighth switch Q8 are discharged; at time t4, the junction capacitance voltage v of the first switch Q1 is... ds_Q1and the junction capacitance voltage v of the seventh switch transistor ds_Q7 Charged sequentially or simultaneously to v in and V o The junction capacitance voltage v of the second switch Q2 ds_Q2 and the junction capacitance voltage v of the eighth switch Q8 ds_Q8 They are discharged to 0 successively or simultaneously;

[0159] (4e) Phase Five:

[0160] At time t4, the second switch Q2 and the eighth switch Q8 are turned on, achieving zero-voltage turn-on for the second switch Q2 and the eighth switch Q8. The third switch Q3, the fourth switch Q4, and the fifth switch Q5 are maintained on, while the first switch Q1, the sixth switch Q6, and the seventh switch Q7 are maintained off. The inductor current i... L Remain unchanged;

[0161] (4f) Work Phase Six:

[0162] At time t5, the second switch Q2 is turned off, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8 are kept on, and the first switch Q1, the sixth switch Q6, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitance of the first switching transistor Q1 is discharged, while the junction capacitance of the second switching transistor Q2 is charged; at time t6, the junction capacitance voltage v of the first switching transistor Q1 is... ds_Q1 When discharged to 0, the junction capacitance voltage v of the second switch Q2... ds_Q2 Charged to v in ;

[0163] (ii) When v in When <0,

[0164] D x D y D z The values ​​are respectively the duty cycle of the fourth switch Q4, the duty cycle of the seventh switch Q7, and the time difference between the turn-on time of Q7 and the turn-on time of Q4 (within one switching cycle, the fourth switch Q4 turns on first, and the seventh switch Q7 turns on later, i.e., D). z >0) and switching period T s The ratio of D; where D x = (T1+T2) / T s D y =T2 / T s D z =T1 / T s The converter operates sequentially in the following phases within one switching cycle:

[0165] (4g) Phase One of the work:

[0166] Before the start of the switching cycle at time t0, the first switch Q1, the second switch Q2, the sixth switch Q6, and the eighth switch Q8 are kept on, while the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7 are kept off. At time t0, the junction capacitance voltage v of the third switch Q3... ds_Q3 Charged to -v in The junction capacitance voltage v of the fourth switch Q4 ds_Q4 The circuit is discharged to 0; at this time, the fourth switch Q4 is turned on, achieving zero-voltage turn-on, maintaining the on state of the first switch Q1, the second switch Q2, the sixth switch Q6, and the eighth switch Q8, and maintaining the off state of the third switch Q3, the fifth switch Q5, and the seventh switch Q7. The inductor current i L Linear increase;

[0167] (4h) Work Phase Two:

[0168] At time t1, the eighth switch Q8 is turned off, while the first, second, fourth, and sixth switches Q1, Q2, Q4, and Q6 remain on, and the third, fifth, and seventh switches Q3, Q5, and Q7 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is discharged, while the junction capacitance of the eighth switch Q8 is charged; at time t2, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 When discharged to 0, the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged to V o ;

[0169] (4i) Phase Three of Work:

[0170] At time t2, the seventh switch Q7 is turned on, achieving zero-voltage turn-on of the seventh switch Q7. This maintains the on-state of the first switch Q1, second switch Q2, fourth switch Q4, and sixth switch Q6, while maintaining the off-state of the third switch Q3, fifth switch Q5, and eighth switch Q8. The inductor current i L Linear decrease;

[0171] (4j) Phase Four of Work:

[0172] At time t3, the fourth switch Q4 and the seventh switch Q7 are turned off, the first switch Q1, the second switch Q2, and the sixth switch Q6 are kept on, and the third switch Q3, the fifth switch Q5, and the eighth switch Q8 are kept off. The inductor current i LThe junction capacitances of the third switch Q3 and the eighth switch Q8 are discharged, while the junction capacitances of the fourth switch Q4 and the seventh switch Q7 are charged; at time t4, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 and the junction capacitance voltage v of the eighth switch Q8 ds_Q8 When the transistors are discharged to 0 sequentially or simultaneously, the junction capacitance voltage v of the fourth switching transistor Q4... ds_Q4 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 Charged to -V sequentially or simultaneously in and V o ;

[0173] (4k) Phase Five of the Work:

[0174] At time t4, the third switch Q3 and the eighth switch Q8 are turned on, achieving zero-voltage turn-on for the third switch Q3 and the eighth switch Q8. This maintains the on-state of the first switch Q1, the second switch Q2, and the sixth switch Q6, while maintaining the off-state of the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7. The inductor current i... L Remain unchanged;

[0175] (4l) Work Phase Six:

[0176] At time t5, the third switch Q3 is turned off, while the first, second, sixth, and eighth switches Q1, Q2, Q6, and Q8 remain on, and the fourth, fifth, and seventh switches Q4, Q5, and Q7 remain off. The inductor current i L The junction capacitance of the third switch Q3 is charged, while the junction capacitance of the fourth switch Q4 is discharged; at time t6, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 Charged to -v in The junction capacitance voltage v of the fourth switch Q4 ds_Q4 Discharged to 0;

[0177] The main waveforms of the converter operating under modulation strategy four are as follows: Figure 10 and Figure 11 As shown, where Figure 10 It is v in The main waveform when >0, Figure 11 It is v in The main waveform when <0.

[0178] The mode in which the converter operates under modulation strategy four is named PseudoTriangle Discontinuous Conduction Mode Three (PTDCM3), and the prerequisite for executing modulation strategy four is |v in | <Vo When modulation strategy four is executed, the sampled output voltage is compared with the voltage reference value. The error signal is processed by the error compensator, and the output is multiplied by a sinusoidal quantity in phase with the power frequency input voltage to obtain the reference value i of the input current. in T1, T2, and T4 can be solved according to the following calculation principles:

[0179] 1) The integral of the inductor voltage with respect to time is zero within one switching cycle;

[0180] 2) Controlling the inductor current i at time t0 L =-I zvs To ensure v in At time >0, the first switching transistor Q1 achieves zero-voltage turn-on and v in When the voltage is less than 0, the fourth switch Q4 achieves zero-voltage turn-on and controls v. in When the current is greater than 0, the average current flowing through the first switching transistor Q1 is equal to the reference current i of the power frequency AC input current. in and v in When the current is less than 0, the average current flowing through the fourth switch Q4 is equal to the reference current i of the power frequency AC input current. in ;

[0181] 3) The sum of T1, T2, and T4 is the switching period T. s .

[0182] The four modulation strategies described above correspond to different loss magnitudes. Within one power frequency cycle, when the input voltage value and the converter's operating conditions change, switching to the modulation strategy with the lowest converter loss via converter control allows the converter to operate under the optimal modulation strategy. When the AC input voltage is near the zero-crossing point, the amplitude of the AC input voltage is very small, and the inductor current cannot be modulated into an ideal waveform, causing input current distortion. Therefore, near the zero-crossing point, the valley value of the inductor current reaches -I. zvs It is not a necessary condition for the converter to work.

[0183] Example

[0184] To verify the effectiveness of the present invention, the following simulation verification was performed.

[0185] The simulation uses an AC input voltage RMS value of 220V, an AC input voltage frequency of 50Hz, an energy transfer inductor L with an inductance of 14μH, and an output voltage V. o 300V, load resistance R L The resistance is 180Ω, and the DC-side filter capacitor C o The capacitance is 2000μF, and the switching frequency is f. s The frequency is 500kHz, and the switching period T is... s The junction capacitance C of all switching transistors is 2μs.oss The capacitance is 50pF, and the dead time is 1% of the switching cycle. To allow for adequate margin, the absolute value of the minimum inductor current I required to achieve zero-voltage turn-on for all switches is defined. ZVS The value is 2A. Figure 12 Simulation results for the converter are presented, with the input current i... in It approximately exhibits a sine wave and is related to the input voltage v. in The fact that they are in phase proves that the converter of this invention can achieve power factor correction; Figure 13 The above is a simulation waveform diagram of the converter operating in the pseudo-quadrilateral discontinuous conduction mode of the modulation strategy. The inductor current is |v in | / L Slope change time T1, with (|v in |-V o The time T2 of the slope change () / L, with -V o The time T3 for the slope of / L to change and the time T4 for it to remain constant are both greater than 0; Figure 14 The simulation waveform diagram is shown for the converter operating in the modulation strategy one pseudo quadrilateral critical conduction mode, where the inductor current remains constant for a time T4 of 0. Figure 15 This is a simulation waveform diagram of the converter operating under modulation strategy two, with the inductor current expressed as |v... in The time T1 for the slope change of | / L is 0; Figure 16 The above is a simulation waveform diagram of the converter operating under modulation strategy three, with the inductor current expressed as (|v in |-V o The time T2 for the slope change of ) / L is 0; Figure 17 The following is a simulation waveform diagram of the converter operating under modulation strategy four, with the inductor current at -V. o The time T3 for the slope of / L to change is 0.

[0186] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0187] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A high power factor soft-switching bridgeless Buck-Boost PFC converter, characterized in that, It includes eight switching transistors Q1~Q8, an energy transfer inductor L, and an output filter capacitor C. o The source of the first switch Q1 is connected to the drain of the second switch Q2; the drain of the third switch Q3 is connected to the source of the fourth switch Q4; the source of the second switch Q2 is connected to the source of the third switch Q3; the drain of the fifth switch Q5 is connected to the drain of the sixth switch Q6; the source of the fifth switch Q5 is connected to the source of the first switch Q1 and the drain of the second switch Q2; the source of the sixth switch Q6 is connected to the drain of the third switch Q3 and the source of the fourth switch Q4; and the drain of the first switch Q1 is connected to the AC input voltage. One end, defined as end a, connects the drain of the fourth switch Q4 to the AC input voltage. The other end, defined as end b, connects the source of the seventh switch Q7 to the drain of the eighth switch Q8. One end of the energy transfer inductor L connects to the drains of the fifth switch Q5 and the sixth switch Q6, while the other end connects to the source of the seventh switch Q7 and the drain of the eighth switch Q8. The source of the eighth switch Q8 connects to the sources of the second switch Q2 and the third switch Q3. The drain of the seventh switch Q7 is connected to the output filter capacitor C. o The positive terminal of the transistor Q8 is connected to the source of the output filter capacitor C. o The negative end; All the switching transistors in the converter consist of a unidirectional switching transistor and a diode connected in reverse parallel. The unidirectional switching transistor is a transistor, IGBT, or MOSFET. When the unidirectional switching transistor is a transistor or IGBT, the source of the unidirectional switching transistor corresponds to the emitter of the transistor or IGBT, the drain of the unidirectional switching transistor corresponds to the collector of the transistor or IGBT, the cathode of the diode is connected to the drain of the unidirectional switching transistor, and the anode of the diode is connected to the source of the unidirectional switching transistor. When the unidirectional switching transistor is a MOSFET, the source of the unidirectional switching transistor corresponds to the source of the MOSFET, the drain of the unidirectional switching transistor corresponds to the drain of the MOSFET, and the diode is the body diode of the MOSFET.

2. A modulation method for the high power factor soft-switching bridgeless Buck-Boost PFC converter as described in claim 1, characterized in that, Specifically as follows: When the AC input voltage v in When the voltage at terminal a of the converter is greater than the voltage at terminal b, the drive signals of the first switch Q1 and the second switch Q2 are complementary and have a dead time. The third switch Q3, the fourth switch Q4 and the fifth switch Q5 are always on, the sixth switch Q6 is always off, and the drive signals of the seventh switch Q7 and the eighth switch Q8 are complementary and have a dead time. When the AC input voltage v in When the voltage is less than 0, i.e., when the voltage at terminal a of the converter is less than the voltage at terminal b, the first switch Q1, the second switch Q2, and the sixth switch Q6 are always on, the drive signals of the third switch Q3 and the fourth switch Q4 are complementary and have a dead time, the fifth switch Q5 is always off, and the drive signals of the seventh switch Q7 and the eighth switch Q8 are complementary and have a dead time.

3. The modulation method for a high power factor soft-switching bridgeless Buck-Boost PFC converter according to claim 2, characterized in that, Execute modulation strategy one, as follows: Define the current in the energy transfer inductor L as |v in The slope of | / L changes over time T1, and the inductor current changes at (|v) in |-V o The slope changes over time T2, and the inductor current changes with a slope of -V / L. o The time for the slope of / L to change is T3, the time for the inductor current to remain constant is T4, and the dead time is t. dead The absolute value of the minimum inductor current that enables all switching transistors to turn on at zero voltage is I. ZVS V o For the output voltage, T4 = T s -T1-T2-T3, the working mode with T1>0, T2>0, T3>0, and T4>0 is named the pseudo-quadrilateral discontinuous conduction mode, and the working mode with T1>0, T2>0, T3>0, and T4=0 is named the pseudo-quadrilateral critical conduction mode; Define the start time of a switching cycle as t0, and the time elapsed after t0 is (T1-t) dead The time after the specified time length is t1, and time t1 is t... dead The time after the specified time length is t2, and time t2 is the time elapsed after (T2-t). dead The time after the specified time length is t3, and t3 is the time elapsed after t. dead The time after the specified duration is t4. Time t4 is the time interval (T3-t). dead The time after the specified time length is t5. Time t5 is t... dead The time after the specified duration is t6, and time t6 is the time interval (T4-t). dead The time after the specified time length is t7. Time t7 elapses after t dead The time after the duration is t8; (a) When v in When the value is >0, the converter includes the following operating phases within one switching cycle: (1a) Phase 1 of the work: Before the start of the switching cycle at time t0, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8 are kept on, while the first switch Q1, the second switch Q2, the sixth switch Q6, and the seventh switch Q7 are kept off. At time t0, the junction capacitance voltage v of the first switch Q1... ds_Q1 When discharged to 0, the junction capacitance voltage v of the second switch Q2... ds_Q2 Charged to v in At this time, the first switch Q1 is turned on, achieving zero-voltage turn-on of the first switch Q1, maintaining the on state of the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8, and maintaining the off state of the second switch Q2, the sixth switch Q6, and the seventh switch Q7. The inductor current i L Linear increase; (1b) Phase Two of Work: At time t1, the eighth switch Q8 is turned off, while the first, third, fourth, and fifth switches Q1, Q3, Q4, and Q5 remain on, and the second, sixth, and seventh switches Q2, Q6, and Q7 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is discharged, while the junction capacitance of the eighth switch Q8 is charged; at time t2, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 When discharged to 0, the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged to V o ; (1c) Phase Three of Work: At time t2, the seventh switch Q7 is turned on, achieving zero-voltage turn-on of the seventh switch Q7. This maintains the on-state of the first switch Q1, third switch Q3, fourth switch Q4, and fifth switch Q5, while maintaining the off-state of the second switch Q2, sixth switch Q6, and eighth switch Q8. During this operating phase, if v in >V o Inductor current i L Linear increase; if v in <V o Inductor current i L Linear decrease; (1d) Phase Four of the Work: At time t3, the first switch Q1 is turned off, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7 are kept on, and the second switch Q2, the sixth switch Q6, and the eighth switch Q8 are kept off. The inductor current i L The junction capacitance of the first switching transistor Q1 is charged, while the junction capacitance of the second switching transistor Q2 is discharged; at time t4, the junction capacitance voltage v of the first switching transistor Q1 is... ds_Q1 Charged to v in The junction capacitance voltage v of the second switch Q2 ds_Q2 Discharged to 0; (1e) Phase Five of the Work: At time t4, the second switch Q2 is turned on, achieving zero-voltage turn-on of the second switch Q2. This maintains the on-state of the third switch Q3, fourth switch Q4, fifth switch Q5, and seventh switch Q7, while maintaining the off-state of the first switch Q1, sixth switch Q6, and eighth switch Q8. The inductor current i... L Linear decrease; (1f) Work Phase Six: At time t5, the seventh switch Q7 is turned off, while the second, third, fourth, and fifth switches Q2, Q3, Q4, and Q5 remain on, and the first, sixth, and eighth switches Q1, Q6, and Q8 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is charged, while the junction capacitance of the eighth switch Q8 is discharged; at time t6, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 Charged to V o The junction capacitance voltage v of the eighth switch Q8 ds_Q8 Discharged to 0; (1g) Working Stage Seven: At time t6, the eighth switch Q8 is turned on, achieving zero-voltage turn-on of the eighth switch Q8. This maintains the on-state of the second, third, fourth, and fifth switches Q2, Q3, Q4, and Q5, while maintaining the off-state of the first, sixth, and seventh switches Q1 and Q6. The inductor current i... L Remain unchanged; (1h) Work Phase Eight: At time t7, the second switch Q2 is turned off, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8 are kept on, and the first switch Q1, the sixth switch Q6, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitance of the first switching transistor Q1 is discharged, while the junction capacitance of the second switching transistor Q2 is charged; at time t8, the junction capacitance voltage v of the first switching transistor Q1 is... ds_Q1 When discharged to 0, the junction capacitance voltage v of the second switch Q2... ds_Q2 Charged to v in ; (ii) When v in When <0, the converter includes the following operating phases within one switching cycle: (1i) Phase 1 of the work: Before the start of the switching cycle at time t0, the first switch Q1, the second switch Q2, the sixth switch Q6, and the eighth switch Q8 are kept on, while the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7 are kept off. At time t0, the junction capacitance voltage v of the third switch Q3... ds_Q3 Charged to -v in The junction capacitance voltage v of the fourth switch Q4 ds_Q4 The circuit is discharged to 0; at this time, the fourth switch Q4 is turned on, achieving zero-voltage turn-on of the fourth switch Q4, maintaining the on state of the first switch Q1, the second switch Q2, the sixth switch Q6, and the eighth switch Q8, and maintaining the off state of the third switch Q3, the fifth switch Q5, and the seventh switch Q7. The inductor current i L Linear increase; (1j) Phase Two of Work: At time t1, the eighth switch Q8 is turned off, while the first, second, fourth, and sixth switches Q1, Q2, Q4, and Q6 remain on, and the third, fifth, and seventh switches Q3, Q5, and Q7 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is discharged, while the junction capacitance of the eighth switch Q8 is charged; at time t2, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 When discharged to 0, the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged to V o ; (1k) Phase Three of Work: At time t2, the seventh switch Q7 is turned on, achieving zero-voltage turn-on of the seventh switch Q7. This maintains the on-state of the first switch Q1, second switch Q2, fourth switch Q4, and sixth switch Q6, while maintaining the off-state of the third switch Q3, fifth switch Q5, and eighth switch Q8. During this operating phase, if -v in >V o Inductor current i L Linear increase; if -v in <V o Inductor current i L Linear decrease; (1l) Phase Four of the Work: At time t3, the fourth switch Q4 is turned off, while the first, second, sixth, and seventh switches Q1, Q2, Q6, and Q7 remain on, and the third, fifth, and eighth switches Q3, Q5, and Q8 remain off. The inductor current i L The junction capacitance of the third switch Q3 is discharged, while the junction capacitance of the fourth switch Q4 is charged; at time t4, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 When discharged to 0, the junction capacitance voltage v of the fourth switch Q4... ds_Q4 Charged to -v in ; (1m) Working Phase Five: At time t4, the third switch Q3 is turned on, achieving zero-voltage turn-on of the third switch Q3. This maintains the on-state of the first switch Q1, second switch Q2, sixth switch Q6, and seventh switch Q7, while maintaining the off-state of the fourth switch Q4, fifth switch Q5, and eighth switch Q8. The inductor current i L Linear decrease; (1n) Work Phase Six: At time t5, the seventh switch Q7 is turned off, while the first, second, third, and sixth switches Q1, Q2, Q3, and Q6 remain on, and the fourth, fifth, and eighth switches Q4, Q5, and Q8 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is charged, while the junction capacitance of the eighth switch Q8 is discharged; at time t6, the junction capacitance voltage v of the seventh switch Q7 is controlled. ds_Q7 Charged to V o The junction capacitance voltage v of the eighth switch Q8 ds_Q8 Discharged to 0; (1o) Work Phase Seven: At time t6, the eighth switch Q8 is turned on, achieving zero-voltage turn-on of the eighth switch Q8. This maintains the on-state of the first switch Q1, second switch Q2, third switch Q3, and sixth switch Q6, while maintaining the off-state of the fourth switch Q4, fifth switch Q5, and seventh switch Q7. The inductor current i... L Remain unchanged; (1p) Work Phase Eight: At time t7, the third switch Q3 is turned off, while the first, second, sixth, and eighth switches Q1, Q2, Q6, and Q8 remain on, and the fourth, fifth, and seventh switches Q4, Q5, and Q7 remain off. The inductor current i L The junction capacitance of the third switch Q3 is charged, while the junction capacitance of the fourth switch Q4 is discharged; at time t8, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 Charged to -v in The junction capacitance voltage v of the fourth switch Q4 ds_Q4 Discharged to 0; In the pseudo-quadrilateral discontinuous conduction mode, the specific principles for determining T1, T2, T3, and T4 are as follows: 1) The integral of the inductor voltage with respect to time is zero within one switching cycle; 2) Control the inductor current i at time t0 L =-I zvs To ensure v in At time >0, the first switching transistor Q1 achieves zero-voltage turn-on and v in When the voltage is less than 0, the fourth switch Q4 achieves zero-voltage turn-on and controls v. in When the current is greater than 0, the average current flowing through the first switching transistor Q1 within one switching cycle is equal to the reference current i of the power frequency AC input current. in and v in When <0, the average current flowing through the fourth switch Q4 within one switching cycle is equal to the reference i of the power frequency AC input current. in ; 3) When |v in | <V o At time t3, control the inductor current i L =I zvs To ensure v in At >0, the second switch Q2 achieves zero-voltage turn-on and v in When |v < 0, the third switch Q3 achieves zero-voltage turn-on. in |>V o At time t1, control the inductor current i L =I zvs This is to ensure that the seventh switch Q7 achieves zero-voltage turn-on; 4) The sum of T1, T2, T3, and T4 is the switching period T. s ; In the pseudo-quadrilateral critical conduction mode, the specific principles for determining T1, T2, and T3 are as follows: 1) The integral of the inductor voltage with respect to time is zero during one switching cycle; 2) Control the inductor current i at time t0 L =-I zvs To ensure v in At time >0, the first switching transistor Q1 achieves zero-voltage turn-on and v in When the voltage is less than 0, the fourth switch Q4 achieves zero-voltage turn-on and controls v. in When the current is greater than 0, the average current flowing through the first switching transistor Q1 within one switching cycle is equal to the reference current i of the power frequency AC input current. in and v in When <0, the average current flowing through the fourth switch Q4 within one switching cycle is equal to the reference i of the power frequency AC input current. in ; 3) The sum of T1, T2, and T3 is the switching period T. s .

4. The modulation method for a high power factor soft-switching bridgeless Buck-Boost PFC converter according to claim 2, characterized in that, Execute modulation strategy two, as follows: The prerequisite for the converter to operate under modulation strategy two is |v in |>V o Define the current in the energy transfer inductor L as |v in The slope of | / L changes over time T1, and the inductor current changes at (|v) in |-V o The slope changes over time T2, and the inductor current changes with a slope of -V / L. o The time for the slope of / L to change is T3, the time for the inductor current to remain constant is T4, and the dead time is t. dead The absolute value of the minimum inductor current that enables all switching transistors to turn on at zero voltage is I. ZVS Where T1=0 and T4=T s -T1-T2-T3, the mode in which the converter operates under modulation strategy two is named pseudo-triangle discontinuous conduction mode one; Define the start time of a switching cycle as t0, and the time elapsed after t0 is (T2-t) dead The time after the specified time length is t1, and time t1 is t... dead The time after the specified time length is t2, and time t2 is (T3-t) dead The time after the specified time length is t3, and t3 is the time elapsed after t. dead The time after the specified duration is t4. Time t4 is the time interval (T4-t). dead The time after the specified time length is t5. Time t5 is t... dead The time after the specified duration is t6; (a) When v in When the value is >0, the converter includes the following operating phases within one switching cycle: (2a) Phase 1 of the work: Before the start of the switching cycle at time t0, the third switch Q3, the fourth switch Q4, and the fifth switch Q5 are kept on, while the first switch Q1, the second switch Q2, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8 are kept off. At time t0, the junction capacitance voltage v of the first switch Q1... ds_Q1 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 When the transistors are discharged to 0 sequentially or simultaneously, the junction capacitance voltage v of the second switching transistor Q2... ds_Q2 and the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged sequentially or simultaneously to v in and V o At this time, the first switch Q1 and the seventh switch Q7 are turned on, achieving zero-voltage turn-on of the first switch Q1 and the seventh switch Q7, maintaining the on state of the third switch Q3, the fourth switch Q4 and the fifth switch Q5, and maintaining the off state of the second switch Q2, the sixth switch Q6 and the eighth switch Q8. The inductor current i L Linear increase; (2b) Phase Two of Work: At time t1, the first switch Q1 is turned off, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the fifth switch Q7 are kept on, and the second switch Q2, the sixth switch Q6, and the eighth switch Q8 are kept off. The inductor current i L The junction capacitance of the first switching transistor Q1 is charged, while the junction capacitance of the second switching transistor Q2 is discharged; at time t2, the junction capacitance voltage v of the first switching transistor Q1 is... ds_Q1 Charged to v in The junction capacitance voltage v of the second switch Q2 ds_Q2 Discharged to 0; (2c) Phase Three of the Work: At time t2, the second switch Q2 is turned on, achieving zero-voltage turn-on of the second switch Q2; the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7 are maintained on, while the first switch Q1, the sixth switch Q6, and the eighth switch Q8 are maintained off. The inductor current i L Linear decrease; (2d) Work Phase Four: At time t3, the seventh switch Q7 is turned off, while the second, third, fourth, and fifth switches Q2, Q3, Q4, and Q5 remain on, and the first, sixth, and eighth switches Q1, Q6, and Q8 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is charged, while the junction capacitance of the eighth switch Q8 is discharged; at time t4, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 Charged to V o The junction capacitance voltage v of the eighth switch Q8 ds_Q8 Discharged to 0; (2e) Phase Five of the Work: At time t4, the eighth switch Q8 is turned on, achieving zero-voltage turn-on of the eighth switch Q8. This maintains the on-state of the second, third, fourth, and fifth switches Q2, Q3, Q4, and Q5, while maintaining the off-state of the first, sixth, and seventh switches Q1 and Q6. The inductor current i... L Remain unchanged; (2f) Work Phase Six: At time t5, the second switch Q2 and the eighth switch Q8 are turned off, the third switch Q3, the fourth switch Q4, and the fifth switch Q5 are kept on, and the first switch Q1, the sixth switch Q6, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitances of the first switch Q1 and the seventh switch Q7 are discharged, while the junction capacitances of the second switch Q2 and the eighth switch Q8 are charged; at time t6, the junction capacitance voltage v of the first switch Q1 is... ds_Q1 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 When the transistors are discharged to 0 sequentially or simultaneously, the junction capacitance voltage v of the second switching transistor Q2... ds_Q2 and the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged sequentially or simultaneously to v in and V o ; (ii) When v in When <0, the converter includes the following operating phases within one switching cycle: (2g) Working Phase One: Before the start of the switching cycle at time t0, the first switch Q1, the second switch Q2, and the sixth switch Q6 are kept on, while the third switch Q3, the fourth switch Q4, the fifth switch Q5, the seventh switch Q7, and the eighth switch Q8 are kept off. At time t0, the junction capacitance voltage v of the third switch Q3... ds_Q3 and the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged to -V sequentially or simultaneously in and V o The junction capacitance voltage v of the fourth switch Q4 ds_Q4 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 The transistors are discharged to 0 sequentially or simultaneously; at this time, the fourth switch Q4 and the seventh switch Q7 are turned on, achieving zero-voltage turn-on of the fourth switch Q4 and the seventh switch Q7, maintaining the on state of the first switch Q1, the second switch Q2, and the sixth switch Q6, and maintaining the off state of the third switch Q3, the fifth switch Q5, and the eighth switch Q8. The inductor current i L Linear increase; (2h) Work Phase Two: At time t1, the fourth switch Q4 is turned off, while the first switch Q1 and the second switch Q1 are kept in operation. 2、 The sixth switch Q6 and the seventh switch Q7 are turned on, while the third switch Q3, the fifth switch Q5, and the eighth switch Q8 are turned off. The inductor current i L The junction capacitance of the third switch Q3 is discharged, while the junction capacitance of the fourth switch Q4 is charged; at time t2, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 When discharged to 0, the junction capacitance voltage v of the fourth switch Q4... ds_Q4 Charged to -v in ; (2i) Phase Three of Work: At time t2, the third switch Q3 is turned on, achieving zero-voltage turn-on of the third switch Q3. This maintains the on-state of the first switch Q1, second switch Q2, sixth switch Q6, and seventh switch Q7, while maintaining the off-state of the fourth switch Q4, fifth switch Q5, and eighth switch Q8. The inductor current i L Linear decrease; (2j) Phase Four of the Work: At time t3, the seventh switch Q7 is turned off, while the first, second, third, and sixth switches Q1, Q2, Q3, and Q6 remain on, and the fourth, fifth, and eighth switches Q4, Q5, and Q8 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is charged, while the junction capacitance of the eighth switch Q8 is discharged; at time t4, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 Charged to V o The junction capacitance voltage v of the eighth switch Q8 ds_Q8 Discharged to 0; (2k) Phase Five: At time t4, the eighth switch Q8 is turned on, achieving zero-voltage turn-on of the eighth switch Q8. This maintains the on-state of the first switch Q1, second switch Q2, third switch Q3, and sixth switch Q6, while maintaining the off-state of the fourth switch Q4, fifth switch Q5, and seventh switch Q7. The inductor current i... L Remain unchanged; (2l) Work Phase Six: At time t5, the third switch Q3 and the eighth switch Q8 are turned off, the first switch Q1, the second switch Q2, and the sixth switch Q6 are kept on, and the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitances of the third switch Q3 and the eighth switch Q8 are charged, while the junction capacitances of the fourth switch Q4 and the seventh switch Q7 are discharged; at time t6, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 and the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged to -V sequentially or simultaneously in and V o The junction capacitance voltage v of the fourth switch Q4 ds_Q4 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 They are discharged to 0 successively or simultaneously; In the pseudo-triangular discontinuous conduction mode, the specific principles for determining T2, T3, and T4 are as follows: 1) The integral of the inductor voltage with respect to time is zero during one switching cycle; 2) Control the inductor current i at time t0 L =-I zvs To ensure v in At time >0, the first switching transistor Q1 achieves zero-voltage turn-on and v in When the voltage is less than 0, the fourth switch Q4 achieves zero voltage and controls v. in When the current is greater than 0, the average current flowing through the first switching transistor Q1 within one switching cycle is equal to the reference current i of the power frequency AC input current. in and v in When <0, the average current flowing through the fourth switch Q4 within one switching cycle is equal to the reference i of the power frequency AC input current. in ; 3) The sum of T2, T3, and T4 is the switching period T. s .

5. The modulation method for a high power factor soft-switching bridgeless Buck-Boost PFC converter according to claim 2, characterized in that, Execute modulation strategy three, as follows: Define the current in the energy transfer inductor L as |v in The slope of | / L changes over time T1, and the inductor current changes at (|v) in |-V o The slope changes over time T2, and the inductor current changes with a slope of -V / L. o The time for the slope of / L to change is T3, the time for the inductor current to remain constant is T4, and the dead time is t. dead The absolute value of the minimum inductor current that enables all switching transistors to turn on at zero voltage is I. ZVS Where T2=0 and T4=T s -T1-T2-T3, the mode in which the converter operates under modulation strategy three is named pseudo-triangle discontinuous conduction mode two; Define the start time of a switching cycle as t0, and the time elapsed after t0 is (T1-t) dead The time after the specified time length is t1, and time t1 is t... dead The time after the specified time length is t2, and time t2 is (T3-t) dead The time after the specified time length is t3, and t3 is the time elapsed after t. dead The time after the specified duration is t4. Time t4 is the time interval (T4-t). dead The time after the specified time length is t5. Time t5 is t... dead The time after the specified duration is t6; (a) When v in When the value is >0, the converter includes the following operating phases within one switching cycle: (3a) Phase 1 of the work: Before the start of the switching cycle at time t0, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8 are kept on, while the first switch Q1, the second switch Q2, the sixth switch Q6, and the seventh switch Q7 are kept off. At time t0, the junction capacitance voltage v of the first switch Q1... ds_Q1 When discharged to 0, the junction capacitance voltage v of the second switch Q2... ds_Q2 Charged to v in At this time, the first switch Q1 is turned on, achieving zero-voltage turn-on of the first switch Q1, maintaining the on state of the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8, and maintaining the off state of the second switch Q2, the sixth switch Q6, and the seventh switch Q7. The inductor current i L Linear increase; (3b) Phase Two of the Work: At time t1, the first switch Q1 and the eighth switch Q8 are turned off, the third switch Q3, the fourth switch Q4, and the fifth switch Q5 are kept on, and the second switch Q2, the sixth switch Q6, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitances of the first switch Q1 and the eighth switch Q8 are charged, while the junction capacitances of the second switch Q2 and the seventh switch Q7 are discharged; at time t2, the junction capacitance voltage v of the first switch Q1 is... ds_Q1 and the junction capacitance voltage v of the eighth switch ds_Q8 Charged sequentially or simultaneously to v in and V o The junction capacitance voltage v of the second switch Q2 ds_Q2 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 They are discharged to 0 successively or simultaneously; (3c) Work Phase Three: At time t2, the second switch Q2 and the seventh switch Q7 are turned on, achieving zero-voltage turn-on for the second switch Q2 and the seventh switch Q7. The third switch Q3, the fourth switch Q4, and the fifth switch Q5 are maintained on, while the first switch Q1, the sixth switch Q6, and the eighth switch Q8 are maintained off. The inductor current i... L Linear decrease; (3d) Phase Four of the Work: At time t3, the seventh switch Q7 is turned off, while the second, third, fourth, and fifth switches Q2, Q3, Q4, and Q5 remain on, and the first, sixth, and eighth switches Q1, Q6, and Q8 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is charged, while the junction capacitance of the eighth switch Q8 is discharged; at time t4, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 Charged to V o The junction capacitance voltage v of the eighth switch Q8 ds_Q8 Discharged to 0; (3e) Phase Five of the Work: At time t4, the eighth switch Q8 is turned on, achieving zero-voltage turn-on of the eighth switch Q8. This maintains the on-state of the second, third, fourth, and fifth switches Q2, Q3, Q4, and Q5, while maintaining the off-state of the first, sixth, and seventh switches Q1 and Q6. The inductor current i... L Remain unchanged; (3f) Work Phase Six: At time t5, the second switch Q2 is turned off, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8 are kept on, and the first switch Q1, the sixth switch Q6, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitance of the first switch Q1 is discharged, while the junction capacitance of the second switch Q2 is charged; at time t6, the junction capacitance voltage v of the first switch Q1 is... ds_Q1 When discharged to 0, the junction capacitance voltage v of the second switch Q2... ds_Q2 Charged to v in ; (ii) When v in When <0, the converter includes the following operating phases within one switching cycle: (3g) Working Phase One: Before the start of the switching cycle at time t0, the first switch Q1, the second switch Q2, the sixth switch Q6, and the eighth switch Q8 are kept on, while the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7 are kept off. At time t0, the junction capacitance voltage v of the fourth switch Q4... ds_Q4 When discharged to 0, the junction capacitance voltage v of the third switch Q3... ds_Q3 Charged to -v in At this time, the fourth switch Q4 is turned on, achieving zero-voltage turn-on of the fourth switch Q4, maintaining the on state of the first switch Q1, the second switch Q2, the sixth switch Q6, and the eighth switch Q8, and maintaining the off state of the third switch Q3, the fifth switch Q5, and the seventh switch Q7. The inductor current i L Linear increase; (3h) Work Phase Two: At time t1, the fourth switch Q4 and the eighth switch Q8 are turned off, the first switch Q1, the second switch Q2, and the sixth switch Q6 are kept on, and the third switch Q3, the fifth switch Q5, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitances of the fourth switch Q4 and the eighth switch Q8 are charged, while the junction capacitances of the third switch Q3 and the seventh switch Q7 are discharged; at time t2, the junction capacitance voltage v of the fourth switch Q4 is... ds_Q4 and the junction capacitance voltage v of the eighth switch ds_Q8 Charged to -V sequentially or simultaneously in and V o The junction capacitance voltage v of the third switch Q3 ds_Q3 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 They are discharged to 0 successively or simultaneously; (3i) Phase Three of Work: At time t2, the third switch Q3 and the seventh switch Q7 are turned on, achieving zero-voltage turn-on for the third switch Q3 and the seventh switch Q7. This maintains the on-state of the first switch Q1, the second switch Q2, and the sixth switch Q6, while maintaining the off-state of the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8. The inductor current i... L Linear decrease; (3j) Phase Four of the Work: At time t3, the seventh switch Q7 is turned off, while the first, second, third, and sixth switches Q1, Q2, Q3, and Q6 remain on, and the fourth, fifth, and eighth switches Q4, Q5, and Q8 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is charged, while the junction capacitance of the eighth switch Q8 is discharged; at time t4, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 Charged to V o The junction capacitance voltage v of the eighth switch Q8 ds_Q8 Discharged to 0; (3k) Phase Five: At time t4, the eighth switch Q8 is turned on, achieving zero-voltage turn-on of the eighth switch Q8. This maintains the on-state of the first switch Q1, second switch Q2, third switch Q3, and sixth switch Q6, while maintaining the off-state of the fourth switch Q4, fifth switch Q5, and seventh switch Q7. The inductor current i... L Remain unchanged; (3l) Work Phase Six: At time t5, the third switch Q3 is turned off, while the first, second, sixth, and eighth switches Q1, Q2, Q6, and Q8 remain on, and the fourth, fifth, and seventh switches Q4, Q5, and Q7 remain off. The inductor current i L The junction capacitance of the third switch Q3 is charged, while the junction capacitance of the fourth switch Q4 is discharged; at time t6, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 Charged to -v in The junction capacitance voltage v of the fourth switch Q4 ds_Q4 Discharged to 0; In the second pseudo-triangular discontinuous conduction mode, the specific principles for determining T1, T3, and T4 are as follows: 1) The integral of the inductor voltage with respect to time is zero within one switching cycle; 2) Control the inductor current i at time t0 L =-I zvs To ensure v in At time >0, the first switching transistor Q1 achieves zero-voltage turn-on and v in When the voltage is less than 0, the fourth switch Q4 achieves zero-voltage turn-on and controls v. in When the current is greater than 0, the average current flowing through the first switching transistor Q1 is equal to the reference current i of the power frequency AC input current. in and v in When the current is less than 0, the average current flowing through the fourth switch Q4 is equal to the reference current i of the power frequency AC input current. in ; 3) The sum of T1, T3, and T4 is the switching period T. s .

6. The modulation method for a high power factor soft-switching bridgeless Buck-Boost PFC converter according to claim 2, characterized in that, Execute modulation strategy four, as follows: The prerequisite for the converter to operate under modulation strategy four is |v in | <V o Define the current in the energy transfer inductor L as |v in The slope of | / L changes over time T1, and the inductor current changes at (|v) in |-V o The slope changes over time T2, and the inductor current changes with a slope of -V / L. o The time for the slope of / L to change is T3, the time for the inductor current to remain constant is T4, and the dead time is t. dead The absolute value of the minimum inductor current that enables all switching transistors to turn on at zero voltage is I. ZVS Where T3=0 and T4=T s -T1-T2-T3, the mode in which the converter operates under modulation strategy four is named pseudo-triangular discontinuous conduction mode three; Define the start time of a switching cycle as t0, and the time elapsed after t0 is (T1-t) dead The time after the specified time length is t1, and time t1 is t... dead The time after the specified time length is t2, and time t2 is the time elapsed after (T2-t). dead The time after the specified time length is t3, and t3 is the time elapsed after t. dead The time after the specified duration is t4. Time t4 is the time interval (T4-t). dead The time after the specified time length is t5. Time t5 is t... dead The time after the specified duration is t6; (a) When v in When the value is >0, the converter includes the following operating phases within one switching cycle: (4a) Phase 1 of the work: Before the start of the switching cycle at time t0, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8 are kept on, while the first switch Q1, the second switch Q2, the sixth switch Q6, and the seventh switch Q7 are kept off. At time t0, the junction capacitance voltage v of the first switch Q1... ds_Q1 When discharged to 0, the junction capacitance voltage v of the second switch Q2... ds_Q2 Charged to v in At this time, the first switch Q1 is turned on, achieving zero-voltage turn-on of the first switch Q1, maintaining the on state of the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8, and maintaining the off state of the second switch Q2, the sixth switch Q6, and the seventh switch Q7. The inductor current i L Linear increase; (4b) Phase Two of the Work: At time t1, the eighth switch Q8 is turned off, while the first, third, fourth, and fifth switches Q1, Q3, Q4, and Q5 remain on, and the second, sixth, and seventh switches Q2, Q6, and Q7 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is discharged, while the junction capacitance of the eighth switch Q8 is charged; at time t2, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 When discharged to 0, the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged to V o ; (4c) Phase Three of the Work: At time t2, the seventh switch Q7 is turned on, achieving zero-voltage turn-on of the seventh switch Q7. This maintains the on-state of the first switch Q1, third switch Q3, fourth switch Q4, and fifth switch Q5, while maintaining the off-state of the second switch Q2, sixth switch Q6, and eighth switch Q8. The inductor current i L Linear decrease; (4d) Phase Four of the Work: At time t3, the first switch Q1 and the seventh switch Q7 are turned off, the third switch Q3, the fourth switch Q4, and the fifth switch Q5 are kept on, and the second switch Q2, the sixth switch Q6, and the eighth switch Q8 are kept off. The inductor current i L The junction capacitances of the first switch Q1 and the seventh switch Q7 are charged, while the junction capacitances of the second switch Q2 and the eighth switch Q8 are discharged; at time t4, the junction capacitance voltage v of the first switch Q1 is... ds_Q1 and the junction capacitance voltage v of the seventh switch transistor ds_Q7 Charged sequentially or simultaneously to v in and V o The junction capacitance voltage v of the second switch Q2 ds_Q2 and the junction capacitance voltage v of the eighth switch Q8 ds_Q8 They are discharged to 0 successively or simultaneously; (4e) Phase Five of the Work: At time t4, the second switch Q2 and the eighth switch Q8 are turned on, achieving zero-voltage turn-on for the second switch Q2 and the eighth switch Q8. The third switch Q3, the fourth switch Q4, and the fifth switch Q5 are maintained on, while the first switch Q1, the sixth switch Q6, and the seventh switch Q7 are maintained off. The inductor current i... L Remain unchanged; (4f) Work Phase Six: At time t5, the second switch Q2 is turned off, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the eighth switch Q8 are kept on, and the first switch Q1, the sixth switch Q6, and the seventh switch Q7 are kept off. The inductor current i L The junction capacitance of the first switch Q1 is discharged, while the junction capacitance of the second switch Q2 is charged; at time t6, the junction capacitance voltage v of the first switch Q1 is... ds_Q1 When discharged to 0, the junction capacitance voltage v of the second switch Q2... ds_Q2 Charged to v in ; (ii) When v in When <0, the converter includes the following operating phases within one switching cycle: (4g) Working Phase One: Before the start of the switching cycle at time t0, the first switch Q1, the second switch Q2, the sixth switch Q6, and the eighth switch Q8 are kept on, while the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7 are kept off. At time t0, the junction capacitance voltage v of the third switch Q3... ds_Q3 Charged to -v in The junction capacitance voltage v of the fourth switch Q4 ds_Q4 The circuit is discharged to 0; at this time, the fourth switch Q4 is turned on, achieving zero-voltage turn-on, maintaining the on state of the first switch Q1, the second switch Q2, the sixth switch Q6, and the eighth switch Q8, and maintaining the off state of the third switch Q3, the fifth switch Q5, and the seventh switch Q7. The inductor current i L Linear increase; (4h) Work Phase Two: At time t1, the eighth switch Q8 is turned off, while the first, second, fourth, and sixth switches Q1, Q2, Q4, and Q6 remain on, and the third, fifth, and seventh switches Q3, Q5, and Q7 remain off. The inductor current i L The junction capacitance of the seventh switch Q7 is discharged, while the junction capacitance of the eighth switch Q8 is charged; at time t2, the junction capacitance voltage v of the seventh switch Q7 is... ds_Q7 When discharged to 0, the junction capacitance voltage v of the eighth switch Q8 ds_Q8 Charged to V o ; (4i) Phase Three of Work: At time t2, the seventh switch Q7 is turned on, achieving zero-voltage turn-on of the seventh switch Q7. This maintains the on-state of the first switch Q1, second switch Q2, fourth switch Q4, and sixth switch Q6, while maintaining the off-state of the third switch Q3, fifth switch Q5, and eighth switch Q8. The inductor current i L Linear decrease; (4j) Phase Four of the Work: At time t3, the fourth switch Q4 and the seventh switch Q7 are turned off, the first switch Q1, the second switch Q2, and the sixth switch Q6 are kept on, and the third switch Q3, the fifth switch Q5, and the eighth switch Q8 are kept off. The inductor current i L The junction capacitances of the third switch Q3 and the eighth switch Q8 are discharged, while the junction capacitances of the fourth switch Q4 and the seventh switch Q7 are charged; at time t4, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 and the junction capacitance voltage v of the eighth switch Q8 ds_Q8 When the transistors are discharged to 0 sequentially or simultaneously, the junction capacitance voltage v of the fourth switching transistor Q4... ds_Q4 and the junction capacitance voltage v of the seventh switch Q7 ds_Q7 Charged to -V sequentially or simultaneously in and V o ; (4k) Phase Five of the Work: At time t4, the third switch Q3 and the eighth switch Q8 are turned on, achieving zero-voltage turn-on for the third switch Q3 and the eighth switch Q8. This maintains the on-state of the first switch Q1, the second switch Q2, and the sixth switch Q6, while maintaining the off-state of the fourth switch Q4, the fifth switch Q5, and the seventh switch Q7. The inductor current i... L Remain unchanged; (4l) Work Phase Six: At time t5, the third switch Q3 is turned off, while the first, second, sixth, and eighth switches Q1, Q2, Q6, and Q8 remain on, and the fourth, fifth, and seventh switches Q4, Q5, and Q7 remain off. The inductor current i L The junction capacitance of the third switch Q3 is charged, while the junction capacitance of the fourth switch Q4 is discharged; at time t6, the junction capacitance voltage v of the third switch Q3 is... ds_Q3 Charged to -v in The junction capacitance voltage v of the fourth switch Q4 ds_Q4 Discharged to 0; In the pseudo-triangular discontinuous conduction mode three, the specific principles for determining T1, T2, and T4 are as follows: 1) The integral of the inductor voltage with respect to time is zero within one switching cycle; 2) Control the inductor current i at time t0 L =-I zvs To ensure v in At time >0, the first switching transistor Q1 achieves zero-voltage turn-on and v in When the voltage is less than 0, the fourth switch Q4 achieves zero-voltage turn-on and controls v. in When the current is greater than 0, the average current flowing through the first switching transistor Q1 is equal to the reference current i of the power frequency AC input current. in and v in When the current is less than 0, the average current flowing through the fourth switch Q4 is equal to the reference current i of the power frequency AC input current. in ; 3) The sum of T1, T2, and T4 is the switching period T. s .

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