A method, apparatus, device and storage medium for converting signal mode

Abstract

The application discloses a method, device, equipment and storage medium for converting signal modes. The method comprises the following steps: receiving a short-distance transmission bus ESD enabling signal, prolonging the enabling time of the ESD enabling signal to obtain a medium-distance enabling signal; after the ESD enabling signal is disabled, setting the ESD message signal to a first preset signal and a second preset signal in sequence to obtain a medium-distance message signal; receiving an EMD message signal, determining a to-be-eliminated signal in the current EMD message signal by using a first end identifier signal of the previous EMD message signal and a message feature in the current EMD message signal, and obtaining a short-distance message signal by eliminating the to-be-eliminated signal. The technical scheme of the embodiment of the application realizes bidirectional conversion of the ESD mode signal and the EMD mode signal.

Description

Technical Field

[0001] This invention relates to the field of train communication technology, and in particular to a method, apparatus, device, and storage medium for switching signal modes. Background Technology

[0002] MVB (Multifunction Vehicle Bus) is a multi-functional vehicle bus that connects fixed equipment within the vehicle compartment. The physical layer transmission medium of MVB can include three types: 1) ESD (Electrical Short Distance) medium, typically used for short-distance transmission, such as 20 meters; 2) EMD (Electrical Middle Distance) medium, typically used for medium-distance transmission, such as 200 meters; 3) OGF (optical glass fiber) medium, typically used for long-distance transmission, such as 2 kilometers.

[0003] Any of the three transmission media mentioned above can connect several MVB devices to form a bus segment in MVB. Due to the length of on-orbit vehicles, EMD is the most widely used. Typically, MVB transmit / receive control is implemented using chips or modules. However, there is a problem that some MVB chips or modules only support ESD mode signal transmission and reception, and not EMD mode signal transmission and reception. When a chip or module that only supports ESD mode is directly connected to MVB, neither the received nor the transmitted signals can be recognized. Summary of the Invention

[0004] This invention provides a method, apparatus, device, and storage medium for converting signal modes to solve the problem that MVB chips or modules do not support the transmission and reception of signals in EMD mode.

[0005] In a first aspect, the present invention provides a method for converting signal modes, comprising:

[0006] Receive the short-range transmission bus ESD enable signal and extend the enable time of the ESD enable signal to obtain the medium-range enable signal;

[0007] After the ESD enable signal fails, the ESD message signal is set to the first preset signal and the second preset signal in sequence to obtain the mid-range message signal. The first preset signal and the second preset signal are both determined based on the characteristics of the end identifier signal of the mid-range transmission bus EMD message signal. The mid-range message signal is used to output to the multi-function vehicle bus (MVB), and the mid-range enable signal is used to control the output of the mid-range message signal to the MVB.

[0008] The system receives EMD message signals, uses the first end identifier signal of the previous EMD message signal and the message characteristics in the current EMD message signal to determine the signal to be eliminated in the current EMD message signal, and obtains a short-range message signal by eliminating the signal to be eliminated. The signal to be eliminated is the signal in the second end identifier signal of the current EMD message signal that is consistent with the second preset signal. The short-range message signal is used to output to the MVB module in ESD mode.

[0009] Secondly, the present invention provides an apparatus for converting signal modes, comprising:

[0010] The enable signal determination module is used to receive the short-range transmission bus ESD enable signal and extend the enable time of the ESD enable signal to obtain the medium-range enable signal.

[0011] The mid-range message determination module is used to set the ESD message signal to a first preset signal and a second preset signal successively after the ESD enable signal fails, thereby obtaining a mid-range message signal. The first preset signal and the second preset signal are both determined based on the characteristics of the end identifier signal of the mid-range transmission bus EMD message signal. The mid-range message signal is used to output to the multi-function vehicle bus (MVB), and the mid-range enable signal is used to control the output of the mid-range message signal to the MVB.

[0012] The short-range message determination module is used to receive EMD message signals, determine the signal to be eliminated in the current EMD message signal by using the first end identifier signal of the previous EMD message signal and the message characteristics in the current EMD message signal, and obtain a short-range message signal by eliminating the signal to be eliminated. The signal to be eliminated is the signal in the second end identifier signal of the current EMD message signal that is consistent with the second preset signal. The short-range message signal is used to output to the MVB module in ESD mode.

[0013] Thirdly, the present invention provides an electronic device comprising:

[0014] At least one processor;

[0015] and memory that is communicatively connected to at least one processor;

[0016] The memory stores a computer program that can be executed by at least one processor, which enables the at least one processor to perform the method of switching signal modes described in the first aspect.

[0017] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a processor to execute the method for switching signal modes described in the first aspect.

[0018] The present invention provides a scheme for switching signal modes, which receives a short-range transmission bus ESD enable signal and extends the enable time of the ESD enable signal to obtain a medium-range enable signal. After the ESD enable signal fails, the ESD message signal is successively set to a first preset signal and a second preset signal to obtain a medium-range message signal. The first preset signal and the second preset signal are both determined based on the characteristics of the end identifier signal of the medium-range transmission bus EMD message signal. The medium-range message signal is used to output to the multi-function vehicle bus (MVB). The medium-range enable signal is used to control the output of the medium-range message signal to the MVB. The system receives the EMD message signal, uses the first end identifier signal of the previous EMD message signal and the message characteristics in the current EMD message signal to determine the signal to be eliminated in the current EMD message signal, and obtains a short-range message signal by eliminating the signal to be eliminated. The signal to be eliminated is the signal in the second end identifier signal of the current EMD message signal that is consistent with the second preset signal. The short-range message signal is used to output to the MVB module in ESD mode. By adopting the above technical solution, by extending the signal enable time and changing the message tail frame signal, the converted ESD enable signal has the characteristics of the EMD enable signal, and the ESD message signal has the characteristics of the EMD message signal. The signal to be eliminated in the current EMD message signal is determined by using the end identifier signal of the previous EMD message signal. After eliminating the signal, the ESD message signal can be obtained. This realizes the bidirectional conversion between ESD mode signals and EMD mode signals.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of a method for switching signal modes according to Embodiment 1 of the present invention;

[0022] Figure 2 This is a schematic diagram of EMD signal and ESD signal conversion processing according to Embodiment 1 of the present invention;

[0023] Figure 3 This is a schematic diagram of a state machine transition according to Embodiment 1 of the present invention;

[0024] Figure 4 This is a flowchart of a method for switching signal modes according to Embodiment 2 of the present invention.

[0025] Figure 5 This is a timing diagram of a transmission process provided according to Embodiment 2 of the present invention;

[0026] Figure 6 This is a timing diagram of a receiving process provided according to Embodiment 2 of the present invention;

[0027] Figure 7 This is a schematic diagram of a device for switching signal modes according to Embodiment 3 of the present invention;

[0028] Figure 8 This is a schematic diagram of the structure of an electronic device provided according to Embodiment 4 of the present invention. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0031] The MVB data encoding rules described in IEC 61375-3-1 are Manchester encoding. If the MVB transmission rate is 1.5 Mbps (megabits per second), then the transmission duration of 1 bit is 666.7 nanoseconds. The frame signal on MVB is mainly divided into three parts: frame header, frame data, and frame trailer. Based on frame type, MVB frame signals can be divided into master frames and slave frames. Structurally, the main difference between master frames and slave frames lies in the shape of the separator in the frame header. An "invalid symbol" usually appears in both the frame header and frame trailer. The frame trailer typically serves as a marker to distinguish between ESD and EMD signals. For ESD signals, the frame trailer will display an "invalid symbol" (i.e., the end-of-frame identifier) ​​NL, which is a one-bit low-level signal. For EMD signals, the frame trailer will display both "invalid symbols" NL and NH, meaning that after the one-bit low-level signal, there is an additional one-bit high-level signal. Therefore, chips or modules that only support ESD signals cannot transmit or parse EMD signals.

[0032] Example 1

[0033] Figure 1 The flowchart below shows a method for switching signal modes according to Embodiment 1 of the present invention. This embodiment is applicable to situations involving switching signal modes. The method can be executed by a device for switching signal modes. The device for switching signal modes can be implemented in hardware and / or software. The device for switching signal modes can be configured in an electronic device, which can be composed of two or more physical entities or a single physical entity.

[0034] like Figure 1As shown, the method for switching signal modes provided in Embodiment 1 of the present invention specifically includes the following steps:

[0035] S101. Receive the short-distance transmission bus ESD enable signal and extend the enable time of the ESD enable signal to obtain a medium-distance enable signal.

[0036] Figure 2 This is a schematic diagram illustrating the conversion and processing of EMD and ESD signals. In this embodiment, as shown... Figure 2 As shown, when converting ESD signals (i.e., signals OC and SF emitted by the left-side MVB control chip / module) into EMD signals (signals OC_EMD output to the MVB from the right side), at least the SF and OC signals need to be processed. The SF signal is the ESD enable signal, and the OC signal is the ESD message signal. For the ESD enable signal, since it is emitted in ESD mode, its tail frame is usually a low-level signal. However, the tail frame of the EMD signal is usually one low-level signal and one high-level signal. Therefore, when converting the EMD signal to the ESD signal, one more low-level signal and one more high-level signal can be sent. Therefore, the enable time of the ESD enable signal needs to be extended, with an extension time of at least the duration of transmitting 2 bits of data. Figure 2 The FPGA (Field Programmable Gate Array) processing module is the module that implements the signal mode conversion method in this paper. The single-ended / differential conversion module can perform single-ended to differential and differential to single-ended operations on the signal.

[0037] S102. After the ESD enable signal fails, the ESD message signal is set to the first preset signal and the second preset signal in sequence to obtain the mid-range message signal. The first preset signal and the second preset signal are both determined based on the characteristics of the end identifier signal of the mid-range transmission bus EMD message signal. The mid-range message signal is used to output to the multi-function vehicle bus (MVB), and the mid-range enable signal is used to control the output of the mid-range message signal to the MVB.

[0038] In this embodiment, since the ESD message signal's end-of-line identifier is characterized by a low-level signal followed by a high-level signal, the processing of the ESD message signal can be divided into two parts. After the ESD enable signal is disabled, the ESD message signal is first set to a low-level signal (the first preset signal), and then set to a high-level signal (the second preset signal), thus obtaining the desired result. Figure 2OC1 (i.e., mid-range message signal) in the MVB. The duration of the first preset signal and the duration of the second preset signal can both be the transmission time of 1 bit character. The mid-range enable signal is enabled before the mid-range message signal is output to the MVB.

[0039] S103. Receive EMD message signal, use the first end identifier signal of the previous EMD message signal and the message characteristics in the current EMD message signal to determine the signal to be eliminated in the current EMD message signal, and obtain a short-range message signal by eliminating the signal to be eliminated. The signal to be eliminated is the signal in the second end identifier signal of the current EMD message signal that is consistent with the second preset signal. The short-range message signal is used to output to the MVB module in ESD mode.

[0040] In this embodiment, as Figure 2As shown, when converting the EMD signal (i.e., the signal IC_EMD emitted by the MVB on the right) to an ESD signal (the signal ICA / ICB input to the MVB control chip / module on the left), the start_bit (i.e., the start bit identifier signal) of the EMD message signal is usually a high-level signal and a low-level signal. However, the frame header of the EMD message signal is susceptible to various influences. For example, ESD mode chips or modules usually need to trigger the determination of whether a new EMD message signal has arrived through a rising edge from low to high before determining whether the start_bit has appeared. However, since the frame tail of the EMD signal is usually a high-level signal, this high-level signal will fluctuate for a long time on the MVB, and the single-ended value obtained after differential to single-ended conversion is often uncertain. That is to say, the EMD message signal before the start_bit may be a high-level signal or a low-level signal. Therefore, the arrival of the signal cannot be determined solely based on the falling edge when judging the start_bit. First, the (first) end-of-signal signal of the previous EMD message can be determined, which consists of one low-level signal and one high-level signal. Then, the arrival of a new signal can be determined based on the falling edge following the high-level signal, and the signal appearing after the falling edge is identified as the start_bit in the current EMD message. After determining the start_bit of the current EMD message, if a signal matching the characteristics of an abnormal message appears in the current EMD message, that signal can be discarded. When another falling edge is detected, the signal appearing after that falling edge is again identified as the start_bit in the current EMD message. After determining the start_bit, the end-of-signal signal in the current EMD message can be determined based on its characteristics. According to the characteristics of the end-of-signal signal of the ESD message described above, the end-of-signal signal of the EMD message does not contain a high-level signal. Therefore, the signal to be eliminated in the current EMD message is the high-level signal in the second end-of-signal signal, which is consistent with the second preset signal. Figure 2 As shown, after removing the signal to be eliminated from the EMD message signals ICA1 / ICB1, the ESD message signals ICA / ICB, i.e., short-range message signals, can be obtained. ICA1 and ICA are the master frames, and ICB1 and ICB are the slave frames, as shown below. Figure 2 As shown, short-range message signals can be used to output to MVB (control) modules or MVB (control) chips where both the transmitted and received signals are ESD signals.

[0041] The method for switching signal modes provided in this embodiment of the invention receives a short-range transmission bus ESD enable signal and extends the enable time of the ESD enable signal to obtain a medium-range enable signal. After the ESD enable signal fails, the ESD message signal is successively set to a first preset signal and a second preset signal to obtain a medium-range message signal. The first preset signal and the second preset signal are both determined based on the characteristics of the end identifier signal of the medium-range transmission bus EMD message signal. The medium-range message signal is used to output to the multi-function vehicle bus (MVB). The medium-range enable signal is used to control the output of the medium-range message signal to the MVB. The method receives an EMD message signal, uses the first end identifier signal of the previous EMD message signal and the message characteristics in the current EMD message signal to determine the signal to be eliminated in the current EMD message signal, and obtains a short-range message signal by eliminating the signal to be eliminated. The signal to be eliminated is the signal in the second end identifier signal of the current EMD message signal that is consistent with the second preset signal. The short-range message signal is used to output to the MVB module in ESD mode. The technical solution of this invention utilizes the method of extending the signal enable time and changing the message tail frame signal to make the converted ESD enable signal have the characteristics of the EMD enable signal, and make the ESD message signal have the characteristics of the EMD message signal. The signal to be eliminated in the current EMD message signal is determined by using the end identifier signal of the previous EMD message signal. After eliminating the signal, the ESD message signal can be obtained. This realizes the bidirectional conversion between ESD mode signals and EMD mode signals.

[0042] Optionally, before setting the ESD message signal to the first preset signal and the second preset signal sequentially, the method further includes: sampling the original ESD message signal at intervals of a first preset period to obtain a sampled signal; and holding each sampled signal for a second preset period to obtain the ESD message signal. The advantage of this configuration is that by using sampling and waveform reshaping, the waveform integrity of the ESD message signal is ensured.

[0043] Specifically, because MVB has requirements on the width and change time of the data waveform, directly sampling the original ESD message signal and outputting it may result in deviations or even distortions in the waveform shape of the output ESD message signal. Therefore, a sampling and waveform reshaping method can be used to preprocess the original ESD message signal. That is, the waveform of the original ESD message signal is first sampled, once every half cycle (the first preset cycle duration), to obtain the sampled signal. Then, each sampled signal is held for half a cycle duration (the second preset cycle duration) to obtain the ESD message signal.

[0044] Optionally, determining the signal to be eliminated in the current EMD message signal using the first end identifier signal of the previous EMD message signal and the message features in the current EMD message signal includes: determining the signal appearing after the first end identifier signal of the previous EMD message signal as the first start identifier signal, wherein the first start identifier signal is the start identifier signal in the current EMD message signal; if it is determined that the current EMD message signal contains an abnormal signal that satisfies preset abnormal features, then updating the first start identifier signal using a target signal that appears after the abnormal signal and is consistent with the preset message signal, wherein the preset message signal is determined based on the features of the end identifier signal of the EMD message signal; determining a second end identifier signal using the updated first start identifier signal, and determining the signal in the second end identifier signal that is consistent with the second preset signal as the signal to be eliminated. The advantage of this setting is that by utilizing the first end identifier signal of the previous EMD message signal, the accuracy of judging the start bit identifier signal in the current EMD message signal can be improved. If an abnormal signal appears in the current EMD message signal, the start bit identifier signal in the current EMD message signal can be quickly determined by identifying the target signal that appears after the abnormal signal and is consistent with the preset message signal.

[0045] Optionally, obtaining a short-range message signal by eliminating the signal to be eliminated includes: replacing the signal to be eliminated with the first preset signal to obtain the short-range message signal, wherein the output time of the short-range message signal is delayed by at least a first preset duration compared to the reception time of the current EMD message signal, and the first preset duration is longer than the duration corresponding to the second preset signal. The advantage of this configuration is that by replacing the signal to be eliminated with the first preset signal that satisfies the characteristics of the ESD termination signal, the conversion of the EMD message signal is achieved.

[0046] For example, Figure 3 This is a diagram illustrating the transitions of a state machine, such as... Figure 3 As shown, a preset state machine can be used to eliminate the signal to be eliminated in the current EMD message signal. This state machine can be built into the aforementioned FPGA processing module. Figure 2 The state machine transition process of the FPGA processing module is as follows:

[0047] 1) IDLE state, which is the initial state and the state for determining whether a data frame has been received.

[0048] This state primarily waits for the falling edge of IC1 (i.e., ICA1 or ICB1). The output of IC1 in this state is a low-level signal (i.e., ICA or ICB). If a falling edge of IC1 is received, the process jumps to the START_BIT state. If the current EMD message signal is the first EMD message signal received, then the falling edge of IC1 is the falling edge following the rising edge. This IDLE state's monitoring of the falling edge resolves the uncertainty of the level before start_bit. The FPGA processing module outputs a low-level signal in the IDLE state.

[0049] 2) START_BIT state, i.e., receiving START_BIT state.

[0050] This state primarily waits for the rising edge of IC1. Typically, the width of START_BIT has a certain range, allowing for waiting for the rising edge of IC1 within a specified time frame. If a rising edge occurs within the specified time frame and the current state is maintained for a preset duration (greater than or equal to 166.7 nanoseconds and less than or equal to 447.9 nanoseconds), it is determined that a new frame of data has arrived, and the system enters the DEL state. Otherwise, the received signal is considered a glitch and can be filtered out without output, and the system enters the IDLE state. This addresses the issue of large fluctuations in the start_bit width. In this state, the IC output of the FPGA processing module is a low-level signal.

[0051] 3) DEL state, i.e., the state for judging the separator.

[0052] This state primarily determines the validity of the delimiter signal. Since the characteristics of the delimiter signals in the main frame and slave frames of the EMD message differ significantly, and they share almost no commonalities, the determination can be made based on the characteristics of the frames preceding and following the delimiter signal. Typically, in the delimiter signals of both the main and slave frames, the longest duration of consecutive high-level and consecutive low-level signals will not exceed 1.5 bits of transmission time. That is, a normal delimiter signal will not contain consecutive high-level signals exceeding 1.5 bits in length and / or consecutive low-level signals exceeding 1.5 bits in length. Considering sampling jitter and signal jitter, the preset length threshold can be set to 1.875 bits. If the delimiter signal contains consecutive high-level signals and / or consecutive low-level signals exceeding this preset length threshold, a delimiter error is determined, subsequent output ceases, and the system returns to the IDLE state. When the timing length of the DEL state is greater than or equal to the preset duration threshold, such as 8 bits of transmission time, and no error occurs, the system can transition to the END state. Here, 1.5-bit transmission duration indicates the time required to transmit 1.5 bits. The IC output by the FPGA processing module in the DEL state is the preset delay time, such as 1.25-bit transmission duration, followed by IC1.

[0053] 4) END state, i.e., waiting for the end of the frame.

[0054] In the END state, the system continuously checks for an end-of-frame indicator signal. Since the separator frame has passed, the signals received in the END state will exhibit high and low level transitions. If an end-of-frame indicator signal, an excessively long continuous low-level signal, or an excessively long high-level signal (e.g., a continuous low-level signal exceeding 1.875 bits of transmission duration) is detected, the system enters the IDLE state. In the END state, the FPGA processing module outputs IC1 with a delay of 1.25 bits of transmission duration.

[0055] Specifically, when the state machine normally transitions from the END state to the IDLE state, it can wait for the falling edge in the IDLE state to enter the START_BIT state, whereby the signal appearing after the first end marker signal of the previous EMD message signal is determined as the first start marker signal. When the state machine abnormally transitions from any of the START_BIT, DEL, or END states to the IDLE state, it is determined that the current EMD message signal contains an abnormal signal that meets the preset abnormal characteristics. In this case, the IDLE state can wait for the falling edge and determine whether a target signal consistent with the preset message signal appears, thus entering the START_BIT state. This involves using the target signal that appears after the abnormal signal and is consistent with the preset message signal to update the first start marker signal. The process of replacing the signal to be eliminated with the first preset signal to obtain the short-range message signal is the transition process between the END and IDLE states described above.

[0056] It is worth noting that during the operation of the state machine, the IC output by the FPGA processing module is IC1 with a delay of 1.25 bits (i.e., the first preset duration). Therefore, when determining whether an end-of-life marker signal has appeared in the END state, before outputting the last high-level signal of IC1 (i.e., the high-level signal in the end-of-life marker signal), the state will transition from END to IDLE. In the IDLE state, a low-level signal is output instead of continuing to output IC1, thereby filtering the high-level signal in the end-of-life marker signal. This means replacing the signal to be eliminated with the first preset signal to obtain a short-range message signal.

[0057] Example 2

[0058] Figure 4 This is a flowchart of a method for converting signal modes according to Embodiment 2 of the present invention. The technical solution of the present invention is further optimized based on the above optional technical solutions, and a specific method for converting signal modes is given.

[0059] Optionally, before determining that the current EMD message signal contains an abnormal signal that meets preset abnormal characteristics, the method further includes: determining whether the duration of the delimiter signal in the current EMD message signal is greater than a preset threshold; wherein, determining that the current EMD message signal contains an abnormal signal that meets preset abnormal characteristics includes: if the duration is greater than the preset threshold, then determining that the current EMD message signal contains an abnormal signal that meets preset abnormal characteristics. The advantage of this setting is that by determining the duration of the delimiter signal, it is possible to quickly determine whether a delimiter error has occurred.

[0060] Optionally, the step of setting the ESD message signal to a first preset signal and a second preset signal sequentially after the ESD enable signal fails to obtain a mid-range message signal includes: setting the short-range transmission bus ESD message signal to the first preset signal within a second preset time period after the ESD enable signal fails; and setting the ESD signal to the second preset signal within a third preset time period after the second preset time period has elapsed to obtain a mid-range message signal. The advantage of this setting is that by setting the duration of the first and second preset signals, it further ensures that the characteristics of the obtained mid-range message signal are consistent with the characteristics of the EMD signal.

[0061] like Figure 4 As shown in Embodiment 2 of the present invention, a method for switching signal modes specifically includes the following steps:

[0062] S201: Receive the short-distance transmission bus ESD enable signal and extend the enable time of the ESD enable signal to obtain the medium-distance enable signal.

[0063] Optionally, extending the enable time of the ESD enable signal to obtain a mid-range enable signal includes: extending the enable time of the ESD enable signal by a fourth preset duration, wherein the fourth preset duration is greater than the sum of the second preset duration and the third preset duration. The advantage of this setting is that by setting a fourth preset duration, the insufficient enable time of the mid-range enable signal due to delay is avoided.

[0064] For example, Figure 5 This is a timing diagram of the transmission process. Figure 5 In the diagram, SF1 is the ESD enable signal, OC1 is the original ESD message signal, clk_3M is the clock signal, SF1 is the mid-range enable signal, and OC1 is the mid-range message signal. Figure 5 As shown by the dashed area, if both the second preset duration and the third preset duration are the transmission duration of 1 bit character, then considering the delay, the total extension time of the ESD enable signal can be the duration corresponding to the sum of this delay and the transmission duration of 2 bits (i.e., the sum of the second preset duration and the third preset duration). Wherein, the second preset duration is the preset duration for which the short-distance transmission bus ESD message signal is set to the first preset signal, and the third preset duration is the preset duration for which the short-distance transmission bus ESD message signal is set to the second preset signal.

[0065] S202. At each first preset period of time, the original ESD message signal is sampled to obtain the sampled signal.

[0066] S203. Hold each sampled signal for a second preset period of time to obtain the ESD message signal.

[0067] S204. Within a second preset time period after the ESD enable signal fails, the short-distance transmission bus ESD message signal is set to the first preset signal.

[0068] For example, such as Figure 5 As shown in the dashed area, if the second preset duration is the transmission duration of 1 bit character and the first preset signal is a low-level signal, then within the transmission duration of 1 bit character after the ESD enable signal fails, the ESD message signal will be set to a low-level signal.

[0069] S205. After the second preset time period, within the third preset time period, the ESD signal is set to the second preset signal to obtain the medium-range message signal.

[0070] For example, such as Figure 5 As shown in the dashed area, if the third preset duration is the transmission duration of 1 bit character and the second preset signal is a high-level signal, then within the transmission duration of 1 bit character after the transmission duration of 1 bit character, the ESD signal is set to a high-level signal to obtain a medium-distance message signal.

[0071] S206. Receive EMD message signal and determine the signal that appears after the first end identifier signal of the previous EMD message signal as the first start bit identifier signal.

[0072] S207. Determine whether the duration of the separator signal in the current EMD message signal is greater than the preset threshold. If yes, proceed to step 208; otherwise, proceed to step 210.

[0073] Specifically, as mentioned above, the DEL state of the state machine can be used to determine whether the duration of the separator signal after the first start bit identifier signal is too long, i.e., whether it exceeds a preset threshold. If so, the state needs to be entered into IDLE state, i.e., step 208 is executed; otherwise, the state needs to be entered into END state, i.e., step 210 is executed. The preset threshold can be 1.875 bits of transmission time.

[0074] S208. Update the first start bit identifier signal using the target signal that appears after the abnormal signal and is consistent with the preset message signal.

[0075] Specifically, if the duration of the separator signal in the current EMD message signal exceeds a preset threshold, the state machine described above can transition from the DEL state to the IDLE state, and then to the START_BIT state. The START_BIT value redefined in the START_BIT state is the updated first start bit identifier signal. The preset message signal can be the falling edge signal in the IDLE state.

[0076] S209. The updated first start bit identifier signal is used to determine the second end identifier signal, and the signal in the second end identifier signal that is consistent with the second preset signal is determined as the signal to be eliminated. The signal to be eliminated is replaced with the first preset signal to obtain the short-range message signal.

[0077] S210. The second end identifier signal is determined using the first start bit identifier signal, and the signal in the second end identifier signal that is consistent with the second preset signal is determined as the signal to be eliminated. The signal to be eliminated is replaced with the first preset signal to obtain the short-range message signal.

[0078] The method for converting signal modes provided in this embodiment of the invention can quickly determine whether a delimiter error has occurred by determining the duration of the delimiter signal, and further ensure that the characteristics of the obtained mid-range message signal are consistent with the characteristics of the EMD signal by setting the duration of the first preset signal and the second preset signal, thereby realizing the conversion of the EMD message signal.

[0079] Example 3

[0080] Figure 7 This is a schematic diagram of a signal mode conversion device provided in Embodiment 3 of the present invention. Figure 7 As shown, the device includes: an enable signal determination module 301, a mid-range message determination module 302, and a short-range message determination module 303, wherein:

[0081] The enable signal determination module is used to receive the short-range transmission bus ESD enable signal and extend the enable time of the ESD enable signal to obtain the medium-range enable signal.

[0082] The mid-range message determination module is used to set the ESD message signal to a first preset signal and a second preset signal successively after the ESD enable signal fails, thereby obtaining a mid-range message signal. The first preset signal and the second preset signal are both determined based on the characteristics of the end identifier signal of the mid-range transmission bus EMD message signal. The mid-range message signal is used to output to the multi-function vehicle bus (MVB), and the mid-range enable signal is used to control the output of the mid-range message signal to the MVB.

[0083] The short-range message determination module is used to receive EMD message signals, determine the signal to be eliminated in the current EMD message signal by using the first end identifier signal of the previous EMD message signal and the message characteristics in the current EMD message signal, and obtain a short-range message signal by eliminating the signal to be eliminated. The signal to be eliminated is the signal in the second end identifier signal of the current EMD message signal that is consistent with the second preset signal. The short-range message signal is used to output to the MVB module in ESD mode.

[0084] The device for converting signal modes provided in this embodiment of the invention utilizes the method of extending the signal enable time and changing the message tail frame signal to make the converted ESD enable signal have the characteristics of an EMD enable signal, and to make the ESD message signal have the characteristics of an EMD message signal. It also uses the end identifier signal of the previous EMD message signal to determine the signal to be eliminated in the current EMD message signal. After eliminating the signal, the ESD message signal can be obtained. This realizes the bidirectional conversion between ESD mode signals and EMD mode signals.

[0085] Optionally, the device may also include:

[0086] The sampling signal determination module is used to sample the original ESD message signal at intervals of a first preset period before the ESD message signal is set to the first preset signal and the second preset signal, so as to obtain the sampling signal.

[0087] The message determination module is used to hold each of the sampled signals for a second preset period of time to obtain an ESD message signal.

[0088] Optional, the short-range message determination module includes:

[0089] The identification signal determination unit is used to determine the signal appearing after the first end identification signal of the previous EMD message signal as the first start bit identification signal, wherein the first start bit identification signal is the start bit identification signal in the current EMD message signal;

[0090] The update unit is configured to update the first start bit identifier signal by using a target signal that appears after the abnormal signal and is consistent with the preset message signal if it is determined that the current EMD message signal contains an abnormal signal that meets the preset abnormal characteristics. The preset message signal is determined based on the characteristics of the end identifier signal of the EMD message signal.

[0091] The signal to be eliminated determination unit is used to determine the second end identifier signal using the updated first start bit identifier signal, and to determine the signal in the second end identifier signal that is consistent with the second preset signal as the signal to be eliminated.

[0092] Optional, the short-range message determination module includes:

[0093] A signal replacement unit is used to replace the signal to be eliminated with the first preset signal to obtain a short-range message signal, wherein the output time of the short-range message signal is delayed by at least a first preset duration compared with the reception time of the current EMD message signal, and the first preset duration is longer than the duration corresponding to the second preset signal.

[0094] Optionally, the short-range message determination module also includes:

[0095] The judgment unit is used to determine whether the duration of the separator signal in the current EMD message signal is greater than a preset threshold before determining that an abnormal signal satisfying the preset abnormal characteristics appears in the current EMD message signal.

[0096] Optionally, determining that an abnormal signal satisfying preset abnormal characteristics appears in the current EMD message signal includes: if the duration is greater than the preset threshold, then determining that an abnormal signal satisfying preset abnormal characteristics appears in the current EMD message signal.

[0097] Optional, the mid-range message determination module includes:

[0098] The signal switching unit is used to set the short-distance transmission bus ESD message signal to the first preset signal within a second preset time period after the ESD enable signal fails.

[0099] The mid-range message determination unit is used to set the ESD signal to the second preset signal within a third preset time period after the second preset time period, so as to obtain the mid-range message signal.

[0100] Optionally, the enable signal determination module includes:

[0101] An enable signal determination unit is used to extend the enable time of the ESD enable signal by a fourth preset duration to obtain a mid-range enable signal, wherein the fourth preset duration is greater than the sum of the second preset duration and the third preset duration.

[0102] The device for switching signal modes provided in the embodiments of the present invention can execute the method for switching signal modes provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0103] Example 4

[0104] Figure 8 A schematic diagram of an electronic device 40 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0105] like Figure 8As shown, the electronic device 40 includes at least one processor 41 and a memory, such as a read-only memory (ROM) 42 or a random access memory (RAM) 43, communicatively connected to the at least one processor 41. The memory stores computer programs executable by the at least one processor. The processor 41 can perform various appropriate actions and processes based on the computer program stored in the ROM 42 or loaded into the RAM 43 from storage unit 48. The RAM 43 may also store various programs and data required for the operation of the electronic device 40. The processor 41, ROM 42, and RAM 43 are interconnected via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0106] Multiple components in electronic device 40 are connected to I / O interface 45, including: input unit 46, such as keyboard, mouse, etc.; output unit 47, such as various types of monitors, speakers, etc.; storage unit 48, such as disk, optical disk, etc.; and communication unit 49, such as network card, modem, wireless transceiver, etc. Communication unit 49 allows electronic device 40 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0107] Processor 41 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 41 performs the various methods and processes described above, such as methods for converting signal modes.

[0108] In some embodiments, the method for switching signal modes may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 40 via ROM 42 and / or communication unit 49. When the computer program is loaded into RAM 43 and executed by processor 41, one or more steps of the method for switching signal modes described above may be performed. Alternatively, in other embodiments, processor 41 may be configured to perform the method for switching signal modes by any other suitable means (e.g., by means of firmware).

[0109] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0110] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0111] The computer equipment provided above can be used to execute the method for converting signal modes provided in any of the above embodiments, and has corresponding functions and beneficial effects.

[0112] Example 5

[0113] In the context of this invention, a computer-readable storage medium may be a tangible medium, and the computer-executable instructions, when executed by a computer processor, are used to perform a method for switching signal modes, the method comprising:

[0114] Receive the short-range transmission bus ESD enable signal and extend the enable time of the ESD enable signal to obtain the medium-range enable signal;

[0115] After the ESD enable signal fails, the ESD message signal is set to the first preset signal and the second preset signal in sequence to obtain the mid-range message signal. The first preset signal and the second preset signal are both determined based on the characteristics of the end identifier signal of the mid-range transmission bus EMD message signal. The mid-range message signal is used to output to the multi-function vehicle bus (MVB), and the mid-range enable signal is used to control the output of the mid-range message signal to the MVB.

[0116] The system receives EMD message signals, uses the first end identifier signal of the previous EMD message signal and the message characteristics in the current EMD message signal to determine the signal to be eliminated in the current EMD message signal, and obtains a short-range message signal by eliminating the signal to be eliminated. The signal to be eliminated is the signal in the second end identifier signal of the current EMD message signal that is consistent with the second preset signal. The short-range message signal is used to output to the MVB module in ESD mode.

[0117] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by, or in conjunction with, an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0118] The computer equipment provided above can be used to execute the method for converting signal modes provided in any of the above embodiments, and has corresponding functions and beneficial effects.

[0119] It is worth noting that in the embodiments of the above-mentioned signal mode conversion device, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of the present invention.

[0120] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for converting signal modes, characterized in that, include: Receive the short-range transmission bus ESD enable signal and extend the enable time of the ESD enable signal to obtain the medium-range enable signal; After the ESD enable signal fails, the ESD message signal is successively set to a first preset signal and a second preset signal to obtain a mid-range message signal. The first preset signal is a low-level signal, and the second preset signal is a high-level signal. Both the first and second preset signals are determined based on the characteristics of the end-of-line identifier signal of the mid-range transmission bus EMD message signal, which is characterized by a low-level signal followed by a high-level signal. The mid-range message signal is used to output to the Multifunction Vehicle Bus (MVB), and the mid-range enable signal is used to control the output of the mid-range message signal to the MVB. The system receives EMD message signals, uses the first end identifier signal of the previous EMD message signal and the message characteristics in the current EMD message signal to determine the signal to be eliminated in the current EMD message signal, and obtains a short-range message signal by eliminating the signal to be eliminated. The signal to be eliminated is the signal in the second end identifier signal of the current EMD message signal that is consistent with the second preset signal. The short-range message signal is used to output to the MVB module in ESD mode.

2. The method according to claim 1, characterized in that, Before setting the ESD message signal to the first preset signal and the second preset signal sequentially, the method further includes: Every first preset period of time, the original ESD message signal is sampled to obtain the sampled signal; Each of the sampled signals is held for a second preset period of time to obtain an ESD message signal.

3. The method according to claim 1, characterized in that, The step of determining the signal to be eliminated in the current EMD message signal by utilizing the first end identifier signal of the previous EMD message signal and the message characteristics in the current EMD message signal includes: The signal appearing after the first end identifier signal of the previous EMD message signal is determined as the first start bit identifier signal, wherein the first start bit identifier signal is the start bit identifier signal in the current EMD message signal; If it is determined that the current EMD message signal contains an abnormal signal that meets the preset abnormal characteristics, then the first start bit identifier signal is updated using the target signal that appears after the abnormal signal and is consistent with the preset message signal, wherein the preset message signal is determined based on the characteristics of the end identifier signal of the EMD message signal. The updated first start bit identifier signal is used to determine the second end identifier signal, and the signal in the second end identifier signal that is consistent with the second preset signal is determined as the signal to be eliminated.

4. The method according to claim 1, characterized in that, The process of obtaining a short-range message signal by eliminating the signal to be eliminated includes: The signal to be eliminated is replaced with the first preset signal to obtain a short-range message signal, wherein the output time of the short-range message signal is delayed by at least a first preset duration compared to the reception time of the current EMD message signal, and the first preset duration is longer than the duration corresponding to the second preset signal.

5. The method according to claim 3, characterized in that, Before determining that the current EMD message signal contains an abnormal signal that meets the preset abnormal characteristics, the method further includes: Determine whether the duration of the separator signal in the current EMD message signal is greater than a preset threshold; The step of determining that the current EMD message signal contains an abnormal signal that meets preset abnormal characteristics includes: If the duration is greater than the preset threshold, then it is determined that the current EMD message signal contains an abnormal signal that meets the preset abnormal characteristics.

6. The method according to claim 1, characterized in that, After the ESD enable signal fails, the ESD message signal is successively set to a first preset signal and a second preset signal to obtain a mid-range message signal, including: Within a second preset time period after the ESD enable signal fails, the short-distance transmission bus ESD message signal is set to the first preset signal; Within a third preset time period after the second preset time period, the ESD message signal is set to the second preset signal to obtain a mid-range message signal.

7. The method according to claim 6, characterized in that, Extending the enable time of the ESD enable signal to obtain a mid-range enable signal includes: The enable time of the ESD enable signal is extended by a fourth preset duration to obtain a mid-range enable signal, wherein the fourth preset duration is greater than the sum of the second preset duration and the third preset duration.

8. A device for converting signal modes, characterized in that, include: The enable signal determination module is used to receive the short-range transmission bus ESD enable signal and extend the enable time of the ESD enable signal to obtain the medium-range enable signal. The mid-range message determination module is used to, after the ESD enable signal fails, set the ESD message signal to a first preset signal and a second preset signal sequentially to obtain a mid-range message signal. The first preset signal is a low-level signal, and the second preset signal is a high-level signal. Both the first and second preset signals are determined based on the characteristics of the end-of-line identifier signal of the mid-range transmission bus EMD message signal, which is characterized by a low-level signal followed by a high-level signal. The mid-range message signal is used to output to the multi-function vehicle bus (MVB), and the mid-range enable signal is used to control the output of the mid-range message signal to the MVB. The short-range message determination module is used to receive EMD message signals, determine the signal to be eliminated in the current EMD message signal by using the first end identifier signal of the previous EMD message signal and the message characteristics in the current EMD message signal, and obtain a short-range message signal by eliminating the signal to be eliminated. The signal to be eliminated is the signal in the second end identifier signal of the current EMD message signal that is consistent with the second preset signal. The short-range message signal is used to output to the MVB module in ESD mode.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, which enables the at least one processor to perform the method of switching signal modes according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a processor to execute the method of switching signal modes as described in any one of claims 1-7.

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