A method for synchronizing an arbitrary waveform generator

Abstract

A kind of arbitrary waveform generator synchronization method, setting delay generator outputs two-way synchronization trigger signal, two-way synchronization trigger signal is input respectively two PXIe chassis trigger signal input port, PXIe chassis is routed delay generator trigger signal to respective system trigger signal module by chassis backplane, system trigger signal module distributes external trigger signal to arbitrary waveform generator in the chassis by PXI_STAR, control computer sends the instruction of setting the ratio of external trigger signal cycle and FPGA clock cycle to arbitrary waveform generator, arbitrary waveform generator samples external trigger signal after executing the ratio setting instruction, the rising edge of external trigger signal is taken as starting point to count FPGA clock cycle, internal trigger signal is generated and recouning when the count value reaches the set ratio, arbitrary waveform generator sends waveform under the trigger of internal trigger signal after starting waveform sending, waveform synchronization between arbitrary waveform generator in two PXIe chassis is realized.

Description

Technical Field

[0001] This invention relates to the field of instrument technology, and more specifically to a synchronization method for an arbitrary waveform generator. Background Technology

[0002] In some cutting-edge scientific research fields, multiple arbitrary waveform generators need to work together. When the number of arbitrary waveform generators increases, the waveforms sent by the arbitrary waveform generators exhibit phase jitter, which is unacceptable in applications with high synchronization requirements. Therefore, providing a synchronization method for arbitrary waveform generators is a technical problem that needs to be solved. Summary of the Invention

[0003] To overcome the shortcomings of the above technologies, this invention provides a method for waveform synchronization between arbitrary waveform generators in two PXIe chassis.

[0004] The technical solution adopted by this invention to overcome its technical problems is:

[0005] A synchronization method for an arbitrary waveform generator includes the following steps:

[0006] a) Establish a system consisting of a measurement and control computer, a clock source, a delay generator, and two PXIe chassis. The clock source provides a reference clock for the delay generator and the PXIe chassis. Each PXIe chassis contains a system trigger signal module and several arbitrary waveform generators. The clocks of the system trigger signal module and the arbitrary waveform generators are synchronized with the clock used by the PXIe chassis.

[0007] b) The PXIe chassis routes the delay generator trigger signal to the system trigger signal module through the chassis backplane. The system trigger signal module distributes the external trigger signal to each arbitrary waveform generator. The arbitrary waveform generator FPGA samples the rising edge of the external trigger signal.

[0008] c) Configure the delay generator to output two synchronous trigger signals, and input the two synchronous trigger signals to the trigger signal input ports of the two PXIe chassis respectively;

[0009] d) The measurement and control computer sends a command to the arbitrary waveform generator to set the ratio of the external trigger signal period to the FPGA clock period;

[0010] e) The arbitrary waveform generator samples the external trigger signal after executing the instruction to set the ratio;

[0011] f) If the arbitrary waveform generator samples the rising edge of the external trigger signal, then proceed to step g); if the arbitrary waveform generator does not sample the rising edge of the external trigger signal, then return to step e).

[0012] g) Start counting the FPGA clock cycles for the arbitrary waveform generator;

[0013] h) When the count value of the FPGA clock cycle reaches the ratio of the external trigger signal cycle to the FPGA clock cycle, execute step i); if the count value of the FPGA clock cycle does not reach the ratio of the external trigger signal cycle to the FPGA clock cycle, return to execute step g).

[0014] i) An arbitrary waveform generator generates an internal trigger signal and recounts the FPGA clock cycles;

[0015] j) The measurement and control computer loads waveform data for the arbitrary waveform generator and starts waveform transmission;

[0016] k) The arbitrary waveform generator sends waveforms when triggered by an internal trigger signal.

[0017] Furthermore, in step a), the clock source provides a 10MHz reference clock for the delay generator and the PXIe chassis.

[0018] Furthermore, in step b), the system trigger signal module distributes external trigger signals to each arbitrary waveform generator via PXI_STAR. The arbitrary waveform generator FPGA samples the rising edge of the external trigger signal using the rising edge of a clock with a clock period of 4ns.

[0019] Furthermore, in step c), the delay generator outputs two synchronous trigger signals as square waves with a period of 200μs.

[0020] Furthermore, when it is necessary to change the internal trigger signal period of the arbitrary waveform generator, the measurement and control computer sends a command to the arbitrary waveform generator to reset the ratio of the external trigger signal period to the FPGA clock period.

[0021] The beneficial effects of this invention are as follows: A delay generator outputs two synchronous trigger signals, which are respectively input to the trigger signal input ports of two PXIe chassis. The PXIe chassis route the delay generator trigger signals to their respective system trigger signal modules via the chassis backplane. The system trigger signal modules distribute external trigger signals to the arbitrary waveform generator in their respective chassis via PXI_STAR. The measurement and control computer sends an instruction to set the ratio of the external trigger signal period to the FPGA clock period to the arbitrary waveform generator. After executing the ratio setting instruction, the arbitrary waveform generator samples the external trigger signal and counts the FPGA clock period starting from the rising edge of the external trigger signal. Whenever the count value reaches the set ratio, an internal trigger signal is generated and the counting restarts. After the arbitrary waveform generator starts waveform transmission, it transmits the waveform under the trigger of the internal trigger signal, thus achieving waveform synchronization between the arbitrary waveform generators in the two PXIe chassis. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the composition of the trigger signal correlation system of the present invention;

[0023] Figure 2 This is a schematic diagram of the synchronization method of the present invention. Detailed Implementation

[0024] The following is in conjunction with the appendix Figure 1 Appendix Figure 2 The present invention will be further described below.

[0025] A synchronization method for an arbitrary waveform generator includes the following steps:

[0026] a) Establish a system consisting of a measurement and control computer, a clock source, a delay generator, and two PXIe chassis. The clock source provides a reference clock for the delay generator and the PXIe chassis. Each PXIe chassis contains a system trigger signal module and several arbitrary waveform generators. The clocks of the system trigger signal module and the arbitrary waveform generators are synchronized with the clock used by the PXIe chassis.

[0027] b) The PXIe chassis routes the delay generator trigger signal to the system trigger signal module through the chassis backplane. The system trigger signal module distributes the external trigger signal to each arbitrary waveform generator. The arbitrary waveform generator FPGA samples the rising edge of the external trigger signal.

[0028] c) Configure the delay generator to output two synchronous trigger signals, and input the two synchronous trigger signals to the trigger signal input ports of the two PXIe chassis respectively;

[0029] d) The measurement and control computer sends a command to the arbitrary waveform generator to set the ratio of the external trigger signal period to the FPGA clock period;

[0030] e) The arbitrary waveform generator samples the external trigger signal after executing the instruction to set the ratio;

[0031] f) If the arbitrary waveform generator samples the rising edge of the external trigger signal, then proceed to step g); if the arbitrary waveform generator does not sample the rising edge of the external trigger signal, then return to step e).

[0032] g) Start counting the FPGA clock cycles for the arbitrary waveform generator;

[0033] h) When the count value of the FPGA clock cycle reaches the ratio of the external trigger signal cycle to the FPGA clock cycle, execute step i); if the count value of the FPGA clock cycle does not reach the ratio of the external trigger signal cycle to the FPGA clock cycle, return to execute step g).

[0034] i) An arbitrary waveform generator generates an internal trigger signal and recounts the FPGA clock cycles;

[0035] j) The measurement and control computer loads waveform data for the arbitrary waveform generator and starts waveform transmission;

[0036] k) The arbitrary waveform generator sends waveforms when triggered by an internal trigger signal.

[0037] The delay generator outputs two synchronous trigger signals, which are input to the trigger signal input ports of two PXIe chassis respectively. The PXIe chassis route the delay generator trigger signals to their respective system trigger signal modules through the chassis backplane. The system trigger signal modules distribute external trigger signals to the arbitrary waveform generators in their respective chassis via PXI_STAR. The measurement and control computer sends an instruction to set the ratio of the external trigger signal period to the FPGA clock period to the arbitrary waveform generator. After executing the setting ratio instruction, the arbitrary waveform generator samples the external trigger signal and counts the FPGA clock period starting from the rising edge of the external trigger signal. Whenever the count value reaches the set ratio, an internal trigger signal is generated and the counting is restarted. After the arbitrary waveform generator starts waveform transmission, it sends the waveform under the trigger of the internal trigger signal, realizing waveform synchronization between the arbitrary waveform generators in the two PXIe chassis.

[0038] Example 1:

[0039] In step a), the clock source provides a 10MHz reference clock for the delay generator and the PXIe chassis.

[0040] Example 2:

[0041] In step b), the system trigger signal module distributes external trigger signals to each arbitrary waveform generator via PXI_STAR. The arbitrary waveform generator FPGA samples the rising edge of the external trigger signal using the rising edge of a clock with a clock period of 4ns.

[0042] Example 3:

[0043] In step c), the delay generator outputs two synchronous trigger signals, which are square waves with a period of 200μs.

[0044] Example 4:

[0045] When it is necessary to change the internal trigger signal period of the arbitrary waveform generator, the measurement and control computer sends a command to the arbitrary waveform generator to reset the ratio of the external trigger signal period to the FPGA clock period.

[0046] Specifically:

[0047] Assume that PXIe chassis 1 contains two arbitrary waveform generators, AWG1 and AWG2, and PXIe chassis 2 contains two arbitrary waveform generators, AWG3 and AWG4.

[0048] The delay generator is configured to output two synchronous trigger signals. The trigger signals are square waves with a period of 200us. The trigger signals are input to the trigger signal input ports on the front panels of PXIe chassis 1 and PXIe chassis 2.

[0049] The measurement and control computer sends instructions to set the ratio of the external trigger signal period to the FPGA clock period to AWG1 and AWG2 in PXIe chassis 1 and AWG3 and AWG4 in PXIe chassis 2. The ratio is 200000÷4=50000. AWG1 and AWG2 are set first, and then AWG3 and AWG4 are set.

[0050] AWG1 receives and executes the setting ratio command, and samples the external trigger signal after the command is executed.

[0051] When AWG1 samples the rising edge of the external trigger signal, it begins counting the FPGA clock cycles, with its timing starting point being 0.

[0052] AWG2 receives and executes the setting ratio command, and samples the external trigger signal after the command is executed.

[0053] AWG2 samples the rising edge of the external trigger signal and begins counting the FPGA clock cycles.

[0054] AWG3 receives and executes the setting ratio command, and samples the external trigger signal after the command is executed.

[0055] When AWG3 samples the rising edge of the external trigger signal, it begins counting the FPGA clock cycles.

[0056] AWG4 receives and executes the setting ratio command, and samples the external trigger signal after the command is executed.

[0057] When AWG4 samples the rising edge of the external trigger signal, it begins counting the FPGA clock cycles.

[0058] Whenever the count value of the FPGA clock cycle reaches 50000, AWG1 and AWG2, as well as AWG3 and AWG4, each generate an internal trigger signal and restart the count of the FPGA clock cycle.

[0059] The measurement and control computer loads waveform data for AWG1, AWG2, AWG3, and AWG4 and starts waveform transmission.

[0060] AWG1 and AWG2, as well as AWG3 and AWG4, transmit waveforms under the triggering of their respective internal trigger signals.

[0061] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An arbitrary waveform generator synchronization method, characterized by, It comprises the following steps: a) Establishing a system composed of a measurement and control computer, a clock source, a delay generator and two PXIe chassis, the clock source providing reference clock for the delay generator and the PXIe chassis, each of the PXIe chassis containing a system trigger signal module and a plurality of arbitrary waveform generators, the clock of the system trigger signal module and the arbitrary waveform generators being synchronized to the clock used by the PXIe chassis; b) The PXIe chassis routes the delay generator trigger signal to the system trigger signal module through the chassis backplane, the system trigger signal module distributing the external trigger signal to each arbitrary waveform generator, the FPGA of the arbitrary waveform generator sampling the rising edge of the external trigger signal; c) The delay generator outputs two synchronous trigger signals, which are input into the trigger signal input ports of the two PXIe chassis respectively; d) The measurement and control computer sends a command to set the ratio of the external trigger signal period to the FPGA clock period to the arbitrary waveform generator; e) The arbitrary waveform generator samples the external trigger signal after executing the command to set the ratio; f) When the arbitrary waveform generator samples the rising edge of the external trigger signal, step g) is executed, if the arbitrary waveform generator does not sample the rising edge of the external trigger signal, step e) is executed; g) Start counting the FPGA clock period; h) When the count value of the FPGA clock period reaches the ratio of the external trigger signal period to the FPGA clock period, step i) is executed, if the count value of the FPGA clock period does not reach the ratio of the external trigger signal period to the FPGA clock period, step g) is executed; i) The arbitrary waveform generator generates an internal trigger signal and re-counts the FPGA clock period; j) The measurement and control computer loads waveform data for the arbitrary waveform generator and starts waveform transmission; k) The arbitrary waveform generator transmits the waveform under the trigger of the internal trigger signal.

2. The arbitrary waveform generator synchronization method of claim 1, wherein: In step a), the clock source provides a 10MHz reference clock for the delay generator and the PXIe chassis.

3. The arbitrary waveform generator synchronization method of claim 1, wherein: In step b), the system trigger signal module distributes the external trigger signal to each arbitrary waveform generator through PXI_STAR, and the FPGA of the arbitrary waveform generator samples the rising edge of the external trigger signal using the rising edge of a clock with a clock period of 4ns.

4. The arbitrary waveform generator synchronization method of claim 1, wherein: In step c), the delay generator outputs two synchronous trigger signals with a square wave period of 200μs.

5. The arbitrary waveform generator synchronization method of claim 1, wherein: When it is necessary to change the internal trigger signal period of the arbitrary waveform generator, the measurement and control computer sends a command to the arbitrary waveform generator to reset the ratio of the external trigger signal period to the FPGA clock period.

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