Parameter Extraction Method for Large-Signal Models Based on GaN HEMT Physical Basis for Switching

Abstract

The application discloses a kind of GaN HEMT physical base large signal model parameter extraction methods for switch, belong to semiconductor device modeling and design field, including transistor current model parameter extraction;Transistor intrinsic gate-source and gate-drain capacitance calculation;Edge capacitance model parameter extraction.The application is accurately extracted by the mode of considering the equivalent gate voltage model parameter of source-drain interaction effect under reverse bias condition, accurately characterizes the current characteristics under the condition of drain reverse bias;Using the parameter extraction method of edge capacitance bias-dependent model, the accurate characterization of deep pinch-off region nonlinear capacitance is realized, and then the precise modeling of small signal and large signal characteristics under the off state of switch device is successfully realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device modeling and design technology, and more specifically to a method for extracting parameters of a large-signal model based on GaNHEMT for switching. Background Technology

[0002] In recent years, the continuous development of communications, radar, and electronic warfare fields has placed higher demands on the power performance of RF transceiver front-end systems. As a crucial component of the front-end system, the power capacity of switches significantly impacts the overall system's power characteristics. GaN HEMTs (high-electron-mobility transistors) possess advantages such as high output power and high efficiency, making them not only widely used in high-power amplifiers but also ideal devices for ultra-high power capacity switch designs. Accurate large-signal modeling of GaN HEMT switches is crucial for promoting the engineering application of GaN HEMT switching devices in high-power capacity switch chip design.

[0003] Currently, most large-signal models for GaN switching devices are based on empirical base models, resulting in an excessive number of fitting parameters that severely impacts the efficiency of parameter extraction. The emerging physical basis modeling method for GaN HEMT transistors, which directly correlates model parameters with device fabrication characteristics, significantly reduces the number of parameters compared to empirical base models, making it an ideal model for GaN HEMT switching. However, the parameter extraction of this type of model does not consider the source-drain interleaving effect under reverse drain bias and the nonlinear capacitance effect of the deep pinch-off region, leading to insufficient model accuracy for high-power applications.

[0004] Therefore, it is urgent to propose a method for extracting parameters of the large-signal model of GaN HEMT physical basis for switching, so as to accurately characterize the source-drain interleaving effect in reverse bias state and the nonlinear capacitance effect in deep pinch-off state, thereby improving the model accuracy of physical basis switching model in high-power capacity design applications. Summary of the Invention

[0005] In view of this, the present invention provides a method for extracting parameters of a large-signal model of a GaN HEMT physical base for switching, which enables accurate characterization of the source-drain interleaving effect in the reverse bias state and the nonlinear capacitance effect in the deep pinch-off state.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A method for extracting parameters of a large-signal model of a GaN HEMT physical base for switching includes the following steps:

[0008] Multi-bias static DCIV characteristics and S-parameters were tested, and measured DCIV data and multi-bias S-parameter measured data were obtained respectively.

[0009] The parameters of the transistor current model are extracted using the source-drain interleaving effect and the measured DCIV data.

[0010] Calculate the intrinsic gate-source capacitance C of a transistor. gs and intrinsic gate-drain capacitance C gd ;

[0011] Edge capacitance model parameters are extracted based on the measured data of the multi-bias S-parameters.

[0012] Preferably, the model equation for the transistor current model is:

[0013]

[0014] Among them, I sat =Wqn s (V gs )v sat W is the gate width, q is the electron charge, and v sat n is the electron saturation velocity. s (V gs ) represents the electron surface density, l s , l d and l g These represent the gate-source spacing, gate-drain spacing, and gate length, respectively. sat This represents the maximum current of the device under the applied gate voltage, β is the order of the field-velocity relationship, and V ds E is the drain-source voltage. c The equations for the equivalent critical electric field model are as follows:

[0015] E c =(a0+a1V) gs (b0+b1T+b2T) 2 );

[0016] In the formula, a0, a1, b0, b1, and b2 are the fitting parameters, and V gs is the gate-source voltage, and T is the transistor channel temperature.

[0017] Preferably, the gate-source voltage V gs Gate-source voltage V after source-drain substitution gst The calculation yields the following formula:

[0018] V gst =V gs -(tanh(K•V ds )+1)·V ds / 2;

[0019] Wherein, K is the fitting parameter, which is extracted based on the measured DCIV data and the least squares method.

[0020] Preferably, the extraction of edge capacitance model parameters based on the measured data of the multi-bias S-parameters includes:

[0021] Parasitic parameters are extracted using S-parameters measured under cold pinch-off conditions;

[0022] Intrinsic parameters are extracted using S-parameters measured under thermal bias. These intrinsic parameters include the gate-source capacitance C. gs1 and gate-drain capacitance C gd1 ;

[0023] Make the gate-source capacitance C gs1 Subtract the intrinsic gate-source capacitance C gs The gate-drain capacitor C gd1 Subtract the intrinsic gate-drain capacitance C gs The source-end edge capacitance C under different biases was obtained respectively. fs and drain edge capacitance C fd Discrete data.

[0024] Preferably, the source-side edge capacitance model formula is:

[0025] C fs =C ofs +C ifs,max ×tanh(F×(V gs -V th ));

[0026] The formula for the drain edge capacitance model is:

[0027] C fd =C ofd +C ifd,max ×tanh(F×(V gs -V th ));

[0028] In the formula, C ofs and C ofd C represents the external capacitance at the source and the external capacitance at the drain, respectively. ifs,max and C ifs,max V represents the internal capacitance of the source and the internal capacitance of the drain, respectively. gs V is the gate-source voltage. th is the threshold voltage; F is another fitting parameter, which can be obtained by least squares fitting after removing the intrinsic channel capacitance from the capacitance extracted based on the measured S parameters.

[0029] Preferably, the extraction of edge capacitance model parameters based on the measured data of the multi-bias S-parameters further includes:

[0030] The least squares method is used, combining the source-side edge capacitance model formula, the drain-side edge capacitance model formula, and the source-side edge capacitance C. fs and drain edge capacitance C fd From discrete data, we obtain parameter C. ofs C ofd C ifs,max C ifd,max .

[0031] Preferably, the method for extracting parameters of the large-signal model using GaN HEMT physical basis for the switch further includes model verification;

[0032] Based on the large-signal equivalent circuit structure, the insertion loss / isolation (S) in the on-state and off-state is calculated. 21 Model validation was performed using power scan characteristics.

[0033] As can be seen from the above technical solution, the present invention discloses a method for extracting large-signal model parameters of GaN HEMT physical base for switching, which has the following advantages compared with the prior art:

[0034] 1. To address the problem that current physical transistor model parameter extraction does not consider the effect of source and drain bias interchange under reverse bias conditions, which leads to a decrease in model accuracy under this condition, this invention achieves accurate characterization of the current characteristics under reverse bias conditions by accurately extracting the equivalent gate voltage model parameters that take into account the source-drain interchange effect under reverse bias conditions.

[0035] 2. To address the problem that traditional physical basis capacitance model parameter extraction does not consider the nonlinearity of the edge capacitance bias in the deep pinch-off region of the device, making it difficult to apply the existing physical basis model to the modeling of switching devices, this invention proposes a parameter extraction method for the edge capacitance bias related model, which realizes the accurate characterization of the nonlinear capacitance in the deep pinch-off region, and thus successfully achieves accurate modeling of the small-signal and large-signal characteristics of the switching device in the off state. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0037] Figure 1 This is a flowchart of a method for extracting large-signal model parameters of a GaN HEMT physical base for switching according to the present invention;

[0038] Figure 2This is a comparison chart of transistor current model simulation and actual measurement provided in the embodiments of the present invention;

[0039] Figure 3 This is a diagram of the large-signal equivalent circuit topology provided in an embodiment of the present invention;

[0040] Figure 4(a) shows the invention V gs = Insertion loss / isolation at 0V (S) 21 Figure 4(b) shows a comparison between the model simulation and actual measurement of V. gs Comparison of model simulation and actual measurement of power characteristics at 0V;

[0041] Figure 5(a) shows the invention V gs = Insertion loss / isolation at -40V (S) 21 Figure 5(b) shows the comparison between the model simulation and the actual measurement of V. gs Comparison of model simulation and actual measurement of power characteristics at -40V. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] Currently, scholars both domestically and internationally have conducted extensive research on transistor switching models. However, most of these studies are based on empirical baseline models and do not consider the source-drain inter-polarization effect under reverse-biased conditions or the nonlinear capacitance effect of the deep pinch-off region. This results in the model accuracy failing to meet engineering application requirements in high-power capacity designs. Therefore, this invention provides an embodiment that accurately extracts the equivalent gate voltage model parameters considering the source-drain inter-polarization effect under reverse bias, thereby achieving accurate characterization of the drain current characteristics under reverse bias. Furthermore, by utilizing parameter extraction methods from edge capacitance bias-related models, accurate characterization of the nonlinear capacitance of the deep pinch-off region is achieved, thus successfully realizing precise modeling of the small-signal and large-signal characteristics of the switching device in the off-state.

[0044] This invention discloses a method for extracting large-signal model parameters of a GaN HEMT physical base for switching applications, such as... Figure 1 As shown, it includes the following steps:

[0045] ① Multi-bias static DCIV characteristics and S-parameter tests. Specifically, multi-bias static DCIV characteristics and S-parameter tests were performed to obtain measured DCIV data and multi-bias S-parameter measured data, respectively.

[0046] For transistors from which parameters need to be extracted, a static DC IV test is performed at room temperature (25℃) (where the gate-source bias voltage range is V). gs = -3.2~0V, drain-source bias voltage range is V ds =-4~20V) and S-parameter test (where the gate-source bias voltage range is V) gs =-40~0V, drain-source bias voltage range is V ds =0V, the S-parameter frequency range at each bias point is 0.1GHz~20GHz), and the gate-source bias voltages V are obtained for different bias points. gs and drain-source bias voltage V ds The drain-source current I under ds The characteristic curves are the static DCIV characteristic curves and the gate-source bias voltages V. gs and drain-source bias voltage V ds The S-parameters are as follows.

[0047] ② Transistor current model parameter extraction. Specifically, the parameters of the transistor current model are extracted using the source-drain interleaving effect and measured DCIV data.

[0048] In this embodiment, a GaN HEMT physical base current model based on transistor region partitioning is adopted, and its model equations are as follows:

[0049]

[0050] Where β is the order of the field-velocity relation, and this embodiment uses a second-order field-velocity relation, i.e., β = 2. sat The maximum current of the device under the applied gate voltage can be written as I. sat =Wqn s (V gs )v sat Where W is the gate width, q is the electron charge, and v sat n is the electron saturation velocity. s (V gs ) represents the electron surface density, l s , l d and l g These are the source-gate spacing, drain-gate spacing, and gate length, respectively.

[0051] E c For the equivalent critical electric field model, E can be fitted using the following fitting function. c Relationship with gate voltage and transistor channel temperature T:

[0052] E c =(a0+a1V) gs (b0+b1T+b2T) 2 );

[0053] In the formula, a0, a1, b0, b1, and b2 are fitting parameters, extracted using simple curve fitting with the least squares method; V gs and V ds These are the gate-source voltage and the drain-source voltage, respectively.

[0054] In V ds During the process of changing from a forward voltage to a reverse voltage, the source and drain of the device will be replaced, which can be equivalent to the source becoming the drain and the drain becoming the source. In order to satisfy this change, V in the above two equations gs Using the transformed gate-source voltage V gst The calculation yields the following formula:

[0055] V gst =V gs -(tanh(K·V ds )+1)·V ds / 2;

[0056] Wherein, K is the fitting parameter, which can be extracted from the measured DCIV data using the least squares method.

[0057] Substituting the model parameters obtained from the above extraction process into the transistor current model equation, we obtain the current model simulation results, which are then compared with the measured data. The results are as follows: Figure 2 As shown in the figure. The root mean square error calculation results indicate that the root mean square error of the extracted model is less than 5%.

[0058] ③ Calculate the intrinsic gate-source capacitance C of the transistor. gs and intrinsic gate-drain capacitance C gd .

[0059] The intrinsic gate-source capacitance C is calculated using the surface potential equation. gs and intrinsic gate-drain capacitance C gd :

[0060]

[0061]

[0062] Q g To calculate the gate charge using the surface potential equation, V s and V d These are the source and drain voltages, respectively. g The expression is as follows:

[0063]

[0064] Where L is the channel length, W is the gate width, and V gt For the equivalent gate voltage, C gFor the gate capacitance per unit area, V th For the threshold voltage, φ sm The surface potential at the midpoint of the channel, φ sd φ is the surface potential at the drain end. ss The surface potential at the source end.

[0065] ④ Extraction of edge capacitance model parameters.

[0066] The edge capacitance model includes the source-side edge capacitance model and the drain-side edge capacitance model, with the following formulas:

[0067] C fs =C ofs +C ifs,max ×tan(F×(V gs -V th ));

[0068] C fd =C ofd +C ifd,max ×tanh(F×(V gs -V th ));

[0069] In the formula, C ofs C ofd C ifs,max C ifd,max C is the parameter to be extracted. ofs and C ofd C represents the external capacitance at the source and the external capacitance at the drain, respectively. ifs,max and C ifd,max V represents the internal capacitance of the source and the internal capacitance of the drain, respectively. gs V is the gate-source voltage. th is the threshold voltage; F is another fitting parameter, which can be obtained by least squares fitting after removing the intrinsic channel capacitance from the capacitance extracted based on the measured S parameters.

[0070] Specifically, the above parameters can be extracted by combining the measured data of the multi-bias S-parameters in ①. First, using the cold pinch-off state (V gs =0V, V ds Parasitic parameters are extracted from S-parameters measured at 0V. (The transistor model contains parasitic parameters and intrinsic parameters. Parasitic parameters are located on the periphery of the overall model topology, while intrinsic parameters are located inside the topology and are enclosed by parasitic parameters. To obtain intrinsic parameters, for example, C...) gs1 and C gd1 First, parasitic parameters need to be extracted, and then de-embedding and stripping should be performed based on the S parameters before intrinsic parameters can be extracted to obtain C. gs1 and C gd1 Next, intrinsic parameters, including gate-source capacitance C, are extracted using S-parameters measured under thermal bias.gs1 and gate-drain capacitance C gd1 Then make the gate-source capacitance C gs1 Subtract the intrinsic gate-source capacitance C calculated in step ③ gs The source-end edge capacitance C under different biases was obtained. fs Similarly, for discrete data, the gate-drain capacitance C is... gd1 Subtract the intrinsic gate-drain capacitance C calculated in step ③ gs The drain edge capacitance C under different biases was obtained. fd The discrete data is obtained; finally, the least squares method is used, combined with the edge capacitance model formula and the discrete edge capacitance data obtained above, to extract the parameter C to be extracted. ofs , Cof d, C ifs,max C ifd,max .

[0071] ⑤ Model validation.

[0072] To further verify the radio frequency characteristic characterization capability of the switching transistor model in this invention, the following will be used: Figure 3 The large-signal equivalent circuit structure shown is embedded in commercial simulation software to calculate and verify the insertion loss / isolation (S) in the on and off states. 21 ) and power scanning characteristics.

[0073] Based on Figures 4(a) and 5(a), the model established in this embodiment can accurately characterize the insertion loss of the transistor in the on-state (bias point Vgs = 0V, Vds = 0V) and off-state (bias point Vgs = -40V, Vds = 0V), with root mean square errors of 13% and 6%, respectively. As shown in Figures 4(b) and 5(b), the established model can accurately characterize the changes in output power and gain of the transistor with input power in the on-state (bias point Vgs = 0V, Vds = 0V) and off-state (bias point Vgs = -5V, Vds = 0V), with root mean square errors of 0.06% and 0.58%, respectively.

[0074] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0075] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for extracting parameters of a large-signal model of a GaN HEMT physical base for switching, characterized in that, Includes the following steps: Multi-bias static DCIV characteristics and S-parameters were tested, and measured DCIV data and multi-bias S-parameter measured data were obtained respectively. The parameters of the transistor current model are extracted using the source-drain interleaving effect and the measured DCIV data; the model equation of the transistor current model is: ； in, I sat = Wqn s ( V gs ) v sat , q The amount of electron charge. v sat For electron saturation velocity, W For grid width, n s ( V gs () represents the electron surface density. l s , l d and l g These are the source-gate spacing, drain-gate spacing, and gate length, respectively. I sat This indicates the maximum current of the device under the applied gate voltage. Let V be the order of the field-velocity relationship. ds This is the drain-source voltage. The equations for the equivalent critical electric field model are as follows: E c = ( a 0 +a 1 V gs )( b 0 +b 1 T+b 2 T 2 )； In the formula a 0 , a 1 , b 0 , b 1 and b 2 V is the fitting parameter. gs Gate-source voltage, T This refers to the transistor channel temperature. The gate-source voltage V gs Gate-source voltage V after source-drain substitution gst The calculation yields the following formula: ； in, K These are the fitting parameters, which are extracted based on the measured DCIV data using the least squares method. Calculate the intrinsic gate-source capacitance of a transistor and intrinsic gate-drain capacitance ; The edge capacitance model parameters are extracted based on the measured data of the multi-bias S-parameters, including: Parasitic parameters are extracted using S-parameters measured under cold pinch-off conditions; Intrinsic parameters, including gate-source capacitance, are extracted using S-parameters measured under thermal bias. and gate-drain capacitance ; Make the gate-source capacitance Subtract the intrinsic gate-source capacitance The gate-drain capacitor Subtract the intrinsic gate-drain capacitance The source-end edge capacitance under different biases was obtained. and drain edge capacitance Discrete data; The formula for the source-edge capacitance model is: ； The formula for the drain edge capacitance model is: ； In the formula, and These represent the external capacitance at the source and the external capacitance at the drain, respectively. and These represent the internal capacitance of the source and the internal capacitance of the drain, respectively. Gate-source voltage, Let be the threshold voltage, and F be another fitting parameter.

2. The method for extracting parameters of a large-signal model of a GaN HEMT physical basis for switching according to claim 1, characterized in that, Extracting edge capacitance model parameters based on the measured data of the multi-bias S-parameters also includes: The least squares method is used, combining the source-side edge capacitance model formula, the drain-side edge capacitance model formula, and the source-side edge capacitance. and drain edge capacitance From discrete data, parameters are obtained. , , , .

3. The method for extracting parameters of a large-signal model of a GaN HEMT physical base for switching according to claim 1, characterized in that, The method also includes model validation; Based on the large-signal equivalent circuit structure, the model is verified by calculating the insertion loss / isolation and power sweep characteristics in the on and off states.

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