A front surface junction of a solar cell and a manufacturing method of a crystalline silicon cell

Abstract

The present application provides a method for making a front surface junction and a method for making a crystalline silicon cell, after wet processing the surface of a crystalline silicon wafer; after printing, coating or depositing a layer of boron source on the surface of the crystalline silicon, laser doping is performed to clean the excess boron source on the surface of the silicon wafer and the partial laser damage in the doped area; and then the laser damage in the laser doped area is repaired by using the high temperature in the subsequent process, and then the surface is passivated with aluminum oxide and coated with silicon nitride, and finally a layer of silver paste or silver-aluminum paste with adjusted silver-aluminum content is printed and sintered, and finally a front surface junction structure with high-quality passivation, low metal composite and low contact resistance is formed. Compared with the prior art, only the process of printing, coating or depositing boron source and laser doping is added. Considering that the laser grooving step can be omitted in the subsequent metallization, only one process of printing, coating or depositing boron source is actually added, and the process is simple, and mass production can be easily achieved.

Description

Technical Field

[0001] The present application belongs to the technical field of solar cells, and in particular, relates to a method for preparing a front surface junction by local laser doping and a method for manufacturing a crystalline silicon cell. Background Art

[0002] As the maturity of tunnel passivation contact technology continues to improve, N-type-based Topcon technology has gradually become an important way to improve efficiency and is favored by major battery manufacturers. However, due to the cost of silicon wafers, the cost of the entire battery is relatively high. As the most mainstream product at present, the P-type PERC battery has very mature technology, but due to the limitations of the battery theoretical structure, the efficiency potential has basically reached its limit, and it is difficult to improve efficiency. Considering that the cost of P-type batteries is relatively much lower and the production capacity is large, the development of P-type Topcon batteries is of great significance.

[0003] The structure of the current mainstream P-type Topcon battery is as follows Figure 1 As shown, 1: front gate line, 2. front silicon nitride layer, 3. front aluminum oxide layer, 5. silicon substrate, 6. back tunneling oxide layer, 7. phosphorus-doped polysilicon layer (N-type emitter), 8. back silicon nitride layer, 9. back silver gate line.

[0004] In this structure, the polysilicon layer is placed on the back of the cell, which effectively avoids light absorption compared to the front. At the same time, because it is placed on the back, reflectivity does not need to be considered, so the back can be polished to further increase the passivation ability. The phosphorus doping technology of polysilicon is already very mature and is easy to implement for such a structure. At the same time, the phosphorus doping step of the polysilicon on the back also forms an N-type emitter. The tunnel passivation contact technology here significantly reduces the recombination on the back.

[0005] However, there are still many shortcomings in the positive structure:

[0006] 1. The front side adopts a suede structure because of reflectivity considerations. Therefore, compared with the polished structure, the passivation effect of aluminum oxide is affected.

[0007] 2. The front side is grooved with silicon nitride laser, and aluminum paste is partially printed and sintered to form the front aluminum grid line structure. On the one hand, as the front side is a light absorption surface, the grid line blocking area must be small, and the characteristics of aluminum paste determine that the aluminum grid line must not be printed thin, because the resistivity of aluminum paste is higher. If the aluminum grid line is printed thin, it has a larger series resistance than the silver grid line, which will seriously affect the FF.

[0008] 3. When printing aluminum grid lines on the front, due to the Kirkendall effect, during the sintering and cooling process, the silicon in the aluminum-silicon alloy does not have time to return to the silicon base, and a certain number of voids will be formed. The contact resistance at the voids is significantly higher, which will affect the series resistance of the battery cell.

[0009] In summary, the front structure of the existing P-type back-junction Topcon battery has a large room for optimization. Based on this, the present invention proposes a method that can increase the front light absorption, while strengthening the quality of the front surface junction and reducing recombination. Summary of the invention

[0010] In view of the defects in the prior art, the present application proposes a method for manufacturing a front surface junction of a solar cell and a method for manufacturing a crystalline silicon cell, which can optimize the front surface passivation effect, improve the contact characteristics, and increase the short-circuit current.

[0011] Specifically, a method for manufacturing a crystalline silicon cell comprises the following steps:

[0012] S1, wet-treating the surface of the crystalline silicon wafer;

[0013] S2, printing, coating or depositing a boron source on the front side of the crystalline silicon;

[0014] S3, laser doping the printed, coated or deposited boron source to incorporate the surface boron into the silicon substrate;

[0015] S4, cleaning the laser-doped silicon wafer to remove excess boron source and at least part of the damage;

[0016] S5, depositing a tunnel oxide layer and a polysilicon layer on the polished back surface and performing phosphorus diffusion, and using the high temperature of phosphorus diffusion to perform annealing and repair treatment on some lattice defects generated by laser doping;

[0017] S6, after washing away the coating layer and the oxide layer on the surface, preparing a passivation structure layer on the surface structure;

[0018] S7, complete metallization production;

[0019] S8. Finally, high temperature sintering and hydrogen passivation treatment are performed.

[0020] Furthermore, the main components of the boron source include boric acid and tributyl borate or boron tribromide or nano-silicon boron slurry, and the boron source can be coated on the surface of the single crystal silicon substrate by spraying, spin coating, screen printing, laser transfer or other coating methods.

[0021] Furthermore, the boron source may also be a boron-containing oxide layer or other boron-containing silicate layer, which may be deposited by PECVD, LPCVD, APCVD or other diffusion furnace deposition.

[0022] Furthermore, the boron source may be printed, coated or deposited on the entire surface or in the form of grid lines consistent with the metallization pattern.

[0023] Furthermore, during laser doping, the entire surface of the boron source may be doped to form a front surface junction of the entire surface, or only local doping may be performed to form a local front surface junction.

[0024] Furthermore, the parameters of the crystalline silicon surface laser doping include: laser wavelength of 355-1064nm, laser power of 20-1000W, it can be pulsed laser or continuous laser, scanning speed of 5-50m / s, and spot size of 20-150μm.

[0025] Furthermore, the laser doped boron source forms a front surface junction with a surface doping concentration of 1E+19cm -3 ~2E+21cm -3 , junction depth ≥ 0.5μm.

[0026] Furthermore, when the laser doped boron source is of P type, the high-low junction formed on the front surface is a deep junction, which can also be called the front surface field, and the junction depth is ≥1μm. When the substrate is of N type, the front surface junction formed is a deep junction, and the junction depth is ≥1μm. After the cleaning step after laser doping to remove excess boron source and partial damage, another gas phase boron diffusion is performed to form a selective emitter on the front surface. The doping of boron atoms is difficult. Under normal conditions, it takes a long time and a lot of energy to reach 0.6-0.8μm. The laser doping proposed in this application can adjust the process to dope boron atoms to more than 1μm in a short time.

[0027] Furthermore, an in-situ doping method may be selected to prepare the back N-type emitter, and the laser damage repair of crystalline silicon may be simultaneously performed during the annealing step after the polysilicon film is deposited on the back.

[0028] Furthermore, the front surface passivation structure layer is aluminum oxide and silicon nitride coating.

[0029] Furthermore, the metallization process may not require laser grooving, and a slurry that can burn through the silicon nitride layer may be directly used.

[0030] Furthermore, the paste used in the metallization process is not simply aluminum paste, but silver paste or silver aluminum paste. The resistivity of this paste is about 1-20E-6ohm*cm, which has absolute advantages in contact resistance and line thinning. The content ratio of silver and aluminum can be adjusted to achieve a balance between cost and performance.

[0031] Compared with the prior art, this application has the following advantages:

[0032] The front surface is laser doped with a high concentration of boron atoms to form a high-low junction front surface field structure, which further hinders the movement of minority carriers (electrons) to the front surface for recombination, compensates for the reduction of passivation effect under the suede structure, and has obvious advantages in open circuit voltage.

[0033] At the same time, due to the presence of high concentration of boron atoms, boron and aluminum will co-diffusion during the slurry sintering process, which increases the thickness of the local front surface junction, enhances the passivation effect, and effectively reduces metal composites.

[0034] Because the concentration of doped boron atoms is as high as 1E+19cm -3 —2E+21cm -3 , using silver aluminum paste can fully achieve excellent ohmic contact, and high concentration of boron atoms can avoid Kirkendall voids during sintering, further reduce contact resistance and improve FF. The front surface junction is a deep junction, which can make the silver aluminum paste have a larger contact interface in the vertical depth to a greater extent, ensuring low contact resistance and small reverse leakage.

[0035] Finally, due to the characteristics of silver paste and silver aluminum paste, they naturally have absolute advantages over aluminum grid lines in terms of line thinning. Moreover, due to their lower resistivity, they can maintain excellent line resistance even when the printed line width is very thin, thus significantly improving the short-circuit current.

[0036] In summary, compared with the prior art, this application has theoretical support for improving open circuit voltage, fill factor, and short circuit current. Compared with the existing process, only the steps of printing, coating or depositing boron source and laser doping are added. Considering that the laser grooving step can be omitted in the subsequent metallization, only one step of printing, coating or depositing boron source is actually added. The process is simple and can be easily mass-produced. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0038] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0039] Figure 1 It is a schematic diagram of the structure of a P-type Topcon battery in the prior art;

[0040] Figure 2A schematic diagram of the battery structure of an embodiment of the present application;

[0041] Figure 3 This is an ECV curve diagram of the boron source after laser doping according to an embodiment of the present application;

[0042] Figure 4 This is a schematic diagram of the N-type battery structure of an embodiment of the present application;

[0043] 1: front gate line, 2. front silicon nitride layer, 3. front aluminum oxide layer, 4. P+ junction formed by laser doping, 5. silicon substrate, 6. back tunneling oxide layer, 7. phosphorus-doped polysilicon layer (N-type emitter), 8. back silicon nitride layer, 9. back silver gate line, silicon substrate 2-1, boron paste 2-2, doped area 2-3, lightly doped area 2-4, heavily doped area 2-5. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0045] The pn junction formed by reverse doping on the surface of commercial crystalline silicon solar cells is generally within 0.5μm. The front surface junction manufacturing method of the solar cell proposed in this application includes wet processing of the surface of the crystalline silicon wafer; printing, coating or depositing a boron source on the front of the crystalline silicon; laser doping of the printed, coated or deposited boron source to incorporate the surface boron into the silicon base to form a deep junction with a junction depth of ≥0.5μm, which can be optimized with the conductive paste and the surface passivation layer to form a deep junction with a junction depth of ≥0.8μm or even a junction depth of ≥1μm or more as required. The deep junction can provide a large-area contact interface between the junction area and the conductive paste to the greatest extent, ensuring that the formed high-low junction contact has the excellent characteristics of low contact resistance and small reverse leakage.

[0046] During laser doping, the entire surface of the silicon wafer may be doped with a boron source, or only local doping may be performed to form a local front surface junction structure, on which an electrode structure is correspondingly formed.

[0047] Example 1

[0048] The front surface junction manufacturing method proposed in this application is used to manufacture a P-type back junction Topcon battery. The manufacturing method of a P-type back junction front surface junction Topcon battery is as follows:

[0049] (1) Using alkaline texturing, place P-type single crystal silicon in a texturing tank to remove the damaged layer and texturing to form a pyramid texture surface with a height of 0.5μm-5μm.

[0050] (2) On the surface of crystalline silicon, a grid-line boron paste consistent with the metallization pattern is printed by screen printing. The main components of the boron paste include boric acid and tributyl borate or boron tribromide or nano-silicon boron paste.

[0051] (3) The printed boron paste is dried at a temperature of 120°C for 1 minute. Boron paste is used as a doping source and laser doping is performed. Because the boron paste is a grid-line pattern, the laser has high precision requirements. When grabbing the printed boron paste, the marking points left on the silicon wafer are positioned, and the area printed with the boron paste is laser doped. The laser wavelength used is 532nm, the laser power is 100W, the frequency is 20MHZ, the scanning speed is 18m / s, and the spot size is 100μm. A local P+ junction 4 is formed on the surface of the silicon wafer. In this embodiment, only grid-line boron paste is printed, which saves the amount of boron paste, and no front surface junction is formed in the non-metallized area.

[0052] (4) After laser doping, the surface of the silicon wafer is cleaned. On the one hand, the damage caused by laser doping is removed, and on the other hand, the boron slurry on the surface of the silicon wafer is completely cleaned to prevent the residual boron slurry on the surface from being further doped as a boron source at high temperature, resulting in uneven square resistance.

[0053] (5) After the back side is polished, a tunneling oxide layer and a polysilicon layer are deposited in an intrinsic manner, and a phosphorus diffusion method is used to prepare the back side N-type emitter. The deposition is carried out at 780-810°C for about 30-45 minutes, and the diffusion is carried out at 850-900°C for 30-45 minutes. The high temperature in this process is used to repair the internal lattice defects caused by laser doping.

[0054] (6) After cleaning and removing the coating and oxide layer on the surface, a layer of aluminum oxide is grown on the front side by atomic layer deposition. The thickness of the aluminum oxide is about 4 nm. Then, PECVD is used to complete the silicon nitride coating on the front and back sides.

[0055] (7) Laser grooving on the front side, the grooving area overlaps with the laser doping area of ​​the previous process, and then a layer of silver-aluminum paste with adjusted silver-aluminum content is printed. The resistivity of the paste is about 7-8E-6ohm*cm, which is about 50% lower than the resistivity of pure aluminum paste. The line width after printing is about 60μm, and the gate breaking condition is good.

[0056] (8) Finally, high temperature sintering and hydrogen passivation treatment are carried out. After sintering, the contact resistance is about 3-6mohm*cm 2 , the contact resistance is reduced by more than 50% compared with simple aluminum paste.

[0057] Finally, compared with the front surface of the conventional P-type back junction Topcon cell, this embodiment obtains the following Figure 3 The ECV doping curve shown in the figure shows that the concentration of boron atoms reaches 1E+20cm -3 The junction depth is about 1.65μm. With the silver-aluminum paste with adjusted silver-aluminum content, a line width of 60μm is obtained. The line resistance does not increase compared with the aluminum gate line, and even slightly decreases. The final contact resistance is also significantly lower than the contact resistance of the conventional aluminum gate line (10-15mohm*cm 2 ).

[0058] Example 2

[0059] This application proposes another method for manufacturing the front surface structure of a P-type back junction Topcon cell as follows:

[0060] (1) Using alkaline texturing, place P-type single crystal silicon in a texturing tank to remove the damaged layer and texturing to form a pyramid texture surface with a height of 0.5μm-5μm.

[0061] (2) On the surface of crystalline silicon, a borosilicate glass layer is deposited by PECVD, wherein the boron source concentration in the borosilicate glass layer is ≥1E+21cm -3 , thickness is about 100-200nm, and reaction temperature is about 150-650℃.

[0062] (3) The entire borosilicate glass layer is selectively and locally laser doped, wherein the laser used is continuous light with a wavelength of 1064nm, a laser power of 120W, a scanning speed of 20m / s, and a spot size of 100μm. A local P+ junction is formed on the surface of the silicon wafer.

[0063] (4) After laser doping, the surface of the silicon wafer is cleaned to remove the damage caused by laser doping and to remove the excess borosilicate glass layer.

[0064] (5) After the back side is polished, a tunneling oxide layer and phosphorus-doped polysilicon are deposited by in-situ doping and annealed at high temperature to prepare the N-type emitter on the back side. When the polysilicon layer is annealed and crystallized, the high temperature in the process is used to repair the internal lattice defects caused by laser doping. The crystallization temperature is 850-900°C and the time is 30-45 minutes.

[0065] (6) After cleaning and removing the coating and oxide layer on the surface, a layer of aluminum oxide is grown on the front side by atomic layer deposition. The thickness of the aluminum oxide is about 4 nm. Then, PECVD is used to complete the silicon nitride coating on the front and back sides.

[0066] (7) No laser grooving is required on the front side, and a slurry with silicon nitride burn-through capability is directly printed, wherein the slurry is a silver-aluminum paste with an adjusted silver-aluminum content, and the silver content is much higher than that of the silver-aluminum paste in Example 1. The slurry resistivity is about 2-4E-6ohm*cm, the line width after printing is about 30μm, and the gate breaking condition is good.

[0067] (8) Finally, high temperature sintering and hydrogen passivation treatment are carried out. After sintering, the contact resistance is about 2-3mohm*cm 2 .

[0068] Finally, compared with the front surface of the conventional P-type back junction Topcon cell, this embodiment also obtains Figure 3 The ECV doping curve shown in Figure 2 shows that the concentration of boron atoms reaches about 2E+20cm -3 The junction depth is about 1.8μm, and the silver-aluminum paste with adjusted silver-aluminum content is used to obtain a line width of 30μm. The line resistance is slightly lower than that of the aluminum grid line, and the final contact resistance is also significantly lower than that of the conventional aluminum grid line, which is close to the contact resistance of the silver paste.

[0069] Example 3

[0070] See the attached Figure 4 As shown in the schematic diagram of the N-type battery structure, when the front surface junction manufacturing method proposed in this application is used to manufacture an N-type Topcon battery, the manufacturing method of the N-type boron-doped selective emitter Topcon battery is as follows:

[0071] (1) Using alkali texturing, the N-type single crystal silicon substrate 2-1 is placed in a texturing tank to remove the damaged layer and texturing to form a pyramid texture surface with a height of 0.5μm-5μm.

[0072] (2) A layer of boron paste 2-2 having the same pattern as the metal grid line is printed on the surface of crystalline silicon by laser transfer. The width of the boron paste grid line is 90 μm. The main components of the boron paste include boric acid and tributyl borate or boron tribromide or nano-silicon boron paste.

[0073] (3) The printed boron paste is dried at 120°C for 1 minute. On the silicon wafer printed with boron paste, the boron paste is used as the doping source and selective doping is performed by laser. Because the boron paste is a grid-line pattern, the laser precision is required to be high. When grabbing the laser-transferred boron paste, the marking points left on the silicon wafer are positioned and the area printed with the boron paste is laser doped. The laser wavelength used is 532nm, the laser power is 100W, the frequency is 2MHZ, the scanning speed is 18m / s, and the spot size is 100μm. Doping areas 2-3 of a certain concentration are formed on the surface of the silicon wafer.

[0074] (4) After laser doping, the surface of the silicon wafer is cleaned. On the one hand, the damage caused by laser doping is removed, and on the other hand, the boron slurry on the surface of the silicon wafer is completely cleaned. The cleaning time is short. This step requires that the boron slurry be completely cleaned to avoid abnormal non-uniform square resistance in the shallow doping area during high-temperature diffusion.

[0075] (5) The cleaned silicon wafer is sent to a diffusion tube for boron vapor diffusion, wherein BCl3 is used as a diffusion source, and source deposition is performed at 850-900°C for 20 minutes, and then the temperature is raised to 1000°C for a short oxygen-free push, followed by a post-oxidation step for 90 minutes. In this step, the non-laser doped area is diffused through vapor phase to form shallow doped areas 2-4, with a square resistance of about 170 ohm and a surface concentration of about 1.2E+19 cm -3 The junction depth is about 0.6μm, and the laser doped region has a certain boron atom concentration before gas phase diffusion. After gas phase diffusion, a higher concentration heavily doped region 2-5 is formed, with a square resistance of about 100ohm and a surface concentration of about 2.6E+19cm -3 , the junction depth is about 1.2μm, forming an effective selective emitter structure.

[0076] (6) After the selective emitter is completed, a tunnel junction and front and rear surface passivation layers and an electrode structure are formed on the back of the N-type silicon wafer to complete the production of a boron-doped selective emitter N-type Topcon cell.

[0077] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0078] It should be noted that in the description of the present application, it should be understood that the terms "upper", "lower", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0079] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0080] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a crystalline silicon cell, characterized in that: The method comprises the following steps: S1, wet-treating the surface of a crystalline silicon wafer; S2, printing, coating or depositing a boron source on the front side of the crystalline silicon wafer; S3, laser doping the printed, coated or deposited boron source, doping the surface boron into the crystalline silicon, and forming a junction depth of ≥1μm; S4, cleaning the laser-doped silicon wafer to remove excess boron source and at least part of the damage; S5, depositing a tunneling oxide layer and a polysilicon layer on the polished back surface, and using the high temperature of diffusion to anneal and repair some lattice defects caused by laser doping; S6, after washing away the surface coating and oxide layer, preparing a passivation structure layer on the surface structure; S7, complete metallization; S8, finally perform high temperature sintering and hydrogen passivation treatment; finally, the front surface junction formed by laser doping boron source has a surface doping concentration of 1E+20cm -3 ~2E+21cm -3 .

2. The method for manufacturing a crystalline silicon cell according to claim 1, characterized in that: The main components of the boron source include boric acid and tributyl borate or boron tribromide or nano-silicon boron slurry, and the boron source can be coated on the surface of the single crystal silicon substrate by spraying, spin coating, screen printing, laser transfer or other coating methods.

3. The method for manufacturing a crystalline silicon cell according to claim 1, characterized in that: The boron source may also be a boron-containing oxide layer or other boron-containing silicate layer, which may be deposited by PECVD, LPCVD, APCVD or other diffusion furnace deposition.

4. The method for manufacturing a crystalline silicon cell according to claim 1, characterized in that: The boron source can be printed, coated or deposited on the entire surface or in the form of grid lines consistent with the metallization pattern.

5. The method for manufacturing a crystalline silicon cell according to claim 1, characterized in that: During laser doping, the entire surface of the boron source may be doped to form a front surface field of the entire surface, or only local doping may be performed to form a local front surface junction.

6. The method for manufacturing a crystalline silicon cell according to claim 1, characterized in that: The laser parameters of the boron source laser doping on the surface of the crystalline silicon include: laser wavelength of 355-1064nm, laser power of 20-1000W, scanning speed of 5-50m / s, and spot size of 20-150μm.

7. The method for manufacturing a crystalline silicon cell according to claim 1, characterized in that: When the substrate is P-type, the surface doping concentration of the front surface junction formed by the laser doped boron source is 1E+20cm -3 ~2E+21cm -3 ; or the substrate is N-type, and a laser-doped boron source forms a pn junction on the surface of the silicon wafer.

8. The method for manufacturing a crystalline silicon cell according to claim 1, characterized in that: When the substrate is of N-type, after the cleaning step after laser doping to remove excess boron source and partial damage, another gas phase boron diffusion is performed to form a selective emitter on the front surface.

9. The method for manufacturing a crystalline silicon cell according to claim 1, characterized in that: Laser damage repair of crystalline silicon can be performed simultaneously during the annealing step after the polysilicon film is deposited on the back side.

10. The method for manufacturing a crystalline silicon cell according to claim 1, characterized in that: The paste used in the metallization process is silver paste or silver aluminum paste, and the resistivity of the paste is about 1-20E-6ohm*cm.

11. The method for manufacturing a crystalline silicon cell according to claim 1, characterized in that: In step S7, laser grooving is not performed, and a slurry that can burn through the passivation structure layer is directly used.

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