Driving method of display panel and display device

Abstract

A driving method and display device for a display panel (100) are disclosed. The driving method includes: acquiring raw display data of the current display frame (S100); when a first driving mode is determined to be adopted, loading a first gate scan signal (GA1_1~GA12_1) onto the gate lines (GA, GA1~GA12) in the display panel (100), and loading a data voltage onto the data lines (DA, DA1~DA7) in the display panel (100) according to the target display data obtained after deleting part of the raw display data, so that each sub-pixel in the display panel (100) is charged with a data voltage (S200); wherein, for at least one gate line (GA1, ..., GA12) among the multiple gate lines (GA, GA1~GA12), the first gate scan signal (GA1_1~GA12_1) loaded on the gate line (GA1, ..., GA12) is... The effective pulse of the first gate scan signal (GA1_1, ..., GA12_1) loaded on the adjacent previous gate line (GA1, ..., GA12) has a first overlap duration (t11, t12, t13, t14, ...) and the effective pulse of the first gate scan signal (GA1_1, ..., GA12_1) loaded on the adjacent previous gate line (GA1, ..., GA12) has a second overlap duration (t21, t22, t23, t24, ...) and the effective pulse of the first gate scan signal (GA1_1, ..., GA12_1) loaded on the adjacent next gate line (GA1, ..., GA12) has a second overlap duration (t21, t22, t23, t24, ...). The first overlap duration (t11, t12, t13, t14, ...) is different from the second overlap duration (t21, t22, t23, t24, ...).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving method for a display panel and a display device. Background Technology

[0002] Displays such as Liquid Crystal Displays (LCDs) and Organic Light-Emitting Diodes (OLEDs) typically consist of multiple pixel units. Each pixel unit can include multiple subpixels of different colors. By controlling the brightness of each subpixel, the desired colors are mixed to display a color image. Summary of the Invention

[0003] The display panel driving method provided in this disclosure includes:

[0004] Get the raw display data of the current display frame;

[0005] When the first driving mode is determined to be adopted, a first gate scan signal is loaded onto the gate lines in the display panel, and according to the target display data obtained after deleting part of the original display data, a data voltage is loaded onto the data lines in the display panel so that each sub-pixel in the display panel is charged with data voltage.

[0006] The display panel includes multiple gate lines. For at least one of the multiple gate lines, the effective pulse of the first gate scan signal loaded on the gate line has a first overlap duration with the effective pulse of the first gate scan signal loaded on the adjacent previous gate line, and the effective pulse of the first gate scan signal loaded on the gate line has a second overlap duration with the effective pulse of the first gate scan signal loaded on the adjacent next gate line. The first overlap duration and the second overlap duration are different.

[0007] In some examples, for the 2kth gate line, the first overlap duration corresponding to the 2kth gate line is less than the second overlap duration; where k is an integer greater than 0.

[0008] In some examples, the first overlap duration corresponding to the 2kth gate line is the same; and / or, the second overlap duration corresponding to the 2kth gate line is the same.

[0009] In some examples, the second overlap duration corresponding to the 2kth gate line is an even multiple of the first overlap duration.

[0010] In some examples, for the 2m+1th gate line, the first overlap duration corresponding to the 2m+1th gate line is greater than the second overlap duration; where m is an integer greater than 0.

[0011] In some examples, the first overlap duration corresponding to the 2m+1th gate line is the same; and / or, the second overlap duration corresponding to the 2m+1th gate line is the same.

[0012] In some examples, the first overlap duration corresponding to the 2m+1th gate line is an even multiple of the second overlap duration.

[0013] In some examples, the display panel includes multiple gate lines, with at least four gate lines forming a gate line group. The start time of the effective pulse of the first gate scan signal loaded on the gate line in each gate line group appears sequentially in the order of the first gate line, the third gate line, the second gate line, and the fourth gate line in the gate line group.

[0014] In some examples, the display panel includes multiple subpixel rows; the multiple subpixel rows are divided into multiple subpixel row groups, and each subpixel row group includes subpixel rows spaced N times apart; N is an integer greater than 0;

[0015] The target display data includes the display data corresponding to each sub-pixel in one of the sub-pixel row groups.

[0016] In some examples, the plurality of subpixel row groups include a first subpixel row group and a second subpixel row group; the first subpixel row group includes an odd-numbered subpixel row, and the second subpixel row group includes an even-numbered subpixel row;

[0017] The current display frame is the odd-numbered display frame in a series of consecutive displays, and the target display data includes display data corresponding to each sub-pixel in the first sub-pixel row group or the second sub-pixel row group; and / or,

[0018] The current display frame is the even-numbered display frame in a series of consecutive displays, and the target display data includes the display data of each sub-pixel in the first sub-pixel row group or the second sub-pixel row group.

[0019] In some examples, two adjacent sub-pixels in the same column share a single data voltage.

[0020] In some examples, loading a first gate scan signal onto the gate lines in the display panel includes:

[0021] Multiple different first clock signals are input to the gate drive circuit in the display panel so that the valid pulses in the first clock signals are loaded onto the gate lines as valid pulses of the first gate scan signal.

[0022] In some examples, the gate drive circuit includes multiple shift register units; each shift register unit has an output clock signal terminal.

[0023] The multiple different first clock signals are divided into three clock signal groups; in the three adjacent gate groups, the output clock signal terminal of the shift register unit corresponding to the first gate group is coupled to the first clock signal group in the three clock signal groups, the output clock signal terminal of the shift register unit corresponding to the second gate group is coupled to the second clock signal group in the three clock signal groups, and the output clock signal terminal of the shift register unit corresponding to the third gate group is coupled to the third clock signal group in the three clock signal groups.

[0024] In some examples, the plurality of different first clock signals include 12 first clock signals; the 12 first clock signals are divided into three clock signal groups, and in each clock signal group, the effective pulse of each first clock signal appears sequentially in the order of the first first clock signal, the third first clock signal, the second first clock signal, and the fourth first clock signal in the clock signal group;

[0025] The start time of the effective pulse of the fourth first clock signal in the first clock signal group is earlier than the start time of the effective pulse of the first first clock signal in the second clock signal group; and the start time of the effective pulse of the fourth first clock signal in the second clock signal group is earlier than the start time of the effective pulse of the first first clock signal in the third clock signal group.

[0026] In some examples, within the same group of clock signals, the first clock signal and the fourth clock signal are out of phase.

[0027] In some examples, the clock signals appearing in the same sequence in the first clock signal group and the second clock signal group are 2π / 3 out of phase; the clock signals appearing in the same sequence in the second clock signal group and the third clock signal group are 2π / 3 out of phase.

[0028] In some examples, the shift register unit also has a control clock signal terminal; in three adjacent gate line groups, the control clock signal terminal of the shift register unit corresponding to the first gate line group is coupled to the first first clock signal in the first clock signal group, the control clock signal terminal of the shift register unit corresponding to the second gate line group is coupled to the first first clock signal in the second clock signal group, and the control clock signal terminal of the shift register unit corresponding to the third gate line group is coupled to the first first clock signal in the third clock signal group.

[0029] In some examples, the shift register unit also has a control clock signal terminal; the driving method further includes:

[0030] While inputting multiple different first clock signals to the gate driving circuit in the display panel, multiple different first clock control signals are also input to the control clock signal terminal of the gate driving circuit.

[0031] In some examples, in three adjacent gate line groups, the control clock signal terminal of the shift register unit corresponding to the first gate line group is coupled to the first first clock control signal among the plurality of different first clock control signals, the control clock signal terminal of the shift register unit corresponding to the second gate line group is coupled to the second first clock control signal among the plurality of different first clock control signals, and the control clock signal terminal of the shift register unit corresponding to the third gate line group is coupled to the third first clock control signal among the plurality of different first clock control signals;

[0032] The first first clock control signal has the same timing as the first first clock signal in the first clock signal group, the second first clock control signal has the same timing as the first first clock signal in the second clock signal group, and the third first clock control signal has the same timing as the first first clock signal in the third clock signal group.

[0033] In some examples, when the second driving mode is determined to be adopted, a second gate scan signal is loaded onto the gate lines in the display panel, and a data voltage is directly loaded onto the data lines according to the original display data so that each sub-pixel in the display panel is charged with data voltage;

[0034] The difference between the start times of the effective pulses of the second gate scan signal loaded on each of the two adjacent gate lines is the same.

[0035] The display device provided in this disclosure includes:

[0036] Display panel;

[0037] The controller is configured to acquire the raw display data of the current display frame; when it is determined that the first driving mode is adopted, a first gate scan signal is loaded onto the gate lines in the display panel, and according to the target display data obtained after deleting part of the raw display data, a data voltage is loaded onto the data lines in the display panel so that each sub-pixel in the display panel is charged with data voltage.

[0038] The display panel includes multiple gate lines. For at least one of the multiple gate lines, the effective pulse of the first gate scan signal loaded on the gate line has a first overlap duration with the effective pulse of the first gate scan signal loaded on the adjacent previous gate line, and the effective pulse of the first gate scan signal loaded on the gate line has a second overlap duration with the effective pulse of the first gate scan signal loaded on the adjacent next gate line. The first overlap duration and the second overlap duration are different.

[0039] In some examples, the controller includes: a system controller and a timing controller;

[0040] The system controller is configured to acquire the raw display data of the current display frame; when it is determined that the first driving mode is adopted, the target display data obtained by deleting part of the raw display data is sent to the timing controller;

[0041] The timing controller is configured to send the received target display data to the source drive circuit;

[0042] The source drive circuit is configured to apply a data voltage to the data lines in the display panel based on the received target display data.

[0043] In some examples, the controller includes: a system controller and a timing controller;

[0044] The system controller is configured to acquire the raw display data of the current display frame and send the raw display data to the timing controller.

[0045] The timing controller is configured to send the target display data obtained by deleting part of the original display data to the source drive circuit when it is determined that the first driving mode is adopted.

[0046] The source drive circuit is configured to apply a data voltage to the data lines in the display panel based on the received target display data.

[0047] In some examples, the controller includes: a system controller and a timing controller;

[0048] The system controller is configured to acquire the raw display data of the current display frame and send the raw display data to the timing controller.

[0049] The timing controller is configured to send the received raw display data to the source drive circuit;

[0050] The source drive circuit is configured to, when the first drive mode is determined, process the original display data by deleting part of the data to obtain target display data, and apply data voltage to the data lines in the display panel according to the target display data.

[0051] In some examples, the display panel further includes: a gate driving circuit for receiving a plurality of different first clock signals; the plurality of different first clock signals are divided into three clock signal groups;

[0052] The gate drive circuit includes multiple shift register units; wherein, one of the shift register units is coupled to multiple adjacent gate lines;

[0053] In each of the three adjacent shift register units, the output clock signal of the first shift register unit is coupled to the first clock signal group of the three clock signal groups, the output clock signal of the second shift register unit is coupled to the second clock signal group of the three clock signal groups, and the output clock signal of the third shift register unit is coupled to the third clock signal group of the three clock signal groups.

[0054] In some examples, in every three adjacent shift register units, the control clock signal terminal of the first shift register unit is coupled to the first first clock signal in the first clock signal group, the control clock signal terminal of the second shift register unit is coupled to the first first clock signal in the second clock signal group, and the control clock signal terminal of the third shift register unit is coupled to the first first clock signal in the third clock signal group.

[0055] In some examples, in each of the three adjacent shift register units, the control clock signal terminal of the first shift register unit is coupled to the first first clock control signal among a plurality of different clock control signals, the control clock signal terminal of the second shift register unit is coupled to the second first clock control signal among the plurality of different clock control signals, and the control clock signal terminal of the third shift register unit is coupled to the third first clock control signal among the plurality of different clock control signals.

[0056] In some examples, the shift register unit includes:

[0057] A pull-up circuit is connected to the input signal terminal, the main pull-up node, and the pull-down node of the shift register unit. The pull-up circuit is configured to provide the signal from the input signal terminal to the main pull-up node and pull down the potential of the main pull-up node under the control of the potential of the pull-down node.

[0058] A control circuit, connected to the main pull-up node and the pull-down node, is configured to control the potential of the pull-down node based on the potential of the main pull-up node;

[0059] A cascaded circuit is connected to the main pull-up node, the pull-down node, and the shift register unit, and to the control clock signal terminal. The cascaded circuit is configured to provide the signal of the control clock signal terminal to the main pull-up node under the control of the potential of the main pull-up node, and to pull down the potential of the pull-down node under the control of the potential of the pull-down node.

[0060] N output circuits are respectively connected to the input signal terminal, the pull-down node, and the N output clock signal terminals, N sub-pull-up nodes, and N output signal terminals of the shift register unit. The nth output circuit is connected to the input signal terminal, the pull-down node, the nth output signal terminal, and the nth sub-pull-up node, and is configured to input the signal from the input signal terminal to the nth sub-pull-up node, provide the signal from the nth output clock signal terminal to the nth output signal terminal under the control of the potential of the nth sub-pull-up node, and pull down the potential of the nth output signal terminal under the control of the potential of the pull-down node. N is an integer greater than 1, and n is an integer where 1 ≤ n ≤ N.

[0061] In some examples, the display panel further includes: a gate driving circuit for receiving a plurality of different first clock signals; the plurality of different first clock signals are divided into three clock signal groups;

[0062] The gate drive circuit includes multiple shift register units; wherein, one of the shift register units is coupled to a gate line;

[0063] A group of adjacent shift register units is formed as a unit group; in each group of three adjacent units, the output clock signal of the shift register unit of the first unit group is coupled to the first clock signal group of the three clock signal groups, the output clock signal of the shift register unit of the second unit group is coupled to the second clock signal group of the three clock signal groups, and the output clock signal of the shift register unit of the third unit group is coupled to the third clock signal group of the three clock signal groups.

[0064] In some examples, the shift register unit includes: a pull-up circuit connected to the input signal terminal, a main pull-up node, and a pull-down node of the shift register unit, wherein the pull-up circuit is configured to provide the signal from the input signal terminal to the main pull-up node and pull down the potential of the main pull-up node under the control of the potential of the pull-down node;

[0065] A control circuit, connected to the main pull-up node and the pull-down node, is configured to control the potential of the pull-down node based on the potential of the main pull-up node;

[0066] A cascaded circuit is connected to the main pull-up node, the pull-down node, and the shift register unit, and to the control clock signal terminal. The cascaded circuit is configured to provide the signal of the control clock signal terminal to the main pull-up node under the control of the potential of the main pull-up node, and to pull down the potential of the pull-down node under the control of the potential of the pull-down node.

[0067] The output circuit is connected to the input signal terminal, the pull-down node, the output clock signal terminal of the shift register unit, the pull-up node, and the output signal terminal, respectively. The output circuit is configured to input the signal from the input signal terminal to the pull-up node, provide the signal from the output clock signal terminal to the output signal terminal under the control of the potential of the pull-up node, and pull down the potential of the output signal terminal under the control of the potential of the pull-down node.

[0068] In some examples, the display panel includes:

[0069] Multiple sub-pixels; wherein the multiple sub-pixels are divided into multiple sub-pixel groups; each sub-pixel group includes two adjacent sub-pixels in the same row;

[0070] Multiple gate lines; wherein each sub-pixel row corresponds to two gate lines; one sub-pixel in the sub-pixel group is coupled to one of the two gate lines, and the other sub-pixel is coupled to the other of the two gate lines.

[0071] Multiple data lines; wherein, a column of sub-pixels is set between each pair of adjacent data lines, and for each pair of adjacent data lines, the first data line is coupled to a column of sub-pixels in the column of sub-pixels between the two data lines that is closer to the second data line, and the second data line is coupled to a column of sub-pixels in the column of sub-pixels between the two data lines that is closer to the first data line. Attached Figure Description

[0072] Figure 1 These are some structural schematic diagrams of the display device in the embodiments of this disclosure;

[0073] Figure 2 These are some structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0074] Figure 3 These are some structural schematic diagrams of the gate drive circuit in the embodiments of this disclosure;

[0075] Figure 4These are some signal timing diagrams from embodiments of this disclosure;

[0076] Figure 5 Here are some other signal timing diagrams in the embodiments of this disclosure;

[0077] Figure 6 This is a schematic diagram of the structure of some sub-pixels in the display panel of the present disclosure embodiment;

[0078] Figure 7 This is a schematic diagram of some other structures of sub-pixels in the display panel of the present disclosure embodiment;

[0079] Figure 8 These are some more signal timing diagrams in the embodiments of this disclosure;

[0080] Figure 9 This is a schematic diagram of some of the structures of sub-pixels in the display panel of the present disclosure embodiment;

[0081] Figure 10 This is a flowchart of the driving method for the display panel in the embodiments of this disclosure;

[0082] Figure 11 These are some more signal timing diagrams in the embodiments of this disclosure;

[0083] Figure 12 These are some more signal timing diagrams in the embodiments of this disclosure;

[0084] Figure 13 This is a schematic diagram of some of the structures of sub-pixels in the display panel of the present disclosure embodiment;

[0085] Figure 14 These are some more signal timing diagrams in the embodiments of this disclosure;

[0086] Figure 15 These are some other structural schematic diagrams of the gate drive circuit in the embodiments of this disclosure;

[0087] Figure 16 These are some structural schematic diagrams of the shift register unit in the embodiments of this disclosure;

[0088] Figure 17 These are schematic diagrams illustrating some specific structures of the shift register unit in the embodiments of this disclosure;

[0089] Figure 18 These are further schematic diagrams of the gate drive circuit in the embodiments of this disclosure;

[0090] Figure 19 These are some more signal timing diagrams in the embodiments of this disclosure;

[0091] Figure 20These are some more signal timing diagrams in the embodiments of this disclosure;

[0092] Figure 21 These are further schematic diagrams of the gate drive circuit in the embodiments of this disclosure;

[0093] Figure 22 These are further structural schematic diagrams of the shift register unit in the embodiments of this disclosure;

[0094] Figure 23 These are further schematic diagrams illustrating specific structures of the shift register unit in the embodiments of this disclosure. Detailed Implementation

[0095] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0096] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “coupled” or “connected” are not limited to physical or mechanical coupling, but can include electrical coupling, whether direct or indirect.

[0097] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual scale and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals are used throughout to denote the same or similar elements or elements having the same or similar functions.

[0098] In some embodiments of this disclosure, see Figure 1 as well as Figure 2As shown, the display device may include a display panel 100 and a controller 400. The display panel 100 may include a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes multiple sub-pixels of different colors. Each sub-pixel may include a transistor and a pixel electrode. For example, a pixel unit may include red, green, and blue sub-pixels, allowing for color mixing of red, green, and blue to achieve color display. Alternatively, a pixel unit may also include red, green, blue, and white sub-pixels, allowing for color mixing of red, green, blue, and white to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here. The following explanation uses a pixel unit including red, green, and blue sub-pixels as an example.

[0099] In some embodiments of this disclosure, such as Figure 1 and Figure 2 As shown, there are multiple gate lines GA (e.g., GA1 to GA12), multiple data lines DA (e.g., DA1, DA2, DA3, DA4, DA5, DA6, DA7), a gate drive circuit 110, and a source drive circuit 120. The gate drive circuit 110 is coupled to the gate lines GA (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7, GA8, GA9, GA10, GA11, GA12), and the source drive circuit 120 can be coupled to the data lines DA (e.g., DA1, DA2, DA3, DA4, DA5, DA6, DA7). The controller 400 can input control signals to the gate driving circuit 110, thereby causing the gate driving circuit 110 to input signals to the gate lines GA (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7, GA8, GA9, GA10, GA11, GA12) to drive the gate lines GA (e.g., GA1, GA2, GA3, GA4, GA5, GA6, GA7, GA8, GA9, GA10, GA11, GA12). Furthermore, the controller 400 can acquire the original display data of the image to be displayed in the current display frame and send the required display data to the source driving circuit 120. This allows the source driving circuit 120 to apply data voltage to the data lines DA (e.g., DA1, DA2, DA3, DA4, DA5, DA6, DA7) in the display panel according to the display data, thereby charging the sub-pixels and enabling the image display function.

[0100] In some embodiments of this disclosure, multiple source drive circuits 120 may be configured, with different source drive circuits coupled to different data lines. For example, as... Figure 1As shown, there can be two source drive circuits 120, with one source drive circuit 120 coupling to half of the data lines and the other source drive circuit 120 coupling to the other half. Of course, there can also be three, four, or more source drive circuits 120, which can be designed and determined according to the actual application requirements, and are not limited here. Additionally, it should be noted that the gate drive circuit can be as follows... Figure 1 The configuration shown is arranged on both sides of the display panel, and the gate driving circuits on both sides of the display panel can jointly drive the same gate line, or the gate driving circuit can be arranged only on one side of the display panel, or the gate driving circuits on both sides of the display panel can drive the gate lines corresponding to different rows of sub-pixels respectively. In this embodiment of the present disclosure, the number of gate driving circuits arranged in the display panel is not further limited, and can be determined according to the actual application requirements.

[0101] In some embodiments of this disclosure, each pixel unit includes multiple sub-pixels. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, allowing for color mixing of red, green, and blue to achieve color display. Alternatively, a pixel unit may include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, also allowing for color mixing of red, green, blue, and white to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0102] In some embodiments of this disclosure, such as Figure 2 As shown, each sub-pixel row can correspond to two gate lines, thus enabling the pixel array in this disclosure to be arranged in a double-gate structure, reducing the number of data lines by half (i.e., including data lines between adjacent columns of pixels, and excluding data lines between adjacent columns of pixels). For example, the first sub-pixel row corresponds to gate lines GA1 and GA2, the second sub-pixel row corresponds to gate lines GA3 and GA4, the third sub-pixel row corresponds to gate lines GA5 and GA6, the fourth sub-pixel row corresponds to gate lines GA7 and GA8, the fifth sub-pixel row corresponds to gate lines GA9 and GA10, and the sixth sub-pixel row corresponds to gate lines GA11 and GA12.

[0103] In some embodiments of this disclosure, multiple subpixels in the display panel can be divided into multiple subpixel groups, and each subpixel group may include two adjacent subpixels in the same row. Furthermore, one subpixel in a subpixel group is coupled to one of two corresponding gate lines, and the other subpixel is coupled to the other of the two corresponding gate lines. For example, as... Figure 2As shown, in the first sub-pixel row, red sub-pixel R11 and green sub-pixel G11 can be grouped into one sub-pixel group, with red sub-pixel R11 coupled to gate line GA2 and green sub-pixel G11 coupled to gate line GA1. Blue sub-pixel B11 and red sub-pixel R12 can be grouped into one sub-pixel group, with blue sub-pixel B11 coupled to gate line GA2 and red sub-pixel R12 coupled to gate line GA1. Green sub-pixel G12 and blue sub-pixel B12 can be grouped into one sub-pixel group, with green sub-pixel G12 coupled to gate line GA2 and blue sub-pixel B12 coupled to gate line GA1. Red sub-pixel R13 and green sub-pixel G13 can be grouped into one sub-pixel group, with red sub-pixel R13 coupled to gate line GA2 and green sub-pixel G13 coupled to gate line GA1. Blue subpixel B13 and red subpixel R14 can be grouped into one subpixel group, with blue subpixel B13 coupled to gate line GA2 and red subpixel R14 coupled to gate line GA1. Green subpixel G14 and blue subpixel B14 can be grouped into one subpixel group, with green subpixel G14 coupled to gate line GA2 and blue subpixel B14 coupled to gate line GA1.

[0104] Furthermore, in the second sub-pixel row, red sub-pixel R21 and green sub-pixel G21 can be grouped into one sub-pixel group, with red sub-pixel R21 coupled to gate line GA4 and green sub-pixel G21 coupled to gate line GA3. Similarly, blue sub-pixel B21 and red sub-pixel R22 can be grouped into one sub-pixel group, with blue sub-pixel B21 coupled to gate line GA4 and red sub-pixel R22 coupled to gate line GA3. Likewise, green sub-pixel G22 and blue sub-pixel B22 can be grouped into one sub-pixel group, with green sub-pixel G22 coupled to gate line GA4 and blue sub-pixel B22 coupled to gate line GA3. Finally, red sub-pixel R23 and green sub-pixel G23 can be grouped into one sub-pixel group, with red sub-pixel R23 coupled to gate line GA4 and green sub-pixel G23 coupled to gate line GA3. Blue subpixel B23 and red subpixel R24 can be grouped into one subpixel group, with blue subpixel B23 coupled to gate line GA4 and red subpixel R24 coupled to gate line GA3. Similarly, green subpixel G24 and blue subpixel B24 can be grouped into one subpixel group, with green subpixel G24 coupled to gate line GA4 and blue subpixel B24 coupled to gate line GA3. The remaining subpixel rows can be divided into subpixel groups in the same way, which will not be elaborated upon here.

[0105] In some embodiments of this disclosure, a column of sub-pixels can be set between every two adjacent data lines. For each pair of adjacent data lines, the first data line is coupled to a column of sub-pixels in the column of sub-pixels between the two data lines, closer to the second data line. In other words, the sub-pixels adjacent to the first data line are coupled to the second data line, and the second data line is coupled to a column of sub-pixels in the column of sub-pixels between the two data lines, closer to the first data line. Alternatively, the sub-pixels adjacent to the second data line are coupled to the first data line. Alternatively, two adjacent columns of sub-pixels can be set between two adjacent data lines. This can reduce the power consumption of the source drive circuit. For example, as shown... Figure 2 As shown, a first sub-pixel group LX1 can be set between data lines DA1 and DA2, a second sub-pixel group LX2 can be set between data lines DA2 and DA3, a third sub-pixel group LX3 can be set between data lines DA3 and DA4, a fourth sub-pixel group LX4 can be set between data lines DA4 and DA5, a fifth sub-pixel group LX5 can be set between data lines DA5 and DA6, and a sixth sub-pixel group LX6 can be set between data lines DA6 and DA7.

[0106] In some embodiments of this disclosure, for the first column of sub-pixel group LX1: data line DA1 is coupled to a column of sub-pixels (i.e., green sub-pixels G11 to G61) in the first column of sub-pixel group LX1 that is closest to data line DA2. Data line DA2 is coupled to a column of sub-pixels (i.e., red sub-pixels R11 to R61) in the first column of sub-pixel group LX1 that is closest to data line DA1.

[0107] In some embodiments of this disclosure, for the second column of sub-pixel group LX2: data line DA2 is coupled to a column of sub-pixels in the second column of sub-pixel group LX2 that is closest to data line DA3 (i.e., red sub-pixels R12 to R62). Data line DA3 is coupled to a column of sub-pixels in the second column of sub-pixel group LX2 that is closest to data line DA2 (i.e., blue sub-pixels B11 to B61).

[0108] The other sub-pixel groups are coupled to the data lines in the same way, which will not be elaborated here.

[0109] It should be noted that the display panel in this embodiment can be a liquid crystal display panel. Exemplarily, a liquid crystal display panel generally includes an upper substrate and a lower substrate of a cell, and liquid crystal molecules encapsulated between the upper and lower substrates. When displaying an image, a voltage difference exists between the data voltage applied to the pixel electrode of each sub-pixel and the common electrode voltage on the common electrode. This voltage difference can form an electric field, causing the liquid crystal molecules to deflect under the influence of this electric field. Because different intensities of electric fields cause different degrees of deflection of the liquid crystal molecules, the transmittance of the sub-pixels differs, enabling the sub-pixels to achieve different grayscale brightness levels, thereby realizing image display. Of course, the display panel in this embodiment can be an OLED display panel, and is not limited thereto.

[0110] Grayscale, in general, divides the brightness variation between the darkest and brightest points into several parts to facilitate screen brightness control. For example, a displayed image may consist of three colors: red, green, and blue. Each color can be displayed at different brightness levels, and combinations of different brightness levels of red, green, and blue can form different colors. For instance, if an LCD panel has a grayscale bit depth of 6 bits, then red, green, and blue each have 64 (i.e., 2^34) grayscale values. 6 There are 64 gray levels, with gray values ​​ranging from 0 to 63. If the LCD panel has an 8-bit gray level, then red, green, and blue each have 256 (i.e., 2^6) gray levels. 8 There are 256 gray levels, with gray values ​​ranging from 0 to 255. If the LCD panel has a 10-bit grayscale, then red, green, and blue each have 1024 (i.e., 2^35) gray levels. 10 There are 1024 gray levels, with gray values ​​ranging from 0 to 1023. If the LCD panel has a 12-bit grayscale, then red, green, and blue each have 4096 (i.e., 2^3) gray levels. 12 There are 4096 gray levels, with gray values ​​ranging from 0 to 4093.

[0111] Taking a sub-pixel as an example, Vcom represents the common electrode voltage. When the data voltage input to the pixel electrode of the sub-pixel is greater than the common electrode voltage Vcom, the liquid crystal molecules at that sub-pixel will be positively polarized, and the corresponding polarity of the data voltage in that sub-pixel will be positive. When the data voltage input to the pixel electrode of the sub-pixel is less than the common electrode voltage Vcom, the liquid crystal molecules at that sub-pixel will be negatively polarized, and the corresponding polarity of the data voltage in that sub-pixel will be negative. For example, the common electrode voltage can be 8.3V. If a data voltage of 8.8V to 16V is input to the pixel electrode of the sub-pixel SPX, the liquid crystal molecules at that sub-pixel SPX will be positively polarized, and the data voltage of 8.8V to 16V will be the corresponding positive polarity data voltage. If a data voltage of 0.6V to 7.8V is input to the pixel electrode of the sub-pixel SPX, the liquid crystal molecules at that sub-pixel SPX will be negatively polarized, and the data voltage of 0.6V to 7.8V will be the corresponding negative polarity data voltage. For example, taking an 8-bit grayscale of 0-255 as an example, if a data voltage of 16V is input to the pixel electrode of a sub-pixel SPX, the sub-pixel SPX can achieve the maximum grayscale value (i.e., grayscale value 255) brightness using a positive polarity data voltage. If a data voltage of 0.6V is input to the pixel electrode of a sub-pixel SPX, the sub-pixel SPX can achieve the maximum grayscale value (i.e., grayscale value 255) brightness using a negative polarity data voltage. It should be noted that there may be a voltage difference between the data voltage for grayscale value 0 and the common electrode voltage. For example, if the common electrode voltage is 8.3V, the data voltage corresponding to the positive polarity of grayscale value 0 could be 8.8V, and the data voltage corresponding to the negative polarity of grayscale value 0 could be 7.8V. In this way, by controlling the polarity of the sub-pixel, the display panel can achieve frame flipping, column flipping, row flipping, dot flipping, etc.

[0112] Of course, the data voltage for 0 grayscale value and the common electrode voltage can also be the same. In practical applications, this can be determined according to the needs of the application, and is not limited here.

[0113] In some embodiments of this disclosure, the display panel may further include multiple clock signal lines, and these multiple clock signal lines are coupled to a gate driving circuit. This allows a corresponding clock signal to be input to the gate driving circuit via the clock signal lines, thereby loading a signal onto the gate line. For example, as... Figure 3As shown, the display panel may further include 12 clock signal lines CK1 to CK12, which are coupled to the gate driving circuit 120. Exemplarily, if the display panel uses a single gate driving circuit design, the gate driving circuit can be coupled to 12 clock signal lines CK1 to CK12. If the display panel uses a dual gate driving circuit design, each gate driving circuit can be coupled to 12 clock signal lines CK1 to CK12. It should be noted that... Figure 3 This example uses 12 clock signal lines. In practical applications, the specific number of clock signal lines can be determined according to the actual application requirements and is not limited here. For example, it can also be other numbers of clock signal lines that are multiples of 2, such as 2, 4, 6, 8, 10, etc.

[0114] In some embodiments of this disclosure, the original display data of the current display frame can be obtained. When it is determined that a second driving mode is adopted, a second gate scan signal can be loaded onto the gate lines in the display panel, and a data voltage can be directly loaded onto the data lines according to the original display data, so that each sub-pixel in the display panel is charged with data voltage. The difference between the start times of the effective pulses of the second gate scan signals loaded on each adjacent two gate lines is the same. For example, the controller 400 can input multiple different second clock signals to the gate driving circuit in the display panel via clock signal lines, so that the effective pulses in the second clock signals are loaded onto the gate lines as effective pulses of the second gate scan signals, thereby driving the gate lines in the display panel row by row to turn on the transistors in the sub-pixels row by row. Furthermore, the controller 400 can acquire the original display data of the image to be displayed in the current display frame (this original display data includes a digital signal form of a data voltage carrying a corresponding grayscale value for each sub-pixel. In this way, the grayscale value corresponding to each sub-pixel can be determined based on the display data of each sub-pixel. In this way, the target data voltage corresponding to each sub-pixel can be obtained based on the determined grayscale value). The controller then sends the original display data to the source drive circuit 120, so that the source drive circuit 120 applies a data voltage to the data lines in the display panel according to the received original display data, thereby charging the sub-pixels and charging each sub-pixel with the corresponding target data voltage, thus realizing the image display function.

[0115] In some embodiments of this disclosure, the controller 400 may include a timing controller 200 and a system controller 300. The system controller 300 can acquire the original display data of the image to be displayed (the original display data includes a digital signal form of a data voltage carrying a corresponding grayscale value for each sub-pixel) in the current display frame. When it is determined that a second driving mode is to be adopted, the system controller 300 sends the original display data (i.e., the original display data includes a digital signal form of a data voltage carrying a corresponding grayscale value for each sub-pixel) to the timing controller 200. The timing controller 200 inputs multiple different second clock signals to the gate driving circuit in the display panel through clock signal lines, so as to load the effective pulses in the second clock signals as effective pulses of the second gate scan signal onto the gate lines, thereby driving the gate lines in the display panel line by line to turn on the transistors in the sub-pixels line by line. Furthermore, the timing controller 200 sends the original display data to the source drive circuit 120, so that the source drive circuit 120 applies data voltage to the data lines in the display panel according to the received original display data, thereby charging the sub-pixels and charging each sub-pixel with the corresponding target data voltage to realize the screen display function.

[0116] In some embodiments of this disclosure, in the second driving mode, Figure 3 The signal timing diagram corresponding to the gate drive circuit shown is as follows: Figure 4 As shown in the diagram. Here, ck1_2 represents the second clock signal input to clock signal line CK1, ck2_2 represents the second clock signal on clock signal line CK2, ck3_2 represents the second clock signal on clock signal line CK3, ck4_2 represents the second clock signal on clock signal line CK4, ck5_2 represents the second clock signal on clock signal line CK5, ck6_2 represents the second clock signal on clock signal line CK6, ck7_2 represents the second clock signal on clock signal line CK7, ck8_2 represents the second clock signal on clock signal line CK8, ck9_2 represents the second clock signal on clock signal line CK9, ck10_2 represents the second clock signal on clock signal line CK10, ck11_2 represents the second clock signal on clock signal line CK11, and ck12_2 represents the second clock signal on clock signal line CK12.

[0117] Furthermore, signal ga1_2 represents the second gate scan signal output by gate drive circuit 110 to gate line GA1, signal ga2_2 represents the second gate scan signal output by gate drive circuit 110 to gate line GA2, ... signal ga10_2 represents the second gate scan signal output by gate drive circuit 110 to gate line GA10, signal ga11_2 represents the second gate scan signal output by gate drive circuit 110 to gate line GA11, and signal ga12_2 represents the second gate scan signal output by gate drive circuit 110 to gate line GA12. Taking the pulse corresponding to the high level as the effective pulse of the second gate scan signal as an example, the difference between the start times of the effective pulses of second gate scan signals ga1_2 and ga2_2 is the same as the difference between the start times of the effective pulses of second gate scan signals ga2_2 and ga3_2. The difference between the start times of the effective pulses of second gate scan signals ga2_2 and ga3_2 is the same as the difference between the start times of the effective pulses of second gate scan signals ga3_2 and ga4_2. The difference between the start times of the effective pulses of the second gate scan signals ga4_2 and ga5_2 is the same as the difference between the start times of the effective pulses of the second gate scan signals ga5_2 and ga6_2. The rest follow the same pattern and will not be elaborated further here.

[0118] Furthermore, the gate driving circuit includes multiple shift register units; each shift register unit has an output clock signal terminal; the output clock signal terminal is coupled to a clock signal line for receiving a second clock signal. Exemplarily, the gate driving circuit 110 outputs the first high level of the second clock signal ck1_2 to the gate line GA1 to generate a high level in signal ga1_2. The gate driving circuit 110 outputs the first high level of the second clock signal ck2_2 to the gate line GA2 to generate a high level in signal ga2_2. ... The gate driving circuit 110 outputs the first high level of the second clock signal ck10_2 to the gate line GA10 to generate a high level in signal ga10_2. The gate driving circuit 110 outputs the first high level of the second clock signal ck11_2 to the gate line GA11 to generate a high level in signal ga11_2. The gate driving circuit 110 outputs the first high level of the second clock signal ck12_2 to the gate line GA12 to generate a high level in signal ga12_2. In other words, the pulse corresponding to the high level of the second clock signal can be considered its valid pulse, and the pulse corresponding to the low level can be considered its invalid pulse. Of course, when the shift register outputs the low level of the second clock signal to generate the low-level signal that controls the transistor to turn on, the pulse corresponding to the low level of the second clock signal can be considered its valid pulse, and the pulse corresponding to the high level can be considered its invalid pulse.

[0119] Combination Figures 2 to 6As shown, taking the sub-pixel coupled by data line DA2 as an example, the process of the display panel displaying the image when using the second driving mode can be described as follows.

[0120] In the data charging phase T11, the signal ga1_2 transmitted on the gate line GA1 is at a high level, the transistor in the red sub-pixel R12 is turned on, and the data voltage D1 corresponding to the display data of the red sub-pixel R12 is applied to the data line DA2, so that the red sub-pixel R12 inputs the target data voltage D1. Also, in the data charging phase T11, the signal ga2_2 on the gate line GA2 is at a high level, and the transistor in the red sub-pixel R11 is turned on. The data voltage D1 is simultaneously input to the red sub-pixel R11 as a pre-charging voltage to pre-charge the red sub-pixel R11. Furthermore, in the data charging phase T11, the signal ga3_2 on the gate line GA3 is at a high level, the transistor in the red sub-pixel R22 is turned on, and the data voltage D1 is simultaneously input to the red sub-pixel R22 as a pre-charging voltage to pre-charge the red sub-pixel R22.

[0121] During the data charging phase T12, the signal ga2_2 transmitted on gate line GA2 is at a high level, and the transistor in the red sub-pixel R11 is turned on. The data voltage D2 corresponding to the display data of the red sub-pixel R11 is applied to data line DA2, so that the red sub-pixel R11 receives the target data voltage D2. Also during the data charging phase T12, the signal ga3_2 on gate line GA3 is at a high level, the transistor in the red sub-pixel R22 is turned on, and the data voltage D2 is simultaneously input to the red sub-pixel R22 as a pre-charging voltage to pre-charge the red sub-pixel R22. Furthermore, during the data charging phase T12, the signal ga4_2 on gate line GA4 is at a high level, the transistor in the red sub-pixel R21 is turned on, and the data voltage D2 is simultaneously input to the red sub-pixel R21 as a pre-charging voltage to pre-charge the red sub-pixel R21.

[0122] During the data charging phase T13, the signal ga3_2 transmitted on gate line GA3 is at a high level, and the transistor in the red sub-pixel R22 is turned on. The data voltage D3 corresponding to the display data of the red sub-pixel R22 is applied to data line DA2, so that the red sub-pixel R22 receives the target data voltage D3. Also during the data charging phase T13, the signal ga4_2 on gate line GA4 is at a high level, the transistor in the red sub-pixel R21 is turned on, and the data voltage D3 is simultaneously input to the red sub-pixel R21 as a pre-charging voltage to pre-charge the red sub-pixel R21. Furthermore, during the data charging phase T13, the signal ga5_2 on gate line GA5 is at a high level, the transistor in the red sub-pixel R32 is turned on, and the data voltage D3 is simultaneously input to the red sub-pixel R32 as a pre-charging voltage to pre-charge the red sub-pixel R32.

[0123] During the data charging phase T14, the signal ga4_2 transmitted on gate line GA4 is at a high level, and the transistor in the red sub-pixel R21 is turned on. The data voltage D4 corresponding to the display data of the red sub-pixel R21 is applied to data line DA2, so that the red sub-pixel R21 receives the target data voltage D4. Also during the data charging phase T14, the signal ga5_2 on gate line GA5 is at a high level, the transistor in the red sub-pixel R32 is turned on, and the data voltage D4 is simultaneously input to the red sub-pixel R32 as a pre-charging voltage to pre-charge the red sub-pixel R32. Furthermore, during the data charging phase T14, the signal ga6_2 on gate line GA6 is at a high level, the transistor in the red sub-pixel R31 is turned on, and the data voltage D4 is simultaneously input to the red sub-pixel R31 as a pre-charging voltage to pre-charge the red sub-pixel R31.

[0124] During the data charging phase T15, the signal ga5_2 transmitted on gate line GA5 is at a high level, and the transistor in the red sub-pixel R32 is turned on. The data voltage D5 corresponding to the display data of the red sub-pixel R32 is applied to data line DA2, so that the red sub-pixel R32 inputs the target data voltage D5. Also during the data charging phase T15, the signal ga6_2 on gate line GA6 is at a high level, the transistor in the red sub-pixel R31 is turned on, and the data voltage D5 is simultaneously input to the red sub-pixel R31 as a pre-charging voltage to pre-charge the red sub-pixel R31. Furthermore, during the data charging phase T15, the signal ga7_2 on gate line GA7 is at a high level, the transistor in the red sub-pixel R42 is turned on, and the data voltage D5 is simultaneously input to the red sub-pixel R42 as a pre-charging voltage to pre-charge the red sub-pixel R42.

[0125] During the data charging phase T16, the signal ga6_2 transmitted on gate line GA6 is at a high level, and the transistor in the red sub-pixel R31 is turned on. The data voltage D6 corresponding to the display data of the red sub-pixel R31 is applied to data line DA2, so that the red sub-pixel R31 receives the target data voltage D6. Also during the data charging phase T16, the signal ga7_2 on gate line GA7 is at a high level, the transistor in the red sub-pixel R42 is turned on, and the data voltage D6 is simultaneously input to the red sub-pixel R42 as a pre-charging voltage to pre-charge the red sub-pixel R42. Furthermore, during the data charging phase T16, the signal ga8_2 on gate line GA8 is at a high level, the transistor in the red sub-pixel R41 is turned on, and the data voltage D6 is simultaneously input to the red sub-pixel R41 as a pre-charging voltage to pre-charge the red sub-pixel R41.

[0126] During the data charging phase T17, the signal ga7_2 transmitted on gate line GA7 is at a high level, and the transistor in the red sub-pixel R42 is turned on. The data voltage D7 corresponding to the display data of the red sub-pixel R42 is applied to data line DA2, so that the red sub-pixel R42 inputs the target data voltage D7. Also during the data charging phase T17, the signal ga8_2 on gate line GA8 is at a high level, the transistor in the red sub-pixel R41 is turned on, and the data voltage D7 is simultaneously input to the red sub-pixel R41 as a pre-charging voltage to pre-charge the red sub-pixel R41. This pre-charging is also performed on subsequent red sub-pixels.

[0127] During the data charging phase T18, the signal ga8_2 transmitted on the gate line GA8 is at a high level, and the transistor in the red sub-pixel R41 is turned on. The data voltage D8 corresponding to the display data of the red sub-pixel R41 is applied to the data line DA2, so that the red sub-pixel R41 receives the target data voltage D8. This also pre-charges subsequent red sub-pixels.

[0128] The implementation methods for the remaining sub-pixels are similar, until all sub-pixels in the entire display panel are charged with the target data voltage, which will not be elaborated here.

[0129] In some embodiments of this disclosure, the original display data of the current display frame can be obtained. When it is determined that the first driving mode is adopted, data voltage can be applied to the data lines in the display panel according to the original display data corresponding to the odd-numbered row sub-pixels in the current display frame, so that each sub-pixel in the display panel is charged with data voltage. Furthermore, the sub-pixels in the same column of adjacent rows receive the same data voltage. For example, taking the sub-pixels coupled to data line DA2 as an example, such as... Figure 7As shown, data voltage D1 represents the target data voltage corresponding to red sub-pixel R12, data voltage D2 represents the target data voltage corresponding to red sub-pixel R11, data voltage D5 represents the target data voltage corresponding to red sub-pixel R32, and data voltage D6 represents the target data voltage corresponding to red sub-pixel R31. Specifically, red sub-pixels R12 and R22 need to input data voltage D1 as their target data voltage. Red sub-pixels R11 and R21 need to input data voltage D2 as their target data voltage. Red sub-pixels R32 and R42 need to input data voltage D5 as their target data voltage. Red sub-pixels R31 and R41 need to input data voltage D6 as their target data voltage.

[0130] However, when determining to adopt the first driving mode, if a second gate scan signal is applied to the gate lines in the display panel, combined with Figure 7 and Figure 8 As shown, taking the sub-pixels coupled to data line DA2 as an example, when driving the gate lines line by line using the second gate scan signal, red sub-pixels R12 and R11 both input data voltage D1 as the target data voltage. Red sub-pixels R22 and R21 both input data voltage D2 as the target data voltage. Red sub-pixels R32 and R31 both input data voltage D5 as the target data voltage. Red sub-pixels R42 and R41 both input data voltage D6 as the target data voltage. Therefore, combined with Figure 7 and Figure 9 As shown, Figure 7 This is a schematic diagram of the target data voltage required as input for the red sub-pixel. Figure 8 This diagram illustrates the actual target data voltage input to the red sub-pixel when the gate lines are driven row by row using the second gate scan signal. It shows that using the second gate scan signal to drive the gate lines row by row will cause a misalignment of the target data voltage charged into the sub-pixel.

[0131] To address the issue of data voltage misalignment, embodiments of this disclosure provide a driving method for a display panel, such as... Figure 10 As shown, it may include the following steps:

[0132] S100: Obtain the raw display data of the current display frame.

[0133] For example, the acquired raw display data may include a digital signal form of a data voltage carrying a corresponding grayscale value, corresponding to each sub-pixel. This allows the grayscale value corresponding to each sub-pixel to be determined based on the display data of each sub-pixel. The target data voltage corresponding to each sub-pixel can then be obtained based on the determined grayscale value.

[0134] S200: When the first driving mode is determined to be adopted, a first gate scan signal is applied to the gate lines in the display panel, and a data voltage is applied to the data lines in the display panel according to the target display data obtained after deleting part of the original display data, so that each sub-pixel in the display panel is charged with data voltage.

[0135] In some embodiments of this disclosure, for at least one of a plurality of gate lines, the effective pulse of the first gate scan signal loaded on the gate line has a first overlap duration with the effective pulse of the first gate scan signal loaded on the adjacent previous gate line, and the effective pulse of the first gate scan signal loaded on the gate line has a second overlap duration with the effective pulse of the first gate scan signal loaded on the adjacent next gate line, wherein the first overlap duration and the second overlap duration are different. For example, in conjunction with... Figure 11As shown, signal ga1_1 represents the first gate scan signal applied to gate line GA1, signal ga2_1 represents the first gate scan signal applied to gate line GA2, signal ga3_1 represents the first gate scan signal applied to gate line GA3, signal ga4_1 represents the first gate scan signal applied to gate line GA4, signal ga5_1 represents the first gate scan signal applied to gate line GA5, signal ga6_1 represents the first gate scan signal applied to gate line GA6, signal ga7_1 represents the first gate scan signal applied to gate line GA7, and signal ga8_1 represents the first gate scan signal applied to gate line GA8. The high level represents its effective pulse. For example, for gate line GA2, the high level of signal ga2_1 and the high level of signal ga1_1 have a first overlap duration t11, and the high level of signal ga2_1 and the high level of signal ga3_1 have a second overlap duration t21. The first overlap duration t11 and the second overlap duration t21 for gate line GA2 are different. For gate line GA3, the high level of signal ga3_1 and the high level of signal ga2_1 have a first overlap duration t12, and the high level of signal ga3_1 and the high level of signal ga4_1 have a second overlap duration t22. The first overlap duration t12 and the second overlap duration t22 for gate line GA3 are different. For gate line GA4, the high level of signal ga4_1 and the high level of signal ga3_1 have a first overlap duration t13, and the high level of signal ga4_1 and the high level of signal ga5_1 have a second overlap duration t23. The first overlap duration t13 and the second overlap duration t23 for gate line GA4 are different. For gate line GA5, the high level of signal ga5_1 and the high level of signal ga4_1 have a first overlap duration t14, and the high level of signal ga5_1 and the high level of signal ga6_1 have a second overlap duration t24. The first overlap duration t14 and the second overlap duration t24 for gate line GA5 are different. The same applies to the others, and will not be elaborated upon here.

[0136] The display panel driving method provided in this embodiment, when determining to adopt the first driving mode, can obtain target display data by deleting some data from the original display data, and apply data voltage to the data lines in the display panel according to the target display data, so that each sub-pixel in the display panel is charged with data voltage. This can increase the refresh rate and improve display smoothness, especially for high-resolution products, this driving mode can increase the charging rate of the display panel. Furthermore, by making the first overlap duration different from the second overlap duration, the generation of data voltage dislocations can be reduced, improving the display effect.

[0137] In some embodiments of this disclosure, the controller can acquire the original display data of the current display frame; when determining to adopt the first driving mode, it can load a first gate scan signal onto the gate lines in the display panel, and load data voltage onto the data lines in the display panel according to the target display data obtained after deleting part of the original display data, so that each sub-pixel in the display panel is charged with data voltage. Exemplarily, the controller may include a system controller and a timing controller; wherein the system controller can acquire the original display data of the current display frame; when determining to adopt the first driving mode, it sends the target display data obtained after deleting part of the original display data to the timing controller. Furthermore, the timing controller can send the received target display data to the source driving circuit. And, the source driving circuit can load data voltage onto the data lines in the display panel according to the received target display data. This can reduce the amount of display data transmitted, reduce power consumption, and increase the transmission rate.

[0138] For example, the controller may include a system controller and a timing controller; wherein the system controller can acquire the raw display data of the current display frame; and when it is determined that a first driving mode is to be adopted, it sends the raw display data to the timing controller. Furthermore, when it is determined that the first driving mode is to be adopted, the timing controller can send the target display data obtained by deleting some data from the raw display data to the source driving circuit. And, the source driving circuit can apply data voltage to the data lines in the display panel according to the received target display data. This can reduce the amount of display data transmitted, reduce power consumption, and increase the transmission rate.

[0139] For example, the controller may include a system controller and a timing controller; wherein, when determining that a first driving mode is adopted, the system controller may acquire the raw display data of the current display frame and send the raw display data to the timing controller. Furthermore, when determining that the first driving mode is adopted, the timing controller may send the received raw display data to the source driving circuit. And, when determining that the first driving mode is adopted, the source driving circuit may, after deleting some data from the raw display data to obtain target display data, apply data voltage to the data lines in the display panel according to the target display data. This can reduce the amount of display data transmitted, reduce power consumption, and increase the transmission rate.

[0140] For example, the system controller can be a system-on-a-chip (SoC). Of course, in practical applications, the system controller can also adopt other implementable structures, which are not limited here.

[0141] In some embodiments of the present disclosure, for the 2k-th gate line, the first overlap duration corresponding to the 2k-th gate line is less than the second overlap duration; where k is an integer greater than 0. Exemplarily, in combination with Figure 2 and Figure 11 as shown, the 2nd gate line GA2 corresponds to the first overlap duration t11 and the second overlap duration t21, and t11 < t21. The 4th gate line GA4 corresponds to the first overlap duration t13 and the second overlap duration t23, and t13 < t23. The rest can be analogized in the same way and will not be elaborated here.

[0142] In some embodiments of the present disclosure, the first overlap durations corresponding to the 2k-th gate lines can be made the same. Exemplarily, in combination with Figure 2 and Figure 11 as shown, the first overlap duration t11 corresponding to the 2nd gate line GA2 and the first overlap duration t13 corresponding to the 4th gate line GA4 are the same. The rest can be analogized in the same way and will not be elaborated here.

[0143] In some embodiments of the present disclosure, the second overlap durations corresponding to the 2k-th gate lines can be made the same. Exemplarily, in combination with Figure 2 and Figure 11 as shown, the second overlap duration t21 corresponding to the 2nd gate line GA2 and the second overlap duration t23 corresponding to the 4th gate line GA4 are the same. The rest can be analogized in the same way and will not be elaborated here.

[0144] In some embodiments of the present disclosure, the second overlap duration corresponding to the 2k-th gate line can be made an even multiple of the first overlap duration. Exemplarily, in combination with Figure 2 and Figure 11 as shown, the second overlap duration corresponding to the 2k-th gate line can be made 2 times the first overlap duration. For example, both the first overlap duration t11 and the first overlap duration t13 are of a duration of 1H (H represents the duration for a row of sub-pixels to be filled with the target data voltage). The second overlap durations t21 and t23 can both be of a duration of 2H. The rest can be analogized in the same way and will not be elaborated here. Of course, in practical applications, the specific multiple of the second overlap duration corresponding to the 2k-th gate line to the first overlap duration can be determined according to the requirements in practical applications, and is not limited here.

[0145] In some embodiments of the present disclosure, for the (2m + 1)-th gate line, the first overlap duration corresponding to the (2m + 1)-th gate line is greater than the second overlap duration; where m is an integer greater than 0. Exemplarily, in combination with Figure 2 and Figure 11 as shown, the 3rd gate line GA3 corresponds to the first overlap duration t12 and the second overlap duration t22, and t

[0146] In some embodiments of this disclosure, the first overlap duration corresponding to the 2m+1th gate line can be made the same. For example, in combination with... Figure 2 and Figure 11 As shown, the first overlap duration t12 corresponding to the third gate line GA3 is the same as the first overlap duration t14 corresponding to the fifth gate line GA5. The rest are similar and will not be elaborated here.

[0147] In some embodiments of this disclosure, the second overlap duration corresponding to the 2m+1th gate line can be made the same. For example, in combination with... Figure 2 and Figure 11 As shown, the second overlap duration t22 corresponding to the third gate line GA3 is the same as the second overlap duration t24 corresponding to the fifth gate line GA5. The rest are deduced similarly and will not be elaborated here.

[0148] In some embodiments of this disclosure, the first overlap duration corresponding to the 2m+1th gate line can be an even multiple of the second overlap duration. For example, in combination with... Figure 2 and Figure 11 As shown, the first overlap duration corresponding to the 2m+1th gate line can be twice the second overlap duration. For example, the first overlap durations t12 and t14 can both be 2 hours. The second overlap durations t22 and t24 can both be 1 hour. The rest can be deduced similarly and will not be elaborated further. Of course, in practical applications, the specific multiple of the first overlap duration to the second overlap duration corresponding to the 2m+1th gate line can be determined according to the specific requirements of the application; this is not limited here.

[0149] In some embodiments of this disclosure, at least four gate lines can be grouped into a gate line group. The start time of the effective pulse of the first gate scan signal loaded on the gate lines in each gate line group appears sequentially in the order of the first gate line, the third gate line, the second gate line, and the fourth gate line in the gate line group. For example, in conjunction with... Figure 2 and Figure 11As shown, a gate line group consists of four gate lines. Gate lines GA1–GA4 form the first gate line group, GA5–GA8 the second, and GA9–GA12 the third. In the first gate line group, GA1 is the first gate line, GA3 the third, GA2 the second, and GA4 the fourth. Specifically, the start time of the effective pulse of the first gate scan signal ga1_1 on gate line GA1 occurs first, followed by the start time of the effective pulse of the first gate scan signal ga3_1 on gate line GA3, then the start time of the effective pulse of the first gate scan signal ga2_1 on gate line GA2, and finally the start time of the effective pulse of the first gate scan signal ga4_1 on gate line GA4. In the second gate line group, gate line GA5 is the first gate line, gate line GA7 is the third gate line, gate line GA6 is the second gate line, and gate line GA8 is the fourth gate line. That is, the start time of the effective pulse of the first gate scan signal ga5_1 on gate line GA5 appears first, followed by the start time of the effective pulse of the first gate scan signal ga7_1 on gate line GA7, then the start time of the effective pulse of the first gate scan signal ga6_1 on gate line GA6, and finally the start time of the effective pulse of the first gate scan signal ga8_1 on gate line GA8. The rest follow the same logic and will not be elaborated further here.

[0150] For example, the subpixel array in the display panel is arranged into multiple subpixel rows and multiple subpixel columns. The multiple subpixel rows can be divided into multiple subpixel row groups, and each subpixel row group includes subpixel rows spaced N times apart; N is an integer greater than 0. The target display data includes the display data corresponding to each subpixel in a subpixel row group.

[0151] For example, N=1 can be used, then each subpixel row group includes subpixel rows spaced one subpixel row apart. That is, multiple subpixel row groups can include a first subpixel row group and a second subpixel row group. The first subpixel row group includes the odd-numbered subpixel row, and the second subpixel row group includes the even-numbered subpixel row. For example, combining... Figure 2 As shown, the first sub-pixel row group includes: the first sub-pixel row R11~B14, the third sub-pixel row R31~B34, and the fifth sub-pixel row R51~B54. The second sub-pixel row group includes the second sub-pixel row R21~B24, the fourth sub-pixel row R41~B44, and the sixth sub-pixel row R61~B64.

[0152] For example, the current display frame can be the odd-numbered display frame in a series of consecutive displays, and the target display data can include the display data of each sub-pixel in the corresponding first sub-pixel row group. That is, when the current display frame is the odd-numbered display frame in a series of consecutive displays, the target display data can include the original display data of each sub-pixel in the corresponding odd-numbered row of sub-pixels. For example, combined with Figure 2 As shown, when the current display frame is the odd-numbered display frame in a series of consecutive displays, the target display data may include the original display data of the corresponding sub-pixels R11 to B14, R31 to B34, and R51 to B54.

[0153] For example, the current display frame can be the odd-numbered display frame in a series of consecutive displays, and the target display data can include the display data of each sub-pixel in the corresponding second sub-pixel row group. That is, when the current display frame is the odd-numbered display frame in a series of consecutive displays, the target display data can include the original display data of each sub-pixel in the corresponding even-numbered row of sub-pixels. For example, combined with Figure 2 As shown, when the current display frame is the odd-numbered display frame in a series of consecutive displays, the target display data may include the original display data of the corresponding sub-pixels R21 to B24, R41 to B44, and R61 to B64.

[0154] For example, the current display frame can be the even-numbered display frame in a series of consecutive displays, and the target display data can include the display data of each sub-pixel in the corresponding first sub-pixel row group. That is, when the current display frame is the even-numbered display frame in a series of consecutive displays, the target display data can include the original display data of each sub-pixel in the corresponding odd-numbered row of sub-pixels. For example, combined with Figure 2 As shown, when the current display frame is the even-numbered display frame in a series of consecutive displays, the target display data may include the original display data of the corresponding sub-pixels R11 to B14, R31 to B34, and R51 to B54.

[0155] For example, the current display frame can be the even-numbered display frame in a series of consecutive displays, and the target display data can include the display data of each sub-pixel in the corresponding second sub-pixel row group. That is, when the current display frame is the even-numbered display frame in a series of consecutive displays, the target display data can include the original display data of each sub-pixel in the corresponding even-numbered row of sub-pixels. For example, combined with Figure 2 As shown, when the current display frame is the even-numbered display frame in a series of consecutive displays, the target display data may include the original display data of the corresponding sub-pixels R21 to B24, R41 to B44, and R61 to B64.

[0156] For example, two adjacent sub-pixels in the same column share a single data voltage. For instance, when the current display frame is an even-numbered display frame in a series of consecutive displays, the target display data may include the original display data for sub-pixels R21–B24, R41–B44, and R61–B64. Then, sub-pixels R11 and R21 share the same data voltage, sub-pixels R31 and R41 share the same data voltage, and sub-pixels R51 and R61 share the same data voltage. The rest are similar and will not be elaborated upon here.

[0157] The following explanation uses the example of the target display data potentially including the original display data corresponding to the odd-numbered row sub-pixels when the current display frame is the first display frame F1 in a series of consecutive displays. Specifically, combining... Figure 7 and Figure 11 Taking the original display data corresponding to the red sub-pixel in the odd-numbered row coupled to data line DA2 as an example, the process of the display panel displaying the image when using the first driving mode can be described as follows.

[0158] In the data charging phase T21, signal ga1_1 is high, the transistor in the red sub-pixel R12 is turned on, and the data voltage D1 corresponding to the display data of the red sub-pixel R12 is applied to the data line DA2, so that the red sub-pixel R12 inputs the target data voltage D1. Also, in the data charging phase T21, signal ga2_1 on the gate line GA2 is high, and the transistor in the red sub-pixel R11 is turned on. The data voltage D1 is simultaneously input to the red sub-pixel R11 as a pre-charging voltage to pre-charge the red sub-pixel R11. The time period corresponding to this pre-charging is the overlap time of the effective pulses of signals ga2_1 and ga1_1, as shown below. Figure 11 As shown, the overlap time corresponding to the high levels in signals ga2_1 and ga1_1. Also, in the data charging phase T21, signal ga3_1 on gate line GA3 is at a high level, the transistor in the red sub-pixel R22 is turned on, and data voltage D1 is simultaneously input to the red sub-pixel R22 as a pre-charging voltage to pre-charge the red sub-pixel R22. The time phase corresponding to this pre-charging is the overlap time of the effective pulses of signals ga3_1 and ga1_1, as shown... Figure 11 As shown, the overlap time corresponding to the high level of signals ga3_1 and ga1_1.

[0159] During the data charging phase T22, signal ga3_1 on gate line GA3 is high, the transistor in red sub-pixel R22 is turned on, and data voltage D1 is simultaneously input to red sub-pixel R22 as the target data voltage. Also during the data charging phase T22, signal ga2_1 is high, and the transistor in red sub-pixel R11 is turned on. Data voltage D1 corresponding to the display data of red sub-pixel R12 is applied to data line DA2, so that red sub-pixel R11 inputs data voltage D1 for pre-charging. Furthermore, during the data charging phase T22, signal ga4_2 on gate line GA4 is high, the transistor in red sub-pixel R21 is turned on, and data voltage D1 is simultaneously input to red sub-pixel R21 as a pre-charging voltage to pre-charge red sub-pixel R21.

[0160] During the data charging phase T23, signal ga2_1 is high, and the transistor in the red sub-pixel R22 is turned on. The data voltage D2 corresponding to the display data of the red sub-pixel R11 is applied to data line DA2, so that the red sub-pixel R11 receives the target data voltage D2. That is, for a valid pulse of signal ga2_1, it includes the pre-charging data voltage D1 of phases T21 and T22, and the target data voltage D2 of phase T23. Also, during the data charging phase T23, signal ga4_1 on gate line GA4 is high, the transistor in the red sub-pixel R21 is turned on, and the data voltage D2 is simultaneously input to the red sub-pixel R21 as a pre-charging voltage to pre-charge the red sub-pixel R21. Also, during the data charging phase T23, signal ga5_1 on gate line GA5 is high, the transistor in the red sub-pixel R32 is turned on, and the data voltage D2 is simultaneously input to the red sub-pixel R32 as a pre-charging voltage to pre-charge the red sub-pixel R32.

[0161] During the data charging phase T24, signal ga4_1 is high, and the transistor in the red sub-pixel R21 is turned on. Data voltage D2, corresponding to the display data of the red sub-pixel R11, is applied to data line DA2 so that the red sub-pixel R21 receives the target data voltage D2. Also during the data charging phase T24, signal ga5_1 on gate line GA5 is high, the transistor in the red sub-pixel R32 is turned on, and data voltage D2 is simultaneously input to the red sub-pixel R32 as a pre-charging voltage to pre-charge the red sub-pixel R32. Furthermore, during the data charging phase T24, signal ga7_1 on gate line GA7 is high, the transistor in the red sub-pixel R42 is turned on, and data voltage D2 is simultaneously input to the red sub-pixel R42 as a pre-charging voltage to pre-charge the red sub-pixel R31.

[0162] During the data charging phase T25, signal ga5_1 is high, and the transistor in the red sub-pixel R32 is turned on. A data voltage D5 corresponding to the display data of the red sub-pixel R32 is applied to data line DA2, so that the red sub-pixel R32 receives the target data voltage D5. Also during the data charging phase T25, signal ga6_1 on gate line GA6 is high, the transistor in the red sub-pixel R31 is turned on, and the data voltage D5 is simultaneously input to the red sub-pixel R31 as a pre-charging voltage to pre-charge the red sub-pixel R31. Furthermore, during the data charging phase T25, signal ga7_1 on gate line GA7 is high, the transistor in the red sub-pixel R42 is turned on, and the data voltage D5 is simultaneously input to the red sub-pixel R42 as a pre-charging voltage to pre-charge the red sub-pixel R42.

[0163] During the data charging phase T26, signal ga7_1 is high, and the transistor in the red sub-pixel R42 is turned on. Data voltage D5, corresponding to the display data of the red sub-pixel R32, is applied to data line DA2 to ensure that the red sub-pixel R42 receives the target data voltage D5. Also during the data charging phase T26, signal ga6_1 on gate line GA6 is high, the transistor in the red sub-pixel R31 is turned on, and data voltage D5 is simultaneously input to the red sub-pixel R31 as a pre-charging voltage to pre-charge it. Furthermore, during the data charging phase T26, signal ga8_1 on gate line GA8 is high, the transistor in the red sub-pixel R41 is turned on, and data voltage D5 is simultaneously input to the red sub-pixel R41 as a pre-charging voltage to pre-charge it.

[0164] During the data charging phase T27, signal ga6_1 is high, and the transistor in the red sub-pixel R31 is turned on. The data voltage D6 corresponding to the display data of the red sub-pixel R31 is applied to data line DA2, so that the red sub-pixel R31 receives the target data voltage D6. Also during the data charging phase T27, signal ga8_1 on gate line GA8 is high, the transistor in the red sub-pixel R41 is turned on, and the data voltage D6 is simultaneously input to the red sub-pixel R41 as a pre-charging voltage to pre-charge the red sub-pixel R41. This pre-charging process is also applied to subsequent red sub-pixels.

[0165] During the data charging phase T28, signal ga8_1 is high, and the transistor in the red sub-pixel R41 is turned on. The data voltage D6 corresponding to the display data of the red sub-pixel R31 is applied to data line DA2, so that the red sub-pixel R41 receives the target data voltage D6. This also pre-charges subsequent red sub-pixels.

[0166] The implementation methods for the remaining sub-pixels are similar, until all sub-pixels in the entire display panel are charged with the target data voltage, which will not be elaborated here.

[0167] Therefore, in this embodiment of the present disclosure, by using the driving method of the first gate scan signal provided in the present disclosure, it is possible to charge each sub-pixel with the target data voltage when the current display frame is the odd-numbered display frame in a series of consecutive displays, and to make two adjacent sub-pixels in the same column share the same target data voltage.

[0168] The following explanation uses the example of the target display data including the original display data corresponding to the even-numbered row sub-pixels when the current display frame is the second display frame F2 in a series of consecutive displays. Specifically, combining... Figure 12 and Figure 13 Taking the original display data corresponding to the red sub-pixel in the odd-numbered row coupled to data line DA2 as an example, the process of the display panel displaying the image when using the first driving mode can be described as follows.

[0169] During the data charging phase T21, signal ga1_1 is high, the transistor in the red sub-pixel R12 is turned on, and the data voltage D3 corresponding to the display data of the red sub-pixel R22 is applied to data line DA2, so that the red sub-pixel R12 inputs the target data voltage D3. Also during the data charging phase T21, signal ga2_1 on gate line GA2 is high, and the transistor in the red sub-pixel R11 is turned on. The data voltage D3 is simultaneously input to the red sub-pixel R11 as a pre-charging voltage to pre-charge the red sub-pixel R11. Furthermore, during the data charging phase T21, signal ga3_1 on gate line GA3 is high, the transistor in the red sub-pixel R22 is turned on, and the data voltage D3 is simultaneously input to the red sub-pixel R22 as a pre-charging voltage to pre-charge the red sub-pixel R22.

[0170] During the data charging phase T22, signal ga3_1 on gate line GA3 is high, the transistor in red sub-pixel R22 is turned on, and data voltage D3 is simultaneously input to red sub-pixel R22 as the target data voltage. Also during the data charging phase T22, signal ga2_1 is high, and the transistor in red sub-pixel R11 is turned on. Data voltage D3 corresponding to the display data of red sub-pixel R12 is applied to data line DA2, so that red sub-pixel R11 receives data voltage D2 for pre-charging. Furthermore, during the data charging phase T22, signal ga4_2 on gate line GA4 is high, the transistor in red sub-pixel R21 is turned on, and data voltage D3 is simultaneously input to red sub-pixel R21 as a pre-charging voltage to pre-charge red sub-pixel R21.

[0171] During the data charging phase T23, signal ga2_1 is high, and the transistor in the red sub-pixel R22 is turned on. Data voltage D4, corresponding to the display data of the red sub-pixel R21, is applied to data line DA2 so that the red sub-pixel R11 receives the target data voltage D4. Also during the data charging phase T23, signal ga4_1 on gate line GA4 is high, the transistor in the red sub-pixel R21 is turned on, and data voltage D4 is simultaneously input to the red sub-pixel R21 as a pre-charging voltage to pre-charge it. Furthermore, during the data charging phase T23, signal ga5_1 on gate line GA5 is high, the transistor in the red sub-pixel R32 is turned on, and data voltage D4 is simultaneously input to the red sub-pixel R32 as a pre-charging voltage to pre-charge it.

[0172] During the data charging phase T24, signal ga4_1 is high, and the transistor in the red sub-pixel R21 is turned on. Data voltage D4, corresponding to the display data of the red sub-pixel R21, is applied to data line DA2 to ensure that the red sub-pixel R21 receives the target data voltage D4. Also during the data charging phase T24, signal ga5_1 on gate line GA5 is high, the transistor in the red sub-pixel R32 is turned on, and data voltage D4 is simultaneously input to the red sub-pixel R32 as a pre-charging voltage to pre-charge it. Furthermore, during the data charging phase T24, signal ga7_1 on gate line GA7 is high, the transistor in the red sub-pixel R42 is turned on, and data voltage D4 is simultaneously input to the red sub-pixel R42 as a pre-charging voltage to pre-charge the red sub-pixel R31.

[0173] During the data charging phase T25, signal ga5_1 is high, and the transistor in the red sub-pixel R32 is turned on. Data voltage D7, corresponding to the display data of the red sub-pixel R42, is applied to data line DA2 to ensure that the red sub-pixel R32 receives the target data voltage D7. Also, during the data charging phase T25, signal ga6_1 on gate line GA6 is high, the transistor in the red sub-pixel R31 is turned on, and data voltage D7 is simultaneously input to the red sub-pixel R31 as a pre-charging voltage to pre-charge it. Furthermore, during the data charging phase T25, signal ga7_1 on gate line GA7 is high, the transistor in the red sub-pixel R42 is turned on, and data voltage D7 is simultaneously input to the red sub-pixel R42 as a pre-charging voltage to pre-charge it.

[0174] During the data charging phase T26, signal ga7_1 is high, and the transistor in the red sub-pixel R42 is turned on. Data voltage D7, corresponding to the display data of the red sub-pixel R42, is applied to data line DA2 to ensure that the red sub-pixel R42 receives the target data voltage D7. Also during the data charging phase T26, signal ga6_1 on gate line GA6 is high, the transistor in the red sub-pixel R31 is turned on, and data voltage D7 is simultaneously input to the red sub-pixel R31 as a pre-charging voltage to pre-charge the red sub-pixel R31. Furthermore, during the data charging phase T26, signal ga8_1 on gate line GA8 is high, the transistor in the red sub-pixel R41 is turned on, and data voltage D7 is simultaneously input to the red sub-pixel R41 as a pre-charging voltage to pre-charge the red sub-pixel R41.

[0175] During the data charging phase T27, signal ga6_1 is high, and the transistor in the red sub-pixel R31 is turned on. The data voltage D8 corresponding to the display data of the red sub-pixel R41 is applied to data line DA2, so that the red sub-pixel R31 receives the target data voltage D8. Also, during the data charging phase T27, signal ga8_1 on gate line GA8 is high, the transistor in the red sub-pixel R41 is turned on, and the data voltage D8 is simultaneously input to the red sub-pixel R41 as a pre-charging voltage to pre-charge the red sub-pixel R41. This pre-charging process is also applied to subsequent red sub-pixels.

[0176] During the data charging phase T28, signal ga8_1 is high, and the transistor in the red sub-pixel R41 is turned on. The data voltage D8 corresponding to the display data of the red sub-pixel R41 is applied to data line DA2, so that the red sub-pixel R41 receives the target data voltage D8. This also pre-charges subsequent red sub-pixels.

[0177] The implementation methods for the remaining sub-pixels are similar, until all sub-pixels in the entire display panel are charged with the target data voltage, which will not be elaborated here.

[0178] Therefore, in this embodiment of the present disclosure, by using the driving method of the first gate scan signal provided in this disclosure, it is possible to charge each sub-pixel with a target data voltage when the current display frame is the even-numbered display frame in a series of consecutive displays, and to make two adjacent sub-pixels in the same column share a target data voltage.

[0179] In some embodiments of this disclosure, loading a first gate scan signal onto the gate lines in the display panel may include: inputting multiple different first clock signals to the gate driving circuit in the display panel, so as to load the valid pulses in the first clock signals as valid pulses of the first gate scan signal onto the gate lines. For example, the timing controller 200 inputs multiple different first clock signals to the gate driving circuit in the display panel via clock signal lines, so as to load the valid pulses in the first clock signals as valid pulses of the first gate scan signal onto the gate lines, thereby enabling the gate lines in the display panel to be driven in a non-progressive manner to turn on the transistors in the sub-pixels.

[0180] In some embodiments of this disclosure, multiple different first clock signals can be divided into three clock signal groups; wherein, in three adjacent gate groups, the output clock signal terminal of the shift register unit corresponding to the first gate group is coupled to the first clock signal group of the three clock signal groups, the output clock signal terminal of the shift register unit corresponding to the second gate group is coupled to the second clock signal group of the three clock signal groups, and the output clock signal terminal of the shift register unit corresponding to the third gate group is coupled to the third clock signal group of the three clock signal groups. For example, in combination with Figure 2 As shown, gate lines GA1-GA4 form the first gate line group, GA5-GA8 form the second gate line group, and GA9-GA12 form the third gate line group. Gate lines GA13-GA16 form the fourth gate line group, GA17-GA20 form the fifth gate line group, and GA21-GA24 form the sixth gate line group. The first to third gate line groups can be considered as three adjacent gate line groups, and the fourth to sixth gate line groups can be considered as another three adjacent gate line groups. This allows the output clock signal terminals of the shift register units corresponding to the first and fourth gate line groups to be coupled to the first clock signal group. Similarly, the output clock signal terminals of the shift register units corresponding to the second and fifth gate line groups are coupled to the second clock signal group. Finally, the output clock signal terminals of the shift register units corresponding to the third and sixth gate line groups are coupled to the third clock signal group.

[0181] In some embodiments of this disclosure, the plurality of different first clock signals may include 12 first clock signals; the 12 first clock signals are divided into three clock signal groups, and in each clock signal group, the effective pulse of each first clock signal appears sequentially in the order of the first, third, second, and fourth first clock signals in the clock signal group. Furthermore, the start time of the effective pulse of the fourth first clock signal in the first clock signal group is before the start time of the effective pulse of the first first clock signal in the second clock signal group; and the start time of the effective pulse of the fourth first clock signal in the second clock signal group is before the start time of the effective pulse of the first first clock signal in the third clock signal group. Exemplarily, in conjunction with... Figure 14 As shown, the 12 first clock signals are ck1_1 to ck12_1. First clock signals ck1_1 to ck4_1 form the first clock signal group, first clock signals ck5_1 to ck8_1 form the second clock signal group, and first clock signals ck9_1 to ck12_1 form the third clock signal group. In the first clock signal group, ck1_1 is the first clock signal, ck3_1 is the third clock signal, ck2_1 is the second clock signal, and ck4_1 is the fourth clock signal. In the second clock signal group, ck5_1 is the first clock signal, ck7_1 is the third clock signal, ck6_1 is the second clock signal, and ck8_1 is the fourth clock signal. In the third clock signal group, ck9_1 is the first clock signal, ck11_1 is the third clock signal, ck10_1 is the second clock signal, and ck12_1 is the fourth clock signal. This allows the output clock signals of the shift register units corresponding to the first and fourth gate groups to be coupled to the first clock signals ck1_1 to ck4_1 in the first clock signal group. Similarly, the output clock signals of the shift register units corresponding to the second and fifth gate groups are coupled to the first clock signals ck5_1 to ck8_1 in the second clock signal group. Finally, the output clock signals of the shift register units corresponding to the third and sixth gate groups are coupled to the first clock signals ck9_1 to ck12_1 in the third clock signal group.

[0182] In some embodiments of this disclosure, within the same group of clock signals, the first and fourth first clock signals are out of phase. Exemplarily, in conjunction with... Figure 14 As shown, the first clock signals ck1_1 and ck4_1 are out of phase. The first clock signals ck5_1 and ck8_1 are out of phase. The first clock signals ck9_1 and ck12_1 are out of phase.

[0183] In some embodiments of this disclosure, the clock signals appearing in the same sequence in the first and second clock signal groups differ in phase by 2π / 3; the clock signals appearing in the same sequence in the second and third clock signal groups also differ in phase by 2π / 3. It should be noted that within the same clock signal group, the first valid pulses of different first clock signals appear in a specific order. Therefore, the order of different first clock signals within their respective clock signal groups can be determined based on the order in which the first valid pulses of different first clock signals appear.

[0184] For example, combined Figure 14 As shown, the first valid pulse of the first clock signal ck1_1 in the first clock signal group appears first, followed by the first valid pulse of the first clock signal ck2_1, then the first valid pulse of the first clock signal ck3_1, and then the first valid pulse of the first clock signal ck4_1. Similarly, the first valid pulse of the first clock signal ck5_1 in the second clock signal group appears first, followed by the first valid pulse of the first clock signal ck6_1, then the first valid pulse of the first clock signal ck7_1, and then the first valid pulse of the first clock signal ck8_1. Therefore, the first clock signals ck1_1 and ck5_1 can be used as timing signals that appear in the same order, the first clock signals ck2_1 and ck6_1 can be used as timing signals that appear in the same order, the first clock signals ck3_1 and ck7_1 can be used as timing signals that appear in the same order, and the first clock signals ck4_1 and ck8_1 can be used as timing signals that appear in the same order.

[0185] Furthermore, the first valid pulse of the first clock signal ck5_1 in the second clock signal group appears first, followed by the first valid pulse of the first clock signal ck6_1 in the second clock signal group, followed by the first valid pulse of the first clock signal ck7_1 in the second clock signal group, followed by the first valid pulse of the first clock signal ck8_1 in the second clock signal group. Similarly, the first valid pulse of the first clock signal ck9_1 in the third clock signal group appears first, followed by the first valid pulse of the first clock signal ck10_1 in the third clock signal group, followed by the first valid pulse of the first clock signal ck11_1 in the third clock signal group, followed by the first valid pulse of the first clock signal ck12_1 in the third clock signal group. Therefore, the first clock signals ck5_1 and ck9_1 can be used as timing signals that appear in the same order, the first clock signals ck6_1 and ck10_1 can be used as timing signals that appear in the same order, the first clock signals ck7_1 and ck11_1 can be used as timing signals that appear in the same order, and the first clock signals ck8_1 and ck12_1 can be used as timing signals that appear in the same order.

[0186] For example, combined Figure 14As shown, the first clock signal ck1_1 in the first clock signal group and the first clock signal ck5_1 in the second clock signal group can be clock signals appearing in the same order, and the phase difference between the first clock signals ck1_1 and ck5_1 is 2π / 3. The first clock signal ck2_1 in the first clock signal group and the first clock signal ck6_1 in the second clock signal group can be clock signals appearing in the same order, and the phase difference between the first clock signals ck2_1 and ck6_1 is 2π / 3. The first clock signal ck3_1 in the first clock signal group and the first clock signal ck7_1 in the second clock signal group can be clock signals appearing in the same order, and the phase difference between the first clock signals ck3_1 and ck7_1 is 2π / 3. The first clock signal ck4_1 in the first clock signal group and the first clock signal ck8_1 in the second clock signal group can be clock signals appearing in the same order, and the phase difference between the first clock signals ck4_1 and ck8_1 is 2π / 3. The first clock signal ck5_1 in the second clock signal group and the first clock signal ck9_1 in the third clock signal group can be clock signals appearing in the same order, and the phase difference between the first clock signals ck5_1 and ck9_1 is 2π / 3. The first clock signal ck6_1 in the second clock signal group and the first clock signal ck10_1 in the third clock signal group can be clock signals appearing in the same order, and the phase difference between the first clock signals ck6_1 and ck10_1 is 2π / 3. The first clock signal ck7_1 in the second clock signal group and the first clock signal ck11_1 in the third clock signal group can be clock signals appearing in the same order, and the phase difference between the first clock signals ck7_1 and ck11_1 is 2π / 3. The first clock signal ck8_1 in the second clock signal group and the first clock signal ck12_1 in the third clock signal group can be clock signals appearing in the same order, and the phase difference between the first clock signals ck8_1 and ck12_1 is 2π / 3.

[0187] In some embodiments of this disclosure, the shift register unit further includes a control clock signal terminal; in three adjacent gate line groups, the control clock signal terminal of the shift register unit corresponding to the first gate line group is coupled to the first first clock signal in the first clock signal group, the control clock signal terminal of the shift register unit corresponding to the second gate line group is coupled to the first first clock signal in the second clock signal group, and the control clock signal terminal of the shift register unit corresponding to the third gate line group is coupled to the first first clock signal in the third clock signal group. Exemplarily, in conjunction with... Figure 14As shown, the control clock signal terminals of the shift register units corresponding to the first and fourth gate line groups are coupled to the first clock signal ck1_1. The control clock signal terminals of the shift register units corresponding to the second and fifth gate line groups are coupled to the first clock signal ck5_1. The control clock signal terminals of the shift register units corresponding to the third and sixth gate line groups are coupled to the first clock signal ck9_1.

[0188] In some embodiments of this disclosure, a shift register unit can be coupled to multiple adjacent gate lines. Furthermore, in every three adjacent shift register units, the output clock signal of the first shift register unit is coupled to the first clock signal group of three clock signal groups, the output clock signal of the second shift register unit is coupled to the second clock signal group of three clock signal groups, and the output clock signal of the third shift register unit is coupled to the third clock signal group of three clock signal groups. Exemplarily, in conjunction with... Figure 14 and Figure 15As shown, the first clock signal ck1_1 can be loaded onto clock signal line CK1, the first clock signal ck2_1 onto clock signal line CK2, the first clock signal ck3_1 onto clock signal line CK3, ... the first clock signal ck11_1 onto clock signal line CK11, and the first clock signal ck12_1 onto clock signal line CK12. Furthermore, one shift register unit is coupled to four adjacent gate lines. When four gate lines form a gate line group, one shift register unit can be coupled to one gate line group. For example, shift register unit SR1 is coupled to gate lines GA1-GA4, shift register unit SR2 is coupled to gate lines GA5-GA8, shift register unit SR3 is coupled to gate lines GA9-GA12, shift register unit SR4 is coupled to gate lines GA13-GA16, shift register unit SR5 is coupled to gate lines GA17-GA20, and shift register unit SR6 is coupled to gate lines GA21-GA24. Furthermore, the output clock signal terminals CLK_1 to CLK_4 of shift register units SR1 and SR4 are coupled to the first clock signals ck1_1 to ck4_1 in the first clock signal group. The output clock signal terminal CLK_1 is coupled to the first clock signal ck1_1 and is coupled to the clock signal line CK1. The output clock signal terminal CLK_2 is coupled to the first clock signal ck2_1 and is coupled to the clock signal line CK2. The output clock signal terminal CLK_3 is coupled to the first clock signal ck3_1 and is coupled to the clock signal line CK3. The output clock signal terminal CLK_4 is coupled to the first clock signal ck4_1 and is coupled to the clock signal line CK4. Furthermore, the output clock signal terminals CLK_1 to CLK_4 of shift register units SR2 and SR5 are coupled to the first clock signals ck5_1 to ck8_1 in the second clock signal group. The output clock signal terminal CLK_1 is coupled to the first clock signal ck5_1 and is coupled to the clock signal line CK5. The output clock signal terminal CLK_2 is coupled to the first clock signal ck6_1 and is coupled to the clock signal line CK6. The output clock signal terminal CLK_3 is coupled to the first clock signal ck7_1 and is coupled to the clock signal line CK7. The output clock signal terminal CLK_4 is coupled to the first clock signal ck8_1 and is coupled to the clock signal line CK8.Furthermore, the output clock signal terminals CLK_1 to CLK_4 of shift register units SR3 and SR6 are coupled to the first clock signals ck9_1 to ck12_1 in the third clock signal group. The output clock signal terminal CLK_1 is coupled to the first clock signal ck9_1 and is coupled to the clock signal line CK9. The output clock signal terminal CLK_2 is coupled to the first clock signal ck10_1 and is coupled to the clock signal line CK10. The output clock signal terminal CLK_3 is coupled to the first clock signal ck11_1 and is coupled to the clock signal line CK11. The output clock signal terminal CLK_4 is coupled to the first clock signal ck12_1 and is coupled to the clock signal line CK12.

[0189] In some embodiments of this disclosure, each shift register unit further includes a control clock signal terminal. Furthermore, in every three adjacent shift register units, the control clock signal terminal of the first shift register unit is coupled to the first first clock signal in the first clock signal group, the control clock signal terminal of the second shift register unit is coupled to the first first clock signal in the second clock signal group, and the control clock signal terminal of the third shift register unit is coupled to the first first clock signal in the third clock signal group. Exemplarily, in conjunction with... Figure 15 As shown, the control clock signal terminal CLK_C of shift register units SR1 and SR4 is coupled to the first clock signal ck1_1 in the first clock signal group and is coupled to the clock signal line CK1. Similarly, the control clock signal terminal CLK_C of shift register units SR2 and SR5 is coupled to the first clock signal ck5_1 in the second clock signal group and is coupled to the clock signal line CK5. Furthermore, the control clock signal terminal CLK_C of shift register units SR3 and SR6 is coupled to the first clock signal ck9_1 in the third clock signal group and is coupled to the clock signal line CK9.

[0190] For example, such as Figure 15 As shown, in every two adjacent shift register units, the GAO_C of the previous shift register unit is coupled to the input signal terminal INP of the next shift register unit. In every three adjacent shift register units, the GAO_C of the third shift register unit is coupled to the reset signal terminal RST_PU of the first shift register unit.

[0191] For example, in the second drive mode, Figure 15 The signal timing diagram corresponding to the gate drive circuit shown is as follows: Figure 14As shown. Shift register unit SR1 can output the first high level of the first clock signal ck1_1 to gate line GA1 to generate the high level in signal ga1_1. Shift register unit SR1 can also output the first high level of the first clock signal ck2_1 to gate line GA2 to generate the high level in signal ga2_1. Shift register unit SR1 can also output the first high level of the first clock signal ck3_1 to gate line GA3 to generate the high level in signal ga3_1. Shift register unit SR1 can also output the first high level of the first clock signal ck4_1 to gate line GA4 to generate the high level in signal ga4_1.

[0192] Furthermore, shift register unit SR2 can output the first high level of the first clock signal ck5_1 to gate line GA5 to generate the high level in signal ga5_1. Shift register unit SR2 can also output the first high level of the first clock signal ck6_1 to gate line GA6 to generate the high level in signal ga6_1. Shift register unit SR2 can also output the first high level of the first clock signal ck7_1 to gate line GA7 to generate the high level in signal ga7_1. Shift register unit SR2 can also output the first high level of the first clock signal ck8_1 to gate line GA8 to generate the high level in signal ga8_1.

[0193] Furthermore, shift register unit SR3 can output the first high level of the first clock signal ck9_1 to gate line GA9 to generate the high level in signal ga9_1. Shift register unit SR3 can also output the first high level of the first clock signal ck10_1 to gate line GA10 to generate the high level in signal ga10_1. Shift register unit SR3 can also output the first high level of the first clock signal ck11_1 to gate line GA11 to generate the high level in signal ga11_1. Shift register unit SR3 can also output the first high level of the first clock signal ck12_1 to gate line GA12 to generate the high level in signal ga12_1.

[0194] Furthermore, shift register unit SR4 can output the second high level of the first clock signal ck1_1 to gate line GA13 to generate a high level in the second gate scan signal on gate line GA13. Shift register unit SR4 can also output the second high level of the first clock signal ck2_1 to gate line GA14 to generate a high level in the second gate scan signal on gate line GA14. Shift register unit SR4 can also output the second high level of the first clock signal ck3_1 to gate line GA15 to generate a high level in the second gate scan signal on gate line GA15. Finally, shift register unit SR4 can output the second high level of the first clock signal ck4_1 to gate line GA16 to generate a high level in the second gate scan signal on gate line GA16.

[0195] Furthermore, shift register unit SR5 can output the second high level of the first clock signal ck5_1 to gate line GA17 to generate a high level in the second gate scan signal on gate line GA17. Shift register unit SR5 can also output the second high level of the first clock signal ck6_1 to gate line GA18 to generate a high level in the second gate scan signal on gate line GA18. Shift register unit SR5 can also output the second high level of the first clock signal ck7_1 to gate line GA19 to generate a high level in the second gate scan signal on gate line GA19. Finally, shift register unit SR5 can output the second high level of the first clock signal ck8_1 to gate line GA20 to generate a high level in the second gate scan signal on gate line GA20.

[0196] Furthermore, shift register unit SR6 can output the second high level of the first clock signal ck9_1 to gate line GA21 to generate a high level in the second gate scan signal on gate line GA21. Shift register unit SR6 can also output the second high level of the first clock signal ck10_1 to gate line GA22 to generate a high level in the second gate scan signal on gate line GA22. Shift register unit SR6 can also output the second high level of the first clock signal ck11_1 to gate line GA23 to generate a high level in the second gate scan signal on gate line GA23. Finally, shift register unit SR6 can output the second high level of the first clock signal ck12_1 to gate line GA24 to generate a high level in the second gate scan signal on gate line GA24.

[0197] In other words, the pulse corresponding to the high level of the first clock signal can be considered its valid pulse, and the pulse corresponding to the low level can be considered its invalid pulse. Of course, when the shift register outputs the low level of the first clock signal to generate the low-level signal that controls the transistor to turn on, the pulse corresponding to the low level of the first clock signal can be considered its valid pulse, and the pulse corresponding to the high level can be considered its invalid pulse.

[0198] For example, in the first drive mode, Figure 15 The signal timing diagram corresponding to the gate drive circuit shown is as follows: Figure 4 As shown. Shift register unit SR1 can output the first high level of the second clock signal ck1_2 to gate line GA1 to generate the high level in signal ga1_2. Shift register unit SR1 can also output the first high level of the second clock signal ck2_2 to gate line GA2 to generate the high level in signal ga2_2. Shift register unit SR1 can also output the first high level of the second clock signal ck3_2 to gate line GA3 to generate the high level in signal ga3_2. Shift register unit SR1 can also output the first high level of the second clock signal ck4_2 to gate line GA4 to generate the high level in signal ga4_2.

[0199] Furthermore, shift register unit SR2 can output the first high level of the second clock signal ck5_2 to gate line GA5 to generate the high level in signal ga5_2. Shift register unit SR2 can also output the first high level of the second clock signal ck6_2 to gate line GA6 to generate the high level in signal ga6_2. Shift register unit SR2 can also output the first high level of the second clock signal ck7_2 to gate line GA7 to generate the high level in signal ga7_2. Shift register unit SR2 can also output the first high level of the second clock signal ck8_2 to gate line GA8 to generate the high level in signal ga8_2.

[0200] Furthermore, shift register unit SR3 can output the first high level of the second clock signal ck9_2 to gate line GA9 to generate the high level in signal ga9_2. Shift register unit SR3 can also output the first high level of the second clock signal ck10_2 to gate line GA10 to generate the high level in signal ga10_2. Shift register unit SR3 can also output the first high level of the second clock signal ck11_2 to gate line GA11 to generate the high level in signal ga11_2. Shift register unit SR3 can also output the first high level of the second clock signal ck12_2 to gate line GA12 to generate the high level in signal ga12_2.

[0201] Furthermore, shift register unit SR4 can output the second high level of the second clock signal ck1_2 to gate line GA13 to generate a high level in the second gate scan signal on gate line GA13. Shift register unit SR4 can also output the second high level of the second clock signal ck2_2 to gate line GA14 to generate a high level in the second gate scan signal on gate line GA14. Shift register unit SR4 can also output the second high level of the second clock signal ck3_2 to gate line GA15 to generate a high level in the second gate scan signal on gate line GA15. Finally, shift register unit SR4 can output the second high level of the second clock signal ck4_2 to gate line GA16 to generate a high level in the second gate scan signal on gate line GA16.

[0202] Furthermore, shift register unit SR5 can output the second high level of the second clock signal ck5_2 to gate line GA17 to generate a high level in the second gate scan signal on gate line GA17. Shift register unit SR5 can also output the second high level of the second clock signal ck6_2 to gate line GA18 to generate a high level in the second gate scan signal on gate line GA18. Shift register unit SR5 can also output the second high level of the second clock signal ck7_2 to gate line GA19 to generate a high level in the second gate scan signal on gate line GA19. Shift register unit SR5 can also output the second high level of the second clock signal ck8_2 to gate line GA20 to generate a high level in the second gate scan signal on gate line GA20.

[0203] Furthermore, shift register unit SR6 can output the second high level of the second clock signal ck9_2 to gate line GA21 to generate a high level in the second gate scan signal on gate line GA21. Shift register unit SR6 can also output the second high level of the second clock signal ck10_2 to gate line GA22 to generate a high level in the second gate scan signal on gate line GA22. Shift register unit SR6 can also output the second high level of the second clock signal ck11_2 to gate line GA23 to generate a high level in the second gate scan signal on gate line GA23. Finally, shift register unit SR6 can output the second high level of the second clock signal ck12_2 to gate line GA24 to generate a high level in the second gate scan signal on gate line GA24.

[0204] In other words, the pulse corresponding to the high level of the second clock signal can be considered its valid pulse, and the pulse corresponding to the low level can be considered its invalid pulse. Of course, when the shift register outputs the low level of the second clock signal to generate the low-level signal that controls the transistor to turn on, the pulse corresponding to the low level of the second clock signal can be considered its valid pulse, and the pulse corresponding to the high level can be considered its invalid pulse.

[0205] In some embodiments of this disclosure, such as Figure 16 As shown, the shift register unit may include: a pull-up circuit 10, a control circuit 20, a cascaded circuit 30, and N output circuits 40.

[0206] Pull-up circuit 10 is connected to the input signal terminal INP of the shift register unit, the total pull-up node PU, and the pull-down node PD. Pull-up circuit 10 is configured to provide the signal of input signal terminal INP to the total pull-up node PU, and pull down the potential of the total pull-up node PU under the control of the potential of pull-down node PD.

[0207] The control circuit 20 is connected to the main pull-up node PU and the pull-down node PD. The control circuit 20 is configured to control the potential of the pull-down node PD according to the potential of the main pull-up node PU.

[0208] The cascade circuit 30 is connected to the main pull-up node PU, the pull-down node PD, the GAO_C of the shift register unit, and the control clock signal terminal CLK_C. The cascade circuit 30 is configured to provide the signal of the control clock signal terminal CLK_C to GAO_C under the control of the potential of the main pull-up node PU, and to pull down the potential of GAO_C under the control of the potential of the pull-down node PD.

[0209] N output circuits 40 are respectively connected to the input signal terminal INP, the pull-down node PD, and the N output clock signal terminals of the shift register unit (e.g., Figure 16 CLK_1 to CLK_N), and N sub-pull-up nodes (e.g., Figure 16 PU_1 to PU_N) and N output signal terminals (e.g., Figure 16(GAO_1 to GAO_N in the diagram). The nth output circuit 40_n is connected to the input signal terminal INP, the pull-down node PD, the nth output signal terminal GAO_n, and the nth pull-up node PU_n. It is configured to input the signal from the input signal terminal INP to the nth pull-up node PU_n, provide the signal from the nth output clock signal terminal CLK_n to the nth output signal terminal GAO_n under the control of the potential of the nth pull-up node PU_n, and pull down the potential of the nth output signal terminal GAO_n under the control of the potential of the pull-down node PD. Here, N is an integer greater than 1, and n is an integer where 1 ≤ n ≤ N. In some embodiments, 2 ≤ N ≤ 8; for example, N can be 2, 3, 4, 5, or 6.

[0210] In some embodiments of this disclosure, N can be set to 4, allowing one gate drive circuit to be coupled to four gate lines. The shift register unit then includes four output circuits, four output clock signal terminals CLK1_1 to CLK1_4, four output signal terminals GAO_1 to GAO_4, and four pull-up nodes PU_1 to PU_4. Figure 17 As shown, the shift register unit includes four output circuits: a first output circuit 40_1, a second output circuit 40_2, a third output circuit 40_3, and a fourth output circuit 40_4. The shift register unit also includes first output clock signal terminals CLK_1 to CLK_4, first output signal terminals GAO_1 to GAO_4, and first output pull-up nodes PU_1 to PU_2. Each output circuit is connected to a corresponding output clock signal terminal, a corresponding output signal terminal, and a corresponding pull-up node. For example, the first output circuit 40_1 is connected to the first output clock signal terminal CLK_1, the first output signal terminal GAO_1, and the first output pull-up node PU_1; the second output circuit 40_2 is connected to the second output clock signal terminal CLK_2, the second output signal terminal GAO_2, and the first output pull-up node PU_3, and so on.

[0211] In some embodiments of this disclosure, such as Figure 17As shown, the pull-up circuit 10 includes an eighteenth transistor M18, a nineteenth transistor M19, and a twentieth transistor M20. The gate and first terminal of the eighteenth transistor M18 are connected to the input signal terminal INP, and the second terminal of the eighteenth transistor M18 is connected to the total pull-up node PU. Optionally, for multiple cascaded shift register units, the input signal terminal INP can be connected to GAO_C, i.e., the cascaded output terminal. Of course, in this embodiment, the gate and first terminal of the eighteenth transistor M18 are electrically connected together, or they can be not connected together. For example, the gate can be connected to GAO_C, and the first terminal can be connected to a DC signal that can turn on the eighteenth transistor, such as the VGH signal; this is not limited here. The gate of the nineteenth transistor M19 is connected to the pull-down node, the first terminal of the nineteenth transistor M19 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit, and the second terminal of the nineteenth transistor M19 is connected to the total pull-up node PU. The gate of the twentieth transistor M20 is connected to the reset signal terminal RST_PU of the shift register unit, the first terminal of the twentieth transistor M20 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL), and the second terminal of the twentieth transistor M20 is connected to the total pull-up node PU.

[0212] In some embodiments of this disclosure, such as Figure 17 As shown, the control circuit 20 may include an eighth transistor M8 and a ninth transistor M9. The gate and first terminal of the eighth transistor M8 are connected to the power supply signal terminal VDD of the shift register unit, and the second terminal of the eighth transistor M8 is connected to the pull-down node PD. The gate of the ninth transistor M9 is connected to the total pull-up node PU, the first terminal of the ninth transistor M9 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit, and the second terminal of the ninth transistor M9 is connected to the pull-down node PD.

[0213] In some embodiments of this disclosure, such as Figure 17 As shown, the cascaded circuit 30 may include a twenty-second transistor M22, a twenty-third transistor M23, and a second capacitor C2. The gate of the twenty-second transistor M22 is connected to the overall pull-up node PU, its first terminal is connected to the control clock signal terminal CLK_C, and its second terminal is connected to GAO_C. The gate of the twenty-third transistor M23 is connected to the pull-down node PD, its first terminal is connected to the reference signal terminal of the shift register unit (e.g., the first reference signal terminal LVGL), and its second terminal is connected to GAO_C. The first terminal of the second capacitor C2 is connected to the gate of the twenty-second transistor M22, and its second terminal is connected to GAO_C.

[0214] In some embodiments of this disclosure, such as Figure 17As shown, in the first output circuit 40_1, the input sub-circuit 401 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a first capacitor C1. The gate and first terminal of the first transistor M1 are connected to the input signal terminal INP, and the second terminal of the first transistor M1 is connected to the first pull-up node PU_1. The gate of the second transistor M2 is connected to the first pull-up node PU_1, the first terminal of the second transistor M2 is connected to the first output clock signal terminal CLK_1, and the second terminal of the second transistor M2 is connected to the first output signal terminal GAO_1. The gate of the third transistor M3 is connected to the pull-down node PD, the first terminal of the third transistor M3 is connected to the reference signal terminal of the shift register unit (e.g., the first reference signal terminal LVGL), and the second terminal of the third transistor M3 is connected to the first pull-up node PU_1. The gate of the fourth transistor M4 is connected to the pull-down node PD, the first terminal of the fourth transistor M4 is connected to the reference signal terminal of the shift register unit (e.g., the second reference signal terminal VGL), and the second terminal of the fourth transistor M4 is connected to the first output signal terminal GAO_1. The first terminal of the first capacitor C1 is connected to the first pull-up node PU_1, and the second terminal of the first capacitor C1 is connected to the first output signal terminal GAO_1.

[0215] The second output circuit 40_2 has a similar structure to the first output circuit 40_1, the difference being that it connects the second pull-up node PU_2, the second output clock signal terminal CLK_2, and the second output signal terminal GAO_2. For example... Figure 17 As shown, in the second output circuit 40_2, the gate and first terminal of the first transistor M1 are connected to the input signal terminal INP, and the second terminal of the first transistor M1 is connected to the second pull-up node PU_2. The gate of the second transistor M2 is connected to the second pull-up node PU_2, the first terminal of the second transistor M2 is connected to the second output clock signal terminal CLK_2, and the second terminal of the second transistor M2 is connected to the second output signal terminal GAO_2. The first terminal of the first capacitor C1 is connected to the second pull-up node PU_2, and the second terminal of the first capacitor C1 is connected to the second output signal terminal GAO_2. The gate of the third transistor M3 is connected to the pull-down node PD, the first terminal of the third transistor M3 is connected to the first reference signal terminal LVGL, and the second terminal of the third transistor M3 is connected to the second pull-up node PU_2. The gate of the fourth transistor M4 is connected to the pull-down node PD, the first terminal of the fourth transistor M4 is connected to the second reference signal terminal VGL, and the second terminal of the fourth transistor M4 is connected to the second output signal terminal GAO_2.

[0216] The third output circuit 40_3 has a similar structure to the first output circuit 40_1, the difference being that it connects the third pull-up node PU_3, the third output clock signal terminal CLK_3, and the third output signal terminal GAO_3. For example... Figure 17 As shown, in the third output circuit 40_3, the gate and first terminal of the first transistor M1 are connected to the input signal terminal INP, and the second terminal of the first transistor M1 is connected to the third pull-up node PU_3. The gate of the second transistor M2 is connected to the third pull-up node PU_3, the first terminal of the second transistor M2 is connected to the third output clock signal terminal CLK_3, and the second terminal of the second transistor M2 is connected to the third output signal terminal GAO_3. The first terminal of the first capacitor C1 is connected to the third pull-up node PU_3, and the second terminal of the first capacitor C1 is connected to the third output signal terminal GAO_3. The gate of the third transistor M3 is connected to the pull-down node PD, the first terminal of the third transistor M3 is connected to the first reference signal terminal LVGL, and the second terminal of the third transistor M3 is connected to the third pull-up node PU_3. The gate of the fourth transistor M4 is connected to the pull-down node PD, the first terminal of the fourth transistor M4 is connected to the second reference signal terminal VGL, and the second terminal of the fourth transistor M4 is connected to the third output signal terminal GAO_3.

[0217] The fourth output circuit 40_4 has a similar structure to the first output circuit 40_1, the difference being that it connects the fourth pull-up node PU_4, the fourth output clock signal terminal CLK_4, and the fourth output signal terminal GAO_4. For example... Figure 17 As shown, in the fourth output circuit 40_4, the gate and first terminal of the first transistor M1 are connected to the input signal terminal INP, and the second terminal of the first transistor M1 is connected to the fourth pull-up node PU_4. The gate of the second transistor M2 is connected to the fourth pull-up node PU_4, the first terminal of the second transistor M2 is connected to the fourth output clock signal terminal CLK_4, and the second terminal of the second transistor M2 is connected to the fourth output signal terminal GAO_4. The first terminal of the first capacitor C1 is connected to the fourth pull-up node PU_4, and the second terminal of the first capacitor C1 is connected to the fourth output signal terminal GAO_4. The gate of the fourth transistor M3 is connected to the pull-down node PD, the first terminal of the fourth transistor M3 is connected to the first reference signal terminal LVGL, and the second terminal of the fourth transistor M3 is connected to the fourth pull-up node PU_4. The gate of the fourth transistor M4 is connected to the pull-down node PD, the first terminal of the fourth transistor M4 is connected to the second reference signal terminal VGL, and the second terminal of the fourth transistor M4 is connected to the fourth output signal terminal GAO_4.

[0218] Combination Figure 14 , Figure 15 and Figure 17 As shown, when inputting to the gate drive circuit Figure 14 As shown in the signal timing diagram, the output signal terminals GAO_1 of shift register unit SR1 can output signal ga1_1, GAO_2 can output signal ga2_1, GAO_3 can output signal ga3_1, and GAO_4 can output signal ga4_1. The output signal terminals GAO_1 of shift register unit SR2 can output signal ga5_1, GAO_2 can output signal ga6_1, GAO_3 can output signal ga7_1, and GAO_4 can output signal ga8_1. The output signal terminals GAO_1 of shift register unit SR3 can output signal ga9_1, GAO_2 can output signal ga10_1, GAO_3 can output signal ga11_1, and GAO_4 can output signal ga12_1. The rest are similar and will not be elaborated further.

[0219] Combination Figure 4 , Figure 15 and Figure 17 As shown, when inputting to the gate drive circuit Figure 4 As shown in the signal timing diagram, the output signal terminals GAO_1 of shift register unit SR1 can output signal ga1_2, GAO_2 can output signal ga2_2, GAO_3 can output signal ga3_2, and GAO_4 can output signal ga4_2. The output signal terminals GAO_1 of shift register unit SR2 can output signal ga5_2, GAO_2 can output signal ga6_2, GAO_3 can output signal ga7_2, and GAO_4 can output signal ga8_2. The output signal terminals GAO_1 of shift register unit SR3 can output signal ga9_2, GAO_2 can output signal ga10_2, GAO_3 can output signal ga11_2, and GAO_4 can output signal ga12_2. The rest are similar and will not be elaborated further.

[0220] In this embodiment of the disclosure, by combining the above-described shift register unit, the gate drive circuit can achieve... Figure 4 and Figure 14 The signal timing diagram shown corresponds to the working process, the specific process of which will not be elaborated here. Of course, in practical applications, other shift register unit structures can also be used to achieve the same result. Figure 4 and Figure 14 The working process corresponding to the signal timing diagram shown is not limited here.

[0221] This disclosure provides other implementation methods, such as... Figure 18As shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0222] In some embodiments of this disclosure, the control clock signal terminal of the shift register unit may also employ a clock control signal independently configured from the first clock signal to improve the corresponding timing signal. Exemplarily, the display panel further includes multiple clock control lines, with different clock control lines transmitting different clock control signals. The shift register unit also has a control clock signal terminal; the driving method further includes: while inputting multiple different first clock signals to the gate driving circuit in the display panel, simultaneously inputting multiple different first clock control signals to the control clock signal terminal of the gate driving circuit.

[0223] For example, in three adjacent gate groups, the control clock signal terminal of the shift register unit corresponding to the first gate group is coupled to the first first clock control signal among multiple different first clock control signals; the control clock signal terminal of the shift register unit corresponding to the second gate group is coupled to the second first clock control signal among multiple different first clock control signals; and the control clock signal terminal of the shift register unit corresponding to the third gate group is coupled to the third first clock control signal among multiple different first clock control signals. The timing of the first first clock control signal is the same as that of the first first clock signal in the first clock signal group; the timing of the second first clock control signal is the same as that of the first first clock signal in the second clock signal group; and the timing of the third first clock control signal is the same as that of the first first clock signal in the third clock signal group. For example, as... Figure 18 and Figure 19 As shown, the display panel may include three clock control lines CKC1 to CKC3. Clock control line CKC1 transmits the first first clock control signal ckc1_1, clock control line CKC2 transmits the second first clock control signal ckc2_1, and clock control line CKC3 transmits the third first clock control signal ckc3_1. The timing of the first first clock control signal ckc1_1 is the same as that of the first clock signal ck1_1, the timing of the second first clock control signal ckc2_1 is the same as that of the first clock signal ck5_1, and the timing of the third first clock control signal ckc3_1 is the same as that of the first clock signal ck9_1.

[0224] In some embodiments of this disclosure, in the second driving mode, in every three adjacent shift register units, the control clock signal terminal of the first shift register unit is coupled to the first first clock control signal among a plurality of different clock control signals, the control clock signal terminal of the second shift register unit is coupled to the second first clock control signal among a plurality of different clock control signals, and the control clock signal terminal of the third shift register unit is coupled to the third first clock control signal among a plurality of different clock control signals. For example, as Figure 18 and Figure 19 As shown, the control clock signal terminals of shift register units SR1 and SR4 are coupled to the first first clock control signal ckc1_1, and are also coupled to the clock control line CKC1. The control clock signal terminals of shift register units SR2 and SR5 are coupled to the second first clock control signal ckc2_1, and are also coupled to the clock control line CKC2. The control clock signal terminals of shift register units SR3 and SR6 are coupled to the third first clock control signal ckc3_1, and are also coupled to the clock control line CKC3.

[0225] For example, such as Figure 18 As shown, in every two adjacent shift register units, the GAO_C of the previous shift register unit is coupled to the input signal terminal INP of the next shift register unit. In every three adjacent shift register units, the GAO_C of the third shift register unit is coupled to the reset signal terminal RST_PU of the first shift register unit.

[0226] For example, in the second drive mode, combined with Figures 17 to 19 As shown, shift register unit SR1 can output the first high level of the first clock signal ck1_1 to gate line GA1 to generate the high level in signal ga1_1. Similarly, shift register unit SR1 can output the first high level of the first clock signal ck2_1 to gate line GA2 to generate the high level in signal ga2_1. Shift register unit SR1 can also output the first high level of the first clock signal ck3_1 to gate line GA3 to generate the high level in signal ga3_1. Finally, shift register unit SR1 can output the first high level of the first clock signal ck4_1 to gate line GA4 to generate the high level in signal ga4_1.

[0227] Furthermore, shift register unit SR2 can output the first high level of the first clock signal ck5_1 to gate line GA5 to generate the high level in signal ga5_1. Shift register unit SR2 can also output the first high level of the first clock signal ck6_1 to gate line GA6 to generate the high level in signal ga6_1. Shift register unit SR2 can also output the first high level of the first clock signal ck7_1 to gate line GA7 to generate the high level in signal ga7_1. Shift register unit SR2 can also output the first high level of the first clock signal ck8_1 to gate line GA8 to generate the high level in signal ga8_1.

[0228] Furthermore, shift register unit SR3 can output the first high level of the first clock signal ck9_1 to gate line GA9 to generate the high level in signal ga9_1. Shift register unit SR3 can also output the first high level of the first clock signal ck10_1 to gate line GA10 to generate the high level in signal ga10_1. Shift register unit SR3 can also output the first high level of the first clock signal ck11_1 to gate line GA11 to generate the high level in signal ga11_1. Shift register unit SR3 can also output the first high level of the first clock signal ck12_1 to gate line GA12 to generate the high level in signal ga12_1.

[0229] Furthermore, shift register unit SR4 can output the second high level of the first clock signal ck1_1 to gate line GA13 to generate a high level in the second gate scan signal on gate line GA13. Shift register unit SR4 can also output the second high level of the first clock signal ck2_1 to gate line GA14 to generate a high level in the second gate scan signal on gate line GA14. Shift register unit SR4 can also output the second high level of the first clock signal ck3_1 to gate line GA15 to generate a high level in the second gate scan signal on gate line GA15. Finally, shift register unit SR4 can output the second high level of the first clock signal ck4_1 to gate line GA16 to generate a high level in the second gate scan signal on gate line GA16.

[0230] Furthermore, shift register unit SR5 can output the second high level of the first clock signal ck5_1 to gate line GA17 to generate a high level in the second gate scan signal on gate line GA17. Shift register unit SR5 can also output the second high level of the first clock signal ck6_1 to gate line GA18 to generate a high level in the second gate scan signal on gate line GA18. Shift register unit SR5 can also output the second high level of the first clock signal ck7_1 to gate line GA19 to generate a high level in the second gate scan signal on gate line GA19. Finally, shift register unit SR5 can output the second high level of the first clock signal ck8_1 to gate line GA20 to generate a high level in the second gate scan signal on gate line GA20.

[0231] Furthermore, shift register unit SR6 can output the second high level of the first clock signal ck9_1 to gate line GA21 to generate a high level in the second gate scan signal on gate line GA21. Shift register unit SR6 can also output the second high level of the first clock signal ck10_1 to gate line GA22 to generate a high level in the second gate scan signal on gate line GA22. Shift register unit SR6 can also output the second high level of the first clock signal ck11_1 to gate line GA23 to generate a high level in the second gate scan signal on gate line GA23. Finally, shift register unit SR6 can output the second high level of the first clock signal ck12_1 to gate line GA24 to generate a high level in the second gate scan signal on gate line GA24.

[0232] In some embodiments of this disclosure, the control clock signal terminal of the shift register unit may also employ a clock control signal independently configured from the first clock signal to improve the corresponding timing signal. Exemplarily, the display panel further includes multiple clock control lines, with different clock control lines transmitting different clock control signals. For example, such as... Figure 18 and Figure 20 As shown, the display panel may include three clock control lines CKC1 to CKC3. CKC1 transmits the first second clock control signal ckc1_2, CKC2 transmits the second second clock control signal ckc2_2, and CKC3 transmits the third second clock control signal ckc3_2.

[0233] In some embodiments of this disclosure, in the first driving mode, in every three adjacent shift register units, the control clock signal terminal of the first shift register unit is coupled to the first second clock control signal among a plurality of different clock control signals, the control clock signal terminal of the second shift register unit is coupled to the second second clock control signal among a plurality of different clock control signals, and the control clock signal terminal of the third shift register unit is coupled to the third second clock control signal among a plurality of different clock control signals. For example, as Figure 18 and Figure 20 As shown, the control clock signal terminals of shift register units SR1 and SR4 are coupled to the first second clock control signal ckc1_2, and are also coupled to the clock control line CKC1. The control clock signal terminals of shift register units SR2 and SR5 are coupled to the second second clock control signal ckc2_2, and are also coupled to the clock control line CKC2. The control clock signal terminals of shift register units SR3 and SR6 are coupled to the third second clock control signal ckc3_2, and are also coupled to the clock control line CKC3.

[0234] For example, in the first drive mode, combined with Figure 17 , Figure 18 as well as Figure 20 As shown, shift register unit SR1 can output the first high level of the second clock signal ck1_2 to gate line GA1 to generate the high level in signal ga1_2. Similarly, shift register unit SR1 can output the first high level of the second clock signal ck2_2 to gate line GA2 to generate the high level in signal ga2_2. Shift register unit SR1 can also output the first high level of the second clock signal ck3_2 to gate line GA3 to generate the high level in signal ga3_2. Finally, shift register unit SR1 can output the first high level of the second clock signal ck4_2 to gate line GA4 to generate the high level in signal ga4_2.

[0235] Furthermore, shift register unit SR2 can output the first high level of the second clock signal ck5_2 to gate line GA5 to generate the high level in signal ga5_2. Shift register unit SR2 can also output the first high level of the second clock signal ck6_2 to gate line GA6 to generate the high level in signal ga6_2. Shift register unit SR2 can also output the first high level of the second clock signal ck7_2 to gate line GA7 to generate the high level in signal ga7_2. Shift register unit SR2 can also output the first high level of the second clock signal ck8_2 to gate line GA8 to generate the high level in signal ga8_2.

[0236] Furthermore, shift register unit SR3 can output the first high level of the second clock signal ck9_2 to gate line GA9 to generate the high level in signal ga9_2. Shift register unit SR3 can also output the first high level of the second clock signal ck10_2 to gate line GA10 to generate the high level in signal ga10_2. Shift register unit SR3 can also output the first high level of the second clock signal ck11_2 to gate line GA11 to generate the high level in signal ga11_2. Shift register unit SR3 can also output the first high level of the second clock signal ck12_2 to gate line GA12 to generate the high level in signal ga12_2.

[0237] Furthermore, shift register unit SR4 can output the second high level of the second clock signal ck1_2 to gate line GA13 to generate a high level in the second gate scan signal on gate line GA13. Shift register unit SR4 can also output the second high level of the second clock signal ck2_2 to gate line GA14 to generate a high level in the second gate scan signal on gate line GA14. Shift register unit SR4 can also output the second high level of the second clock signal ck3_2 to gate line GA15 to generate a high level in the second gate scan signal on gate line GA15. Finally, shift register unit SR4 can output the second high level of the second clock signal ck4_2 to gate line GA16 to generate a high level in the second gate scan signal on gate line GA16.

[0238] Furthermore, shift register unit SR5 can output the second high level of the second clock signal ck5_2 to gate line GA17 to generate a high level in the second gate scan signal on gate line GA17. Shift register unit SR5 can also output the second high level of the second clock signal ck6_2 to gate line GA18 to generate a high level in the second gate scan signal on gate line GA18. Shift register unit SR5 can also output the second high level of the second clock signal ck7_2 to gate line GA19 to generate a high level in the second gate scan signal on gate line GA19. Shift register unit SR5 can also output the second high level of the second clock signal ck8_2 to gate line GA20 to generate a high level in the second gate scan signal on gate line GA20.

[0239] Furthermore, shift register unit SR6 can output the second high level of the second clock signal ck9_2 to gate line GA21 to generate a high level in the second gate scan signal on gate line GA21. Shift register unit SR6 can also output the second high level of the second clock signal ck10_2 to gate line GA22 to generate a high level in the second gate scan signal on gate line GA22. Shift register unit SR6 can also output the second high level of the second clock signal ck11_2 to gate line GA23 to generate a high level in the second gate scan signal on gate line GA23. Finally, shift register unit SR6 can output the second high level of the second clock signal ck12_2 to gate line GA24 to generate a high level in the second gate scan signal on gate line GA24.

[0240] This disclosure provides further implementation methods, such as... Figure 18 As shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0241] In some embodiments of this disclosure, a shift register unit may also be coupled to a gate line. Furthermore, multiple adjacent shift register units are grouped into a unit group; in each group of three adjacent units, the output clock signal of the shift register unit in the first unit group is coupled to the first clock signal group of the three clock signal groups, the output clock signal of the shift register unit in the second unit group is coupled to the second clock signal group of the three clock signal groups, and the output clock signal of the shift register unit in the third unit group is coupled to the third clock signal group of the three clock signal groups.

[0242] For example, such as Figure 21As shown, in every five adjacent shift register units, the GAO_C of the first shift register unit is coupled to the input signal terminal INP of the fifth shift register unit. In every nine adjacent shift register units, the GAO_C of the ninth shift register unit is coupled to the reset signal terminal RST_PU of the first shift register unit.

[0243] For example, such as Figure 21 and Figure 14As shown, each shift register unit is coupled to a gate line. Four adjacent shift register units can be grouped together: shift register units SR1-SR4 form one group, shift register units SR5-SR8 form another group, and shift register units SR9-SR12 form yet another group. Furthermore, in the first drive mode, the output clock signal CLK of shift register unit SR1 is coupled to the first clock signal ck1_1 in the first clock signal group, i.e., the output clock signal CLK of shift register unit SR1 is coupled to clock signal line CK1. The output clock signal CLK of shift register unit SR2 is coupled to the first clock signal ck2_1 in the first clock signal group, i.e., the output clock signal CLK of shift register unit SR2 is coupled to clock signal line CK2. The output clock signal CLK of shift register unit SR3 is coupled to the first clock signal ck3_1 in the first clock signal group, i.e., the output clock signal CLK of shift register unit SR3 is coupled to clock signal line CK3. The output clock signal CLK of shift register unit SR4 is coupled to the first clock signal ck4_1 in the first clock signal group, that is, the output clock signal CLK of shift register unit SR4 is coupled to clock signal line CK4. The output clock signal CLK of shift register unit SR5 is coupled to the first clock signal ck5_1 in the second clock signal group, that is, the output clock signal CLK of shift register unit SR5 is coupled to clock signal line CK5. The output clock signal CLK of shift register unit SR6 is coupled to the first clock signal ck6_1 in the second clock signal group, that is, the output clock signal CLK of shift register unit SR6 is coupled to clock signal line CK6. The output clock signal CLK of shift register unit SR7 is coupled to the first clock signal ck7_1 in the second clock signal group, that is, the output clock signal CLK of shift register unit SR7 is coupled to clock signal line CK7. The output clock signal CLK of shift register unit SR8 is coupled to the first clock signal ck8_1 in the second clock signal group, that is, the output clock signal CLK of shift register unit SR8 is coupled to the clock signal line CK8. The output clock signal CLK of shift register unit SR9 is coupled to the first clock signal ck9_1 in the third clock signal group, that is, the output clock signal CLK of shift register unit SR9 is coupled to the clock signal line CK9. The output clock signal CLK of shift register unit SR10 is coupled to the first clock signal ck10_1 in the third clock signal group, that is, the output clock signal CLK of shift register unit SR10 is coupled to the clock signal line CK10.The output clock signal terminal CLK of shift register unit SR11 is coupled to the first clock signal ck11_1 in the third clock signal group, that is, the output clock signal terminal CLK of shift register unit SR11 is coupled to the clock signal line CK11. The output clock signal terminal CLK of shift register unit SR12 is coupled to the first clock signal ck12_1 in the third clock signal group, that is, the output clock signal terminal CLK of shift register unit SR12 is coupled to the clock signal line CK12.

[0244] For example, such as Figure 21 and Figure 4As shown, each shift register unit is coupled to one gate line. Four adjacent shift register units can be grouped together: shift register units SR1-SR4 form one group, shift register units SR5-SR8 form another group, and shift register units SR9-SR12 form yet another group. Furthermore, in the second drive mode, the output clock signal CLK of shift register unit SR1 is coupled to the second clock signal ck1_2, meaning CLK is coupled to clock signal line CK1. The output clock signal CLK of shift register unit SR2 is coupled to the second clock signal ck2_2, meaning CLK is coupled to clock signal line CK2. The output clock signal CLK of shift register unit SR3 is coupled to the second clock signal ck3_2, meaning CLK is coupled to clock signal line CK3. The output clock signal CLK of shift register unit SR4 is coupled to the second clock signal ck4_2, that is, the output clock signal CLK of shift register unit SR4 is coupled to clock signal line CK4. The output clock signal CLK of shift register unit SR5 is coupled to the second clock signal ck5_2, that is, the output clock signal CLK of shift register unit SR5 is coupled to clock signal line CK5. The output clock signal CLK of shift register unit SR6 is coupled to the second clock signal ck6_2, that is, the output clock signal CLK of shift register unit SR6 is coupled to clock signal line CK6. The output clock signal CLK of shift register unit SR7 is coupled to the second clock signal ck7_2, that is, the output clock signal CLK of shift register unit SR7 is coupled to clock signal line CK7. The output clock signal CLK of shift register unit SR8 is coupled to the second clock signal ck8_2, that is, the output clock signal CLK of shift register unit SR8 is coupled to clock signal line CK8. The output clock signal CLK of shift register unit SR9 is coupled to the second clock signal ck9_2, that is, the output clock signal CLK of shift register unit SR9 is coupled to the clock signal line CK9. The output clock signal CLK of shift register unit SR10 is coupled to the second clock signal ck10_2, that is, the output clock signal CLK of shift register unit SR10 is coupled to the clock signal line CK10. The output clock signal CLK of shift register unit SR11 is coupled to the second clock signal ck11_2, that is, the output clock signal CLK of shift register unit SR11 is coupled to the clock signal line CK11. The output clock signal CLK of shift register unit SR12 is coupled to the second clock signal ck12_2, that is, the output clock signal CLK of shift register unit SR12 is coupled to the clock signal line CK12.

[0245] In some embodiments of this disclosure, such as Figure 22 As shown, the shift register unit may include: pull-up circuit 10, control circuit 20, cascade circuit 30 and output circuit 40.

[0246] Pull-up circuit 10 is connected to the input signal terminal INP of the shift register unit, the total pull-up node PU, and the pull-down node PD. Pull-up circuit 10 is configured to provide the signal of input signal terminal INP to the total pull-up node PU, and pull down the potential of the total pull-up node PU under the control of the potential of pull-down node PD.

[0247] The control circuit 20 is connected to the main pull-up node PU and the pull-down node PD. The control circuit 20 is configured to control the potential of the pull-down node PD according to the potential of the main pull-up node PU.

[0248] The cascade circuit 30 is connected to the main pull-up node PU, the pull-down node PD, the GAO_C of the shift register unit, and the control clock signal terminal CLK_C. The cascade circuit 30 is configured to provide the signal of the control clock signal terminal CLK_C to GAO_C under the control of the potential of the main pull-up node PU, and to pull down the potential of GAO_C under the control of the potential of the pull-down node PD.

[0249] The output circuit 40 is connected to the input signal terminal INP, the pull-down node PD, the output clock signal terminal CLK of the shift register unit, the pull-up node PU_1, and the output signal terminal GAO_O. The output circuit 40 is configured to input the signal from the input signal terminal INP to the pull-up node PU_1, provide the signal from the output clock signal terminal CLK to the output signal terminal GAO_O under the control of the potential of the pull-up node PU_1, and pull down the potential of the output signal terminal GAO_O under the control of the potential of the pull-down node PD.

[0250] In some embodiments of this disclosure, such as Figure 23As shown, the pull-up circuit 10 includes an eighteenth transistor M18, a nineteenth transistor M19, and a twentieth transistor M20. The gate and first terminal of the eighteenth transistor M18 are connected to the input signal terminal INP, and its second terminal is connected to the overall pull-up node PU. The gate of the nineteenth transistor M19 is connected to the pull-down node, its first terminal is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit, and its second terminal is connected to the overall pull-up node PU. The gate of the twentieth transistor M20 is connected to the reset signal terminal RST_PU of the shift register unit, its first terminal is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL), and its second terminal is connected to the overall pull-up node PU.

[0251] In some embodiments of this disclosure, such as Figure 23 As shown, the control circuit 20 may include an eighth transistor M8 and a ninth transistor M9. The gate and first terminal of the eighth transistor M8 are connected to the power supply signal terminal VDD of the shift register unit, and the second terminal of the eighth transistor M8 is connected to the pull-down node PD. The gate of the ninth transistor M9 is connected to the total pull-up node PU, the first terminal of the ninth transistor M9 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit, and the second terminal of the ninth transistor M9 is connected to the pull-down node PD.

[0252] In some embodiments of this disclosure, such as Figure 23 As shown, the cascaded circuit 30 may include a twenty-second transistor M22, a twenty-third transistor M23, and a second capacitor C2. The gate of the twenty-second transistor M22 is connected to the overall pull-up node PU, its first terminal is connected to the control clock signal terminal CLK_C, and its second terminal is connected to GAO_C. The gate of the twenty-third transistor M23 is connected to the pull-down node PD, its first terminal is connected to the reference signal terminal of the shift register unit (e.g., the first reference signal terminal LVGL), and its second terminal is connected to GAO_C. The first terminal of the second capacitor C2 is connected to the gate of the twenty-second transistor M22, and its second terminal is connected to GAO_C.

[0253] In some embodiments of this disclosure, such as Figure 23As shown, the output circuit 40 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a first capacitor C1. The gate and first terminal of the first transistor M1 are connected to the input signal terminal INP, and the second terminal of the first transistor M1 is connected to the pull-up node PU_1. The gate of the second transistor M2 is connected to the pull-up node PU_1, the first terminal of the second transistor M2 is connected to the output clock signal terminal CLK_1, and the second terminal of the second transistor M2 is connected to the output signal terminal GAO. The gate of the third transistor M3 is connected to the pull-down node PD, the first terminal of the third transistor M3 is connected to the reference signal terminal of the shift register unit (e.g., the first reference signal terminal LVGL), and the second terminal of the third transistor M3 is connected to the pull-up node PU_1. The gate of the fourth transistor M4 is connected to the pull-down node PD, the first terminal of the fourth transistor M4 is connected to the reference signal terminal of the shift register unit (e.g., the second reference signal terminal VGL), and the second terminal of the fourth transistor M4 is connected to the output signal terminal GAO. The first terminal of the first capacitor C1 is connected to the pull-up node PU_1, and the second terminal of the first capacitor C1 is connected to the output signal terminal GAO.

[0254] Combination Figure 14 , Figure 21 and Figure 23 As shown, when inputting to the gate drive circuit Figure 14 When the signal timing is shown, the output signal terminal GAO of shift register unit SR1 can output signal ga1_1. The output signal terminal GAO of shift register unit SR2 can output signal ga2_1. The output signal terminal GAO of shift register unit SR3 can output signal ga3_1. ... The output signal terminal GAO of shift register unit SR9 can output signal ga9_1. The output signal terminal GAO of shift register unit SR10 can output signal ga10_1. The output signal terminal GAO of shift register unit SR11 can output signal ga11_1. The output signal terminal GAO of shift register unit SR12 can output signal ga12_1. The rest are similar and will not be elaborated here.

[0255] Combination Figure 4 , Figure 21 and Figure 23 As shown, when inputting to the gate drive circuit Figure 4When the signal timing is shown, the output signal terminal GAO of shift register unit SR1 can output signal ga1_2. The output signal terminal GAO of shift register unit SR2 can output signal ga2_2. The output signal terminal GAO of shift register unit SR3 can output signal ga3_2. ... The output signal terminal GAO of shift register unit SR9 can output signal ga9_2. The output signal terminal GAO of shift register unit SR10 can output signal ga10_2. The output signal terminal GAO of shift register unit SR11 can output signal ga11_2. The output signal terminal GAO of shift register unit SR12 can output signal ga12_2. The rest are similar and will not be elaborated here.

[0256] In this embodiment of the disclosure, by combining the above-described shift register unit, the gate drive circuit can achieve... Figure 4 and Figure 14 The signal timing diagram shown corresponds to the working process, the specific process of which will not be elaborated here. Of course, in practical applications, other shift register unit structures can also be used to achieve the same result. Figure 4 and Figure 14 The working process corresponding to the signal timing diagram shown is not limited here.

[0257] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0258] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0259] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0260] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0261] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0262] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A method for driving a display panel, comprising: Get the raw display data of the current display frame; When the first driving mode is determined to be adopted, a first gate scan signal is loaded onto the gate lines in the display panel, and according to the target display data obtained after deleting part of the original display data, a data voltage is loaded onto the data lines in the display panel so that each sub-pixel in the display panel is charged with data voltage. The display panel includes multiple gate lines. For at least one of the multiple gate lines, the effective pulse of the first gate scan signal loaded on the gate line has a first overlap duration with the effective pulse of the first gate scan signal loaded on the adjacent previous gate line, and the effective pulse of the first gate scan signal loaded on the gate line has a second overlap duration with the effective pulse of the first gate scan signal loaded on the adjacent next gate line. The first overlap duration and the second overlap duration are different. For the 2kth gate line, the first overlap duration corresponding to the 2kth gate line is less than the second overlap duration; where k is an integer greater than 0.

2. The driving method for the display panel as described in claim 1, wherein, The first overlap duration corresponding to the 2kth gate line is the same; and / or, the second overlap duration corresponding to the 2kth gate line is the same.

3. The driving method for the display panel as described in claim 2, wherein, The second overlap duration corresponding to the 2kth gate line is an even multiple of the first overlap duration.

4. The driving method for a display panel as described in any one of claims 1-3, wherein, For the 2m+1th gate line, the first overlap duration corresponding to the 2m+1th gate line is greater than the second overlap duration; where m is an integer greater than 0.

5. The driving method for the display panel as described in claim 4, wherein, The first overlap duration corresponding to the 2m+1th gate line is the same; and / or, the second overlap duration corresponding to the 2m+1th gate line is the same.

6. The driving method for a display panel as described in claim 5, wherein, The first overlap duration corresponding to the 2m+1th grid line is an even multiple of the second overlap duration.

7. The driving method for a display panel as described in any one of claims 1-3, wherein, The display panel includes multiple gate lines, with at least four gate lines forming a gate line group. The start time of the effective pulse of the first gate scan signal loaded on the gate line in each gate line group appears sequentially in the order of the first gate line, the third gate line, the second gate line, and the fourth gate line in the gate line group.

8. The driving method for a display panel as described in any one of claims 1-3, wherein, The display panel includes multiple sub-pixel rows; the multiple sub-pixel rows are divided into multiple sub-pixel row groups, and each sub-pixel row group includes sub-pixel rows spaced N times apart; N is an integer greater than 0; The target display data includes the display data corresponding to each sub-pixel in one of the sub-pixel row groups.

9. The driving method for a display panel as described in claim 8, wherein, N=1, and the plurality of sub-pixel row groups include a first sub-pixel row group and a second sub-pixel row group; the first sub-pixel row group includes the odd-numbered sub-pixel row, and the second sub-pixel row group includes the even-numbered sub-pixel row; The current display frame is the odd-numbered display frame in a series of consecutive displays, and the target display data includes display data corresponding to each sub-pixel in the first sub-pixel row group or the second sub-pixel row group; and / or, The current display frame is the even-numbered display frame in a series of consecutive displays, and the target display data includes the display data of each sub-pixel in the first sub-pixel row group or the second sub-pixel row group.

10. The driving method for a display panel as described in claim 9, wherein, Two adjacent sub-pixels in the same column share a single data voltage.

11. The driving method for a display panel as described in claim 7, wherein, The step of loading a first gate scan signal onto the gate lines in the display panel includes: Multiple different first clock signals are input to the gate drive circuit in the display panel so that the valid pulses in the first clock signals are loaded onto the gate lines as valid pulses of the first gate scan signal.

12. The driving method for a display panel as described in claim 11, wherein, The gate drive circuit includes multiple shift register units; each shift register unit has an output clock signal terminal. The multiple different first clock signals are divided into three clock signal groups; in the three adjacent gate groups, the output clock signal terminal of the shift register unit corresponding to the first gate group is coupled to the first clock signal group in the three clock signal groups, the output clock signal terminal of the shift register unit corresponding to the second gate group is coupled to the second clock signal group in the three clock signal groups, and the output clock signal terminal of the shift register unit corresponding to the third gate group is coupled to the third clock signal group in the three clock signal groups.

13. The driving method for a display panel as described in claim 12, wherein, The plurality of different first clock signals include 12 first clock signals; the 12 first clock signals are divided into three clock signal groups, and in each clock signal group, the effective pulse of each first clock signal appears sequentially in the order of the first first clock signal, the third first clock signal, the second first clock signal, and the fourth first clock signal in the clock signal group; The start time of the effective pulse of the fourth first clock signal in the first clock signal group is earlier than the start time of the effective pulse of the first first clock signal in the second clock signal group; and the start time of the effective pulse of the fourth first clock signal in the second clock signal group is earlier than the start time of the effective pulse of the first first clock signal in the third clock signal group.

14. The driving method for a display panel as described in claim 13, wherein, In the same group of clock signals, the first clock signal and the fourth clock signal have opposite phases.

15. The driving method for a display panel as described in claim 14, wherein, The clock signals appearing in the same sequence in the first clock signal group and the second clock signal group are 2π / 3 out of phase; the clock signals appearing in the same sequence in the second clock signal group and the third clock signal group are 2π / 3 out of phase.

16. The driving method for a display panel as described in any one of claims 13-15, wherein, The shift register unit also has a control clock signal terminal; in the three adjacent gate line groups, the control clock signal terminal of the shift register unit corresponding to the first gate line group is coupled to the first first clock signal in the first clock signal group, the control clock signal terminal of the shift register unit corresponding to the second gate line group is coupled to the first first clock signal in the second clock signal group, and the control clock signal terminal of the shift register unit corresponding to the third gate line group is coupled to the first first clock signal in the third clock signal group.

17. The driving method for a display panel as described in any one of claims 13-15, wherein, The shift register unit also has a control clock signal terminal; the driving method further includes: While inputting multiple different first clock signals to the gate driving circuit in the display panel, multiple different first clock control signals are also input to the control clock signal terminal of the gate driving circuit.

18. The driving method for a display panel as described in claim 17, wherein, In the three adjacent gate line groups, the control clock signal terminal of the shift register unit corresponding to the first gate line group is coupled to the first first clock control signal among the plurality of different first clock control signals, the control clock signal terminal of the shift register unit corresponding to the second gate line group is coupled to the second first clock control signal among the plurality of different first clock control signals, and the control clock signal terminal of the shift register unit corresponding to the third gate line group is coupled to the third first clock control signal among the plurality of different first clock control signals; The first first clock control signal has the same timing as the first first clock signal in the first clock signal group, the second first clock control signal has the same timing as the first first clock signal in the second clock signal group, and the third first clock control signal has the same timing as the first first clock signal in the third clock signal group.

19. The driving method for a display panel as described in any one of claims 1-3, wherein, When the second driving mode is determined to be adopted, a second gate scan signal is loaded onto the gate lines in the display panel, and a data voltage is loaded onto the data lines directly according to the original display data, so that each sub-pixel in the display panel is charged with data voltage; The difference between the start times of the effective pulses of the second gate scan signal loaded on each of the two adjacent gate lines is the same.

20. A display device, comprising: Display panel; The controller is configured to acquire the raw display data of the current display frame; When the first driving mode is determined to be adopted, a first gate scan signal is loaded onto the gate lines in the display panel, and according to the target display data obtained after deleting part of the original display data, a data voltage is loaded onto the data lines in the display panel so that each sub-pixel in the display panel is charged with data voltage. The display panel includes multiple gate lines. For at least one of the gate lines, the effective pulse of the first gate scan signal loaded on the gate line has a first overlap duration with the effective pulse of the first gate scan signal loaded on the adjacent previous gate line, and the effective pulse of the first gate scan signal loaded on the gate line has a second overlap duration with the effective pulse of the first gate scan signal loaded on the adjacent next gate line. The first overlap duration and the second overlap duration are different. For the 2kth gate line, the first overlap duration corresponding to the 2kth gate line is less than the second overlap duration. Here, k is an integer greater than 0.

21. The display device as claimed in claim 20, wherein, The controller includes: a system controller and a timing controller; The system controller is configured to acquire the raw display data of the current display frame; when it is determined that the first driving mode is adopted, the target display data obtained by deleting part of the raw display data is sent to the timing controller; The timing controller is configured to send the received target display data to the source drive circuit. The source drive circuit is configured to apply a data voltage to the data lines in the display panel based on the received target display data.

22. The display device as claimed in claim 20, wherein, The controller includes: a system controller and a timing controller; The system controller is configured to acquire the raw display data of the current display frame and send the raw display data to the timing controller. The timing controller is configured to send the target display data obtained by deleting part of the original display data to the source drive circuit when it is determined that the first driving mode is adopted. The source drive circuit is configured to apply a data voltage to the data lines in the display panel based on the received target display data.

23. The display device as claimed in claim 20, wherein, The controller includes: a system controller and a timing controller; The system controller is configured to acquire the raw display data of the current display frame and send the raw display data to the timing controller. The timing controller is configured to send the received raw display data to the source drive circuit; The source drive circuit is configured to, when the first drive mode is determined, process the original display data by deleting part of the data to obtain target display data, and apply data voltage to the data lines in the display panel according to the target display data.

24. The display device according to any one of claims 20-23, wherein, The display panel further includes: a gate driving circuit that receives multiple different first clock signals; the multiple different first clock signals are divided into three clock signal groups; The gate drive circuit includes multiple shift register units; wherein, one of the shift register units is coupled to multiple adjacent gate lines; In each of the three adjacent shift register units, the output clock signal of the first shift register unit is coupled to the first clock signal group of the three clock signal groups, the output clock signal of the second shift register unit is coupled to the second clock signal group of the three clock signal groups, and the output clock signal of the third shift register unit is coupled to the third clock signal group of the three clock signal groups.

25. The display device as claimed in claim 24, wherein, In each of the three adjacent shift register units, the control clock signal terminal of the first shift register unit is coupled to the first first clock signal in the first clock signal group, the control clock signal terminal of the second shift register unit is coupled to the first first clock signal in the second clock signal group, and the control clock signal terminal of the third shift register unit is coupled to the first first clock signal in the third clock signal group.

26. The display device as claimed in claim 24, wherein, In each of the three adjacent shift register units, the control clock signal terminal of the first shift register unit is coupled to the first first clock control signal among a plurality of different clock control signals, the control clock signal terminal of the second shift register unit is coupled to the second first clock control signal among the plurality of different clock control signals, and the control clock signal terminal of the third shift register unit is coupled to the third first clock control signal among the plurality of different clock control signals.

27. The display device as claimed in claim 25 or 26, wherein, The shift register unit includes: A pull-up circuit is connected to the input signal terminal, the main pull-up node, and the pull-down node of the shift register unit. The pull-up circuit is configured to provide the signal from the input signal terminal to the main pull-up node and pull down the potential of the main pull-up node under the control of the potential of the pull-down node. A control circuit, connected to the main pull-up node and the pull-down node, is configured to control the potential of the pull-down node based on the potential of the main pull-up node; A cascaded circuit is connected to the main pull-up node, the pull-down node, and the shift register unit, and to the control clock signal terminal. The cascaded circuit is configured to provide the signal of the control clock signal terminal to the main pull-up node under the control of the potential of the main pull-up node, and to pull down the potential of the pull-down node under the control of the potential of the pull-down node. N output circuits are respectively connected to the input signal terminal, the pull-down node, and the N output clock signal terminals, N sub-pull-up nodes, and N output signal terminals of the shift register unit. The nth output circuit is connected to the input signal terminal, the pull-down node, the nth output signal terminal, and the nth sub-pull-up node, and is configured to input the signal from the input signal terminal to the nth sub-pull-up node, provide the signal from the nth output clock signal terminal to the nth output signal terminal under the control of the potential of the nth sub-pull-up node, and pull down the potential of the nth output signal terminal under the control of the potential of the pull-down node. N is an integer greater than 1, and n is an integer where 1 ≤ n ≤ N.

28. The display device according to any one of claims 20-23, wherein, The display panel further includes: a gate driving circuit that receives multiple different first clock signals; the multiple different first clock signals are divided into three clock signal groups; The gate drive circuit includes multiple shift register units; wherein, one of the shift register units is coupled to a gate line; A group of adjacent shift register units is formed as a unit group; in each group of three adjacent units, the output clock signal of the shift register unit of the first unit group is coupled to the first clock signal group of the three clock signal groups, the output clock signal of the shift register unit of the second unit group is coupled to the second clock signal group of the three clock signal groups, and the output clock signal of the shift register unit of the third unit group is coupled to the third clock signal group of the three clock signal groups.

29. The display device as claimed in claim 28, wherein, The shift register unit includes: a pull-up circuit connected to the input signal terminal, a main pull-up node, and a pull-down node of the shift register unit. The pull-up circuit is configured to provide the signal from the input signal terminal to the main pull-up node and pull down the potential of the main pull-up node under the control of the potential of the pull-down node. A control circuit, connected to the main pull-up node and the pull-down node, is configured to control the potential of the pull-down node based on the potential of the main pull-up node; A cascaded circuit is connected to the main pull-up node, the pull-down node, and the shift register unit, and to the control clock signal terminal. The cascaded circuit is configured to provide the signal of the control clock signal terminal to the main pull-up node under the control of the potential of the main pull-up node, and to pull down the potential of the pull-down node under the control of the potential of the pull-down node. The output circuit is connected to the input signal terminal, the pull-down node, the output clock signal terminal of the shift register unit, the pull-up node, and the output signal terminal, respectively. The output circuit is configured to input the signal from the input signal terminal to the pull-up node, provide the signal from the output clock signal terminal to the output signal terminal under the control of the potential of the pull-up node, and pull down the potential of the output signal terminal under the control of the potential of the pull-down node.

30. The display device according to any one of claims 20-23, wherein, The display panel includes: Multiple sub-pixels; wherein the multiple sub-pixels are divided into multiple sub-pixel groups; each sub-pixel group includes two adjacent sub-pixels in the same row; Multiple gate lines; wherein each sub-pixel row corresponds to two gate lines; one sub-pixel in the sub-pixel group is coupled to one of the two gate lines, and the other sub-pixel is coupled to the other of the two gate lines. Multiple data lines; wherein, a column of sub-pixels is set between each pair of adjacent data lines, and for each pair of adjacent data lines, the first data line is coupled to a column of sub-pixels in the column of sub-pixels between the two data lines that is closer to the second data line, and the second data line is coupled to a column of sub-pixels in the column of sub-pixels between the two data lines that is closer to the first data line.

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