Superconducting quantum bit chip and method of making the same

Abstract

Provided are a superconducting quantum bit chip and a method for manufacturing the same, wherein the superconducting quantum bit chip comprises a wiring layer chip and a bit layer chip, and the wiring layer chip and the bit layer chip can be coupled to each other through a flip-chip process, and the method comprises: preparing a deep undercut structure on a substrate of a patterned wiring layer chip and a bit layer chip, the deep undercut structure having a size greater than that of a required press-bonded superconductor, wherein the press-bonded superconductor can achieve mechanical and superconducting connection by applying sufficient pressure at room temperature; and preparing a press-bonded superconductor column for press bonding in the deep undercut structure.

Description

Technical Field

[0001] This invention relates to the field of multi-qubit chip design, and more particularly to a superconducting qubit chip and its fabrication method. Background Technology

[0002] In single-layer chip design, the coupling between qubits requires very close spacing or the use of other structures for coupling, making it difficult for coupled qubits to pass through wiring. This limits the arrangement of qubits to a one-dimensional chain, making it difficult to expand into a two-dimensional array. To achieve larger-scale expansion of superconducting qubits and higher connectivity between them, flip-chip bonding is now widely used. Flip-chip bonding involves fabricating qubits and wiring on two separate chips, called the qubit layer chip and the wiring layer chip, respectively. These two chips are then coupled face-to-face to enable the wiring to read and control the qubits. In this design, the wiring on the wiring layer chip can pass through the qubits on the opposite side, allowing control lines to pass between the qubits and thus control the qubits near the center in a two-dimensional array.

[0003] Currently, indium is commonly used to bond bit layer chips and wiring layer chips together to achieve coupling between the two chips. Indium is a relatively soft superconductor, and sufficient pressure applied at room temperature can achieve a good mechanical and superconducting connection between two indium blocks. In existing methods, such as [BFoxen et al, Quantum Sci. Technol., 3014005 (2018)] and [Chan U Lei et al, Appl. Phys. Lett., 116 154002 (2020)], indium is prepared as cubic pillars with a length and width of 10-20 μm and a height of 5-10 μm. During bonding, the indium pillars on the two chip layers need to be aligned, and the applied pressure is such that the height between the two chips after bonding is the same as the height of one indium pillar, that is, the relative indium pillar is compressed to half its original height.

[0004] Existing techniques for fabricating indium pillars suffer from several drawbacks, including photoresist residue during development, poor pillar growth morphology with severely uneven edges, incomplete photoresist removal, and significant residue of photoresist and indium films. Therefore, a method for fabricating indium pillars with optimized procedures and lower costs is needed. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a method for fabricating a superconducting quantum bit chip, wherein the superconducting quantum bit chip includes a wiring layer chip and a bit layer chip, and the wiring layer chip and the bit layer chip can be coupled to each other via a flip-chip bonding process. The method includes:

[0006] Deep undercut structures are fabricated on the substrates of patterned wiring layer chips and bit layer chips. The size of the deep undercut structures is larger than the size of the required bonding superconductor, wherein the bonding superconductor can achieve good mechanical and superconducting connections when sufficient pressure is applied at room temperature.

[0007] In the deep undercut structure, a pressure-welded superconductor pillar for pressure welding is prepared.

[0008] In one embodiment, fabricating the deep undercut structure on the substrates of the patterned wiring layer chip and the bit layer chip includes:

[0009] A first layer of photoresist is spin-coated onto the substrates of the patterned wiring layer chip and bit layer chip, with a thickness greater than the required height of the bonding superconductor.

[0010] The first exposure is performed on the first layer of photoresist, and the exposed pattern is larger than the length and width of the required bonding superconductor;

[0011] A second layer of photoresist is spin-coated, the thickness of which is less than the thickness of the first layer of photoresist.

[0012] A second exposure is performed on the second layer of photoresist, and the exposure pattern is consistent with the length and width of the desired bonding superconductor;

[0013] The deep undercut structure was obtained by developing with a developing solution; and

[0014] Fabricating a pressure-bonded superconductor pillar for pressure bonding in the deep undercut structure includes depositing a pressure-bonded superconductor film, removing the photoresist, and obtaining the pressure-bonded superconductor pillar.

[0015] In one embodiment, the pressure-welded superconductor is indium.

[0016] In one embodiment, after the step of vapor deposition and pressure bonding of the superconducting film, the step further includes: using reactive ion etching to bombard the surface with a mixture of argon and oxygen.

[0017] In one embodiment, during the first and second exposure steps, the portions surrounding the sample region in the sample-out region of the wiring layer wafer where the wiring layer chip is located and the bit layer wafer where the bit layer chip is located are exposed to prepare peripheral bonding superconductor portions in the sample-out region.

[0018] In one embodiment, the peripheral pressure-welded superconductor portion forms a closed loop.

[0019] In one embodiment, during the step of vapor deposition and bonding of the superconducting film, a sheet is used to cover areas on the wafer where there is no bonding superconductor pattern.

[0020] In one embodiment, the method further includes: arranging a plurality of large-area bonding superconductors around a bonding area of ​​one of the bit layer chip and the wiring layer chip, while not growing bonding superconductors at a corresponding location on the other chip, wherein the cross-section of the large-area bonding superconductors is larger than the cross-section of the bonding superconductor pillar.

[0021] In one embodiment, the method further includes:

[0022] Before spin-coating the first layer of photoresist, the film on the surface at the observation window position in the bonding area of ​​the bit layer chip is removed, wherein the substrate of the bit layer chip is a double-sided polished transparent substrate;

[0023] A superconducting pillar is fabricated at the superconducting observation window, and superconducting pillars and / or additional large-area superconductors are also fabricated at the corresponding positions of the wiring layer chip.

[0024] In one embodiment, the method further includes:

[0025] Before spin coating the first layer of photoresist, an electrode for detecting the electrical connection of the bonded superconductor pillars is prepared on the bonding area of ​​the wiring layer chip. The first end of the electrode is located outside the bonding area, and the second end is connected to the bonded superconductor pillar on the wiring layer chip. The corresponding bonded superconductor pillar on the bit layer chip is connected to ground.

[0026] The present invention also provides a superconducting quantum bit chip, which includes a wiring layer chip and a bit layer chip, and the wiring layer chip and the bit layer chip can be coupled to each other by flip-chip bonding; wherein, a plurality of large-area superconducting bonding superconductors are arranged around the bonding area of ​​one of the bit layer chip and the wiring layer chip, while no superconducting bonding superconductor is arranged at the corresponding position of the other chip, wherein the cross-section of the large-area superconducting bonding superconductor is larger than the cross-section of the superconducting bonding superconductor pillar.

[0027] In one embodiment, the bonding area of ​​the wiring layer chip further includes an electrode for detecting electrical connections of the bonding superconducting pillars, a first end of the electrode being located outside the bonding area, and a second end being connected to the bonding superconducting pillar on the wiring layer chip, wherein the corresponding bonding superconducting pillar on the bit layer chip is connected to ground.

[0028] In one embodiment, a long strip of superconductor is provided between the control lines of different qubits on the bit layer chip to suppress crosstalk.

[0029] In one embodiment, the pressure-welded superconductor is indium.

[0030] The superconducting quantum bit chip fabrication method provided by this invention can more stably produce indium with complete structure, good morphology, and clean resist removal. The superconducting quantum bit chip provided by this invention is easier to control in terms of bonding parameters; even when the bonding force fluctuates within a large range, two chips can be bonded to the same height, and the chip is less susceptible to interference from instrument errors. Attached Figure Description

[0031] Figure 1 A schematic diagram of a wafer in the prior art is shown.

[0032] Figure 2A A schematic diagram of a deep undercut structure of indium pillars for fabricating a quantum bit chip according to an embodiment of the present invention is shown.

[0033] Figure 2B A schematic diagram of a method for fabricating indium pillars in a quantum bit chip according to an embodiment of the present invention is shown.

[0034] Figure 3 A flowchart of a method for fabricating indium pillars in a quantum bit chip according to an embodiment of the present invention is shown.

[0035] Figure 4 A schematic diagram of exposing an area outside the sample is shown according to an embodiment of the present invention.

[0036] Figure 5 A schematic diagram of a large area of ​​indium on a chip according to an embodiment of the present invention is shown.

[0037] Figure 6 A schematic diagram of an electrode for detecting electrical connections of an indium pillar according to an embodiment of the present invention is shown.

[0038] Figure 7 A schematic diagram of a strip of indium on a wiring layer chip according to an embodiment of the present invention is shown.

[0039] Figure 8 It shows Figure 7 The cross-sectional view of the elongated indium structure shown. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments given in this invention are for illustrative purposes only and do not limit the scope of protection of this invention.

[0041] Figure 1 A schematic diagram of a wafer in the prior art is shown. (e.g.) Figure 1As shown, wafer 100 includes a sample region 101 and an off-sample region 102. The sample region 101, also known as a patterned region, has a large number of qubits or wiring patterns arranged on it. The off-sample region 102 typically does not have qubits or wiring patterns arranged on it, but may include some marking patterns. The sample region 101 includes multiple qubit chips 103, which can be either qubit layer chips or wiring layer chips. Although in Figure 1 Only nine chips 103 are shown, but those skilled in the art will understand that in practical applications, any suitable number of chips 103 may be included. Unpackaged chips 103 can be obtained by slicing the wafer 100.

[0042] In flip-chip design, qubit layer chips and wiring layer chips are typically fabricated first. After the qubits or wiring patterns in the sample areas of the qubit layer chips and wiring layer chips are fabricated, bonding superconductor pillars for bonding are finally fabricated on the qubit layer chips and wiring layer chips. This bonding superconductor is relatively soft, and sufficient pressure applied at room temperature allows the two superconductor pillars to achieve a good mechanical and superconducting connection. In one embodiment, the bonding superconductor is indium. For convenience, indium pillars are used as an example in the following detailed description, but the invention is not limited thereto. Indium pillars are typically distributed in the overlapping area of ​​the qubit layer chips and wiring layer chips. In one embodiment, the indium pillars are relatively uniformly distributed in the overlapping area of ​​the qubit layer chips and wiring layer chips. Typically, one-to-one corresponding indium pillars for bonding are fabricated on the qubit layer and wiring layer chips, and these indium pillars are bonded together one-to-one during bonding. After slicing, bonding is performed on the qubit layer chips and wiring layer chips, so that the two chips are coupled face-to-face. Then, the bonded chips are packaged to obtain a complete qubit chip.

[0043] Figure 2A A schematic diagram of a deep undercut structure of indium pillars for fabricating a quantum bit chip according to an embodiment of the present invention is shown. Figure 2B A schematic diagram of a method for fabricating indium pillars in a quantum bit chip according to an embodiment of the present invention is shown. Figure 3 A flowchart of a method for fabricating indium pillars in a quantum bit chip according to an embodiment of the present invention is shown, in conjunction with... Figure 2A , Figure 2B and Figure 3 The method includes the following steps:

[0044] Step 31: Spin-coat a first layer of relatively thick photoresist 202 onto the substrate 201 of the patterned wiring layer chip and bit layer chip, the thickness of which is greater than the required height of indium.

[0045] Indium pillars are distributed in the overlapping region of the bit layer chip and the wiring layer chip. Indium pillar fabrication begins after the wiring pattern on the wiring layer chip and the pattern of the qubit devices on the bit layer chip are completed. Here, the patterned wiring layer chip refers to the wiring layer chip after its wiring pattern is completed, and the patterned bit layer chip refers to the bit layer chip after the pattern of the qubit devices is completed.

[0046] Step 32: Perform the first exposure on the first layer of photoresist 202, with the exposed pattern larger than the required length and width of the indium. Typically, exposure is performed only on the sample area.

[0047] In this context, the height of the indium pillar refers to its dimension perpendicular to the substrate (i.e., the z-direction), the length of the indium pillar refers to its dimension along the plane of the paper (i.e., the x-direction), and the width of the indium pillar refers to its dimension perpendicular to the plane of the paper (i.e., the y-direction). The length and width of the exposure pattern are both greater than the required length and width of the indium pillars.

[0048] In this step, after the first exposure, a period of time needs to be waited for the first layer of photoresist 202 to fully react before proceeding to step 33. If the reaction is insufficient, a large number of air bubbles may rapidly overflow from the first layer of photoresist during the baking of the second layer, causing the photoresist to deform.

[0049] Step 33: Spin-coat a second, thinner layer of photoresist 203, the thickness of which is less than the thickness of the first layer of photoresist 202.

[0050] Step 34: Perform a second exposure on the second layer of photoresist 203, with the exposure pattern matching the required length and width of the indium. Typically, exposure is performed only on the sample area.

[0051] Step 35: Develop with developer; the result after development is as follows. Figure 2A The deep undercut structure shown.

[0052] The dimensions of the deep undercut structure are larger than the dimensions of the indium to be prepared. In one embodiment, the length, width, and height of the deep undercut structure are all larger than the length, width, and height of the indium to be prepared. Those skilled in the art should understand that steps 31-35 above are merely illustrative, and other steps can also be used to prepare the deep undercut structure, as long as the dimensions of the deep undercut structure are larger than the dimensions of the indium to be prepared, so that the final indium structure does not come into contact with the photoresist.

[0053] In this step, a sufficient amount of developer is used for long-term development, and the sample and developer should be kept in relative displacement during development. For example, the sample can be shaken or the developer can be stirred to ensure that fresh developer is constantly reacting with the photoresist. Insufficient development time or insufficient amount of developer may result in incomplete development, leaving photoresist residue on the bottom.

[0054] Step 36: Evaporate indium film to obtain as shown Figure 2B The indium pillar 204 is shown.

[0055] Step 37: Remove the photoresist to obtain the indium pillar.

[0056] In one embodiment, after the indium film deposition in step 36, the following step is further included: bombarding the surface with a reactive ion etching (RIE) argon-oxygen mixture. This step can significantly reduce the residual photoresist at the edges of the indium pillars after resist removal. Because indium vapor is not perfectly aligned during thermal evaporation plating, a small amount of indium adheres to the undercut edges. Furthermore, the high temperature of the indium vapor causes the photoresist on the surface to denature, making it more difficult to remove with resist remover. Argon-oxygen mixed reactive ion etching can remove this portion of photoresist with adhering small amounts of indium and some denaturation, resulting in cleaner subsequent resist removal.

[0057] In this method for fabricating superconducting quantum bit chips, a deep undercut is achieved using two spin-coating and two exposure processes. This allows the grown indium 204 to grow without contacting the surrounding photoresist, resulting in a better morphology for the indium 204 and facilitating subsequent photoresist stripping. Therefore, this method can more stably fabricate indium pillars with complete structures, good morphology, and clean photoresist removal.

[0058] However, the inventors discovered that during photoresist removal in step 37, the resist remover could not penetrate the indium film to react with the photoresist underneath, resulting in large areas of unpatterned areas outside the sample on the wafer (see [reference]). Figure 1 The photoresist is difficult to remove. (See again...) Figure 1 In the sample area 101 on the wafer, a large number of patterns are exposed. During resist stripping, although the resist stripper cannot penetrate the indium plated on the surface to react with the photoresist, it can start reacting and stripping from the exposed patterns. However, in the large areas outside the sample on the wafer where there are no patterns, the resist stripper can only penetrate from the edge of the area, making resist stripping difficult. Often, even after being soaked in the resist stripper for a long time, the photoresist near the center in these areas cannot be removed.

[0059] In one embodiment, to ensure cleaner resist removal, the portions surrounding the sample area in the outer region of the wiring layer wafer where the wiring layer chip is located and the bit layer wafer where the bit layer chip is located are exposed in the first and second exposure steps to prepare the peripheral indium portion in the outer region of the sample. Figure 4A schematic diagram of exposing an area outside the sample according to an embodiment of the present invention is shown. Wafer 400 includes a sample area 401 and an area outside the sample 402. The area outside the sample 402 includes a peripheral indium portion 404 exposed in the first and second exposure steps. Thus, during photoresist removal, the photoresist within the peripheral indium portion 404 and the photoresist outside this portion are completely separated. The photoresist remover can react from the edges of the peripheral indium portion 404 and the patterns in the sample area 401, making it easier to remove all the underlying photoresist. Finally, after photoresist removal, the remaining indium film on the surface can be easily blown off using a dropper.

[0060] In one embodiment, the peripheral indium portion 404 can surround the sample region 401 and form a closed loop, which can be of any size and shape.

[0061] If there is still some photoresist at the bottom of the indium film in the sample outer area 402, you can use tweezers to peel off the outer indium film, then replace the photoresist remover and soak it for a period of time to remove the photoresist in the sample outer area 402.

[0062] In another embodiment, during the indium film deposition step, a sheet can be used to shield areas on the wafer without indium patterns as much as possible, preventing indium growth on the photoresist surface outside the sample area. This eliminates the obstruction of the indium film during photoresist removal, making it easier to remove the photoresist from the outside area. In one embodiment, the sheet is clean aluminum foil.

[0063] Furthermore, the inventors discovered that the number of indium pillars is not fixed for different bit-layer and wiring-layer chips due to variations in their layouts or patterns. To bond them to the same height, precise control of the bonding force is required. Therefore, test samples must be prepared for each batch of indium pillars with different numbers and arrangements, and a series of measurements must be performed to determine the bonding height before final samples can be prepared, resulting in high costs.

[0064] To facilitate control of the bonding force, the present invention further designs the indium pattern on the bit layer chip or wiring layer chip. Figure 5 A schematic diagram of a large area of ​​indium on a chip according to an embodiment of the present invention is shown, illustrating the bonding area 501 of the chip, which is typically the overlapping area of ​​a bit layer chip and a wiring layer chip. Figure 5As shown, multiple large-area indium 502 are arranged around the bonding area 501. In one embodiment, a ring of large-area indium 502 is arranged around the bonding area 501. The large-area indium 502 is arranged on the bit layer chip or wiring layer chip, while no indium is grown at the corresponding position on another chip. Preferably, the large-area indium 502 is arranged at a position without qubits or wiring patterns. The large-area indium can be prepared using steps 31-37 above, and the indium pillars and the large-area indium are prepared simultaneously, so they have the same height. The cross-sectional size of the large-area indium 502 is much larger than the cross-sectional size of the indium pillars. Preferably, the cross-sectional size of the large-area indium 502 is 5-10 times the cross-sectional size of the indium pillars. In one embodiment, the cross-sectional size of the large-area indium is 170μm*170μm, and the cross-sectional size of the indium pillars is 20μm*20μm.

[0065] During bonding, the indium pillars on the bit layer chip and the wiring layer chip first come into contact with each other and are then pressed together until the spacing between the two chip layers is equal to the height of the large indium area. Due to its larger size, the large indium area provides greater resistance, making it difficult for the two chip layers to approach further. Therefore, by setting the bonding force slightly larger than the estimated value needed to press the two indium pillars down to the height of one pillar, it is possible to ensure that the spacing between the two chip layers equals the height of the large indium area. In this design, the bonding force tolerance depends on the ratio of the total area of ​​the large indium area to the total area of ​​the indium pillars. The higher this ratio, the greater the pressure the chip can withstand with almost no change in the final spacing between the two chip layers after bonding. This makes it easier to find bonding parameters and reduces the impact of instrument errors on the final result.

[0066] Furthermore, large-area indium can be used for convenient destructive testing of the spacing between chips after bonding. The bonded chips can be pushed aside to observe whether there are any pressure marks on the large-area indium. If there are none, it indicates that the bonding force is insufficient. If there are, a step meter can be used to measure the height of the large-area indium, and this height is the spacing between the chips after bonding.

[0067] By fabricating a large area of ​​indium on a single layer of a flip-chip, the bonding parameters are more easily controlled, making it easier to consistently achieve the desired spacing between the two layers after bonding. Furthermore, the spacing between the two layers can be more accurately measured after the bonding is removed. This method allows for bonding two chips to the same height even with a wide range of bonding force fluctuations when the number of indium pillars is the same. This also means that when the number and arrangement of indium pillars vary significantly, the required bonding force is easier to estimate, making the chip less susceptible to instrument errors.

[0068] In one embodiment, to confirm the spacing between chips after bonding without damaging the chip, four bonding observation windows 503 are provided at the four corners of the bonding area 501. Since the area of ​​the bit layer chip is typically smaller than that of the wiring layer chip in bonding design, and the bit layer chip is located above the wiring layer chip, the bonding observation windows 503 are placed on the bit layer chip. In this embodiment, a double-sided polished transparent substrate is used to fabricate the bit layer chip. Before fabricating the indium pillars, i.e., before step 31 above, the film on the surface at the location of the bonding observation window 503 in the bonding area 501 of the bit layer chip is removed to expose the double-sided polished transparent substrate. Then, steps 31-37 are performed to fabricate indium pillars at the bonding observation window 503, and simultaneously, indium pillars and / or additional large-area indium are fabricated at the corresponding locations on the wiring layer chip. Thus, after bonding, it is possible to observe through the bonding observation window 503 of the bit layer chip whether the large-area indium is pressed and the extent of the indium pillar expansion, thereby estimating the spacing between the two chip layers after bonding. In one embodiment, the chip spacing can be obtained by observing the bonding observation windows 503 at the four corners, and the surface parallelism between two chips can be determined. In one embodiment, the number, position, and area of ​​the bonding observation windows 503 can be set as needed.

[0069] In one embodiment, electrodes for detecting the electrical connection of the indium pillar can be fabricated at the four corners of the pressure bonding area. Figure 6 A schematic diagram of an electrode for detecting the electrical connection of indium pillars according to an embodiment of the present invention is shown. Electrode 601 is disposed on a wiring layer chip and fabricated together with the wiring layer pattern. That is, electrode 601 is fabricated before the indium pillars are fabricated, i.e., before step 31 described above. Electrode 601 includes a first end 601a and a second end 601b, wherein the first end 601a is located outside the overlapping area of ​​the wiring layer chip and the bit layer chip (i.e., the area not obscured by the bit layer chip), and the second end 601b is connected to an indium pillar 602 on the wiring layer chip, and an indium pillar on the bit layer chip corresponding to the indium pillar 602 is connected to ground. When the bonding is good, the indium pillars on the bit layer chip are electrically connected to the indium pillars 602 on the wiring layer chip, therefore electrode 601 is connected to ground. After bonding, the resistance between electrode 602 and ground is tested using a probe station; if the resistance is very small, it indicates a good electrical connection between the indium pillars. In one embodiment, the number, location, and area of ​​electrodes 601 can be set as needed, and the size and number of indium pillars fabricated on the electrodes can be set as needed.

[0070] In this embodiment, the test structure (bonding observation window and electrodes) designed on the chip allows for testing of the spacing, parallelism, and electrical connection of the indium pillars between the two layers of the chip without damaging the chip after bonding, which greatly facilitates the testing of the sample.

[0071] In one embodiment, long strips of indium can also be placed between the control lines of different qubits on the wiring layer chip to suppress crosstalk. Figure 7 A schematic diagram of a strip of indium on a wiring layer chip according to an embodiment of the present invention is shown. Figure 7 As shown, a strip of indium 703 is arranged between the control line 701 of the first quantum bit 702 (where 702 is used to indicate the approximate location of the bit SQUID ring) and the control line 704 of the second quantum bit. This strip of indium 703 is fabricated simultaneously with the indium pillars and the large-area indium. The position of this strip of indium 703 on the corresponding location on the bit layer chip does not require any additional structure fabrication to suppress interference. Preferably, the position of the strip of indium 703 corresponds to the ground electrode on the bit layer chip. After bonding, the strip of indium 703 is bonded to the ground electrode on the bit layer chip, forming a long, closed metal barrier between the control line 701 and the control line 704, which serves to shield the signal and thus prevent the signal on the control line 704 from affecting the first quantum bit 702.

[0072] Figure 8 It shows Figure 7 A cross-sectional view of the elongated indium structure shown. (See diagram below.) Figure 8 As shown, the bit layer chip 802 includes a first quantum bit electrode 803 and its bypass capacitor electrode 806 (where the dashed line represents the projection of the bypass capacitor). After bonding, the bypass capacitor electrode will not contact the indium strip, and the indium strip can be disconnected at the location where the bypass electrode is present. The wiring layer chip 801 includes an indium strip 805 and a control line 804 for the second quantum bit.

[0073] exist Figure 7 and Figure 8 In the illustrated qubit structure, due to the introduction of the bypass capacitor electrode 806, the control line does not need to cross across the opposite side of the qubit electrode and maintains a certain distance from the qubit electrode in the horizontal direction. This allows for the placement of a strip of indium between the control line and the qubit electrode to suppress crosstalk from the control line to the qubit. The strip of indium blocking the control line between the control line and the qubit electrode can suppress crosstalk from the control line to the qubit, which is beneficial to the performance of the qubit and makes it easier to measure and control the qubit.

[0074] In one embodiment, the first photoresist layer 202 is AZ6420 with a thickness of approximately 10 μm, and the second photoresist layer 203 is S1813 with a thickness of approximately 2 μm. The exposure size of the first photoresist layer AZ6420 is 7 μm larger on each side than the exposure size of the second photoresist layer S1813. After exposure, each layer is developed with 238 developer for 20 minutes to ensure complete undercut. Finally, indium evaporation is performed using a dedicated thermal evaporation device, using 2 mm diameter indium spheres as the target material. During deposition, large areas without patterns on the wafer are masked with aluminum foil. After deposition, the surface is cleaned by reactive ion etching (RIE) with argon-oxygen mixed bombardment for 3 minutes, followed by immersion in an 80°C NMP solution for 10 hours to remove the photoresist, resulting in a clean indium wafer with excellent morphology.

[0075] In this embodiment, the structural parameters of the wiring layer chip and the bit layer chip are designed as follows. The wiring layer chip size is 15mm*15mm, the bit layer chip size is 11mm*11mm, and the chip spacing after bonding is 7.5μm, meaning the fabrication height of all indium is 7.5μm. The peripheral indium pattern in the sample area, which facilitates resist removal, is located 200μm away from the sample area and has a width of 20μm. Both chip bonding areas contain approximately 5000 20μm*20μm indium pillars, and the edge of the wiring layer bonding area has a ring of 160 large-area indium pillars of 170μm*170μm. Two 200μm*200μm square holes are etched through the four corners of the bit layer chip to serve as bonding observation windows. One observation window has four indium pillars, and the other has a large-area indium pillar. Four electrode structures for electrical connection testing were fabricated at the four corners of the bonding area. These test electrodes were fabricated on the wiring layer, and each electrode had two indium pillars connected to the ground electrode of the bit layer. Testing showed that the parameter design in this embodiment maintained a chip spacing of approximately 7.5 μm under pressures ranging from 5000g to 7000g during flip-chip bonding, ensuring good electrical connection between the indium pillars. The qubits on the bit layer chip were arranged in a 6x6 square lattice array. Long indium strips, 10 μm wide and 500 μm long, were fabricated on three columns to suppress crosstalk. Two indium strips were used to block the control lines between the qubit to be tested and its nearest neighbor. Testing confirmed that this structure effectively suppressed crosstalk.

[0076] The superconducting quantum bit chip fabrication method provided by this invention can more stably produce indium with complete structure, good morphology, and clean resist removal. The superconducting quantum bit chip provided by this invention is easier to control in terms of bonding parameters; even when the bonding force fluctuates within a large range, two chips can be bonded to the same height, and the chip is less susceptible to interference from instrument errors.

[0077] While the present invention has been described through preferred embodiments, it is not limited to the embodiments described herein, and various changes and modifications are made without departing from the scope of the invention.

Claims

1. A method for fabricating a superconducting quantum bit chip, wherein the superconducting quantum bit chip comprises a wiring layer chip and a bit layer chip, and the wiring layer chip and the bit layer chip are coupled to each other via a flip-chip bonding process, the method comprising: Deep undercut structures are fabricated on the substrates of patterned wiring layer chips and bit layer chips. The size of the deep undercut structures is larger than the size of the required bonding superconductor, wherein the bonding superconductor can achieve mechanical and superconducting connections when sufficient pressure is applied at room temperature. In the deep undercut structure, a pressure-welded superconductor pillar for pressure welding is prepared; The fabrication of the deep undercut structure on the substrates of the patterned wiring layer chip and the bit layer chip includes: A first layer of photoresist is spin-coated onto the substrates of the patterned wiring layer chip and bit layer chip, with a thickness greater than the required height of the bonding superconductor. The first exposure is performed on the first layer of photoresist, and the exposed pattern is larger than the length and width of the required bonding superconductor; A second layer of photoresist is spin-coated, the thickness of which is less than the thickness of the first layer of photoresist. A second exposure is performed on the second layer of photoresist, and the exposure pattern is consistent with the length and width of the desired bonding superconductor; The deep undercut structure was obtained by developing with a developing solution; and Fabricating a pressure-welded superconductor pillar for pressure bonding in the deep undercut structure includes depositing a pressure-welded superconductor film, removing the photoresist, and obtaining the pressure-welded superconductor pillar. The method further includes: Multiple large-area bonding superconductors are arranged around the bonding area of ​​one of the bit layer chip and the wiring layer chip, while no bonding superconductor is grown at the corresponding position of the other chip, wherein the cross-section of the large-area bonding superconductor is larger than the cross-section of the bonding superconductor pillar. The method further includes: Before spin-coating the first layer of photoresist, the film on the surface at the observation window position in the bonding area of ​​the bit layer chip is removed, wherein the substrate of the bit layer chip is a double-sided polished transparent substrate; A superconducting pillar is fabricated at the superconducting observation window, and superconducting pillars and / or additional large-area superconductors are also fabricated at the corresponding positions of the wiring layer chip.

2. The method for fabricating a superconducting quantum bit chip according to claim 1, wherein, The pressure-welded superconductor is indium.

3. The method for fabricating a superconducting quantum bit chip according to claim 1 or 2, wherein, The process includes the following steps after the superconducting film is deposited and bonded: using reactive ion etching to bombard the surface with a mixture of argon and oxygen.

4. The method for fabricating a superconducting quantum bit chip according to claim 1 or 2, wherein, In the first and second exposure steps, the portions surrounding the sample region in the outer regions of the wiring layer wafer where the wiring layer chip is located and the bit layer wafer where the bit layer chip is located are exposed to prepare the peripheral bonding superconductor portion in the outer regions of the sample.

5. The method for fabricating a superconducting quantum bit chip according to claim 1 or 2, wherein, In the step of vapor deposition and bonding of superconducting films, a sheet is used to cover areas on the wafer where there is no bonding superconductor pattern.

6. The method for fabricating a superconducting quantum bit chip according to claim 1, wherein, The method further includes: Before spin coating the first layer of photoresist, an electrode for detecting the electrical connection of the bonded superconductor pillars is prepared on the bonding area of ​​the wiring layer chip. The first end of the electrode is located outside the bonding area, and the second end is connected to the bonded superconductor pillar on the wiring layer chip. The corresponding bonded superconductor pillar on the bit layer chip is connected to ground.

7. A superconducting quantum bit chip, manufactured according to the method for fabricating a superconducting quantum bit chip according to any one of claims 1-6, the superconducting quantum bit chip comprising a wiring layer chip and a bit layer chip, wherein the wiring layer chip and the bit layer chip are mutually coupled via a flip-chip bonding process; wherein, Multiple large-area bonding superconductors are arranged around the bonding area of ​​one of the bit layer chip and the wiring layer chip, while no bonding superconductor is arranged at the corresponding position of the other chip, wherein the cross-section of the large-area bonding superconductor is larger than the cross-section of the bonding superconductor pillar.

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