Integrated circuit, display panel and display system
By introducing a frame synchronization mechanism into the OLED display panel and using a timing controller and control circuit to delay the waiting period, the problem of unstable frame rate is solved, and the stability of frame rate and the reduction of tearing effect are achieved.
CN117292646BActive Publication Date: 2026-07-24NOVATEK MICROELECTRONICS CORP
View PDF 2 Cites 0 Cited by
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NOVATEK MICROELECTRONICS CORP
- Filing Date
- 2022-09-13
- Publication Date
- 2026-07-24
AI Technical Summary
Technical Problem
Existing OLED display panels cannot effectively control the reduction in frame rate under conventional image display solutions, resulting in unstable frame rate and tearing effect.
Method used
A frame synchronization mechanism is adopted, which uses a timing controller and control circuit to delay the waiting period and generate a synchronization signal to adjust the transmission timing of image frames, thereby avoiding a sudden drop in frame rate.
Benefits of technology
It effectively mitigates the instantaneous drop in frame rate, reduces tearing, and improves the frame rate stability of the display panel.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN117292646B_ABST
Abstract
The present disclosure relates to a timing controller with a frame synchronization mechanism, a display panel with the timing controller thereof, and a display system with the timing controller thereof. According to an aspect of the present disclosure, the present disclosure provides an integrated circuit, including: a timing controller, transmitting a first tearing signal to an application processor and receiving a first image frame from the application processor after the application processor receives the first tearing signal; and a control circuit, generating a first synchronization signal when the timing controller receives the first image frame, wherein the control circuit delays a first waiting period to generate a second synchronization signal when the application processor receives a second tearing signal and the application processor is not ready to transmit a second image frame to the timing controller.
Need to check novelty before this filing date? Find Prior Art