Memory device

Abstract

A memory device. The memory device (1) of one embodiment includes a first silicon substrate (W1), a second silicon substrate (W2), and a memory cell array (300). A first CMOS circuit (100) is formed on the first silicon substrate (W1). The second silicon substrate (W2) is disposed above the first silicon substrate (W1). A second CMOS circuit (200) is formed on the second silicon substrate (W2). The memory cell array (300) is disposed above the second silicon substrate (W2). The memory cell array (300) is connected to the first CMOS circuit (100) and the second CMOS circuit (100), and has a plurality of memory cells arranged in the stacking direction of the first silicon substrate (W1) and the second silicon substrate (W2).

Description

[0001] Citation of relevant applications

[0002] This application is based on and claims the benefits of priority claims of prior Japanese Patent Application No. 2022-100918, filed on June 23, 2021, and prior Japanese Patent Application No. 2022-198049, filed on December 12, 2022, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The implementation involves a memory device. Background Technology

[0004] NAND flash memory is known to be capable of storing data non-volatilely. Summary of the Invention

[0005] One implementation method reduces the manufacturing cost of memory devices.

[0006] The memory device of this embodiment includes a first silicon substrate, a second silicon substrate, and a memory cell array. A first CMOS circuit is formed on the first silicon substrate. The second silicon substrate is disposed above the first silicon substrate. A second CMOS circuit is formed on the second silicon substrate. The memory cell array is disposed above the second silicon substrate. The memory cell array is connected to the first CMOS circuit and the second CMOS circuit, and has a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate.

[0007] The memory device also includes a through-silicon via (TSV) that connects the first CMOS circuitry to the second CMOS circuitry, or connects the first CMOS circuitry to the first memory cell array.

[0008] The memory device further includes: a first bonding layer between the first silicon substrate and the second silicon substrate; a first bonding metal contained in the first bonding layer; and wiring of the first CMOS circuit disposed between the first bonding layer and the second silicon substrate and connected via the first bonding metal.

[0009] The memory device further includes: a first bonding layer between the first silicon substrate and the second silicon substrate; wiring of the first CMOS circuit disposed between the first bonding layer and the first silicon substrate; and a first bonding metal contained in the first bonding layer, wherein the wiring is connected to the second CMOS circuit or the first memory cell array via the first bonding metal and the silicon via.

[0010] The memory device further includes: a second bonding layer between the second silicon substrate and the first memory cell array; and a second bonding metal contained in the second bonding layer, wherein the first memory cell array is connected to the first CMOS circuit or the second CMOS circuit via the second bonding metal.

[0011] In the memory device, the second bonding metal has a first portion configured as an inverted cone shape and a second portion configured as a cone shape on the first portion.

[0012] The memory device also includes multiple row decoders classified into a first group and a second group. The first memory cell array has multiple data blocks respectively connected to the multiple row decoders. The row decoders of the first group are included in the first CMOS circuit, and the row decoders of the second group are included in the second CMOS circuit.

[0013] The memory device also includes multiple row decoders, and the first memory cell array has multiple data blocks respectively connected to the multiple row decoders. The multiple elements contained in the multiple row decoders are classified into a first element group and a second element group. The first element group is contained in the first CMOS circuit, and the second element group is contained in the second CMOS circuit.

[0014] The memory device also includes a plurality of sense amplifiers classified into a first group and a second group. The first memory cell array has a plurality of bit lines respectively connected to the plurality of sense amplifiers. The sense amplifiers of the first group are included in the first CMOS circuit, and the sense amplifiers of the second group are included in the second CMOS circuit.

[0015] The memory device also includes multiple sense amplifiers, and the first memory cell array has multiple bit lines respectively connected to the multiple sense amplifiers. The multiple elements included in the multiple sense amplifiers are classified into a third element group and a fourth element group. The third element group is included in the first CMOS circuit, and the fourth element group is included in the second CMOS circuit.

[0016] The memory device also includes multiple row decoders and multiple sense amplifiers. The first memory cell array has multiple word lines connected to the multiple row decoders and multiple bit lines connected to the multiple sense amplifiers. The multiple row decoders are included in one of the first CMOS circuit and the second CMOS circuit, and the multiple sense amplifiers are included in the other of the first CMOS circuit and the second CMOS circuit.

[0017] In the memory device, one of the first CMOS circuit and the second CMOS circuit is composed of a low-voltage transistor, and the other of the first CMOS circuit and the second CMOS circuit is composed of a high-voltage transistor with a higher voltage withstand capability than the low-voltage transistor.

[0018] The memory device also includes multiple row decoders and multiple sense amplifiers. The first memory cell array has multiple word lines connected to the multiple row decoders and multiple bit lines connected to the multiple sense amplifiers. The multiple row decoders are included in one of the first CMOS circuit and the second CMOS circuit, and the multiple sense amplifiers are included in the other of the first CMOS circuit and the second CMOS circuit. The first CMOS circuit and the second CMOS circuit include multiple first high-voltage transistors connected between the multiple sense amplifiers and the multiple bit lines.

[0019] In the memory device, the stacked structure of the gate electrode of the low-voltage transistor included in the first CMOS circuit is different from the stacked structure of the gate electrode of the high-voltage transistor included in the second CMOS circuit.

[0020] In the memory device, the gate electrode of the low-voltage transistor comprises nickel-platinum silicide, and the gate electrode of the high-voltage transistor comprises tungsten silicide or tungsten nitride.

[0021] In a memory device, the first silicon substrate includes a first active region formed at a first pitch, the second silicon substrate includes a second active region formed at a second pitch different from the first pitch, and the memory device includes a resistive element having at least one first active region and at least one second active region connected in series.

[0022] In the memory device, the first CMOS circuit includes a plurality of first gate electrodes having a first gate width, the second CMOS circuit includes a plurality of second gate electrodes having a second gate width different from the first gate width, and the memory device includes a resistive element having at least one first gate electrode and at least one second gate electrode connected in series.

[0023] The memory device further comprises: a first conductor and a second conductor disposed in parallel on a layer on which the first CMOS circuit is formed; and a third conductor and a fourth conductor disposed in parallel on a layer on which the second CMOS circuit is formed, wherein the first conductor and the third conductor are connected via a first through-silicon via (TSV), and the second conductor and the fourth conductor are connected via a second TSV, wherein the first conductor and the third conductor function as one electrode of a capacitor element, and the second conductor and the fourth conductor function as the other electrode of the capacitor element.

[0024] The memory device further includes a second memory cell array disposed above the first memory cell array, wherein the second CMOS circuit is used to control the first memory cell array and the first CMOS circuit is used to control the second memory cell array.

[0025] The memory device further includes a second memory cell array disposed above the first memory cell array, wherein the first CMOS circuit is used to control the first memory cell array and the second CMOS circuit is used to control the second memory cell array.

[0026] Based on the above configuration, the manufacturing cost of memory devices can be suppressed. Attached Figure Description

[0027] Figure 1 This is a block diagram illustrating an example of the configuration of a memory system equipped with the memory device of the first embodiment.

[0028] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array provided by the memory device of the first embodiment.

[0029] Figure 3 This is a circuit diagram illustrating an example of the circuit configuration of the line decoder module included in the memory device of the first embodiment.

[0030] Figure 4 This is a circuit diagram illustrating an example of the circuit configuration of the readout amplifier module included in the memory device of the first embodiment.

[0031] Figure 5 This is a perspective view showing an example of the appearance of the memory device according to the first embodiment.

[0032] Figure 6 This is a schematic diagram illustrating an example of the planar layout of the mating surfaces of the memory device according to the first embodiment.

[0033] Figure 7This is a top view showing an example of the planar layout of the storage layer of the memory device according to the first embodiment.

[0034] Figure 8 This is a top view showing an example of the planar layout of the storage area of ​​the storage layer of the memory device of the first embodiment.

[0035] Figure 9 This is an example of a cross-sectional structure in the storage region of the storage layer of the memory device of the first embodiment, and along... Figure 8 A cross-sectional view of the IX-IX line.

[0036] Figure 10 This is an example of a cross-sectional structure of the memory pillars included in the memory layer of the memory device of the first embodiment, and along... Figure 9 A cross-sectional view of the XX line.

[0037] Figure 11 This is a top view showing an example of the planar layout of the lead-out area of ​​the memory layer of the memory device of the first embodiment.

[0038] Figure 12 This is a cross-sectional view showing an example of the cross-sectional structure of the lead-out region of the memory layer of the memory device of the first embodiment.

[0039] Figure 13 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the first embodiment.

[0040] Figure 14 This is a flowchart illustrating an example of a method for manufacturing a memory device according to the first embodiment.

[0041] Figure 15 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing.

[0042] Figure 16 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing.

[0043] Figure 17 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing.

[0044] Figure 18 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing.

[0045] Figure 19 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing.

[0046] Figure 20 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the second embodiment.

[0047] Figure 21 This is a flowchart illustrating an example of a method for manufacturing a memory device according to the second embodiment.

[0048] Figure 22 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing according to the second embodiment.

[0049] Figure 23 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing according to the second embodiment.

[0050] Figure 24 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing according to the second embodiment.

[0051] Figure 25 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing according to the second embodiment.

[0052] Figure 26 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing according to the second embodiment.

[0053] Figure 27 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the third embodiment.

[0054] Figure 28 This is a flowchart illustrating an example of a method for manufacturing a memory device according to a third embodiment.

[0055] Figure 29 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing according to the third embodiment.

[0056] Figure 30 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing according to the third embodiment.

[0057] Figure 31 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing according to the third embodiment.

[0058] Figure 32 This is a schematic diagram illustrating an example of the circuit configuration of a memory device according to the first configuration example of the fourth embodiment.

[0059] Figure 33 This is a schematic diagram illustrating an example of the circuit configuration of a memory device according to the second configuration example of the fourth embodiment.

[0060] Figure 34This is a schematic diagram illustrating an example of the circuit configuration of a memory device according to a third configuration example of the fourth embodiment.

[0061] Figure 35 This is a schematic diagram illustrating an example of the circuit configuration of a memory device according to a fourth configuration example of the fourth embodiment.

[0062] Figure 36 This is a schematic diagram illustrating an example of the circuit configuration of a memory device according to a fifth configuration example of the fourth embodiment.

[0063] Figure 37 This is a schematic diagram illustrating an example of the circuit configuration of a memory device in the sixth configuration example of the fourth embodiment.

[0064] Figure 38 This is a schematic diagram illustrating an example of the circuit configuration of a memory device in the seventh configuration example of the fourth embodiment.

[0065] Figure 39 This is a schematic diagram illustrating an example of the circuit configuration of a memory device in the eighth configuration example of the fourth embodiment.

[0066] Figure 40 This is a schematic diagram illustrating an example of a layout change of a memory device obtained by applying the fourth embodiment.

[0067] Figure 41 This is a schematic diagram illustrating an example of a change in the layout of the readout amplifier module obtained by applying the seventh configuration example of the fourth embodiment.

[0068] Figure 42 This is a schematic diagram illustrating an example of the layout of a memory device when combining the seventh and eighth configuration examples of the fourth embodiment.

[0069] Figure 43 This is a top view showing an example of the planar layout of the first CMOS layer of the memory device according to the fifth embodiment.

[0070] Figure 44 This is a top view showing an example of the planar layout of the second CMOS layer provided in the memory device of the fifth embodiment.

[0071] Figure 45 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the fifth embodiment.

[0072] Figure 46 This is a perspective view showing an example of the appearance of the memory device according to the sixth embodiment.

[0073] Figure 47 This is a schematic diagram illustrating an example of the circuit configuration of a memory device according to the first configuration example of the sixth embodiment.

[0074] Figure 48 This is a schematic diagram illustrating an example of the circuit configuration of a memory device according to the second configuration example of the sixth embodiment.

[0075] Figure 49 This is a schematic diagram illustrating an example of the layout of a memory device obtained by applying the sixth embodiment.

[0076] Figure 50 This is a perspective view showing an example of the appearance of the memory device of the first modified example.

[0077] Figure 51 This is a perspective view showing an example of the appearance of the memory device of the second variation.

[0078] Figure 52 This is a cross-sectional view showing an example of the detailed cross-sectional structure of the joint of the bonding pads.

[0079] Figure 53 This is a top view showing the configuration of the first silicon wafer used in the memory device 1 of the seventh embodiment.

[0080] Figure 54 This is a top view showing the configuration of the second silicon wafer used in the memory device 1 of the seventh embodiment.

[0081] Figure 55 This is a schematic diagram illustrating an example of a method for manufacturing the memory device 1 according to the seventh embodiment. Detailed Implementation

[0082] Hereinafter, various embodiments will be described with reference to the accompanying drawings. Each embodiment illustrates an apparatus and method for embodying the technical concept of this application. The drawings are schematic diagrams or conceptual diagrams. The dimensions, scales, etc., of each drawing are not necessarily the same as reality. Component illustrations are appropriately omitted. The shading added to the top view is not necessarily related to the raw materials or characteristics of the constituent elements. In this specification, constituent elements having substantially the same function and structure are given the same reference numerals. Numbers, characters, etc., added to the reference numerals are referred to by the same reference numerals and are used to distinguish similar elements from each other.

[0083] [1] First implementation method

[0084] The memory device 1 according to the first embodiment includes a memory cell and a CMOS circuit for accessing the memory cell. Furthermore, the memory device 1 has a structure in which CMOS circuits are arranged on multiple stacked substrates. The details of the first embodiment will be described below.

[0085] [1-1] Overall structure of memory device 1

[0086] Figure 1 This is a block diagram illustrating an example of the overall configuration of the memory device 1 according to the first embodiment. For example... Figure 1 As shown, memory device 1 is controlled by an external memory controller 2. Memory device 1 is, for example, a NAND flash memory capable of non-volatile data storage. Memory device 1 includes, for example, a memory cell array 10, input / output circuitry 11, a logic controller 12, register circuitry 13, sequencer 14, driver circuitry 15, a row decoder module 16, and a sense amplifier module 17.

[0087] The memory cell array 10 is a memory circuit containing multiple data blocks BLK0 to BLKn (where "n" is an integer greater than or equal to 1). A data block BLK is a collection of multiple memory cells. A data block BLK corresponds, for example, to a unit of data erasure. A data block BLK contains multiple pages. A page corresponds to a unit for performing data reading and writing. Although not illustrated, the memory cell array 10 includes multiple bit lines BL0 to BLm (where "m" is an integer greater than or equal to 1) and multiple word lines WL. Each memory cell is associated, for example, with one bit line BL and one word line WL. A data block address is assigned to each data block BLK. A column address is assigned to each bit line BL. A page address is assigned to each word line WL.

[0088] Input / output circuit 11 is an interface circuit responsible for transmitting and receiving input / output signals with memory controller 2. Input / output signals include, for example, data (DAT), status information (STS), address information (ADD), and command (CMD). Input / output circuit 11 can input and output data (DAT) with the sense amplifier module 17 and with memory controller 2, respectively. Input / output circuit 11 can output status information (STS) transmitted from register circuit 13 to memory controller 2. Input / output circuit 11 can output address information (ADD) and command (CMD) transmitted from memory controller 2 to register circuit 13, respectively.

[0089] The logic controller 12 controls the input / output circuit 11 and the sequencer 14 based on control signals input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to enable the memory device 1. The logic controller 12 notifies the input / output circuit 11 that the received input / output signals are commands such as CMD and address information such as ADD. The logic controller 12 commands the input / output circuit 11 to input or output the input / output signals.

[0090] Register circuit 13 temporarily stores status information STS, address information ADD, and command CMD. Status information STS is updated based on the control of sequencer 14 and transmitted to input / output circuit 11. Address information ADD includes data block address, page address, column address, etc. Command CMD contains commands related to various operations of memory device 1.

[0091] The sequencer 14 is a controller that controls the overall operation of the memory device 1. Based on the command CMD and address information ADD stored in the register circuit 13, the sequencer 14 performs read operations, write operations, erase operations, etc.

[0092] The driver circuit 15 is a circuit that generates the voltage used in read operations, write operations, erase operations, etc. The driver circuit 15 supplies the generated voltage to the line decoder module 16, the read amplifier module 17, etc.

[0093] The line decoder module 16 is a circuit used for selecting the data block BLK of the action object and transmitting voltage to the word line WL and other wiring. The line decoder module 16 contains multiple line decoders RD0 to RDn. The line decoders RD0 to RDn are associated with data blocks BLK0 to BLKn, respectively.

[0094] The readout amplifier module 17 is a circuit used to transmit voltage to each bit line BL and read out data. The readout amplifier module 17 includes multiple readout amplifier units SAU0 to SAUm. The readout amplifier units SAU0 to SAUm are associated with multiple bit lines BL0 to BLm, respectively.

[0095] Alternatively, the combination of memory device 1 and memory controller 2 can constitute a semiconductor device. Examples of such semiconductor devices include SD cards. TM Memory cards, such as memory cards, and SSDs (solid-state drives), are examples. The group of storage cell array 10, line decoder module 16, and readout amplifier module 17 is, for example, referred to as a "plain PL". The memory device 1 may also have multiple plane PLs.

[0096] [1-2] Circuit configuration of memory device 1

[0097] Next, the circuit configuration of the memory device 1 according to the first embodiment will be described.

[0098] [1-2-1] Circuit configuration of memory cell array 10

[0099] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 10 included in the memory device 1 of the first embodiment. Figure 2 This shows one of the multiple data blocks BLK contained in the storage cell array 10. For example... Figure 2 As shown, a data block BLK may contain, for example, five string cells SU0 to SU4. Gate lines SGD0 to SGD4, as well as SGS and word lines WL0 to WL7, are selected according to the settings for each data block BLK. Bit lines BL0 to BLm and source line SL are shared across multiple data blocks BLK.

[0100] Each string cell SU contains multiple NAND strings NS. These multiple NAND strings NS are associated with bit lines BL0 to BLm, respectively. That is, each bit line BL is shared by NAND strings NS that have been assigned the same column address across multiple data blocks BLK. Each NAND string NS is connected between its associated bit line BL and source line SL. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each memory cell transistor MT is a memory cell with a control gate and a charge storage layer, non-volatilely holding (storing) data. Select transistors ST1 and ST2 are used to select the string cell SU.

[0101] In each NAND string NS, select transistor ST1, memory cell transistors MT7-MT0, and select transistor ST2 are connected in series in this order. Specifically, the drain and source of select transistor ST1 are connected to the associated bit line BL and the drain of memory cell transistor MT7, respectively. The drain and source of select transistor ST2 are connected to the source of memory cell transistor MT0 and the source line SL, respectively. Memory cell transistors MT0-MT7 are connected in series between select transistors ST1 and ST2.

[0102] Select gate lines SGD0 to SGD4 are associated with serial cells SU0 to SU4, respectively. Each select gate line SGD is connected to the gate of the multiple select transistors ST1 contained in the associated serial cell SU. Select gate line SGS is connected to the gate of the multiple select transistors ST2 contained in the associated data block BLK. Word lines WL0 to WL7 are connected to the control gate of the memory cell transistors MT0 to MT7, respectively.

[0103] A collection of multiple memory cell transistors MT connected to a shared word line WL within the same cell SU is called a "cell group CU". For example, the storage capacity of a cell group CU is defined as "1 page of data" when each memory cell transistor MT stores 1 bit of data. A cell group CU can have a storage capacity of more than 2 pages of data depending on the number of bits of data stored by each memory cell transistor MT.

[0104] Furthermore, the circuit configuration of the memory cell array 10 provided in the memory device 1 of the first embodiment can also be other configurations. For example, the number of string cells SU included in each data block BLK, the number of memory cell transistors MT included in each NAND string NS, and the number of selection transistors ST1 and ST2 can each be designed to be arbitrary.

[0105] [1-2-2] Circuit configuration of line decoder module 16

[0106] Figure 3 This is a circuit diagram illustrating an example of the circuit configuration of the line decoder module 16 provided in the memory device 1 of the first embodiment. Figure 3 The diagram illustrates the connection relationships between the line decoder module 16 and the driver circuit 15 and the memory cell array 10, as well as the detailed circuit configuration of the line decoder RD0. Figure 3 As shown, each row decoder RD is connected to the driver circuit 15 via signal lines CG0-CG7, SGDD0-SGDD4, SGSD, USGD, and USGS. Each row decoder RD is connected to the associated data block BLK via word lines WL0-WL7 and select gate lines SGS and SGD0-SGD4.

[0107] The following focuses on the line decoder RD0, explaining the connection relationships between each element of the line decoder RD and the driver circuit 15 and data block BLK0. Furthermore, the configurations of other line decoders RD are the same as those of line decoder RD0, except for the associated data block BLK. Line decoder RD0 includes, for example, transistors TR0 to TR19, transmission gate lines TG and bTG, and a data block decoder BD.

[0108] Transistors TR0 through TR19 are high-voltage N-type MOS transistors (hereinafter also referred to as "HV (High-Voltage) transistors"). The drain and source of transistor TR0 are connected to signal line SGSD and select gate line SGS, respectively. The drains of transistors TR1 through TR8 are connected to signal lines CG0 through CG7, respectively. The sources of transistors TR1 through TR8 are connected to word lines WL0 through WL7, respectively. The drains of transistors TR9 through TR13 are connected to signal lines SGDD0 through SGDD4, respectively. The sources of transistors TR9 through TR13 are connected to select gate lines SGD0 through SGD4, respectively. The drain and source of transistor TR14 are connected to signal line USGS and select gate line SGS, respectively. The drains of transistors TR15 through TR19 are connected to signal line USGD, respectively. The sources of transistors TR15 through TR19 are connected to select gate lines SGD0 through SGD4, respectively. The gates of transistors TR0 through TR13 are connected to the transmission gate line TG. The gates of transistors TR14 to TR19 are connected to the transmission gate line bTG.

[0109] The data block decoder (BD) is a circuit that decodes data block addresses. Based on the decoded data block address, the BD applies specified voltages to the transmission gate lines TG and bTG. Specifically, the BD corresponding to the selected data block BLK applies "H" and "L" level voltages to the transmission gate lines TG and bTG, respectively. The BD corresponding to the non-selected data block BLK applies "L" and "H" level voltages to the transmission gate lines TG and bTG, respectively. Thus, the voltages of signal lines CG0 to CG7 are transmitted to the word lines WL0 to WL7 of the selected data block BLK, the voltages of signal lines SGDD0 to SGDD4 and SGSD are transmitted to the selection gate lines SGD0 to SGD4 and SGS of the selected data block BLK, respectively, and the signal lines USGD and USGS are transmitted to the selection gate lines SGD and SGS of the non-selected data block BLK, respectively.

[0110] Alternatively, the line decoder module 16 can be configured with other circuitry. For example, the number of transistors TR included in the line decoder module 16 can be varied depending on the number of wirings provided in each data block BLK. Since the signal line CG is shared among multiple data blocks BLK, it can also be called a "global word line". Since the word line WL is set for each data block, it can also be called a "local word line". Since the signal lines SGDD and SGSD are shared among multiple data blocks BLK, they can also be called "global transmission gate lines". Since the select gate lines SGD and SGS are set for each data block, they can also be called "local transmission gate lines".

[0111] [1-2-3] Circuit configuration of readout amplifier module 17

[0112] Figure 4 This is a circuit diagram illustrating an example of the circuit configuration of the readout amplifier module 17 included in the memory device 1 of the first embodiment. Figure 4 The circuit configuration of a sense amplifier unit (SAU) is shown below. Figure 4 As shown, the sense amplifier unit SAU includes, for example, a sense amplifier section SA, a bit line connection section BLHU, latch circuits SDL, ADL, BDL, CDL and XDL, and a bus LBUS. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL and XDL are configured to transmit and receive data via the bus LBUS. Hereinafter, the group of the sense amplifier section SA and the multiple latch circuits will also be referred to as the "sense data latch section SADL".

[0113] The readout amplifier SA is a circuit used to determine the data based on the voltage of the bit line BL and to apply the voltage to the bit line BL. If the control signal STB is asserted during readout operation, the readout amplifier SA determines whether the data read from the selected memory cell transistor MT is "0" or "1" based on the associated bit line BL voltage. The latch circuits SDL, ADL, BDL, CDL, and XDL are circuits that can temporarily hold data. The latch circuit XDL is used for the input and output of the data DAT between the readout amplifier unit SAU and the input / output circuit 11. The latch circuit XDL can also be used as a cache memory.

[0114] The readout amplifier section SA includes transistors T0 to T7, capacitor CP, and nodes ND1, ND2, SEN, and SRC. The bit line connection section BLHU is a switching circuit used to prevent the high voltage applied to the channel of the NAND string NS during the erase operation from being applied to the circuitry within the readout amplifier section SA. The bit line connection section BLHU includes transistor T8. The latch circuit SDL includes inverters IV0 and IV1, transistors T10 and T11, and nodes SINV and SLAT. Transistor T0 is a P-type MOS transistor. Transistors T1 to T8, T10, and T11 are N-type MOS transistors. Transistor T8 is an N-type MOS transistor (HV transistor) with a higher voltage rating than the N-type transistors in the readout amplifier section SA. Hereinafter, transistors with a lower voltage rating than HV transistors are also referred to as "LV (Lov-Voltage) transistors." LV transistors operate at higher speeds than HV transistors.

[0115] The gate of transistor T0 is connected to node SINV. The source of transistor T0 is connected to the power supply line. The drain of transistor T0 is connected to node ND1. Node ND1 is connected to the drains of transistors T1 and T2 respectively. The sources of transistors T1 and T2 are connected to nodes ND2 and SEN respectively. Nodes ND2 and SEN are connected to the source and drain of transistor T3 respectively. Node ND2 is connected to the drains of transistors T4 and T5 respectively. The source of transistor T5 is connected to node SRC. The gate of transistor T5 is connected to node SINV. Node SEN is connected to the gate of transistor T6 and one electrode of capacitor CP. The source of transistor T6 is grounded. The drain and source of transistor T7 are connected to the bus LBUS and the drain of transistor T6 respectively. The drain of transistor T8 is connected to the source of transistor T4. The source of transistor T8 is electrically connected to the bit line BL associated with the sense amplifier unit SAU.

[0116] A power supply voltage VDD is applied to the source of transistor T0, for example. A ground voltage VSS is applied to node SRC, for example. Control signals BLX, HLL, XXL, BLC, and STB are input to the gates of transistors T1, T2, T3, T4, and T7, respectively. A control signal BLS is input to the gate of transistor T8. A clock signal CLK is input to the other electrode of capacitor CP.

[0117] Inverter IV0's input and output nodes are connected to nodes SLAT and SINV, respectively. Inverter IV1's input and output nodes are connected to nodes SINV and SLAT, respectively. One end of transistor T10 is connected to node SINV and the bus LBUS, respectively. A control signal STI is input to the gate of transistor T10. One end of transistor T11 is connected to node SLAT and the bus LBUS, respectively. A control signal STL is input to the gate of transistor T11. The latch circuit SDL holds data at node SLAT and holds the inverted data (reverse-phase data) of the data held at node SINV.

[0118] The circuit configurations of latch circuits ADL, BDL, CDL, and XDL are similar to those of latch circuit SDL. For example, latch circuit ADL holds data at node ALAT and its inverted data at node AINV. Furthermore, the gate of transistor T10 in latch circuit ADL is input with control signal ATI, and the gate of transistor T11 in latch circuit ADL is input with control signal ATL. Latch circuit BDL holds data at node BLAT and its inverted data at node BINV. Furthermore, the gate of transistor T10 in latch circuit BDL is input with control signal BTI, and the gate of transistor T11 in latch circuit BDL is input with control signal BTL. The same applies to latch circuits CDL and XDL, therefore, descriptions are omitted.

[0119] Additionally, control signals BLX, HLL, XXL, BLC, STB, BLS, STI, and STL, as well as the clock signal CLK, are generated, for example, by the sequencer 14. The sense amplifier module 17 can also be configured with other circuits. For example, the number of latching circuits in each sense amplifier unit SAU can be varied depending on the number of bits stored in the memory cell transistor MT. The sense amplifier unit SAU can also have arithmetic circuits capable of performing simple logic operations. During the read operation of each page, the sense amplifier module 17 can determine (determine) the data stored in the memory cell transistor MT by appropriately performing arithmetic processing using latching circuits.

[0120] [1-3] Construction of memory device 1

[0121] Next, the construction of the memory device 1 according to the first embodiment will be described. In the following accompanying drawings, a three-dimensional orthogonal coordinate system is used. The X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the vertical direction relative to the surface of the substrate serving as a reference. The term "up and down" in this specification is defined based on the direction along the Z direction, with the direction away from the substrate serving as a reference being designated as the positive direction (above). For example, the substrate positioned at the bottom in the drawings is used as the substrate designated as the reference. The surface of the substrate corresponds to the side on which the transistor (CMOS circuit) is formed. The back surface of the substrate corresponds to the side opposite to the surface.

[0122] [1-3-1] Appearance of memory device 1

[0123] Figure 5 This is a perspective view showing an example of the appearance of the memory device according to the first embodiment. For example... Figure 5 As shown, the memory device 1 has, for example, a structure in which a first substrate W1, a first CMOS layer 100, a second substrate W2, a second CMOS layer 200, a memory layer 300, a third substrate W3, and a wiring layer 400 are stacked sequentially from bottom to top.

[0124] The first CMOS layer 100 includes CMOS circuitry formed using a first substrate W1. The second CMOS layer 200 includes CMOS circuitry formed using a second substrate W2. The first CMOS layer 100 and the second CMOS layer 200 together include, for example, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a line decoder module 16, and a sense amplifier module 17. The memory layer 300 includes a memory cell array 10 formed using a third substrate W3. The wiring layer 400 includes, for example, multiple pads PD used for connecting the memory device 1 and the memory controller 2. The pads PD are connected to the input / output circuitry 11 and exposed on the surface of the memory device 1.

[0125] The first substrate W1, the second substrate W2, and the third substrate W3 are all silicon substrates. The first substrate W1, the second substrate W2, and the third substrate W3 each have an impurity diffusion region corresponding to the circuit design of the memory device 1. The memory device 1 has a bonding surface between adjacent substrates. In the first embodiment, the contact (boundary) portion between the first CMOS layer 100 and the second substrate W2, and the contact (boundary) portion between the second CMOS layer 200 and the memory layer 300, respectively correspond to the bonding surface. The bonding surface is a surface formed by bonding two wafers (substrates), corresponding to the boundary portion of the two bonded substrates. A layer with circuitry such as the first CMOS layer 100 may also be sandwiched between the two bonded substrates. In this specification, the process of bonding two substrates is referred to as "bonding process".

[0126] (Planar layout of the joint surface)

[0127] Figure 6 This is a schematic diagram showing an example of the planar layout of the mating surfaces of the memory device 1 according to the first embodiment. Figure 6 The layout at the interface between the memory layer 300 and the second CMOS layer 200 is shown, with coordinate axes referenced to the second substrate W2 (second CMOS layer 200). For example... Figure 6 As shown, the bonding surface of the memory layer 300 is, for example, divided into a memory region MR, lead-out regions HR1 and HR2, and an input / output region IOR1. The bonding surface of the second CMOS layer 200 is, for example, divided into a sense amplifier region SR, a peripheral circuit region PERI, transmission regions XR1 and XR2, and an input / output region IOR2.

[0128] The storage region MR is used for data storage and contains multiple NAND strings NS. Lead-out regions HR1 and HR2 sandwich the storage region MR in the X direction. The lead-out region HR is the area used for connections between the stacked wiring of the storage region MR and the transistors disposed in the opposite transmission region XR in the Z direction. The input / output region IOR1 is adjacent to the storage region MR and the lead-out regions HR1 and HR2 in the Y direction, respectively. The input / output region IOR1 contains circuitry related to the input / output circuit 11.

[0129] The sense amplifier region SR contains sense amplifier module 17. The peripheral circuit region PERI contains sequencer 14, etc. The sense amplifier region SR and the peripheral circuit region PERI are arranged adjacent to each other in the Y direction and overlap with the storage region MR in the Z direction. The transmission regions XR1 and XR2 contain line decoder module 16. The transmission regions XR1 and XR2 sandwich the sense amplifier region SR and the peripheral circuit region PERI in the X direction and overlap with the lead-out regions HR1 and HR2, respectively, in the Z direction. The input / output region IOR2 contains input / output circuit 11, etc. The input / output region IOR2 overlaps with the input / output region IOR1 in the Z direction.

[0130] Multiple bonding pads BP are provided on the bonding surface of memory layer 300. Memory region MR, lead-out regions HR1 and HR2, and input / output region IOR1 each contain at least one bonding pad BP. The bonding pad BP of memory region MR is connected, for example, to bit line BL. The bonding pad BP of lead-out region HR is connected, for example, to one of the overlay routes (e.g., word line WL) provided in memory region MR. The bonding pad BP of input / output region IOR1 is electrically connected to a pad PD in routing layer 400.

[0131] Similarly, multiple bonding pads BP are provided on the bonding surface of the second CMOS layer 200. The sense amplifier region SR, the peripheral circuit region PERI, the transmission regions XR1 and XR2, and the input / output region IOR2 each contain at least one bonding pad BP. The bonding pads BP of the transmission regions XR1 and XR2 are connected, for example, to transistors of the line decoder RD. The bonding pads BP of the sense amplifier region SR are connected, for example, to transistors of the sense amplifier unit SAU. The bonding pads BP of the input / output region IOR2 are connected to transistors of the input / output circuit 11.

[0132] Multiple bonding pads BP on the bonding surface of the memory layer 300 are respectively arranged opposite to multiple bonding pads BP on the bonding surface of the second CMOS layer 200. The bonding pads BP of the memory region MR are arranged opposite to the bonding pads BP of the sense amplifier region SR. The bonding pads BP of the transmission regions XR1 and XR2 are respectively arranged opposite to the bonding pads BP of the lead-out regions HR1 and HR2. The bonding pads BP of the input / output region IOR1 are arranged opposite to the bonding pads BP of the input / output region IOR2. The group of two bonding pads BP arranged opposite to each other between the memory layer 300 and the second CMOS layer 200 is bonded by a bonding process. Figure 6 (The "bonding"). Thus, the two opposing bonding pads BP are electrically connected. The bonding pads BP can also be referred to as bonding metal.

[0133] Furthermore, the memory device 1 of the first embodiment is not limited to the configuration described above. For example, at least one lead-out region HR is sufficient. The memory device 1 may also have multiple memory regions MR. The configuration of the memory region MR, lead-out region HR, sense amplifier region SR, peripheral circuit region PERI, and transfer region XR can be appropriately changed. Hereinafter, the input / output region IOR will be described as part of the peripheral circuit region PERI.

[0134] [1-3-2] Construction of storage layer 300

[0135] Next, the detailed structure of storage layer 300 will be explained.

[0136] (1: Planar layout of storage layer 300)

[0137] Figure 7 This is a top view showing an example of the planar layout of the storage layer 300 provided in the memory device 1 of the first embodiment. Figure 7 The regions corresponding to the four data blocks BLK0 to BLK3 contained in the storage cell array 10 are shown. For example... Figure 7 As shown, the storage cell array 10 includes, for example, multiple slits SLT and multiple slits SHE.

[0138] Each slot SLT has a portion extending along the X direction and transversely cutting through the lead-out region HR1, the memory region MR, and the lead-out region HR2 along the X direction. Multiple slot SLTs are arranged in the Y direction. Each slot SLT, for example, has a structure with embedded insulator. Each slot SLT disconnects adjacent wirings (e.g., word lines WL0-WL7, and select gate lines SGD, SGS) via that slot SLT. In the memory cell array 10, the regions divided by the slot SLTs each correspond to a data block BLK.

[0139] Each slot SHE has a portion extending along the X direction and transversely cutting through the memory region MR along the X direction. Multiple slot SHEs are arranged in the Y direction. In this example, four slot SHEs are respectively arranged between two adjacent slots SLT in the Y direction. Each slot SHE has, for example, a structure with embedded insulator. Each slot SHE disconnects adjacent wiring (at least, the selected gate line SGD) via that slot SHE. In the memory cell array 10, the area divided by the slots SLT and SHE corresponds to a string cell SU.

[0140] Furthermore, the planar layout of the memory cell array 10 provided in the memory device 1 of the first embodiment can also be other layouts. For example, the number of slits SHE disposed between two adjacent slits SLT can be designed to be any number. The number of string cells SU provided in each data block BLK can be changed based on the number of slits SHE disposed between two adjacent slits SLT.

[0141] (2: Planar layout of the MR storage area)

[0142] Figure 8 This is a top view showing an example of the planar layout of the storage region MR of the storage layer 300 provided in the memory device 1 of the first embodiment. Figure 8 The diagram shows a region containing a data block BLK (string units SU0 to SU4). For example... Figure 8 As shown, memory device 1 includes, for example, multiple memory pillars MP, multiple contacts CV, and multiple bit lines BL in the memory region MR.

[0143] Each memory column (MP) functions as a NAND string (NS). Multiple memory columns (MP) are arranged in an alternating pattern of 24 columns in the region between two adjacent slots (SLT). For example, counting from the top of the paper, memory columns (MP) in the 5th, 10th, 15th, and 20th columns are arranged in an overlapping configuration of a slot (SHE).

[0144] Each bit line BL has a portion extending along the Y direction. Multiple bit lines are arranged in the X direction. Each bit line BL is configured to overlap with at least one memory post MP for each string cell SU. In this example, two bit lines BL are configured to overlap within one memory post MP. The memory post MP is electrically connected to one of the multiple overlapping bit lines BL via a contact CV. Furthermore, the contact CV between the memory post MP and the bit line BL connected to two different select gate lines SGD can be omitted.

[0145] Furthermore, the planar layout in the storage region MR of the memory device 1 in the first embodiment can also be other layouts. For example, the number and arrangement of storage pillars MP and slits SHE disposed between two adjacent slits SLT can be appropriately changed. The number of bit lines BL overlapping each storage pillar MP can be designed to be arbitrary.

[0146] (3: Cross-sectional structure of the storage region MR)

[0147] Figure 9 This is an example of a cross-sectional structure in the storage region MR of the storage layer 300 provided in the memory device 1 of the first embodiment, and along... Figure 8A cross-sectional view of the IX-IX line. Figure 9 An example of the structure of the memory cell array 10 formed on the third substrate W3 before the bonding process is shown, with coordinate axes based on the third substrate W3. For example... Figure 9 As shown, the memory device 1 includes, for example, conductive layers 20-26, insulating layers 30-35, and contacts V0 and V1 in the storage region MR.

[0148] A conductive layer 20 is disposed on a third substrate W3. An insulating layer 30 is disposed on the conductive layer 20. A conductive layer 21 and an insulating layer 31 are alternately disposed on the insulating layer 30. An insulating layer 32 is disposed on the uppermost conductive layer 22. A conductive layer 23 is disposed on the insulating layer 32. An insulating layer 33 is disposed on the conductive layer 23. A conductive layer 24 is disposed on the insulating layer 33. A contact V0 is disposed on the conductive layer 24. A conductive layer 25 is disposed on the contact V0. A contact V1 is disposed on the conductive layer 25. A conductive layer 26 is disposed on the contact V1. Hereinafter, the wiring layers with conductive layers 24 and 25 will be referred to as "M0" and "M1", respectively. The layer with conductive layer 26 will be referred to as "bonding layer B1".

[0149] Conductor layers 21, 22, and 23 are formed, for example, as plates extending along the XY plane. Conductor layer 24 is formed, for example, as a line extending along the Y direction. Conductor layers 20, 21, and 23 serve as source line SL, select gate line SGS, and select gate line SGD, respectively. Multiple conductor layers 22 are sequentially used as word lines WL0 to WL7 from the third substrate W3 side. Conductor layer 24 serves as bit line BL. Contacts V0 and V1 are pillar-shaped. Conductor layers 24 and 25 are connected via contact V0. Conductor layer 25 and conductor layer 26 are connected via contact V1. Conductor layer 26 corresponds to the bonding pad BP used for bonding the second substrate W2 and the third substrate W3. Conductor layer 26 contains, for example, copper.

[0150] The slit SLT has a plate-like portion formed along the XZ plane, separating the insulating layers 30-32 and the conductive layers 21-23. Each memory pillar MP extends along the Z direction and penetrates the insulating layers 30-32 and the conductive layers 21-23. Each memory pillar MP includes, for example, a core component 40, a semiconductor layer 41, and a laminated film 42. The core component 40 is an insulator that extends along the Z direction. The semiconductor layer 41 covers the core component 40. The lower part of the semiconductor layer 41 is in contact with the conductive layer 20. The laminated film 42 covers the side surface of the semiconductor layer 41. A contact CV is provided on the semiconductor layer 41. The conductive layer 24 is in contact with the contact CV.

[0151] Additionally, the area shown depicts a contact CV corresponding to one of the two memory pillars MP. Memory pillars MP not connected to the contact CV in this area are connected to the contact CV in an area not shown. The portion of the memory pillar MP intersecting with conductor layer 21 functions as selection transistor ST2. The portion of the memory pillar MP intersecting with conductor layer 22 functions as memory cell transistor MT. The portion of the memory pillar MP intersecting with conductor layer 23 functions as selection transistor ST1.

[0152] (4: Cross-sectional structure of storage column MP)

[0153] Figure 10 This is an example of the cross-sectional structure of the memory pillar MP included in the memory layer 300 of the memory device 1 of the first embodiment, and along... Figure 9 A cross-sectional view of the XX line. Figure 10 A cross-section containing the storage pillar MP and the conductive layer 22, and parallel to the surface of the third substrate W3, is shown. (See image.) Figure 10 As shown, the laminated film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a block insulating film 45.

[0154] The core component 40 is disposed, for example, at the center of the memory column MP. A semiconductor layer 41 surrounds the sides of the core component 40. A tunnel insulating film 43 surrounds the sides of the semiconductor layer 41. An insulating film 44 surrounds the sides of the tunnel insulating film 43. A barrier insulating film 45 surrounds the sides of the insulating film 44. A conductive layer 22 surrounds the sides of the barrier insulating film 45. The semiconductor layer 41 serves as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The tunnel insulating film 43 and the barrier insulating film 45 are, for example, composed of silicon oxide. The insulating film 44 serves as the charge storage layer for the memory cell transistor MT and is, for example, composed of silicon nitride. Thus, each of the memory columns MP functions as a NAND string NS.

[0155] (5: Introducing the floor plan layout of the regional HR department)

[0156] In the memory device 1 of the first embodiment, the structure of the lead-out region HR1 of even-numbered data blocks BLK is similar to the structure of the lead-out region HR2 of odd-numbered data blocks BLK, and the structure of the lead-out region HR2 of even-numbered data blocks BLK is similar to the structure of the lead-out region HR1 of odd-numbered data blocks BLK. For example, the planar layout of data block BLK0 in lead-out region HR2 is the same as the planar layout obtained by reversing the structure of data block BLK1 in lead-out region HR1 in the X and Y directions, respectively. The planar layout of data block BLK1 in lead-out region HR2 is the same as the planar layout obtained by reversing the structure of data block BLK0 in lead-out region HR1 in the X and Y directions, respectively. Hereinafter, the planar layout of data block BLK in lead-out regions HR1 and HR2 will be described with focus on the planar layout of even-numbered data blocks BLK in lead-out region HR1.

[0157] Figure 11 This is a top view showing an example of the planar layout of the lead-out area HR of the memory layer 300 provided in the memory device 1 of the first embodiment. Figure 11 The storage region MR near the outgoing region HR1 is also shown. For example... Figure 11 As shown, in the lead-out region HR1, for example, the ends of the select gate line SGS, word lines WL0 to WL7, and select gate line SGD each have a platform portion.

[0158] The platform portion corresponds to the part of the stacked wiring that does not overlap with the upper wiring layer (conductor layer). The structure formed by multiple platform portions is similar to steps, terraces, and rimstones. In this example, the step structure with a step difference in the X direction is formed by the end of the select gate line SGS, the ends of word lines WL0 to WL7 respectively, and the end of the select gate line SGD. In other words, the step difference is formed between the select gate line SGS and word line WL0, between word line WL0 and word line WL1, ..., between word line WL6 and word line WL7, and between word line WL7 and select gate line SGD.

[0159] Furthermore, memory device 1 includes multiple contacts CC in even-numbered data blocks BLK within the lead-out area HR1. The contacts CC are components used for the connection between the line decoder module 16 and the overlay wiring. Each contact CC is connected to one of the platform portions of the overlay wiring, i.e., conductor layers 21-23, located in the memory cell array 10 within the even-numbered data blocks BLK. Additionally, although not shown in the figure, memory device 1 includes multiple contacts CC in odd-numbered data blocks BLK within the lead-out area HR2. Moreover, the multiple contacts CC in the odd-numbered data blocks BLK are connected to one of the platform portions of the overlay wiring, i.e., conductor layers 21-23, located in the memory cell array 10 within the odd-numbered data blocks BLK.

[0160] Furthermore, although the example illustrates a case where a contact CC is connected to a platform portion formed in the lead-out region HR, it is not limited to this. Even if a platform portion is not provided in the lead-out region HR, the memory device 1 can be constructed as long as it has a group of wirings associated with a certain contact CC that is electrically connected to other wirings without short-circuiting.

[0161] (6: Introducing the cross-sectional structure of the regional HR)

[0162] Figure 12 This is a cross-sectional view showing an example of the cross-sectional structure of the lead-out region HR of the memory layer 300 provided in the memory device 1 of the first embodiment. Figure 12 The structure of the lead-out region HR1 of the memory cell array 10 formed on the third substrate W3 before the bonding process is shown, as well as the memory region MR near the lead-out region HR1. Figure 12 As shown, the ends of each of the conductive layers 21 to 23 are stepped and covered by the insulating layer 33. In the lead-out region HR1, insulating layers 34 and 35 are stacked on the insulating layer 33. Furthermore, the memory device 1 includes, for example, a plurality of contacts CC, a plurality of contacts V0 and V1, and a plurality of conductive layers 27, 28 and 29 in the lead-out region HR1.

[0163] Multiple contacts CC are respectively disposed on the platform portions of the select gate line SGS, word lines WL0 to WL7, and select gate line SGD. Each contact CC penetrates the insulating layer 33. A conductive layer 27 is disposed on each of the multiple contacts CC. A contact V0 is disposed on each conductive layer 27. Figure 12Only the contact V0 corresponding to the selected gate line SGS among multiple contacts V0 is shown. A conductive layer 28 is provided on the contact V0. A contact V1 is provided on the conductive layer 28. Conductive layers 27 and 28 and multiple contacts V0 and V1 are covered by an insulating layer 34. On contact V1, a conductive layer 29 is provided through the insulating layer 35. Conductive layer 29 corresponds to the bonding pad BP used for bonding the second substrate W2 and the third substrate W3. Conductive layer 29 contains, for example, copper. Conductive layers 27, 28, and 29 are respectively included in wiring layers M0 and M1 and bonding layer B1.

[0164] The groups of conductive layers 27, 28, and 29 and contacts CC, V0, and V1 described above correspond to the wiring and contacts used to connect one of the conductive layers 21-23 to the line decoder module 16. Although not shown in the figures, conductive layers 22 and 23 are also connected to the line decoder module 16 via the groups of conductive layers 27, 28, and 29 and contacts CC, V0, and V1, respectively.

[0165] [1-3-3] Cross-sectional structure of memory device 1

[0166] Figure 13 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1 according to the first embodiment. Figure 13 This represents a cross-section containing the storage region MR and the lead-out region HR1 in memory device 1, showing a coordinate axis with the first substrate W1 as a reference. For example... Figure 13 As shown, memory device 1 and memory layer 300 correspondingly have the ability to store... Figure 9 The structure of the storage layer 300 shown is obtained by reversing the top and bottom, and the ... Figure 12 The structure of the lead-out region HR1 shown is obtained by reversing the top and bottom. The memory device 1, corresponding to the first CMOS layer 100, includes insulating layers 50 and 51, conductive layers GC1 and 52-54, and contacts CS1 and C0-C3. The memory device 1, corresponding to the second CMOS layer 200, includes insulating layers 60 and 61, conductive layers GC2 and 62-65, and contacts CS2 and C5-C8.

[0167] An insulating layer 50 is disposed on a first substrate W1. The insulating layer 50 covers the circuitry (e.g., conductive layers 52-54, and contacts CS1 and C0-C2) disposed on the first substrate W1. The insulating layer 50 can be composed of multiple insulating layers. Furthermore, the insulating layer 50 sequentially includes wiring layers D0, D1, and D2 from the first substrate W1 side. Wiring for the first CMOS layer 100 is provided in wiring layers D0, D1, and D2. An insulating layer 51 is disposed on the insulating layer 50. The insulating layer 51 is in contact with the back side of the second substrate W2. The boundary between the insulating layer 51 and the second substrate W2 corresponds to the bonding surface between the first substrate W1 and the second substrate W2. The insulating layer 51 is, for example, a silicon oxide film. Hereinafter, the layer containing the insulating layer 51 will be referred to as "bonding layer B2".

[0168] An insulating layer 60 is disposed on the second substrate W2. The insulating layer 60 covers the circuitry (e.g., conductive layers 62-64, and contacts CS2 and C5-C8) disposed on the second substrate W2. The insulating layer 60 can be composed of multiple insulating layers. Furthermore, the insulating layer 60 sequentially includes wiring layers D3, D4, and D5 from the first substrate W1 side. Wiring for the second CMOS layer 200 is disposed on wiring layers D3, D4, and D5. An insulating layer 61 is disposed on the insulating layer 60. The insulating layer 61 is in contact with the insulating layer 35 included in the memory layer 300. The boundary between the insulating layer 61 and the insulating layer 35 corresponds to the bonding surface between the second substrate W2 and the third substrate W3. The insulating layer 61 is, for example, a silicon oxide film. Hereinafter, the layer containing the insulating layer 61 at the bonding surface will be referred to as "bonding layer B3".

[0169] A conductive layer GC1 is disposed on a gate insulating film disposed on a first substrate W1. The conductive layer GC1 in the sense amplifier region SR serves, for example, as the gate electrode of transistor T8. The conductive layer GC1 in the transmission region XR1 serves, for example, as the gate electrode of transistor TR0. Contacts C0 are disposed on each conductive layer GC1. Two contacts CS1 contained in the sense amplifier region SR are connected to two impurity diffusion regions (not shown) disposed on the first substrate W1. For example, these two impurity diffusion regions correspond to the source and drain of transistor T8, respectively. Similarly, two contacts CS1 contained in the transmission region XR1 are connected to two impurity diffusion regions (not shown) disposed on the first substrate W1. For example, these two impurity diffusion regions correspond to the source and drain of transistor TR0, respectively. Shallow trench isolation (STI) is appropriately provided in the first substrate W1 according to the transistor layout.

[0170] Conductive layers 52 are respectively disposed on contacts CS1 and C0 within the sense amplifier region SR. Conductive layer 52 is included in wiring layer D0. Conductive layer 53 is disposed on conductive layer 52 via contact C1. Conductive layer 53 is included in wiring layer D1. Conductive layer 54 is disposed on conductive layer 53 via contact C2. Conductive layer 54 is included in wiring layer D2. Contact C3 is disposed on conductive layer 54. In the first embodiment, contact C3 is disposed through the second substrate W2 and insulating layer 51. Contact C3 is insulated from the second substrate W2 by an insulating film INS. Contact C3 corresponds to a through-silicon via (TSV).

[0171] A conductive layer GC2 is disposed on a gate insulating film disposed on a second substrate W2. The conductive layer GC2 within the sense amplifier region SR serves, for example, as the gate electrode of transistor T4. Contacts C5 are disposed on each conductive layer GC2. Two contacts CS2 contained in the sense amplifier region SR are connected to two impurity diffusion regions (not shown) disposed on the second substrate W2. For example, these two impurity diffusion regions correspond to the source and drain of transistor T4, respectively. STIs are appropriately disposed on the second substrate W2 according to the transistor layout.

[0172] Conductive layers 62 are respectively disposed on contacts CS2, C3, and C5 within the sense amplifier region SR. Conductive layer 62 is included in wiring layer D3. Conductive layer 63 is disposed on conductive layer 62 via contact C6. Conductive layer 63 is included in wiring layer D4. Conductive layer 63 can be disposed in the current path between contact CS2 and C3, or in the current path between contact C3 and bonding pad BP. Conductive layer 64 is disposed on conductive layer 63 via contact C7. Conductive layer 64 is included in wiring layer D4. Conductive layer 65 is disposed on conductive layer 64 via contact C8. Conductive layer 65 is included in bonding layer B3. Conductive layer 65 corresponds to bonding pad BP used for bonding the second substrate W2 and the third substrate W3. Conductive layer 65 contains, for example, copper.

[0173] A conductor layer 26 is disposed opposite to the conductor layer 65. The conductor layer 26 is connected to the associated conductor layer 24 (bit line BL) via contacts V0 and V1 and the conductor layer 25. Thus, the conductor layer 24 (bit line BL) is electrically connected to the transistor T8 disposed on the first substrate W1. Similarly, other conductor layers 24 are connected to the transistor disposed on the first substrate W1 via contacts V0 and conductor layers 25 connected from below the memory pillar MP.

[0174] Similarly, the bonding pad BP of the lead-out region HR1 is connected to the bonding pad BP of the transmission region XR1. Moreover, the stacked wiring (e.g., the select gate line SGS) is electrically connected to the transistor TR0 provided on the first substrate W1 via the conductor layers 52-54 and 62-65, and the contacts CS1, C1-C3 and C6-C8.

[0175] An insulating layer 70 is disposed on a third substrate W3. The insulating layer 70 is included in a wiring layer 400. The wiring layer 400 includes a conductive layer that is connected to circuits contained in one of the first CMOS layer 100, the second CMOS layer 200, and the memory layer 300. This conductive layer is connected, for example, to a pad PD disposed above the insulating layer 70.

[0176] In the above description, the case where the bonding pad BP formed on the memory layer 300 is connected to the transistor on the first substrate W1 is illustrated, but it is not limited to this. The bonding pad BP formed on the memory layer 300 can also be connected to the transistor on the second substrate W2. Transistors T8 and TR0 can also be disposed on the second substrate W2. Transistor T4 can also be disposed on the first substrate W1. For example, an HV transistor is disposed on the first substrate W1. On the other hand, for example, an LV transistor is disposed on the second substrate W2. Thus, the arrangement of transistors in the first CMOS layer 100 and the second CMOS layer 200 can be appropriately changed according to the design of the memory device 1. Specific examples of the circuit arrangement of the memory device 1 will be described in the fourth embodiment.

[0177] [1-4] Method for manufacturing memory device 1

[0178] Figure 14 This is a flowchart illustrating an example of a method for manufacturing the memory device 1 according to the first embodiment. Figures 15-19 These are cross-sectional views showing an example of the cross-sectional structure of the memory device 1 during manufacturing according to the first embodiment. Hereinafter, reference will be made as appropriate. Figure 14 The manufacturing method of the memory device 1 according to the first embodiment will be described.

[0179] First, a third substrate W3 having a memory layer 300 and a first substrate W1 having a first CMOS layer 100 are fabricated (S11). In the memory layer 300 on the fabricated third substrate W3, as shown... Figure 15 As shown, the insulating layer 35 and the bonding pad BP (conductive layer 25) on the bonding layer B1 are exposed. In the first CMOS layer 100 on the fabricated first substrate W1, as... Figure 16 As shown, the insulating layer 51 provided in the bonding layer B2 is exposed. Furthermore, in S11, no structure corresponding to the contact CC is formed in the first substrate W1 and the first CMOS layer 100.

[0180] Next, the first substrate W1 and the second substrate W2 are joined together, as follows: Figure 17 As shown, a first bonding substrate BW1 is formed (S12). Specifically, prior to the process in S12, a silicon oxide film is formed on the bonding surface of the second substrate W2. Then, through the bonding process of the first substrate W1 and the second substrate W2, the insulating layer 51 (silicon oxide film) of the first CMOS layer 100 comes into contact with and is bonded to the silicon oxide film of the second substrate W2. Thus, a first bonding substrate BW1 having a structure in which the second substrate W2 is disposed on the insulating layer 51 is formed.

[0181] Next, a CMP (Chemical Mechanical Polishing) process (S13) is performed on the second substrate W2 contained in the first bonding substrate BW1. Through the process of S13, the second substrate W2 of the first bonding substrate BW1 is polished (thinned). The thickness of the second substrate W2, which is thinned by polishing, corresponds to... Figure 13 The thickness of the second substrate W2 shown.

[0182] Next, as Figure 18 As shown, a second CMOS layer 200 is formed on the first bonding substrate BW1 (S14). The formation process of the second CMOS layer 200 includes an etching process for forming the contact C3. Specifically, firstly, a first hole penetrating the second substrate W2 is formed, overlapping with the conductive layer 54. An insulator is then embedded in the first hole. Next, in the etching process for forming the contact C3, a second hole penetrating the insulator embedded in the second substrate W2 is simultaneously formed. Then, by embedding a conductor in the second hole, the contact C3 connecting the circuitry in the first CMOS layer 100 and the circuitry in the second CMOS layer 200 is formed. After forming the contact C3, wiring layers D3 to D5 and the bonding layer B3 are formed, and the process S14 is completed.

[0183] Next, the first bonding substrate BW1 and the third substrate W3 are joined together, as follows: Figure 19 As shown, a second bonding substrate BW2 is formed (S15). Specifically, through the bonding process of the first bonding substrate BW1 and the third substrate W3, the bonding layer B3 of the insulating layer 61 of the second CMOS layer 200 contacts and is bonded to the insulating layer 35 of the memory layer 300. Furthermore, the bonding pads BP facing each other between the second CMOS layer 200 and the memory layer 300 contact and are bonded. Thus, the second bonding substrate BW2 is formed.

[0184] Next, a CMP process (S16) is performed on the third substrate W3 contained in the second bonding substrate BW2. Through the S16 process, the thickness of the third substrate W3, which is thinned by grinding, corresponds to... Figure 13 The thickness of the third substrate W3 shown.

[0185] Next, a wiring layer 400 is formed on the second bonding substrate BW2 (S17). The process of S17 includes etching the third substrate W3, forming wiring and an insulating film, and forming pads PD. If the process of S17 is completed, the memory device 1 is completed.

[0186] [1-5] Effects of the first embodiment

[0187] The memory device 1 according to the first embodiment can suppress the manufacturing cost of the memory device. The effects of the first embodiment will be described in detail below.

[0188] A memory cell array formed by stacking three-dimensional memory cells can increase its storage capacity by increasing the number of word lines (WL). Furthermore, as a memory device, a structure is known in which a substrate on which the memory cell array is formed is bonded to a substrate on which CMOS circuitry controlling the memory cell array is formed. This structure can hide the area where the CMOS circuitry is formed in the area where the memory cell array is formed, thereby reducing chip area.

[0189] However, as the number of word lines WL increases, the area of ​​the CMOS circuitry controlling the memory cell array 10 also increases. For example, as the number of word lines WL increases, the number of HV transistors (transistors TR within the line decoder module 16) connected to the word lines WL increases. Since these transistors are disposed on the substrate forming the CMOS circuitry, the area of ​​the CMOS circuitry increases.

[0190] The memory device 1 of the first embodiment has a structure in which CMOS circuitry for controlling the memory cell array 10 is disposed on two substrates (a first substrate W and a second substrate W2). In other words, the memory device 1 has multiple silicon substrates on which CMOS circuitry is formed respectively. Further, the memory device 1 includes a first CMOS layer 100 formed on the first substrate W1 and a second CMOS layer 200 formed on the second substrate W2. Moreover, the first CMOS layer 100 and the second CMOS layer 200 are connected by through-silicon vias (TSVs).

[0191] Therefore, the memory device 1 of the first embodiment can ensure the area for configuring CMOS circuitry in the large-capacity memory cell array 10. Specifically, space for configuring the row decoder module 16, whose circuit area increases with the increase in the number of word lines WL, can be ensured by using multiple CMOS layers. As a result, the memory device 1 of the first embodiment can suppress the impact of the increase in the number of word lines WL on the chip area. Therefore, the memory device 1 of the first embodiment can suppress the increase in chip area and suppress the manufacturing cost of the memory device.

[0192] Furthermore, in the memory device 1 of the first embodiment, the thickness of the interlayer insulating film can be varied between the first substrate W1 and the second substrate W2. For example, an HV transistor is disposed on the first substrate W1, and an LV transistor is disposed on the second substrate W2. The interlayer insulating film (insulator layer 60) of the second substrate W2 is designed based on the height of the conductor layer GC2 and the height of the bonding pad BP of the bonding layer B3, and is, for example, less than 1 μm. The interlayer insulating film (insulator layer 50) of the first substrate W1 is designed based on the height of the conductor layer GC1 and the height of the wiring layers D0 to D2, and is, for example, 2 μm or more. Preferably, the interlayer insulating film of the first substrate W1 has a sufficient thickness. As a result, the influence of the electric field generated from the first substrate W1 where the HV transistor is formed on the second substrate W2 where the LV transistor is formed can be suppressed.

[0193] [2] Second implementation method

[0194] The second embodiment employs a manufacturing method different from the first embodiment to form a structure in which a first substrate W1 (first CMOS layer 100) and a second substrate W2 (second CMOS layer 200) are bonded together. The details of the second embodiment will be described below.

[0195] [2-1] Cross-sectional structure of memory device 1a

[0196] Figure 20 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1a according to the second embodiment. For example... Figure 20 As shown, the memory device 1a differs from the memory device 1 described in the first embodiment in the construction of its first CMOS layer 100a. The first CMOS layer 100a of the memory device 1a has a first portion 110 and a second portion 120. Corresponding to the first portion 110 of the first CMOS layer 100, the memory device 1a includes insulating layers 50a and 55, a conductive layer GC1, multiple bonding pads BP, and contacts COa and CS1a. Corresponding to the second portion 120 of the first CMOS layer 100, the memory device 1a includes conductive layers 52-54, insulating layers 56 and 50b, multiple bonding pads BP, and contacts COb, CS1b, C1-C3.

[0197] An insulating layer 50a is disposed on a first substrate W1. The insulating layer 50a covers components (e.g., transistor T8, contact C0a, and CS1a) disposed on the first substrate W1. An insulating layer 55 is disposed on the insulating layer 50a. The insulating layer 55 is, for example, a silicon oxide film. Hereinafter, the layer containing the insulating layer 55 will be referred to as "bonding layer B4". The bonding layer B4 includes a plurality of bonding pads BP. The bonding pads BP contained in the bonding layer B4 are connected to contacts CS1a, C0a, etc.

[0198] An insulating layer 56 is disposed on an insulating layer 55. The insulating layer 56 is, for example, a silicon oxide film. The boundary between the insulating layer 55 and the insulating layer 56 corresponds to the bonding surface of the first portion 110 and the second portion 120 of the first CMOS layer 100. Hereinafter, the layer containing the insulating layer 56 will be referred to as "bonding layer B5". An insulating layer 50b is disposed on the insulating layer 56. The insulating layer 50b can be composed of multiple insulating layers. The insulating layer 50b includes wiring layers D0, D1, and D2. The insulating layer 50b is bonded to the back side of the second substrate W2. The bonding layer B5 includes multiple bonding pads BP. Contacts CS1b, C0b, etc., are disposed on the bonding pads BP included in the bonding layer B5. The contacts CS1b and C0b are respectively bonded to the conductive layer 52 included in the wiring layer D0. The insulating layer 50b covers the circuitry contained in the first CMOS layer 100a (e.g., conductor layers 52-54, and contacts CS1b, C0b, C1, and C2).

[0199] The bonding pads BP contained in bonding layer B4 are respectively connected to the plurality of bonding pads BP contained in bonding layer B5 and arranged opposite each other. Thus, in the second embodiment, the first substrate W1 is electrically connected to the conductive layer 52 of wiring layer D0 through a group of contact CS1a, two oppositely arranged bonding pads BP and contact CS1b, or a group of contact CS0a, two oppositely arranged bonding pads BP and contact CS0b.

[0200] Furthermore, in the second embodiment, the first portion 110 of the first CMOS layer 100a is formed using the first substrate W1. On the other hand, the second portion 120 of the first CMOS layer 100a is formed using the back side of the second substrate W2. The other configurations of the memory device 1a in the second embodiment are the same as those in the memory device 1 of the first embodiment.

[0201] [2-2] Method for manufacturing memory device 1a

[0202] Figure 21 This is a flowchart illustrating an example of a method for manufacturing the memory device 1a according to the second embodiment. Figures 22-26These are cross-sectional views showing an example of the cross-sectional structure of the memory device 1a during manufacturing according to the second embodiment. Hereinafter, reference will be made as appropriate. Figure 21 The manufacturing method of the memory device 1a according to the second embodiment will be described.

[0203] First, a third substrate W3 with a memory layer 300, a first substrate W1 with a first portion 110 of a first CMOS layer 100a, and a second substrate W2 with a second CMOS layer 200 are fabricated (S21). The structure of the memory layer 300 on the fabricated third substrate W3 is similar to that of the first substrate W1. Figure 15 The structure shown is the same. In the first portion 110 of the first CMOS layer 100 on the fabricated first substrate W1, as... Figure 22 As shown, the insulating layer 55 of the bonding layer B4 is exposed. In the second CMOS layer 200 on the fabricated second substrate W2, as... Figure 23 As shown, the insulating layer 61 of the bonding layer B3 and the bonding pad BP (conductive layer 65) are exposed. Furthermore, during S21, no structure corresponding to the contact C3 is formed on the second substrate W2 and the second CMOS layer 200.

[0204] Next, the second substrate W2 and the third substrate W3 are joined together, as follows: Figure 24 As shown, a first bonding substrate BW1a is formed (S22). Specifically, through the bonding process of the second substrate W2 and the third substrate W3, the insulating layer 61 of the second CMOS layer 200 and the insulating layer 35 of the third substrate W3 come into contact and are bonded. Furthermore, the bonding pads BP facing each other between the second CMOS layer 200 and the memory layer 300 come into contact and are bonded. Thus, the first bonding substrate BW1a is formed.

[0205] Next, a CMP process (S23) is performed on the second substrate W2 contained in the first bonding substrate BW1a. Through the S23 process, the thickness of the second substrate W2, which is thinned by polishing, corresponds to... Figure 20 The thickness of the second substrate W2 shown.

[0206] Next, a second portion 120 of the first CMOS layer 100 is formed on the first bonding substrate BW1a (S24). The formation process of the second portion 120 of the first CMOS layer 100 includes an etching process for forming the contact C3. Specifically, firstly, an insulating layer is formed, and a third hole penetrating the second substrate W2 is formed in a manner overlapping the conductive layer 62. Moreover, after the sidewall of the insulating film INS is formed in the hole, a conductor is embedded. Thus, the contact C3 connecting the circuit in the second portion 120 of the first CMOS layer 100 and the circuit in the second CMOS layer 200 is formed. Afterward, the wiring layers D2 to D0 and the bonding layer Bb are formed, and the process of S24 is completed.

[0207] Next, as Figure 26 As shown, a second bonding substrate BW2a is formed by bonding a first bonding substrate BW1a to a first substrate W1 (S25). Specifically, bonding layers B4 and B5 are bonded through the bonding process of the first bonding substrate BW1a and the first substrate W1. More specifically, the insulating layer 56 of the second portion 120 of the first CMOS layer 100 formed on the second substrate W2 contacts and is bonded to the insulating layer 55 of the first portion 110 of the first CMOS layer 100 formed on the first substrate W1. Furthermore, the bonding pads BP facing each other between the first portion 110 and the second portion 120 of the first CMOS layer 100 contact and are bonded. Thus, the second bonding substrate BW2a is formed.

[0208] Next, a CMP process (S26) is performed on the third substrate W3 contained in the second bonding substrate BW2a. Through the S26 process, the thickness of the third substrate W3, which is thinned by polishing, corresponds to... Figure 20 The thickness of the third substrate W3 shown.

[0209] Next, a wiring layer 400 is formed on the second bonding substrate BW2a (S27). The process of S27 includes etching the third substrate W3, forming wiring and an insulating film, and forming pads PD. If the process of S27 is completed, the memory device 1a is completed.

[0210] [2-3] Effects of the second embodiment

[0211] The memory device 1 according to the second embodiment, like the first embodiment, can suppress the increase in chip area and suppress the manufacturing cost of the memory device.

[0212] Furthermore, in the memory device 1 of the second embodiment, the second portion 120 (wiring layers D0 to D2) of the first CMOS layer 100a is formed using the back side of the second substrate W2. Moreover, the first portion 110 of the first CMOS layer 100a is provided on the first substrate W1. As a result, the aspect ratio of the contact CS1a formed on the first substrate W1 is reduced. Therefore, the memory device 1 of the second embodiment can reduce the spacing between the conductive layer GC1 and the contact CS1a, and can reduce the area of ​​the read amplifier module 17.

[0213] Furthermore, in the memory device 1 of the second embodiment, wiring can also be formed using bonding layers B4 and B5. In this case, the process of forming wiring of the first CMOS layer 100a is reduced, which can suppress the manufacturing cost of the memory device 1.

[0214] [3] Third implementation method

[0215] The memory device 1b of the third embodiment has a structure in which a circuit corresponding to the first CMOS layer 100 is formed using a first substrate W1, as in the memory device 1a of the second embodiment. The details of the third embodiment will be described below.

[0216] [3-1] Cross-sectional structure of memory devices

[0217] Figure 27 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1b according to the third embodiment. For example... Figure 27 As shown, the memory device 1b has a structure in which the bonding layers B4 and B5 described in the second embodiment are used in the bonding of the first substrate W1 and the second substrate W2 in the memory device 1 described in the first embodiment. The memory device 1b, corresponding to the first CMOS layer 100b, includes insulating layers 50 and 55, a conductive layer GC1, multiple bonding pads BP, and contacts CS, C0 to C2, and C3a. The back side portion of the memory device 1a, corresponding to the second substrate W2, includes insulating layers 66 and 56, multiple bonding pads BP, and contacts C3b.

[0218] The insulating layer 50, similar to that in the first embodiment, is disposed on the first substrate W1. The insulating layer 50 includes wiring layers D0, D1, and D2. An insulating layer 55 is disposed on the insulating layer 50. The insulating layer 55 is included in the bonding layer B4. The insulating layer 55 is, for example, a silicon oxide film. A plurality of bonding pads BP included in the bonding layer B4 are connected to contacts C3a. Contacts C3a are disposed on corresponding conductive layers 54.

[0219] An insulating layer 56 is disposed on an insulating layer 55. The insulating layer 56 is included in the bonding layer B5. The insulating layer 56 is, for example, a silicon oxide film. The boundary between the insulating layer 55 and the insulating layer 56 corresponds to the bonding surface of the first substrate W1 and the second substrate W2. An insulating layer 66 is disposed on the insulating layer 56. The insulating layer 66 is in contact with the back side of the second substrate W2. Contacts C3b are disposed on a plurality of bonding pads BP included in the bonding layer B5. The contacts C3b are disposed through the second substrate W2 and the insulating layer 56, connecting the corresponding conductive layer 62 to the bonding pads BP. The contacts C3b are insulated from the second substrate W2 by an insulating film INS.

[0220] The bonding pads BP contained in bonding layer B4 are respectively connected to the multiple bonding pads BP contained in bonding layer B5 and arranged opposite each other. Thus, in the third embodiment, the conductive layer 54 of wiring layer D2 and the conductive layer 62 of wiring layer D3 are electrically connected through the group of contact body C3a, the two oppositely arranged bonding pads BP and contact body C3b.

[0221] Furthermore, in the third embodiment, the first CMOS layer 100b, including the bonding layer B4, is formed using the first substrate W1. On the other hand, the bonding layer B5 is formed using the back side of the second substrate W2. The other configurations of the memory device 1b in the third embodiment are the same as those in the memory device 1 of the first embodiment.

[0222] [3-2] Manufacturing method of memory device

[0223] Figure 28 This is a flowchart illustrating an example of a method for manufacturing the memory device 1b according to the third embodiment. Figures 29-31 These are cross-sectional views showing an example of the cross-sectional structure of the memory device 1b during manufacturing according to the third embodiment. Hereinafter, reference will be made as appropriate. Figure 28 The manufacturing method of the memory device 1b according to the third embodiment will be described.

[0224] First, a third substrate W3 with a memory layer 300, a first substrate W1 with a first CMOS layer 100b, and a second substrate W2 with a second CMOS layer 200 are fabricated (S31). The structure of the memory layer 300 on the fabricated third substrate W3 is similar to... Figure 15 The structure shown is the same. In the first CMOS layer 100 on the fabricated first substrate W1, as... Figure 29 As shown, the insulating layer 55 and bonding pad BP in bonding layer B4 are exposed. The structure of the second CMOS layer 200 on the fabricated second substrate W2 is similar to... Figure 23 The structures shown are the same.

[0225] Next, similar to the second embodiment, the second substrate W2 and the third substrate W3 are bonded together to form the first bonding substrate BW1a (S22).

[0226] Next, similar to the second embodiment, a CMP process (S23) is performed targeting the second substrate W2 contained in the first bonding substrate BW1a.

[0227] Next, a bonding layer B5 (S32) is formed above the first bonding substrate BW1a. Specifically, first, an insulating layer 66 is formed. Furthermore, a hole is formed that penetrates the second substrate W2 and the insulating layer 66, overlapping with the conductive layer 62. Then, after forming the sidewalls of the insulating film INS in the hole, a conductor is embedded. This forms a contact C3b. Next, an insulating layer 56 is formed. Then, the portion of the insulating layer 56 where the bonding pad BP is disposed is removed by photolithography and etching. Then, a conductor (bonding pad BP) is embedded in the portion where the insulating layer 56 has been removed. Thus, the bonding pad BP located above the second substrate W2 is connected to the circuitry within the second CMOS layer 200 via the contact C3b.

[0228] Next, as Figure 26 As shown, a second bonding substrate BW2b is formed by bonding the first bonding substrate BW1a and the first substrate W1 (S33). Specifically, bonding layers B4 and B5 are bonded through the bonding process of the first bonding substrate BW1a and the first substrate W1. More specifically, through the bonding process of the first bonding substrate BW1a and the first substrate W1, the insulating layer 56 formed using the second substrate W2 and the insulating layer 55 formed using the first substrate W1 come into contact and are bonded. Furthermore, the set of bonding pads BP facing each other between bonding layers B5 and B4 come into contact and are bonded. Thus, the contact bodies C3a and C3b are electrically connected through the set of bonding pads BP arranged in opposite directions.

[0229] Next, a CMP process (S34) is performed on the third substrate W3 contained in the second bonding substrate BW2b. Through the S34 process, the thickness of the third substrate W3, which is thinned by polishing, corresponds to... Figure 27 The thickness of the third substrate W3 shown.

[0230] Next, a wiring layer 400 is formed on the second bonding substrate BW2b (S35). The process of S35 includes etching the third substrate W3, forming wiring and an insulating film, and forming pads PD. If the process of S35 is completed, the memory device 1b is completed.

[0231] [3-3] Effects of the third implementation method

[0232] The memory device 1 according to the third embodiment, like the second embodiment, can suppress the increase in chip area and suppress the manufacturing cost of the memory device.

[0233] [4] Fourth implementation method

[0234] The fourth embodiment relates to the circuit configuration of the first CMOS layer 100 and the second CMOS layer 200 in the memory device 1. The details of the fourth embodiment will be described below.

[0235] [4-1] Circuit configuration of memory device 1

[0236] Hereinafter, as variations of the circuit configuration of the memory device 1, the first, second, third, fourth, fifth, sixth, seventh, and eighth configuration examples of the fourth embodiment will be described in sequence.

[0237] [4-1-1] First example of composition

[0238] Figure 32 This is a schematic diagram illustrating an example of the circuit configuration of the memory device 1 in the first configuration example of the fourth embodiment. For example... Figure 32 As shown, the memory device 1 of the first configuration example of the fourth embodiment includes row decoder modules 16A, 16B, 16C, and 16D with different associated data blocks BLK. Row decoder modules 16A and 16B of the first configuration example of the fourth embodiment are disposed on the first CMOS layer 100 (first substrate W1) and connected to the stacked wiring of the lead-out regions HR1 and HR2, respectively. Row decoder modules 16C and 16B of the first configuration example of the fourth embodiment are disposed on the second CMOS layer 200 (second substrate W2) and connected to the stacked wiring of the lead-out regions HR1 and HR2, respectively.

[0239] That is, in the first configuration example of the fourth embodiment, the line decoder RD is respectively disposed on one side and the other side of the first substrate W1 in the X direction, and on one side and the other side of the second substrate W2 in the X direction. Furthermore, the line decoder module 16A is connected to the stacked wiring of the lead-out region HR1 via the second substrate W2 and the second CMOS layer 200. The line decoder module 16B is connected to the stacked wiring of the lead-out region HR2 via the second substrate W2 and the second CMOS layer 200. The readout amplifier module 17 of the first configuration example of the fourth embodiment can be disposed on either the first substrate W1 or the second substrate W2.

[0240] [4-1-2] Second example of composition

[0241] Figure 33This is a schematic diagram illustrating an example of the circuit configuration of the memory device 1 in the second configuration example of the fourth embodiment. For example... Figure 33 As shown, the memory device 1 of the second configuration example of the fourth embodiment includes row decoder modules 16A and 16B with different associated data blocks BLK. Row decoder module 16A of the second configuration example of the fourth embodiment is disposed on the second CMOS layer 200 (second substrate W2) and connected to the stacked wiring of the lead-out region HR1. Row decoder module 16B of the second configuration example of the fourth embodiment is disposed on the first CMOS layer 100 (first substrate W1) and connected to the stacked wiring of the lead-out region HR2.

[0242] That is, in the second configuration example of the fourth embodiment, the line decoder RD is disposed on one side of the first substrate W1 in the X direction and the other side of the second substrate W2 in the X direction. Furthermore, the stacked wiring of the line decoder module 16B and the lead-out region HR2 is connected via the second substrate W2 and the second CMOS layer 200. The sense amplifier module 17 of the first configuration example of the fourth embodiment can be disposed on either the first substrate W1 or the second substrate W2.

[0243] [4-1-3] Third example

[0244] Figure 34 This is a schematic diagram illustrating an example of the circuit configuration of the memory device 1 in the third configuration example of the fourth embodiment. For example... Figure 34 As shown, the memory device 1 of the third configuration example of the fourth embodiment includes row decoder modules 16A and 16B with different associated data blocks BLK. Row decoder module 16A of the third configuration example of the fourth embodiment is connected to the stacked wiring of the lead-out region HR1. Row decoder module 16B of the second configuration example of the fourth embodiment is connected to the stacked wiring of the lead-out region HR2.

[0245] Furthermore, in the third configuration example of the fourth embodiment, the plurality of elements constituting the line decoder RD of the line decoder module 16A are classified into a first element group 161A and a second element group 162A. Similarly, the plurality of elements constituting the line decoder RD of the line decoder module 16B are classified into a first element group 161B and a second element group 162B. For example, in the third configuration example of the fourth embodiment, the first element groups 161A and 161B are disposed on the first CMOS layer 100 (first substrate W1) and overlap with the lead-out regions HR1 and HR2, respectively. In addition, the second element groups 162A and 162B are disposed on the second CMOS layer 200 (second substrate W2) and overlap with the lead-out regions HR1 and HR2, respectively. The first element groups 161A and 161B, for example, each include a transistor TR (HV transistor). The second element groups 162A and 162B, for example, each include a data block decoder BD.

[0246] As explained above, in the third configuration example of the fourth embodiment, the line decoder RD includes at least one transistor disposed on the first CMOS layer 100 and at least one transistor disposed on the second CMOS layer 200. Furthermore, the component allocation of the first component groups 161A and 161B and the second component groups 162A and 162B can be appropriately modified. The readout amplifier module 17 of the third configuration example of the fourth embodiment can be disposed on either the first substrate W1 or the second substrate W2.

[0247] [4-1-4] Fourth example of composition

[0248] Figure 35 This is a schematic diagram illustrating an example of the circuit configuration of the memory device 1 in the fourth configuration example of the fourth embodiment. For example... Figure 35 As shown, the memory device 1 of the fourth embodiment of the fourth configuration example includes sense amplifier modules 17A and 17B with different associated bit lines BL. The sense amplifier modules 17A and 17B of the fourth embodiment of the fourth configuration example are respectively disposed on the first CMOS layer 100 (first substrate W1) and the second CMOS layer 200 (second substrate W2), and are respectively connected to the associated bit lines BL in the memory region MR.

[0249] That is, in the fourth configuration example of the fourth embodiment, the sense amplifier module 17 is disposed on the first substrate W1 and the second substrate W2, respectively. The sense amplifier module 17A and the associated bit line BL are connected via the second substrate W2 and the second CMOS layer 200. In addition, the line decoder module 16 of the fourth configuration example of the fourth embodiment can be disposed on either the first substrate W1 or the second substrate W2. In this example, the line decoder modules 16A and 16B are disposed on the first CMOS layer 100 (first substrate W1) and are respectively connected to the stacked wiring of the lead-out regions HR1 and HA2.

[0250] Alternatively, the wiring of the input / output circuit 11 can be respectively disposed on the first substrate W1 and the second substrate W2, and a sense amplifier unit SAU can be respectively disposed on the first substrate W1 and the second substrate W2 corresponding to the wiring of the input / output circuit 11.

[0251] [4-1-5] Fifth example

[0252] Figure 36 This is a schematic diagram illustrating an example of the circuit configuration of the memory device 1 in the fifth configuration example of the fourth embodiment. For example... Figure 36 As shown, the readout amplifier module 17 of the fifth configuration example of the fourth embodiment is connected to the associated bit line BL in the memory region MR.

[0253] Furthermore, in the fifth configuration example of the fourth embodiment, the multiple components constituting the sense amplifier module 17 are classified into a first component group 171 and a second component group 172. For example, in the fifth configuration example of the fourth embodiment, the first component group 171 is disposed on the first CMOS layer 100 (first substrate W1), and the second component group 172 is disposed on the second CMOS layer 200 (second substrate W2). The first component group 171 includes, for example, a transistor for a bit line connection portion BLHU. The second component group 172 includes, for example, a transistor for a sense data latch portion SADL.

[0254] As explained above, in the fifth configuration example of the fourth embodiment, the readout amplifier module 17 includes at least one transistor disposed on the first CMOS layer 100 and at least one transistor disposed on the second CMOS layer 200. Furthermore, the line decoder module 16 of the fifth configuration example of the fourth embodiment can be disposed on either the first substrate W1 or the second substrate W2. In this example, line decoder modules 16A and 16B are disposed on the first CMOS layer 100 (first substrate W1) and are respectively connected to the stacked wiring of the lead-out regions HR1 and HR2.

[0255] [4-1-6] Sixth example

[0256] Figure 37 This is a schematic diagram illustrating an example of the circuit configuration of the memory device 1 in the sixth configuration example of the fourth embodiment. For example... Figure 37 As shown, in the memory device 1 of the sixth configuration example of the fourth embodiment, the row decoder module 16 and the sense amplifier module 17 are disposed on different substrates. Specifically, in the sixth configuration example of the fourth embodiment, for example, the row decoder modules 16A and 16B are disposed on the first CMOS layer 100 (first substrate W1) in a manner that overlaps with the lead-out regions HR1 and HR2, respectively. Moreover, the sense amplifier module 17 is disposed on the second CMOS layer 200 (second substrate W2) in a manner that overlaps with the memory region MR.

[0257] That is, in the sixth configuration example of the fourth embodiment, the line decoder module 16 includes a plurality of transistors disposed on the first CMOS layer 100, and the readout amplifier module 17 includes a plurality of transistors disposed on the second CMOS layer 200. Furthermore, the substrate on which the line decoder module 16 is configured and the substrate on which the readout amplifier module 17 is configured are interchangeable.

[0258] [4-1-7] Seventh example

[0259] Figure 38 This is a schematic diagram illustrating an example of the circuit configuration of the memory device 1 in the seventh configuration example of the fourth embodiment. For example... Figure 38As shown, in the memory device 1 of the seventh configuration example of the fourth embodiment, the HV transistor and the LV transistor are disposed on different substrates. Specifically, in the seventh configuration example of the fourth embodiment, for example, the HV transistor is disposed on the first CMOS layer 100 (first substrate W1), and the LV transistor is disposed on the second CMOS layer 200 (second substrate W2). The first CMOS layer 100 includes line decoder modules 16A and 16B disposed in a manner overlapping with the lead-out regions HR1 and HR2, respectively, and a first element group 171 disposed in a manner overlapping with the memory region MR and corresponding to the bit line connection portion BLHU. On the other hand, the second CMOS layer 200 includes a second element group 172 disposed in a manner overlapping with the memory region MR and corresponding to the read data latch portion SADL.

[0260] Furthermore, in the seventh configuration example of the fourth embodiment, the structure of the gate electrode of the transistor can be changed between the substrate where the HV transistor is disposed and the substrate where the LV transistor is disposed. For example, a WSi gate structure or a W polymetal structure can be used for the gate electrode of the transistor disposed on the substrate where the HV transistor is disposed. On the other hand, for example, a self-aligned silicide structure can be used for the gate electrode of the transistor disposed on the substrate where the LV transistor is disposed. The structures of the gate electrodes of the first substrate W1 and the second substrate W2 are designed, for example, according to the reduction of chip area and the performance requirements of the input / output circuit 11.

[0261] The HV transistor with WSi gate structure has, for example, a structure in which polysilicon (Poly-Si), tungsten silicide (WSi), and titanium nitride (TiN) are sequentially stacked on a gate insulating film (oxide film) as gate electrodes, and silicon nitride (SiN) is formed on the gate electrodes as a capping layer.

[0262] The W-polymetallic HV transistor has, for example, a structure in which polysilicon (Poly-Si), titanium nitride (TiN), tungsten nitride (WN), and tungsten (W) are sequentially stacked on a gate insulating film (oxide film) as gate electrodes, and silicon nitride (SiN) is formed on the gate electrodes as a capping layer. This gate electrode structure can also be called a W-polymetallic gate.

[0263] LV transistors with self-aligned silicide structures have configurations in which, for example, polycrystalline silicon (Poly-Si) or nickel-platinum silicide (NiPtSi) is formed on the gate insulating film (oxide film) as the gate electrode. This gate electrode configuration can also be referred to as a NiPtSi gate.

[0264] [4-1-8] Eighth example

[0265] Figure 39This is a schematic diagram illustrating an example of the circuit configuration of the memory device 1 in the eighth configuration example of the fourth embodiment. For example... Figure 39 As shown, the memory device 1 of the eighth configuration example of the fourth embodiment has a relative to Figure 35 The fifth configuration example of the fourth embodiment shown is a configuration in which the layout of the memory cell array 10 and the row decoder module 16 is rotated by 90°. In the eighth configuration example of the fourth embodiment, the bit line BL is provided to extend along the X direction, and the word line WL is provided to extend along the Y direction. Moreover, the lead-out regions HR1 and HR2 are arranged to sandwich the memory region MR in the Y direction, and the row decoder modules 16A and 16B are arranged to overlap with the lead-out regions HR1 and HR2, respectively.

[0266] [4-2] Effects of the fourth embodiment

[0267] The memory device 1 according to the fourth embodiment, like the first embodiment, can reduce chip area and manufacturing cost. The effects of the fourth embodiment will be described in detail below.

[0268] Figure 40 This is a schematic diagram illustrating an example of a change in the layout of the memory device 1 obtained by applying the fourth embodiment. Figure 40 (A) shows an example of the layout of memory device 1 in which a sense amplifier unit SAU and a line decoder RD are formed on a substrate. Figure 41 (B) and (C) show an example of the layout of the memory device 1 when the fourth embodiment is applied.

[0269] like Figure 40 As shown in (A), if the integration density of the memory cell array 10 increases, the width LY1 in the Y direction of the peripheral circuit region PERI and the sense amplifier module 17 may be larger than the width in the Y direction of the line decoder RD. The remaining area TB formed by the peripheral circuit region PERI extending in the Y direction may become an important factor in the chip area of ​​the memory device 1.

[0270] If the fourth embodiment is applied, for example, the line decoder module 16 and the readout amplifier module 17 are configured on different substrates. Specifically, as... Figure 40 As shown in (B), in the second substrate W2, which is configured with a sense amplifier unit SAU and a portion of the peripheral circuit region PERI, the width in the X direction becomes LX2, which is narrower than LX1, and the width in the Y direction becomes LY2, which is narrower than LY1. Furthermore, as... Figure 40As shown in (C), in the first substrate W1, which is configured with a line decoder RD and a portion of the peripheral circuit region PERI, the width in the X direction becomes LX3, which is narrower than LX1, and the width in the Y direction becomes LY3, which is narrower than LY1.

[0271] That is, regardless of whether it is the first substrate W1 or the second substrate W2, the chip area can be suppressed compared to the case where the fourth embodiment is not applied. Furthermore, by overlapping the first substrate W1 and the second substrate W2, the memory device 1 can suppress the generation of the remaining area TB. Therefore, even when the integration density of the memory cell array 10 increases, the memory device 1 of the fourth embodiment can avoid the combined area of ​​the first CMOS layer 100 and the second CMOS layer 200 being larger than the area of ​​the memory layer 300. As a result, the memory device 1 of the fourth embodiment can suppress the chip area and reduce the manufacturing cost of the memory device 1.

[0272] Figure 41 This is a schematic diagram illustrating an example of a change in the layout of the readout amplifier module 17 obtained by applying the seventh configuration example of the fourth embodiment. Figure 41 (A) shows an example of the layout of memory device 1 in the case where a sense amplifier unit SAU is formed on a substrate. Figure 41 (B) shows an example of the layout of the memory device 1 when the seventh configuration example of the fourth embodiment is applied.

[0273] like Figure 41 As shown in (A), the read data latch unit SADL and the bit line connection unit BLHU are arranged, for example, in the Y direction (the extension direction of the bit line BL). Specifically, four read data latch units SADL1 to SADL4 are arranged in the Y direction. Moreover, the bit line connection unit BLHU associated with SADL is arranged between read data latch units SADL1 and SADL2. The bit line connection unit BLHU associated with SADL is arranged between read data latch units SADL3 and SADL4. In this example, the width of the Y direction used to arrange the read data latch units SADL1 to SADL4 is LY4.

[0274] On the other hand, if the seventh configuration example of the fourth embodiment is applied, the read data latch unit SADL and the bit line connection unit BLHU are formed on different substrates. As a result, as... Figure 41 As shown in (B), the bit line connection portion BLHU (formed on a different substrate) is omitted. Therefore, the width in the Y direction of the read data latches SADL1 to SADL4 is LY5, which is narrower than LY4. That is, the seventh configuration example of the fourth embodiment can suppress the width in the Y direction of the read data latches SADL disposed on the second substrate W2.

[0275] For example, the width of the memory device 1 in the X direction is limited by the width of the sense amplifier module 17 in the X direction, and the width of the memory device 1 in the Y direction is limited by the width of the line decoder module 16 in the Y direction. Figure 42 This is a schematic diagram illustrating an example of the layout of the memory device 1 when combining the seventh and eighth configuration examples of the fourth embodiment. Figure 42 As shown, by aligning the directions of the readout amplifier module 17 and the line decoder module 16, the CMOS circuit can be configured efficiently. Therefore, the combination of the seventh and eighth configuration examples of the fourth embodiment enables efficient configuration of the CMOS circuit and suppresses the generation of residual region TB.

[0276] The seventh configuration of the fourth embodiment allows for changing the gate electrode structure between the LV transistor and the HV transistor. As a result, the seventh configuration of the fourth embodiment can more easily optimize the performance requirements of both the LV transistor and the HV transistor. Furthermore, by separating the substrate forming the LV transistor from the substrate forming the HV transistor, parasitic capacitance caused by the contact CS in the LV transistor can be reduced. As a result, the seventh configuration of the fourth embodiment can improve the operating performance of the memory device 1. Moreover, in the HV transistor, since the effect of the electric field propagating from wiring layers D1 to D3 is suppressed, deviations in the conduction current can be suppressed.

[0277] [5] Fifth implementation method

[0278] The fifth embodiment relates to a structure of a passive element that can be formed in the memory device 1. The details of the fifth embodiment will be described below.

[0279] [5-1] Construction of memory devices

[0280] The memory device 1 of the fifth embodiment includes a passive element composed of a combination of a first CMOS layer 100 and a second CMOS layer 200. Furthermore, the passive element described in the fifth embodiment is a resistive element and a capacitive element. In addition, in the fifth embodiment, a case is described using the seventh configuration example of the fourth embodiment, in which an HV transistor is provided on the first substrate W1 and an LV transistor is provided on the second substrate W2.

[0281] [5-1-1] Planar layout of the first CMOS layer 100

[0282] Figure 43 This is a top view showing an example of the planar layout of the first CMOS layer 100 provided in the memory device 1 of the fifth embodiment, and also shows the impurity diffusion region (active region) formed on the first substrate W1. Figure 43As shown, the first CMOS layer 100 includes, for example, multiple active regions AA1, multiple conductive layers GC3, conductive portions CP1a and CP2a.

[0283] Multiple active regions AA1 are arranged in the X direction with a first spacing P1. The active regions AA1 can be either P-type or N-type impurity diffusion regions formed on the first substrate W1. Although not shown in the figure, STIs are provided around each active region AA1. Multiple conductive layers GC3 are arranged, for example, in the X direction. The conductive layers GC3 have the same stacked structure as the gate electrode (conductive layer GC1) of the transistor utilizing the first substrate W1. The conductive layers GC3 have a gate width GW1. Conductor portions CP1a and CP2a, for example, have portions extending in the same direction. In this example, the conductive portions CP1a and CP2a are respectively extended in the Y direction.

[0284] [5-1-2] Planar layout of the second CMOS layer 200

[0285] Figure 44 This is a top view showing an example of the planar layout of the second CMOS layer 200 provided in the memory device 1 of the fifth embodiment, and also shows the impurity diffusion region (active region) formed on the second substrate W2. Figure 44 As shown, the second CMOS layer 200 includes, for example, multiple active regions AA2, multiple conductor layers GC4, conductor portions CP1b and CP2b.

[0286] Multiple active regions AA2 are arranged in the X direction, for example, with a second pitch P2 narrower than the first pitch P1. The active regions AA2 can also be either P-type or N-type impurity diffusion regions formed on the second substrate W2. Although not shown in the figure, STIs are provided around each active region AA2. Multiple conductive layers GC4 are arranged in the X direction, for example. The conductive layers GC4 have the same stacked structure as the gate electrode (conductive layer GC2) of the transistor utilizing the second substrate W2. The conductive layers GC4, for example, have a gate width GW2 narrower than the gate width GW1. Conductor portions CP1b and CP2b, for example, have portions extending in the same direction. In this example, conductor portions CP1b and CP2b extend in the Y direction. Furthermore, conductor portions CP1b and CP2b are arranged to overlap with conductor portions CP1a and CP2a, respectively.

[0287] [5-1-3] Cross-sectional structure of memory device 1

[0288] Figure 45This is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1 according to the fifth embodiment, illustrating the cross-sectional structure of the storage region MR and the cross-sectional structure of the region forming passive elements. Figure 45 As shown, the construction of the storage region MR is the same as that used in the first embodiment. Figure 13 The construction described is the same. Furthermore, the memory device 1 also includes a region for forming a resistive element REG1, a region for forming a resistive element REG2, and a region for forming a capacitive element CAP. In addition, the memory device 1 includes, for example, conductive layers 71-76 and contacts CS1x, CS1y, CS2x, CS2y, C0x, C0y, C5x, and C5y in the regions forming the resistive elements REG1, REG2, and the capacitive element CAP.

[0289] Conductor layers 71-76 are disposed, for example, between the third substrate W3 and the insulating layer 70. Conductor layers 71-76 are connected, for example, to conductor layer 28 of wiring layer M0 via contact CC. Conductor layers 71 and 72 are wirings corresponding to one end and the other end of resistive element REG1, respectively. Conductor layers 73 and 74 are wirings corresponding to one end and the other end of resistive element REG2, respectively. Conductor layers 75 and 76 are wirings corresponding to one end and the other end of capacitive element CAP, respectively.

[0290] Resistive element REG1, for example, has a structure in which active regions AA1 and AA2 are connected in series. Specifically, contacts CS1x and CS1y are connected to one end and the other end of active region AA1, respectively. Contacts CS2x and CS2y are connected to one end and the other end of active region AA2, respectively. Contact CS1x is connected to conductive layer 71, for example, via conductive layers 28, 29, 52-54 and 62-64, contacts C1-C3, C6-C8, V0, V1 and CC, and the bonded bonding pad BP. Contact CS1y is connected to contact CS2y, for example, via conductive layers 52-54, 62 and 63, and contacts C1-C3 and C6. Contact CS2x is connected to conductive layer 72 via conductive layers 28, 29 and 62-64, contacts C6-C8, V0, V1 and CC, and the bonded bonding pad BP. Furthermore, the resistor element REG1 can have a structure in which multiple active regions AA1 are connected in series, or it can have a structure in which multiple active regions AA2 are connected in series. The resistor element REG1 can also have a structure in which active regions AA1 and AA2 are connected in parallel. The resistor element REG1 can have a structure that includes at least an active region AA1 provided on the first substrate W1 and an active region AA2 provided on the second substrate W2.

[0291] Resistive element REG2, for example, has a structure in which conductive layers GC3 and GC4 are connected in series. Specifically, contacts C0x and C0y are connected to one end and the other end of conductive layer GC3, respectively. Contacts C5x and C5y are connected to one end and the other end of conductive layer GC4, respectively. Contact C0x is connected to conductive layer 73, for example, via conductive layers 28, 29, 52-54 and 62-64, contacts C1-C3, C6-C8, V0, V1 and CC, and the bonded bonding pad BP. Contact C0y is connected to contact C5y, for example, via conductive layers 52-54, 62 and 63, and contacts C1-C3 and C6. Contact C5x is connected to conductive layer 74 via conductive layers 28, 29 and 62-64, contacts C6-C8, V0, V1 and CC, and the bonded bonding pad BP. Furthermore, the resistive element REG2 can have a structure in which multiple conductive layers GC3 are connected in series, or it can have a structure in which multiple conductive layers GC4 are connected in series. Additionally, the resistive element REG2 can also have a structure in which conductive layers GC3 and GC4 are connected in parallel. The resistive element REG2 only needs to have a structure with at least a conductive layer GC3 disposed on the first substrate W1 and a conductive layer GC4 disposed on the second substrate W2. In this example, conductive layers GC3 and GC4 are respectively disposed above STI. Thus, conductive layers GC3 and GC4 can also be disposed above an insulator embedded near the surface of the substrate.

[0292] A capacitor element CAP, for example, has a configuration in which conductive portions CP1a and CP1b are connected in series, and conductive portions CP2a and CP2b are connected in series, arranged in parallel. Specifically, conductive layer 75, conductive layers 52-54 corresponding to conductive portion CP1a and a group of contacts C1-C3, conductive layers 62-64 corresponding to conductive portion CP1b and a group of contacts C6-C8, conductive layers 28 and 29, and contacts V0, V1, and CC are connected in series. Conductor layer 76, conductive layers 52-54 corresponding to conductive portion CP2a and a group of contacts C1-C3, conductive layers 62-64 corresponding to conductive portion CP2b and a group of contacts C6-C8, conductive layers 28 and 29, and contacts V0, V1, and CC are connected in series. The conductive layers and contacts of the first CMOS layer 100, the second CMOS layer 200, and the storage layer 300 connected to the conductive layer 75, and the conductive layers and contacts of the first CMOS layer 100, the second CMOS layer 200, and the storage layer 300 connected to the conductive layer 76, are arranged facing each other to function as capacitor elements. Furthermore, multiple capacitor elements (CAPs) can be connected in parallel. The capacitor element (CAP) only requires the construction of the first CMOS layer 100 and the second CMOS layer 200.

[0293] Furthermore, the above description illustrates the configuration of resistors REG1 and REG2 and capacitor CAP based on the structure of the memory device 1 described in the first embodiment, but is not limited thereto. The configurations of resistors REG1 and REG2 and capacitor CAP can also be formed using one of the second and third embodiments. In this case, a set of two bonding pads BP for bonding the first substrate W1 and the second substrate W2 is added between the first substrate W1 and the second substrate W2.

[0294] [5-2] Effects of the fifth embodiment

[0295] As explained above, the memory device 1 of the fifth embodiment includes passive components spanning multiple substrates. For example, resistive elements are connected in series between the first substrate W1 and the second substrate W2 via TSVs. Capacitive elements are connected in parallel between the first substrate W1 and the second substrate W2 via TSVs. Furthermore, in the fifth embodiment, for example, the area of ​​the CMOS circuits formed on the first substrate W1 and the second substrate W2 is less than the area of ​​the memory cell array 10. Moreover, the portions of the first substrate W1 and the second substrate W2 where no CMOS circuits are formed are configured with the passive components described in the fifth embodiment.

[0296] Therefore, the memory device 1 of the fifth embodiment can suppress the area used to form passive components and can suppress the chip area. As a result, the memory device 1 of the fifth embodiment can suppress the manufacturing cost of the memory device 1.

[0297] Furthermore, the memory device 1 of the fifth embodiment can flexibly configure passive components based on the dedicated area of ​​the CMOS circuits of the first substrate W1 and the second substrate W2. For example, when the area of ​​the CMOS circuit on the first substrate W1 is smaller than the area of ​​the CMOS circuit on the second substrate W2, the total area of ​​the plurality of active regions AA1 is designed to be larger than the total area of ​​the plurality of active regions AA2. On the other hand, when the area of ​​the CMOS circuit on the first substrate W1 is larger than the area of ​​the CMOS circuit on the second substrate W2, the total area of ​​the plurality of active regions AA1 is designed to be smaller than the total area of ​​the plurality of active regions AA2. As a result, the memory device 1 of the fifth embodiment can efficiently configure CMOS circuits and passive components on the first substrate W1 and the second substrate W2, and can suppress chip area.

[0298] Furthermore, in the fifth embodiment, for example, a WSi gate structure is used as the gate electrode of the first substrate W1 where the HV transistor is configured, and a Ti / TiN / W or NiPtSi gate structure is used as the gate electrode of the second substrate W2 where the LV transistor is configured. This reduces the area of ​​the passive components and suppresses Hump. Thus, in the fifth embodiment, it is preferable to select the stacked structure of the gate electrodes according to the purpose.

[0299] [6] Sixth implementation method

[0300] The memory device 1c according to the sixth embodiment has a configuration consisting of multiple substrates having storage circuitry and multiple substrates having CMOS circuitry stacked together. The details of the sixth embodiment will be described below.

[0301] [6-1] Appearance of memory device 1c

[0302] Figure 46 This is a perspective view showing an example of the appearance of the memory device 1c according to the sixth embodiment. Figure 46 As shown, the memory device 1c has, for example, a structure in which a first substrate W1, a first CMOS layer 100a, a second substrate W2, a second CMOS layer 200a, a first storage layer 300a, a third substrate W3, a second storage layer 300b, a fourth substrate W4, and a wiring layer 400 are stacked sequentially from bottom to top.

[0303] The first CMOS layer 100a includes CMOS circuitry formed using the first substrate W1. The second CMOS layer 200a includes CMOS circuitry formed using the second substrate W2. The first CMOS layer 100a and the second CMOS layer 200a can each include an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a line decoder module 16, and a sense amplifier module 17. These circuits are configured in either the first CMOS layer 100a or the second CMOS layer 200a. These circuits can also be constructed from combinations of transistors configured in the first CMOS layer 100a and transistors configured in the second CMOS layer 200a.

[0304] The first storage layer 300a includes a storage cell array 10 formed using a third substrate W3. The second storage layer 300b includes a storage cell array 10 formed using a fourth substrate W4. The first storage layer 300a and the second storage layer 300b may each include multiple storage cell arrays 10. The wiring layer 400, similar to the first embodiment, includes multiple pads PD used for connecting the memory device 1 and the memory controller 2.

[0305] The first substrate W1, the second substrate W2, the third substrate W3, and the fourth substrate W4 are all silicon substrates. Each of the first substrate W1, the second substrate W2, the third substrate W3, and the fourth substrate W4 has an impurity diffusion region corresponding to the circuit design of the memory device 1c. The memory device 1c has bonding surfaces between adjacent substrates. In the memory device 1c, the contact (boundary) portions between the first CMOS layer 100a and the second substrate W2, the contact (boundary) portions between the second CMOS layer 200a and the first memory layer 300a, and the contact (boundary) portions between the third substrate W3 and the second memory layer 300b correspond to bonding surfaces. Furthermore, the bonding surface between the first substrate W1 and the second substrate W2 can also be constructed using the second or third embodiment.

[0306] [6-2] Circuit configuration of memory device 1c

[0307] Hereinafter, as variations of the circuit configuration of the memory device 1c, the first configuration example and the second configuration example of the sixth embodiment will be described in turn.

[0308] [6-2-1] First example of composition

[0309] Figure 47 This is a schematic diagram illustrating an example of the circuit configuration of the memory device in the first configuration example of the sixth embodiment. For example... Figure 47As shown, the memory device 1c of the first configuration example of the sixth embodiment includes, for example, four memory cell arrays 10-1 to 10-4 and four CMOS circuit sections CM1 to CM4. The memory cell arrays 10-1 to 10-4 are controlled by the CMOS circuit sections CM1 to CM4 respectively.

[0310] Each memory cell array 10 has, for example, a memory region MR and a lead-out region HR as described in the first embodiment. Each CMOS circuit section CM includes circuitry for controlling the associated memory cell array 10. Each CMOS circuit section CM includes at least a row decoder module 16 and a sense amplifier module 17. The configuration of CMOS circuitry other than the row decoder module 16 and the sense amplifier module 17 (sequencer 14, driver circuitry 15, etc.) can be appropriately changed according to the design of the memory device 1c.

[0311] In the first configuration example of the sixth embodiment, memory cell arrays 10-1 and 10-2 are disposed on the first memory layer 300a and arranged in the X direction. In the first configuration example of the sixth embodiment, memory cell arrays 10-3 and 10-4 are disposed on the second memory layer 300b and arranged in the X direction. In the first configuration example of the sixth embodiment, CMOS circuit units CM1 and CM2 are disposed on the second CMOS layer 200a and arranged in the X direction. In the first configuration example of the sixth embodiment, CMOS circuit units CM3 and CM4 are disposed on the first CMOS layer 100a and arranged in the X direction. In the first configuration example of the sixth embodiment, memory cell arrays 10-1 and 10-3 overlap with CMOS circuit units CM1 and CM3 in the Z direction. Similarly, memory cell arrays 10-2 and 10-4 overlap with CMOS circuit units CM2 and CM4 in the Z direction.

[0312] In the first configuration example of the sixth embodiment, the group of memory cell array 10-1 and CMOS circuit section CM1, and the group of memory cell array 10-2 and CMOS circuit section CM2 are respectively arranged adjacent to each other in the Z direction. On the other hand, the group of memory cell array 10-1 and CMOS circuit section CM1 is arranged between memory cell array 10-3 and CMOS circuit section CM3. Similarly, the group of memory cell array 10-2 and CMOS circuit section CM2 is arranged between memory cell array 10-4 and CMOS circuit section CM4.

[0313] [6-2-2] Second example of composition

[0314] Figure 48 This is a schematic diagram illustrating an example of the circuit configuration of a memory device according to the second configuration example of the sixth embodiment. For example... Figure 48As shown, the memory device 1c of the second configuration example of the sixth embodiment is the same as that of the first configuration example of the sixth embodiment, and includes four memory cell arrays 10-1 to 10-4 and four CMOS circuit sections CM1 to CM4.

[0315] In the second configuration example of the sixth embodiment, memory cell arrays 10-1 and 10-2 are disposed on the first memory layer 300a and arranged in the X direction. In the second configuration example of the sixth embodiment, memory cell arrays 10-3 and 10-4 are disposed on the second memory layer 300b and arranged in the X direction. In the second configuration example of the sixth embodiment, CMOS circuit units CM1 and CM2 are disposed on the first CMOS layer 100a and arranged in the X direction. CMOS circuit units CM3 and CM4 are disposed on the second CMOS layer 200a and arranged in the X direction. In the second configuration example of the sixth embodiment, memory cell arrays 10-1 and 10-3 overlap with CMOS circuit units CM1 and CM3 in the Z direction. Similarly, memory cell arrays 10-2 and 10-4 overlap with CMOS circuit units CM2 and CM4 in the Z direction.

[0316] In the second configuration example of the sixth embodiment, the CMOS circuit section CM3 is arranged between the memory cell array 10-1 and the CMOS circuit section CM1. Similarly, the CMOS circuit section CM4 is arranged between the memory cell array 10-2 and the CMOS circuit section CM2. Furthermore, in the second configuration example of the sixth embodiment, the memory cell array 10-1 is arranged between the memory cell array 10-3 and the CMOS circuit section CM3. Similarly, the memory cell array 10-2 is arranged between the memory cell array 10-4 and the CMOS circuit section CM4. That is, in the second configuration example of the sixth embodiment, the spacing between the associated memory cell array 10 and the CMOS circuit section CM along the Z direction is constant.

[0317] [6-2] Effects of the sixth implementation method

[0318] The memory device 1c according to the sixth embodiment, like the first embodiment, can reduce chip area and manufacturing cost. The effects of the sixth embodiment will be described in detail below.

[0319] Figure 49 This is a schematic diagram showing an example of the layout of the memory device 1 obtained by applying the fourth embodiment. Figure 49 (A) shows an example of the layout of the CMOS circuit section of the memory device 1 of the comparative example. Figure 49 (B) shows an example of the layout of the CMOS circuit section of the memory device 1 when the sixth embodiment is applied.

[0320] like Figure 49 As shown in (A), in the memory device 1 of the comparative example, two CMOS circuit sections CM1 and CM2 disposed on the same substrate form the remaining area TB. In the comparative example, the width in the X direction of the layout of the CMOS circuit sections CM1 and CM2 is LX4, and the width in the Y direction is LY5.

[0321] On the other hand, such as Figure 49 As shown in (B), the memory device 1c of the sixth embodiment arranges a portion of the peripheral circuit region PERI between two adjacent CMOS circuit sections CM1 and CM2. Specifically, the CMOS circuit section CM1 of the sixth embodiment has a peripheral circuit region PERIa in a manner that does not form a residual region TB. The CMOS circuit section CM2 of the sixth embodiment has a peripheral circuit region PERIa in a manner that does not form a residual region TB. Moreover, in the sixth embodiment, a peripheral circuit region PERIb is provided between the CMOS circuit sections CM1 and CM2. The CMOS circuits arranged in the peripheral circuit region PERIb include, for example, the circuits used in the CMOS circuit section CM1 and the circuits used by the CMOS circuit section CM2. In this case, in the sixth embodiment, the width in the X direction of the layout of the CMOS circuit sections CM1 and CM2 is LX5, which is wider than LX4, and the width in the Y direction is LY6, which is narrower than LY5.

[0322] Thus, compared to the comparative example, the width in the X direction of the sixth embodiment is wider, while the width in the Y direction is narrower. Furthermore, since the sixth embodiment can omit the remaining area TB, the area required for chip formation can be reduced compared to the comparative example.

[0323] Furthermore, the remaining area TB in the comparative example can also be used as a wiring area to connect circuits disposed on different substrates to each other. In the sixth embodiment, an example is shown where a memory cell array 10 or a CMOS circuit section CM corresponding to two planes PL is disposed on a single substrate, but this is not a limitation. The sixth embodiment can also involve disposing a memory cell array 10 or a CMOS circuit section CM corresponding to one plane PL or three or more planes PL on a single substrate. In the sixth embodiment, disposing a memory cell array 10 or a CMOS circuit section CM corresponding to a multiple of four planes PL on a single substrate is most efficient.

[0324] [7] Variations, etc.

[0325] The following describes variations of the memory device 1 described in the above embodiments. The above embodiments can also be combined in various ways. For example, the second embodiment can be combined with one of the fourth to sixth embodiments. The third embodiment can also be combined with one of the fourth to sixth embodiments.

[0326] Figure 50 This is a perspective view showing an example of the appearance of the memory device 1 in the first modified example. For example... Figure 50 As shown, the memory device 1 of the first modified example has a structure in which a first substrate W1, a first CMOS layer 100, a second substrate W2, a second CMOS layer 200, a memory layer 300, and a wiring layer 400 are stacked sequentially from bottom to top. Thus, the memory device 1 described in the first to third embodiments may also have a structure that omits the third substrate W3. That is, in each of the processes S16, S26, and S34, the third substrate W3 may be completely removed. Furthermore, the memory device 1 described in the first to third embodiments may have at least two substrates on which CMOS circuitry is formed, and at least one substrate on which the memory cell array 10 is formed. That is, the CMOS circuitry may be arranged across three or more substrates. The memory device 1 may also have multiple memory layers 300.

[0327] Figure 51 This is a perspective view showing an example of the appearance of the memory device 1c of the second modified example. For example... Figure 51 As shown, the memory device 1c of the second variation has a structure in which a first substrate W1, a first CMOS layer 100a, a second substrate W2, a second CMOS layer 200a, a memory layer 300a, a memory layer 300b, and a wiring layer 400 are stacked sequentially from bottom to top. Thus, the memory device 1c described in the sixth embodiment may also have a structure that omits the third substrate W3 and the fourth substrate W4. Furthermore, the memory device 1c described in the sixth embodiment only needs to have at least two substrates on which CMOS circuitry is formed and at least two substrates on which the memory cell array 10 is formed. That is, the memory device 1c may have three or more CMOS layers or three or more memory layers 300.

[0328] Figure 52 This is a cross-sectional view showing an example of the detailed cross-sectional structure of the joint of the bonding pad BP. Figure 52 The conductive layer 65 (bonding pad BP) of the second CMOS layer 200 and the conductive layer 26 (bonding pad BP) of the memory layer 300 are shown, along with a portion of the contacts and wiring connected to these bonding pads BP. Figure 52As shown, the two opposing bonding pads BP have different conical shapes based on the etching direction during formation. Specifically, the conductive layer 65 (bonding pad BP) formed using the second substrate W2 has, for example, an inverted conical shape. The conductive layer 26 (bonding pad BP) formed using the third substrate W3 has, for example, a conical shape. Since the bonding pads BP, which are formed inverted conical shapes, are bonded by reversing their orientation during the bonding process, they can be considered as conical shapes when referenced to the second substrate W2.

[0329] Furthermore, the two opposing bonding pads BP can be staggered and bonded according to the alignment during the bonding process. Therefore, a step difference can be formed between the upper surface of conductor layer 65 and the lower surface of conductor layer 26. The two opposing bonding pads BP can have a boundary or be integrated. The bonding pad BP and the contact connected to it can also be integrally formed. There can be multiple contacts connected to the bonding pad BP. For example, conductor layer 65 (bonding pad BP) can also be connected to conductor layer 64 via multiple contacts C8. Similarly, conductor layer 26 (bonding pad BP) can also be connected to conductor layer 25 via multiple contacts V1. Although not shown in the figures, the shapes of the two opposing bonding pads BP in other parts can also be formed similarly to conductor layers 65 and 26.

[0330] In the above embodiments, the circuit configuration, planar layout, and cross-sectional structure of the memory device 1 can be appropriately modified. For example, the semiconductor layer 41 of the memory pillar MP and the source line SL can be connected via the side of the memory pillar MP. The memory pillar MP can also have a structure in which two or more pillars are connected in the Z direction. The memory pillar MP can also have a structure in which pillars corresponding to the select gate line SGD and pillars corresponding to the word line WL are connected. Each contact can also be connected by multiple contacts connected in the Z direction. A conductive layer can also be inserted at the connection portion of the multiple contacts. The number of wiring layers and contacts provided by the memory device 1 can be appropriately modified.

[0331] In the accompanying drawings used for illustration in the above embodiments, the case where the storage columns MP have the same diameter in the Z direction is shown as an example, but it is not limited to this. The storage column MP may also have a conical shape, an inverted conical shape, or a bowed shape. Similarly, the slits SLT and SHE may also have a conical shape, an inverted conical shape, or a bowed shape, respectively. Similarly, each contact body may also have a conical shape, an inverted conical shape, or a bowed shape. The cross-sectional structure of the storage column MP and the contacts CC and C3 may be either circular or elliptical.

[0332] In the first embodiment, a memory layer 300 is provided above the first CMOS layer 100 and the second CMOS layer 200, but the first CMOS layer 100 and the second CMOS layer 200 may also be provided above the memory layer 300. In this case, for example, a wiring layer 400 (pad PD) is provided on the second CMOS layer 200. The memory device 1 of the first embodiment may also include multiple memory layers 300. The memory device 1c of the sixth embodiment may also include three or more CMOS layers and three or more memory layers. In the sixth embodiment, one or more memory cell arrays 10 may be configured in one memory layer 300. In the sixth embodiment, the number of groups of row decoder modules 16 and readout amplifier modules 17 in the CMOS layer can be changed according to the number of memory cell arrays 10 contained in the associated memory layer.

[0333] In this specification, "connection" means electrical connection, excluding the possibility of other components intervening therein. "Electrical connection" can also be via an insulator, provided it can operate in the same manner as an electrical connection. "Conical shape" indicates a shape that tapers as it moves away from the substrate serving as a reference. "Inverted conical shape" indicates a shape that widens as it moves away from the substrate serving as a reference. "Columnar" refers to a structure provided within a hole formed during the manufacturing process of memory device 1. "Diameter" refers to the inner diameter of a hole, etc., on a cross-section parallel to the surface of the substrate. "Width" refers, for example, to the width of a constituent element in the X or Y direction. "Semiconductor layer" can also be referred to as "conductive layer".

[0334] In this specification, "region" can also be considered as a configuration included by a substrate serving as a reference. For example, if the first substrate W1 is specified to include a storage region MR and a lead-out region HR, the storage region MR and the lead-out region HR are respectively associated with different regions above the first substrate W1. "Height" corresponds, for example, to the distance between the configuration of the object being measured and the first substrate W1 in the Z direction. Configurations other than the first substrate W1 can also be used as a reference for "height". "Planar position" indicates the position of a configuration element in a planar layout. "Top (planar) view" corresponds, for example, to viewing the first substrate W1 from the side of the second substrate W2.

[0335] [8] Seventh implementation method

[0336] In the seventh embodiment, the memory devices 1, 1a, 1b, and 1c described in the above embodiments are formed using two types of silicon wafers. The details of the seventh embodiment will be described below.

[0337] [8-1] Composition

[0338] As two types of silicon wafers in the seventh embodiment, a "first silicon wafer WAF1" and a "second silicon wafer WAF2" can be used respectively. Both the first silicon wafer WAF1 and the second silicon wafer WAF2 are single-crystal silicon wafers. Furthermore, in this specification, a "notch" is a portion provided corresponding to the crystal orientation of the silicon wafer and is used as a reference for the orientation of the substrate in a semiconductor manufacturing apparatus. For example, in photolithography, the exposure apparatus determines the exposure position based on the notch. Additionally, other structures such as an orientation plane can also be used as a reference for the orientation of the silicon wafer in a semiconductor manufacturing apparatus. The "silicon wafer" can also be referred to as a "silicon substrate" or simply a "substrate." Furthermore, in this specification, the extension direction of the channels of the PMOS transistor and the NMOS transistor is parallel to either the X-direction or the Y-direction.

[0339] Figure 53 This is a top view illustrating an example of the configuration of the first silicon wafer WAF1 used in the formation of memory devices 1, 1a, 1b, and 1c. (See attached image.) Figure 53 As shown, the Miller index of the face of the first silicon wafer WAF1 is (100). In other words, the face orientation of the first silicon wafer WAF1 is (100). In the first silicon wafer WAF1, the Miller index of the crystal orientation corresponding to the X and Y directions is <110>. In other words, in the first silicon wafer WAF1, the Miller index of the crystal orientation corresponding to the extension direction of the transistor channel is <110>. The first silicon wafer WAF1 has slots arranged corresponding to <110>. The first silicon wafer WAF1 can also be referred to as a "0-degree slot wafer".

[0340] Figure 54 This is a top view illustrating an example of the configuration of the second silicon wafer WAF2 used in the formation of memory devices 1, 1a, 1b, and 1c. (See attached image.) Figure 54 As shown, the Miller index of the face from which the second silicon wafer WAF2 is cut is the same as that of the first silicon wafer WAF1, which is (100). Furthermore, in the second silicon wafer WAF2, the Miller indices of the crystal orientations corresponding to the X and Y directions are <100>. In other words, in the second silicon wafer WAF2, the Miller index of the crystal orientation corresponding to the extension direction of the transistor channel is <100>. The second silicon wafer WAF2 has slots arranged corresponding to <100>. Because the second silicon wafer WAF2 has a configuration where slots are arranged in a portion rotated 45 degrees from the first silicon wafer WAF1, it can also be called a "45-degree slot wafer".

[0341] The Young's modulus of the first silicon wafer WAF1 is, for example, 170 GPa. On the other hand, the Young's modulus of the second silicon wafer WAF2 is, for example, 130 GPa. Thus, the Young's modulus of the second silicon wafer WAF2 is smaller than that of the first silicon wafer WAF1. That is, when the same structure is formed on the first silicon wafer WAF1 and the second silicon wafer WAF2, the warpage of the second silicon wafer WAF2 will be greater than that of the first silicon wafer WAF1.

[0342] In the memory device 1 of the above embodiment, silicon wafers with the same crystal orientation are used for each substrate (e.g., first substrate W1, second substrate W2, third substrate W3, and fourth substrate W4). Furthermore, in the memory device 1 of the above embodiment, at least one of the substrates used for forming the CMOS circuit uses a second silicon wafer WAF2. Specifically, for example, the first silicon wafer WAF1 is used as the first substrate W1, and the second silicon wafer WAF2 is used as the second substrate W2. The third substrate W3 may also use either the first silicon wafer WAF1 or the second silicon wafer WAF2. The fourth substrate W4 may also use either the first silicon wafer WAF1 or the second silicon wafer WAF2.

[0343] [8-2] Manufacturing method

[0344] Figure 55 This is a schematic diagram illustrating an example of a method for manufacturing the memory device 1 according to the seventh embodiment. Figure 55 (A) to (D) correspond to the process of bonding and thinning the semiconductor substrate in the manufacturing process of memory device 1, and the illustrations of the CMOS layer and the memory layer are omitted.

[0345] like Figure 55 As shown in (A), the first substrate W1 and the second substrate W2 are joined by aligning the positions of the slots of the first substrate W1 and the slots of the second substrate W2, thereby forming a first bonding substrate BW1. This process corresponds, for example, to... Figure 14 The processing of S12. In this example, a first silicon wafer WAF1 is used as the first substrate W1, and a second silicon wafer WAF2 is used as the second substrate W2.

[0346] Next, as Figure 55 As shown in (B), the second substrate W2 is thinned. This process corresponds, for example, to... Figure 14 The process of S13 is performed. As a result, the second substrate W2 becomes thinner than the first substrate W1.

[0347] Next, as Figure 55As shown in (C), the first bonding substrate BW1 and the third substrate W3 are joined by aligning the positions of the slots of the first bonding substrate BW1 and the slots of the third substrate W3, thereby forming the second bonding substrate BW2. This process corresponds, for example, to... Figure 14 The processing of S15. In this example, the first silicon wafer WAF1 is used as the third substrate W3.

[0348] Next, as Figure 55 As shown in (D), the third substrate W3 is thinned. This process corresponds, for example, to... Figure 14 The process of S16 is performed. As a result, the third substrate W3 becomes thinner than the first substrate W1.

[0349] Subsequently, the first substrate W1 can be thinned through subsequent processes. Furthermore, the first substrate W1, located at the bottom layer of the memory device 1, is retained to be thicker than other substrates in order to ensure the strength of the memory device 1.

[0350] Furthermore, the above description illustrates a case where the memory device 1 of the first embodiment is composed of multiple silicon wafers, but it is not limited to this. Similarly, in the second to sixth embodiments, the first substrate W1 and the second substrate W2 can also be composed of multiple silicon wafers.

[0351] [8-3] Effects of the seventh implementation method

[0352] To improve the performance of memory devices, it is desirable to enhance the characteristics of CMOS circuits. For example, the drive current of a PMOS transistor formed on a 45-degree slot wafer increases compared to that formed on a 0-degree slot wafer due to strain from both directions parallel and perpendicular to the channel. In other words, the performance of a PMOS transistor formed on a 45-degree slot wafer is improved compared to that formed on a 0-degree slot wafer. Therefore, a 45-degree slot wafer is preferred as the substrate for providing a CMOS circuit containing PMOS transistors.

[0353] However, because 45-degree slot wafers have a smaller Young's modulus compared to 0-degree slot wafers, controlling wafer warpage and achieving mass production in semiconductor manufacturing processes can become difficult. For example, when using 45-degree slot wafers, the XY difference in wafer warpage becomes larger. Consequently, they may not be able to be processed by semiconductor manufacturing equipment, i.e., mass production is not possible.

[0354] Therefore, in the seventh embodiment, in the memory device 1 having multiple substrates on which CMOS circuits are formed, at least one of the multiple substrates on which the CMOS circuits are formed uses a 45-degree notch wafer. For example, in the seventh embodiment, a 0-degree notch wafer is used as the first substrate W1, and a 45-degree notch wafer is used as the second substrate W2. In this case, the 45-degree notch wafer is, for example, produced by... Figure 14 The S13 process thins the wafer, making it thinner than a 0-degree slot wafer. That is, in the memory device 1 as a whole, the proportion of 0-degree slot wafers, which have a higher Young's modulus compared to 45-degree slot wafers, increases.

[0355] Therefore, the warpage caused by the 45-degree notch wafer is suppressed by the 0-degree notch wafer, and the overall warpage of memory device 1 can be suppressed. As a result, memory devices 1, 1a, 1b, and 1c using the seventh embodiment can improve the warpage characteristics of the wafer and can be mass-produced. Furthermore, memory devices 1, 1a, 1b, and 1c using the seventh embodiment can improve the performance of PMOS transistors by arranging PMOS transistors in the 45-degree notch wafer. Therefore, the seventh embodiment can achieve both improvement in wafer warpage characteristics and improvement in CMOS circuit characteristics.

[0356] Alternatively, NMOS transistors can be configured on the 45-degree slot wafer. At least one PMOS transistor (low-voltage PMOS transistor) that is desired to operate at high speed can be configured on the 45-degree slot wafer. In the CMOS circuit of the memory device 1, there are cases where the area ratio of NMOS transistors to PMOS transistors differs. For example, the area occupied by NMOS transistors is larger than that occupied by PMOS transistors. In this case, considering a circuit using PMOS transistors and a portion of a circuit using NMOS transistors configured on the 45-degree slot wafer, the remaining circuit using NMOS transistors is configured on the 0-degree slot wafer. Therefore, the area of ​​the CMOS circuit in the first substrate W1 and the area of ​​the CMOS circuit in the second substrate W2 can be designed to be approximately the same, thus suppressing the chip size of the memory device 1.

[0357] Furthermore, in the seventh configuration example combining the seventh and fourth embodiments, LV transistors are disposed on a 45-degree slot wafer, and HV transistors are disposed on a 0-degree slot wafer. Therefore, the combination of the seventh and fourth embodiments in the seventh configuration example allows for easier optimization of the performance requirements for the LV transistors and HV transistors, respectively. Furthermore, by separating the substrate forming the LV transistors from the substrate forming the HV transistors, parasitic capacitance caused by the contact CS in the LV transistors can be reduced. As a result, the combination of the seventh and fourth embodiments in the seventh configuration example improves the operational performance of the memory device 1.

[0358] In the seventh embodiment, a first silicon wafer WAF1 is described as being used as the first substrate W1 and a second silicon wafer WAF2 as the second substrate W2, but this is not a limitation. As long as warpage is not a problem in the manufacturing process of the memory device 1, the second silicon wafer WAF2 can be used on both the first substrate W1 and the second substrate W2. Alternatively, the second silicon wafer WAF2 can be used as the first substrate W1, and the first silicon wafer WAF1 can be used as the second substrate W2. By configuring the second silicon wafer WAF2 with CMOS circuitry including PMOS transistors, the performance of the PMOS transistors can be improved, thereby improving the performance of the memory devices.

[0359] In this specification, the warpage of the substrate (wafer) is expressed, for example, by the difference between the height of the outer periphery of the wafer and the height of the center of the wafer. The unit for measuring the warpage is, for example, micrometers (μm). The warpage can also be expressed as a marked distance from a three-point reference plane, based on a measurement of the height of the wafer's center. The warpage is, for example, set to be positive when above the three-point reference plane and negative when below it. The warpage can be measured, for example, by measuring the height of each coordinate of the wafer using a laser displacement meter, a confocal displacement meter, an electrostatic capacitive heterodyne interferometer, a Fizeau interferometer, etc., to calculate the wafer shape (warpage).

[0360] In this specification, a "high-voltage PMOS transistor," or "P-type HV transistor," is illustrated for example, as follows: the gate oxide film is 20 nm or more; P-type carriers are injected into the source / drain regions adjacent to the gate, and N-type carriers are injected into the channel region under the gate; applying a voltage to the gate reverses the channel region, thereby obtaining current. A "low-voltage PMOS transistor," or "P-type LV transistor," is illustrated for example, as follows: the threshold voltage is lower than that of a high-voltage PMOS transistor, for example, the gate oxide film is 10 nm or less; P-type carriers are injected into the source / drain regions adjacent to the gate, and N-type carriers are injected into the channel region under the gate; applying a voltage to the gate reverses the channel region, thereby obtaining current. A "high-voltage NMOS transistor," or "N-type HV transistor," is illustrated for example, as follows: the gate oxide film is 20 nm or more; N-type carriers are injected into the source / drain regions adjacent to the gate, and P-type carriers are injected into the channel region under the gate; applying a voltage to the gate reverses the channel region, thereby obtaining current. A “low-voltage NMOS transistor” or “N-type LV transistor” is a transistor with a lower threshold voltage than a high-voltage NMOS transistor, for example, with a gate oxide film of less than 10 nm. N-type carriers are injected into the source / drain region next to the gate, and P-type carriers are injected into the channel region under the gate. Applying a voltage to the gate causes the channel region to reverse, thereby obtaining current.

[0361] In addition, some or all of the above embodiments may also be described as follows, but are not limited to the following.

[0362] (Postscript 1)

[0363] A memory device includes: a first silicon substrate on which a first CMOS circuit is formed; a second silicon substrate disposed above the first silicon substrate and on which a second CMOS circuit is formed; and a first memory cell array disposed above the second silicon substrate, connected to the first CMOS circuit and the second CMOS circuit, and having a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate, wherein the group formed by the first silicon substrate and the second silicon substrate includes a third silicon substrate with a surface orientation of (100) and provided with a PMOS transistor, wherein the extension direction of the channel of the PMOS transistor is parallel to the crystal orientation <100> of the third silicon substrate.

[0364] (Postscript 2)

[0365] The memory device described in Appendix 1 comprises a first silicon substrate and a second silicon substrate, including a fourth silicon substrate with a surface orientation of (100) and provided with an NMOS transistor, wherein the extension direction of the channel of the NMOS transistor is provided parallel to the crystal orientation <110> of the fourth silicon substrate.

[0366] (Note 3)

[0367] As described in Appendix 2, in the memory device, the fourth silicon substrate corresponds to the first silicon substrate, and the third silicon substrate corresponds to the second silicon substrate.

[0368] (Postscript 4)

[0369] As described in Appendix 2, the aforementioned PMOS transistor is a low-voltage PMOS transistor.

[0370] (Note 5)

[0371] As described in Appendix 4, the NMOS transistors described above are high-voltage NMOS transistors.

[0372] While several embodiments of this application have been described, these embodiments are provided as examples and are not intended to limit the scope of the application. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the application. These embodiments and their variations are included within the scope and spirit of the application, and are also included within the scope of the technical solutions described in the claims and their equivalents.

Claims

1. A memory device, characterized in that, have: A first silicon substrate on which a first CMOS circuit is formed; A second silicon substrate is disposed above the first silicon substrate and a second CMOS circuit is formed thereon; and A first memory cell array is disposed above the second silicon substrate and connected to the first CMOS circuit and the second CMOS circuit, having a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate. The memory device also includes multiple line decoders classified into a first group and a second group. The first storage cell array has multiple data blocks that are respectively connected to the multiple row decoders. The first group of line decoders is contained within the first CMOS circuit. The second group of line decoders is contained in the second CMOS circuit.

2. A memory device, characterized in that, have: A first silicon substrate on which a first CMOS circuit is formed; A second silicon substrate is disposed above the first silicon substrate and a second CMOS circuit is formed thereon; and A first memory cell array is disposed above the second silicon substrate and connected to the first CMOS circuit and the second CMOS circuit, having a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate. The memory device also includes multiple line decoders. The first storage cell array has multiple data blocks that are respectively connected to the multiple row decoders. The multiple elements contained in the multiple line decoders are classified into a first element group and a second element group. The first component group is included in the first CMOS circuit. The second component group is included in the second CMOS circuit.

3. A memory device, characterized in that, have: A first silicon substrate on which a first CMOS circuit is formed; A second silicon substrate is disposed above the first silicon substrate and a second CMOS circuit is formed thereon; and A first memory cell array is disposed above the second silicon substrate and connected to the first CMOS circuit and the second CMOS circuit, having a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate. The memory device also includes multiple sense amplifiers classified into a first group and a second group. The first memory cell array has multiple bit lines that are respectively connected to the plurality of sense amplifiers. The first group of sense amplifiers is included in the first CMOS circuit. The second group of readout amplifiers is included in the second CMOS circuit.

4. A memory device, characterized in that, have: A first silicon substrate on which a first CMOS circuit is formed; A second silicon substrate is disposed above the first silicon substrate and a second CMOS circuit is formed thereon; and A first memory cell array is disposed above the second silicon substrate and connected to the first CMOS circuit and the second CMOS circuit, having a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate. The memory device also includes multiple sense amplifiers. The first memory cell array has multiple bit lines that are respectively connected to the plurality of sense amplifiers. The multiple elements contained in the plurality of sense amplifiers are classified into a third element group and a fourth element group. The third component group is included in the first CMOS circuit. The fourth element group is included in the second CMOS circuit.

5. A memory device, characterized in that, have: A first silicon substrate on which a first CMOS circuit is formed; A second silicon substrate is disposed above the first silicon substrate and a second CMOS circuit is formed thereon; and A first memory cell array is disposed above the second silicon substrate and connected to the first CMOS circuit and the second CMOS circuit, having a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate. The memory device also includes multiple row decoders and multiple readout amplifiers. The first memory cell array has multiple word lines connected to the multiple row decoders and multiple bit lines connected to the multiple sense amplifiers. The plurality of line decoders are contained in one of the first CMOS circuit and the second CMOS circuit. The plurality of sense amplifiers are included in the other of the first CMOS circuit and the second CMOS circuit.

6. A memory device, characterized in that, have: A first silicon substrate on which a first CMOS circuit is formed; A second silicon substrate is disposed above the first silicon substrate and a second CMOS circuit is formed thereon; and A first memory cell array is disposed above the second silicon substrate and connected to the first CMOS circuit and the second CMOS circuit, having a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate. One of the first CMOS circuit and the second CMOS circuit is composed of low-voltage transistors. The first CMOS circuit and the other of the second CMOS circuit are composed of high-voltage transistors with higher voltage withstand capability compared to the low-voltage transistors.

7. The memory device as claimed in any one of claims 1 to 6, characterized in that, It also features through-silicon vias that connect the first CMOS circuit to the second CMOS circuit, or connect the first CMOS circuit to the first memory cell array.

8. The memory device as claimed in claim 7, characterized in that, It also has: A first bonding layer between the first silicon substrate and the second silicon substrate; The first bonding metal contained in the first bonding layer; and Wiring of the first CMOS circuit disposed between the first bonding layer and the second silicon substrate and connected via the first bonding metal.

9. The memory device as claimed in claim 7, characterized in that, It also has: A first bonding layer between the first silicon substrate and the second silicon substrate; The wiring of the first CMOS circuit disposed between the first bonding layer and the first silicon substrate; and The first bonding metal contained in the first bonding layer The wiring is connected to the second CMOS circuit or the first memory cell array via the first bonding metal and the silicon via.

10. The memory device as claimed in claim 7, characterized in that, It also has: The second bonding layer between the second silicon substrate and the first memory cell array; and The second bonding metal contained in the second bonding layer, The first memory cell array is connected to the first CMOS circuit or the second CMOS circuit via the second bonding metal.

11. The memory device as claimed in claim 10, characterized in that, The second bonding metal has a first portion configured as an inverted cone shape and a second portion configured as a cone shape on the first portion.

12. The memory device as claimed in claim 6, characterized in that, It also features multiple line decoders and multiple readout amplifiers. The first memory cell array has multiple word lines connected to the multiple row decoders and multiple bit lines connected to the multiple sense amplifiers. The plurality of line decoders are contained in one of the first CMOS circuit and the second CMOS circuit. The plurality of sense amplifiers are included in the other of the first CMOS circuit and the second CMOS circuit. The first CMOS circuit and one of the second CMOS circuits include a plurality of first high-voltage transistors connected between the plurality of sense amplifiers and the plurality of bit lines.

13. The memory device as claimed in claim 6, characterized in that, The stacked structure of the gate electrode of the low-voltage transistor included in the first CMOS circuit is different from the stacked structure of the gate electrode of the high-voltage transistor included in the second CMOS circuit.

14. The memory device as claimed in claim 13, characterized in that, The gate electrode of the low-voltage transistor comprises nickel-platinum silicide. The gate electrode of the high-voltage transistor contains tungsten silicide or tungsten nitride.

15. The memory device as claimed in any one of claims 1 to 6, characterized in that, The first silicon substrate includes a first active region formed at a first spacing. The second silicon substrate includes a second active region formed at a second spacing different from the first spacing. The memory device includes a resistive element having at least one first active region and at least one second active region connected in series.

16. The memory device as claimed in any one of claims 1 to 6, characterized in that, The first CMOS circuit includes a plurality of first gate electrodes having a first gate width. The second CMOS circuit includes a plurality of second gate electrodes having a second gate width different from the first gate width. The memory device includes a resistive element having at least one first gate electrode and at least one second gate electrode connected in series.

17. The memory device as claimed in any one of claims 1 to 6, characterized in that, It also has: The first conductor and the second conductor are included in the layer on which the first CMOS circuit is formed and are arranged in parallel; and The third and fourth conductors are included in the layer on which the second CMOS circuit is formed and are arranged in parallel. The first conductor and the third conductor are connected via a first silicon via. The second conductor and the fourth conductor are connected via a second silicon via. The first conductor and the third conductor function as one electrode of the capacitor element. The second conductor and the fourth conductor function as the other electrode of the capacitor element.

18. The memory device as claimed in any one of claims 1 to 6, characterized in that, It also includes a second memory cell array positioned above the first memory cell array. The second CMOS circuit is used to control the first memory cell array. The first CMOS circuit is used to control the second memory cell array.

19. The memory device as claimed in any one of claims 1 to 6, characterized in that, It also includes a second memory cell array positioned above the first memory cell array. The first CMOS circuit is used to control the first memory cell array. The second CMOS circuit is used to control the second memory cell array.

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