A kind of based on laminated CrOCl auxiliary storage floating gate structure optoelectronic synapse device and preparation method

Abstract

The application discloses a kind of based on laminated CrOCl auxiliary storage's floating gate structure optoelectronic synapse device and preparation method, belong to semiconductor device technical field.Device includes by lower to upper sequentially arranged substrate, Gr nanosheet, CrOCl nanosheet, h-BN nanosheet and MoS2 Nanosheet, wherein, MoS2 Nanosheet two ends are connected with active electrode and drain electrode, Gr nanosheet, CrOCl nanosheet, h-BN nanosheet and MoS2 Nanosheet are combined by Van der Waals interaction;MoS2 / h-BN / CrOCl / Gr floating gate optoelectronic synapse device of the application can effectively increase double scanning storage window by the secondary adsorption electron capacity of CrOCl, widen multi-level storage capacity, can realize multi-level storage under the joint modulation of electric pulse and light pulse, show excellent electrical writing and optical erasing technology in photoelectric hybrid storage, in addition, under the common modulation of photoelectricity, show good synapse characteristics, including long-term plasticity, short-term plasticity, the recognition accuracy of neural network constructed by MoS2 / h-BN / CrOCl / Gr floating gate device of the application can reach 97% on direction identification data set.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and specifically to a floating gate structure opto-synaptic device based on stacked CrOCl-assisted storage and its fabrication method. Background Technology

[0002] With the deep integration of artificial intelligence and Internet of Things technologies, the global data volume is surging, posing severe challenges to the data processing and energy efficiency of traditional computing architectures. For a long time, the semiconductor industry has relied on the miniaturization of transistor size and the increase in integration to drive the growth of computing power. However, as process technology approaches below 1 nanometer, physical limits such as quantum effects make the development model of Moore's Law unsustainable.

[0003] To address this challenge, the academic community is primarily seeking breakthroughs in two areas: materials and architecture. In terms of materials, researchers are developing novel semiconductor channel materials to improve carrier mobility and gate controllability, expanding the scope for performance enhancements in post-Moore's Law devices. In terms of architecture, inspired by biological neural networks, in-memory computing architectures have emerged. These neuromorphic devices, by mimicking the working mechanisms of biological synapses and neurons, integrate storage and computation within a single unit, effectively overcoming the data transfer bottleneck of the von Neumann architecture and laying the hardware foundation for building high-efficiency edge intelligent systems and brain-like computing platforms.

[0004] Two-dimensional (2D) materials offer an ideal platform for constructing highly integrated, optoelectronically integrated neuromorphic devices due to their excellent electrical tunability, strong photo-matter interactions, and outstanding heterogeneous integration compatibility. Furthermore, the absence of dangling bonds on the surface of 2D materials, with layers naturally bonded by van der Waals forces, simplifies the stacking process compared to traditional silicon-based devices. However, existing floating gate structures based on 2D materials still face challenges in low-power operation, multi-level storage capabilities, and optoelectronic co-modulation, particularly in charge retention and expanding the storage window. Moreover, the limited storage window of traditional floating gate structures under gate voltage modulation restricts their application in neuromorphic computing.

[0005] Therefore, developing a floating gate structure opto-synaptic device with a larger storage window, better charge retention capability, and opto-co-modulation capability is of great research significance and application value. Summary of the Invention

[0006] Based on the above analysis, and addressing the problems of limited storage window and insufficient charge retention capacity in existing floating gate structures, this invention aims to provide a floating gate structure optoelectronic synaptic device and its fabrication method based on stacked CrOCl-assisted storage. By suspending Cl atoms on the surface of the CrOCl atomic structure, it exhibits strong electron adsorption properties, effectively maintaining the retention state of electrons in Gr after tunneling through the FFN effect. This allows low gate voltage signals to adjust the number of charge carriers in the MoS2 nanosheets and Gr nanosheets to regulate the storage state, maintaining a large storage window while ensuring data processing efficiency, and achieving multi-level storage under optoelectronic synergistic modulation.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution: This invention provides a photoelectric synaptic device based on a floating gate structure for stacked CrOCl-assisted storage, comprising a substrate, Gr (graphene) nanosheets, CrOCl (chromium oxychloride) nanosheets, h-BN (hexagonal boron nitride) nanosheets, and MoS2 (molybdenum disulfide) nanosheets arranged sequentially from bottom to top. The two ends of the MoS2 nanosheet are connected to an active electrode and a drain electrode, respectively; the Gr nanosheets, CrOCl nanosheets, h-BN nanosheets and MoS2 nanosheets are bonded together by van der Waals forces; the CrOCl nanosheets partially cover the Gr nanosheets, and the exposed part of the Gr surface is used to set an additional control electrode; the h-BN nanosheets cover the stacked region of the CrOCl nanosheets and Gr nanosheets.

[0008] Preferably, the substrate is a silicon substrate with a silicon dioxide insulating layer disposed on its surface.

[0009] Preferably, the source electrode, drain electrode, and additional control electrode are all metal electrodes made of Cr / Au multilayer metal, wherein the Cr layer has a thickness of 5–20 nm and the Au layer has a thickness of 40–80 nm.

[0010] As a preferred embodiment of the present invention, the thickness of the Gr nanosheets, CrOCl nanosheets, h-BN nanosheets, and MoS2 nanosheets is 4–20 nm.

[0011] Preferably, the MoS2 nanosheets are used as a photosensitive layer and an electron transport layer, the h-BN nanosheets and CrOCl nanosheets are used as a tunneling layer, the Gr nanosheets are used as an electron confinement layer, and the substrate is used as a back gate electrode.

[0012] This invention also provides a method for fabricating a photoelectric synaptic device based on a floating gate structure with stacked CrOCl-assisted storage, comprising the following steps: S1. Gr nanosheets, CrOCl nanosheets, h-BN nanosheets and MoS2 nanosheets were prepared by mechanical exfoliation. The substrate was ultrasonically cleaned and then dried. S2. Using a two-dimensional material transfer platform, Gr nanosheets are transferred to the substrate surface to prepare a Gr layer; CrOCl nanosheets are transferred onto Gr nanosheets to prepare a CrOCl / Gr stack; h-BN nanosheets are transferred onto the CrOCl / Gr stacked nanosheets to prepare an h-BN / CrOCl / Gr stack; MoS2 nanosheets are transferred onto the h-BN / CrOCl / Gr stack to prepare a MoS2 / h-BN / CrOCl / Gr floating gate structure. S3. Fabricate source electrode, drain electrode and additional control electrode on substrate, define electrode shape, and ensure that source electrode and drain electrode are not placed in direct contact with the underlying Gr nanosheet, and additional control electrode is placed on the part of Gr nanosheet not covered by CrOCl nanosheet and h-BN nanosheet.

[0013] Preferably, the dry transfer in step S2 uses polydimethylsiloxane (PDMS) assisted transfer, and the material adhesion is promoted by heating during the transfer process. The heating temperature is 90-100°C and the holding time is 5-10 minutes.

[0014] Preferably, in step S3, the electrode pattern is defined using ultraviolet lithography, electron beam lithography, or laser direct writing, and the source electrode, drain electrode, and additional control electrode are prepared by combining thermal evaporation, electron beam evaporation, and lift-off processes.

[0015] Preferably, the CrOCl nanosheets partially cover the Gr nanosheets during transfer to expose the Gr surface for additional control electrode placement; when the h-BN nanosheets are transferred onto the CrOCl / Gr stacked nanosheets, the h-BN nanosheets cover the CrOCl / Gr nanosheet stacked region.

[0016] Preferably, the substrate is ultrasonically cleaned with deionized water, acetone, and ethanol and then dried with nitrogen before use.

[0017] Compared with the prior art, the present invention can achieve the following beneficial effects: 1. Due to the strong electron adsorption capacity of CrOCl, the device of the present invention has excellent non-volatile storage performance under low control pulse modulation. After being erased / written by pulse gate control voltage (pulse width 1 s, pulse amplitude ±60 V), the retention time exceeds 1000 s, and more than 500 erase / write cycles can be completed.

[0018] 2. Thanks to the introduction of the CrOCl auxiliary storage layer, the device of the present invention can achieve multi-level storage through the joint modulation of electrical pulses and optical pulses, exhibiting excellent optical erasure and electrical writing characteristics in optoelectronic hybrid storage.

[0019] 3. The device of the present invention can simulate the short-term and long-term plasticity of biological synapses under photoelectric modulation, and has good biomimetic characteristics of synapses.

[0020] 4. The neural network constructed based on the device of this invention can achieve a recognition accuracy of 97% in the orientation recognition task, which verifies its application potential in neuromorphic computing.

[0021] 5. The MoS2 / h-BN / CrOCl / Gr floating gate device of the present invention has the characteristics of simple structure, low cost, high load capacity, high reliability and easy maintenance. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of the present invention; Figure 2 These are scanning electron microscope images of the present invention; Figure 3 This is a schematic diagram of the mechanism of the present invention; Figure 4 (a) is the time-varying current curve of the device of the present invention when the control voltage is ±60 V. Figure 4 (b) is the present invention after 500 erase / write cycles under control voltage ±60 V; Figure 5 (a) shows the double-sweep transfer curves of the present invention under different gate control voltages. Figure 5 (b) is a comparison of the switching ratio and storage window extracted from the dual-scan transfer curve of the present invention and the CrOCl-free device; Figure 6 (a) shows the multi-level current time-varying curves of the present invention under continuous 532nm laser pulses (pulse power 13.2 μW, pulse frequency 1 Hz). Figure 6 (b) is the multi-stage current time-varying curve of the present invention under gate control voltage (pulse width 0.1 s, pulse amplitude 8 V); Figure 7 (a) is a schematic diagram of the present invention simulating the nervous system to identify the direction of vehicle movement. Figure 7 (b) is the current spectrum based on time mapping according to the present invention. Figure 7 (c) is the accuracy curve of the neural network constructed in this invention for orientation recognition.

[0023] The meanings of the labels in the attached diagram are as follows: 1. Substrate; 2. Oxide insulating layer; 3. Gr nanosheets; 4. Additional control electrode; 5. CrOCl nanosheets; 6. h-BN nanosheets; 7. MoS2 nanosheets; 8. Drain electrode; 9. Source electrode. Detailed Implementation

[0024] The present application will now be described in further detail with reference to the accompanying drawings. It should be noted that the following specific embodiments are only used to further illustrate the present application and should not be construed as limiting the scope of protection of the present application. Those skilled in the art can make some non-essential improvements and adjustments to the present application based on the above application content.

[0025] Example 1 like Figures 1-3 As shown, a photoelectric synaptic device based on a floating gate structure for stacked CrOCl-assisted storage includes, from bottom to top: a substrate 1, an oxide insulating layer 2, a Gr nanosheet 3, an additional control electrode 4, a CrOCl nanosheet 5, an h-BN nanosheet 6, a MoS2 nanosheet 7, a metal drain electrode 8, and a metal source electrode 9. The CrOCl nanosheet 5 is located above the Gr nanosheet 3 and partially covers it. The h-BN nanosheet 6 is located above the CrOCl nanosheet 5 and covers it. The MoS2 nanosheet 7 is located above the h-BN nanosheet 6 and is perpendicularly overlapped with the h-BN nanosheet 6, the CrOCl nanosheet 5, and the Gr nanosheet 3.

[0026] A metal drain electrode 8 and a metal source electrode 9 are disposed above the MoS2 nanosheet 7. Both the metal drain electrode 8 and the metal source electrode 9 are placed above the overlapping area of ​​the Gr nanosheet 3, CrOCl nanosheet 5, h-BN nanosheet 6 and MoS2 nanosheet 7. The control electrode 4 is located in the non-overlapping part of the Gr nanosheet 3 and CrOCl nanosheet 5, which is used to improve the gate coupling ratio of the device.

[0027] MoS2 nanosheets 7 are used as a photosensitive layer and an electron transport layer, h-BN nanosheets 6 and CrOCl nanosheets 5 are used as tunneling layers, Gr nanosheets 3 are used as an electron confinement layer, and substrate 1 is used as a back gate electrode.

[0028] As a preferred embodiment, one or more of the Gr nanosheets 3, h-BN nanosheets 6, CrOCl nanosheets 5, and MoS2 nanosheets 7 can be replaced with other two-dimensional materials with similar photoelectric properties, such as WSe2, black phosphorus (BP), ReS2, WS2, etc.

[0029] In a preferred embodiment, the thicknesses of the Gr nanosheets 3, CrOCl nanosheets 5, h-BN nanosheets 6, and MoS2 nanosheets 7 are all 4–20 nm. Specifically, in this embodiment, the thicknesses are selected as follows: Gr nanosheet 3 is approximately 4 nm, CrOCl nanosheet 5 is approximately 5.2 nm, h-BN nanosheet 6 is approximately 8.81 nm, and MoS2 nanosheet 7 is approximately 4.7 nm. In a preferred embodiment, the source electrode 9, drain electrode 8, and additional control electrode 4 are all metal electrodes made of Cr / Au multilayer metal, wherein the Cr layer thickness is 5–20 nm and the Au layer thickness is 40–80 nm; in this embodiment, the Cr layer thickness is specifically chosen to be 10 nm and the Au layer thickness is 60 nm. As a preferred embodiment, in the stacked CrOCl-assisted storage floating gate structure photoelectric synapse device prepared in this embodiment, the substrate 1 is Si / SiO. 2。

[0030] Example 2 This embodiment corresponds to the preparation method described in claims 5-10, and the following detailed description is provided in conjunction with specific operation steps.

[0031] A method for fabricating a photoelectric synaptic device based on a floating gate structure with stacked CrOCl-assisted storage includes the following steps: Step 1: Gr (graphene) nanosheets 3 are obtained by mechanical exfoliation: Use tweezers to pick up an appropriate amount of graphene single crystal and place it on a white film tape. Use the blank tape area to repeatedly peel the Gr material 5-10 times. Stick the tape with the Gr material on it onto polydimethylsiloxane (PDMS), press it gently and let it stand for 5 minutes, then peel off the tape. Then observe the exfoliated Gr nanosheets 3 under an optical microscope and select Gr nanosheets 3 of appropriate thickness and size for later use.

[0032] Step 2: Using the same method as in Step 1, CrOCl (chromium oxychloride) nanosheets 5 are prepared by the adhesive force of the tape and adhered to the polydimethylsiloxane (PDMS) film. Taking advantage of the fact that the adhesive force between PDMS and CrOCl is greater than the van der Waals adsorption force between CrOCl layers, the CrOCl nanosheets 5 are peeled off onto the PDMS film for later use.

[0033] Step 3: Using the same method as in Step 1, h-BN (hexagonal boron nitride) nanosheets 6 are prepared by the adhesive force of the tape and adhered to the tape onto the polydimethylsiloxane (PDMS) film. Taking advantage of the fact that the adhesive force between PDMS and h-BN is greater than the adhesive force of the h-BN layer, the h-BN nanosheets 6 are peeled off onto the PDMS film for later use.

[0034] Step 4: Using the same method as in Step 1, prepare MoS2 (molybdenum disulfide) nanosheets by means of the adhesive force of the tape, and adhere them to the polydimethylsiloxane (PDMS) film. Taking advantage of the fact that the adhesive force between PDMS and MoS2 is greater than the interlayer adhesive force of MoS2, the MoS2 nanosheets are peeled off onto the PDMS film for later use.

[0035] Step 5: Take the cut silicon oxide wafer (1 cm × 1 cm) as substrate 1, immerse it in deionized water, acetone, ethanol and deionized water in sequence for ultrasonic cleaning for 10 min, and then dry it with a nitrogen gun for later use. Step 6: Attach the side of the polydimethylsiloxane (PDMS) without Gr nanosheets 3 to the upper surface of the glass slide. Place the glass slide with the PDMS side containing Gr nanosheets 3 facing down on the microscope-assisted two-dimensional material micro-area transfer platform. Place the prepared silicon oxide slide on the stage, align the Gr nanosheets 3 with the silicon oxide slide, and slowly rotate the knob while continuously adjusting their positions to bring them closer together. When the Gr nanosheets 3 adhere to the silicon wafer surface under the same field of view, heat the substrate to approximately 95 °C and wait for about 10 minutes. Lift the glass slide and raise the PDMS film to obtain the Gr nanosheets 3 on the silicon substrate 1. Step 7: Using the method in Step 6, CrOCl nanosheets 5 and Gr nanosheets 3 are tightly bonded together to obtain a CrOCl / Gr stacked structure; Step 8: Using the method in Step 6, h-BN nanosheets 6 are tightly bonded to CrOCl / Gr stacked nanosheets to obtain the h-BN / CrOCl / Gr stacked structure; Step 9: Using the method in Step 6, tightly bond the MoS2 nanosheets to the h-BN / CrOCl / Gr stacked structure to obtain the MoS2 / h-BN / CrOCl / Gr floating gate structure; Step 10: Spin-coat the above-prepared floating gate structure with polymethyl methacrylate (PMMA) photoresist using a spin coater and heat at 130 °C for 3 minutes; design the source, drain, and control electrode patterns using CAD Design 3d Max software; and use an electron beam exposure system to precisely position and expose the electrode patterns, followed by development and fixing; Step 11: Deposit 10 nm Cr and 60 nm Au using thermal evaporation, then immerse in acetone at 65 °C for 1 hour to remove the unexposed portions. Dry with a nitrogen gun to fabricate the source, drain, and control electrodes, constructing a MoS2 / h-BN / CrOCl / Gr floating gate structure photoelectric synaptic device. Figure 2 As shown.

[0036] The working mechanism of this example is as follows: Figure 3As shown, when a positive control voltage is applied, the conduction band bottom of the MoS2 channel forms a tilted band structure with the tunneling barriers of h-BN and CrOCl (left and middle figures). At this time, electrons penetrate the h-BN and CrOCl barriers through the Fowler-Nordheim tunneling mechanism and are captured in the Gr floating gate layer, causing Gr to form electron doping. Since the Cl atoms on the surface of the CrOCl material are suspended, electrons can be pulled and adsorbed on the basis of tunneling, so as to quickly deplete the channel electrons. Due to the zero band gap and half-metallic state of Gr, high-density charge storage can be achieved. The carrier concentration of the MoS2 channel is depleted due to the separation of electrons and holes caused by the positive gate voltage, and its Fermi level shifts down, resulting in an increase in channel resistivity of 2-3 orders of magnitude. By adjusting the control pulse amplitude and pulse width, the threshold voltage offset can be precisely controlled.

[0037] Under 532 nm laser irradiation (right figure), a high concentration of electron-hole pairs is generated in the MoS2 channel. Photogenerated holes and electrons migrate along a specific crystal orientation to the h-BN interface. Holes are neutralized by electrons pulled by Cl atoms on the CrOCl layer surface, causing a change in the carrier concentration in the MoS2 channel. Subsequently, photogenerated electrons tunnel through the h-BN dielectric and CrOCl insulating layer and neutralize the holes stored in the Gr floating gate layer, causing a change in the charge concentration in the MoS2 channel.

[0038] The device current holding capability in this example Figure 4 As shown, Figure 4 As shown in (a), after a 60 V programming gate voltage with a pulse width of 1 s and a −60 V erasing gate voltage, the current remains level when the bias voltage is 1 V and the gate voltage is 0 V for reading. The device's on / off ratio is still greater than 10 after 1000 s. 4 , Figure 4 (b) shows the device's current cycle level after 500 cycles at a bias voltage of 1 V and a gate voltage of 0 V, following a pulse width of 200 ms, a programming gate voltage of 60 V and an erasing gate voltage of −60 V.

[0039] Figure 5 (a) shows the device double-sweep transfer curves of this example under different gate voltages. Figure 5 (b) shows the curves of the storage window and the device switching ratio with and without CrOCl device in this example. It can be seen that the MoS2 / h-BN / CrOCl / Gr floating gate structure has a larger switching ratio and storage window.

[0040] Figure 6 (a) shows the multi-level time-varying current curves of this example under continuous 532nm laser pulses (pulse power 13.2 μW, pulse frequency 1 Hz). Figure 6(b) shows the multi-level current time-varying curve of the present invention under gate control voltage (pulse width 0.1 s, pulse amplitude 8 V). The device shows good multi-level storage capability under continuous optical / electric pulse modulation.

[0041] Based on the device's excellent multi-level storage capability, a vehicle motion direction recognition system based on a floating gate structure photoelectric synapse was constructed. Figure 7 As shown in (a), the right-hand vehicle video is extracted from the database video, and the extracted 4 frames of image pixels are mapped to the light pulse current value to obtain feature values. A three-layer RC model is used to perform convolution operation and learn. Figure 7 (b) shows the current magnitude spectrum of the device after mapping the optical pulse current values ​​of four frames. Figure 7 (c) is the accuracy curve of the device for recognizing the movement of the vehicle in five directions after 200 cycles, with an accuracy of up to 97%.

[0042] The above-described working mechanism enables the device of the present invention to achieve multi-level storage and synaptic plasticity simulation under the joint modulation of electrical pulses and optical pulses, providing a hardware foundation for neuromorphic computing.

[0043] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A photoelectric synaptic device based on a floating gate structure with stacked CrOCl-assisted storage, characterized in that, The substrate consists of a substrate (1), Gr nanosheets (3), CrOCl nanosheets (5), h-BN nanosheets (6) and MoS2 nanosheets (7) arranged from bottom to top. The two ends of the MoS2 nanosheet (7) are connected to the active electrode (9) and the drain electrode (8), respectively; the Gr nanosheet (3), CrOCl nanosheet (5), h-BN nanosheet (6) and MoS2 nanosheet (7) are bonded together by van der Waals forces; the CrOCl nanosheet (5) partially covers the Gr nanosheet (3), and the exposed part of the Gr surface is used to set an additional control electrode (4); the h-BN nanosheet (6) covers the stacked region of the CrOCl nanosheet (5) and the Gr nanosheet (3).

2. The photoelectric synaptic device based on a floating gate structure with stacked CrOCl-assisted storage according to claim 1, characterized in that, The substrate (1) is a silicon substrate with a silicon dioxide insulating layer on its surface.

3. The photoelectric synaptic device based on a floating gate structure with stacked CrOCl-assisted storage according to claim 1, characterized in that, The source electrode (9), drain electrode (8) and additional control electrode (4) are all metal electrodes made of Cr / Au multilayer metal, wherein the thickness of the Cr layer is 5-20 nm and the thickness of the Au layer is 40-80 nm.

4. The photoelectric synaptic device based on a floating gate structure with stacked CrOCl-assisted storage according to claim 1, characterized in that, The thicknesses of the Gr nanosheets (3), CrOCl nanosheets (5), h-BN nanosheets (6), and MoS2 nanosheets (7) are all 4–20 nm.

5. A method for fabricating a photoelectric synaptic device based on a floating gate structure with stacked CrOCl-assisted storage as described in any one of claims 1-4, characterized in that, Includes the following steps: S1. Gr nanosheets (3), CrOCl nanosheets (5), h-BN nanosheets (6) and MoS2 nanosheets (7) were prepared by mechanical exfoliation. The substrate was ultrasonically cleaned and dried. S2. Using a two-dimensional material transfer platform, Gr nanosheets (3) are transferred to the surface of substrate (1) to prepare a Gr layer; CrOCl nanosheets (5) are transferred to Gr nanosheets (3) to prepare a CrOCl / Gr stack; h-BN nanosheets (6) are transferred to the CrOCl / Gr stack nanosheets to prepare an h-BN / CrOCl / Gr stack; MoS2 nanosheets are transferred to the h-BN / CrOCl / Gr stack to prepare a MoS2 / h-BN / CrOCl / Gr floating gate structure. S3. Prepare a source electrode (9), a drain electrode (8) and an additional control electrode (4) on a substrate (1), define the electrode shape, and ensure that the source electrode (9) and the drain electrode (8) are placed in a position that does not directly contact the underlying Gr nanosheet (3), and place the additional control electrode (4) on the part of the Gr nanosheet (3) that is not covered by the CrOCl nanosheet (5) and the h-BN nanosheet (6).

6. The preparation method according to claim 5, characterized in that, The dry transfer method described in step S2 uses polydimethylsiloxane-assisted transfer, and heating is used during the transfer process to promote material adhesion.

7. The preparation method according to claim 6, characterized in that, The heating temperature is 90-100℃, and the holding time is 5-10 minutes.

8. The preparation method according to claim 5, characterized in that, In step S3, the electrode pattern is defined using ultraviolet lithography, electron beam lithography, or laser direct writing, and the source electrode, drain electrode, and additional control electrode are prepared by combining thermal evaporation, electron beam evaporation, and lift-off processes.

9. The preparation method according to claim 5, characterized in that, The CrOCl nanosheet (5) partially covers the Gr nanosheet (3) during transfer to expose the Gr surface for setting of additional control electrodes (4); when the h-BN nanosheet (6) is transferred to the CrOCl / Gr stacked nanosheet, the h-BN nanosheet (6) covers the CrOCl / Gr nanosheet stacked region.

10. The preparation method according to claim 5, characterized in that, The substrate (1) is ultrasonically cleaned with deionized water, acetone, and ethanol and dried with nitrogen before use.

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