A circuit structure with power-off isolation protection function

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a circuit structure with power-off isolation protection function, which comprises a control signal generating circuit, a port device and a power-off monitoring circuit; the control signal generating circuit is used for controlling the conduction and disconnection of the port device after processing the input control signal; the port device is controlled by the control signal CP to transmit signals between PIN1 and PIN2 ports or make the port device in a disconnected state; the power-off monitoring circuit is used for monitoring the power-off condition of the source voltage VDD, making the gate control signal CP potential and the substrate potential of the port device follow the highest potential in PIN1 and PIN2, and ensuring that the port device is in a cut-off state without electricity leakage to realize power-off isolation protection. The application can reduce the power consumption of a system using a multi-chip backup mode, and protect the chip itself from damage in the case of abnormal power-off of the integrated circuit chip.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a circuit structure with power-off isolation protection function. Background Technology

[0002] With the rapid development of electronic information systems and integrated circuits, modern electronic information systems place increasingly higher demands on low power consumption and the reliability of integrated circuit chips. Regarding low power consumption, modern electronic information systems typically employ a multi-chip backup approach for critical integrated circuit chips to improve system reliability. However, to further reduce system power consumption, the backup integrated circuit chip must be powered off while other ports can still receive signals. This necessitates that the integrated circuit chip possess both power-off isolation and power-off protection functions. Integrated circuit chips with power-off isolation and protection functions can effectively protect themselves from damage in the event of an abnormal power outage, thus improving the reliability of the integrated circuit chip.

[0003] Conventional integrated circuit chips that lack power-off isolation protection will experience the following consequences if a signal is applied to their ports during a power outage: Figure 1 When the source or drain PN junction of the port device shown is forward-biased, it generates an abnormally large current. This abnormally large current can cause crosstalk between signals, or even burn out the port device and cause the integrated circuit chip to malfunction.

[0004] In summary, conventional integrated circuit chips without power-off isolation protection cannot meet the high reliability and low power consumption requirements of systems employing multi-chip backup. Furthermore, an abnormal power outage can cause irreversible damage to the integrated circuit chip. Therefore, integrated circuit chips need to have power-off isolation protection to meet these requirements. Summary of the Invention

[0005] To solve the above-mentioned technical problems, the present invention proposes a circuit structure with power failure isolation protection function, including: a control signal generation circuit, port devices and a power failure monitoring circuit;

[0006] The control signal generation circuit is used to process the control signal IN to generate control signals CP and IN+, which respectively control the on / off state of the port device and the MOS transistor P10 in the power-off monitoring circuit.

[0007] Under the control of the gate signal CP, the port device transmits the signal from the PIN1 port to the PIN2 port or the signal from the PIN2 port to the PIN1 port, or keeps the PIN1 port and the PIN2 port in a high-impedance state, i.e., the port device is in an open state.

[0008] The power failure monitoring circuit is used to ensure that the substrate potential P_bulk of devices P4, P6, P7, P8, P9, and P10 follows the highest potential among the three signals VDD, PIN1, and PIN2. This ensures that the source-substrate PN and drain-substrate PN junctions of devices P4, P6, P7, P8, P9, and P10 are in a reverse-biased cutoff state. At the same time, when VDD is detected to be de-energized, the circuit can make the gate control signal CP potential and substrate potential of the port devices follow the highest potential among PIN1 and PIN2, ensuring that the port devices are in a shut-off and non-leakage state to achieve power failure isolation protection.

[0009] Preferably, the control signal generation circuit includes MOS transistors P1, P2, P3, P4, P5, N1, N2, N3, N4, and N5;

[0010] P1 is connected to the gate of N1 to receive the control signal IN. The source of P1 is connected to its substrate and connected to the power supply VDD. The source of N1 is connected to its substrate and grounded. P1 is connected to the drain of N1 and interconnected with the gates of P2 and N2. The source of P2 is connected to its substrate and connected to the power supply VDD. The source of N2 is connected to its substrate and grounded. The connection between the drains of P2 and N2 generates the control signal IN+ and interconnected with the gates of P3 and N3. The source of P3 is connected to its substrate and connected to the power supply VDD. N3's... The source is connected to its substrate and grounded. The drains of P3 and N3 are connected together and interconnected with the drains of P4 and N4. The gate of N4 is connected to the power supply VDD. The substrate of N4 is grounded. The gate of P4 is interconnected with the drains of N5 and P5. The source of P4 and N4 is connected to output signal CP. The substrate of P4 is connected to potential P_bulk. The gates of N5 and P5 are connected and connected to the power supply VDD. The source of N5 is connected to its substrate and grounded. The source of P5 is connected to its substrate and connected to the signal CP, port devices, and power failure monitoring circuit.

[0011] Preferably, the power failure monitoring circuit includes MOSFETs P6, P7, P8, P9, and P10, and diodes D1, D2, and D3;

[0012] The gates of P6 and P7 are connected to the power supply VDD. The source of P6 is connected to the potential PIN1, and the source of P7 is connected to the potential PIN2. The drain of P6 is connected to the source of P8 and the positive terminal of diode D2. The negative terminal of diode D2 is connected to the negative terminal of diode D3, the drain of P8, the drain of P9, and the source of P10. The drain of P7 is connected to the positive terminal of diode D3 and the source of P9. The gate of P9 is connected to the potential PIN1, and the gate of P8 is connected to the potential PIN2. The gate of P10 is connected to the control signal IN+ generated by the control signal generation circuit. The drain of P10 is connected to the port device. The positive terminal of diode D1 is connected to the power supply VDD, and the negative terminal of diode D1 generates a substrate potential P_bulk equivalent to the potential of the power supply VDD on the substrate of the MOS transistor.

[0013] Preferably, the port device includes a MOS transistor P11;

[0014] The gate of P11 receives the control signal CP, the drain is connected to PIN1, the source is connected to PIN2, and the substrate is connected to the drain of P10 in the power failure monitoring circuit.

[0015] This invention provides a circuit structure with power-off isolation protection. When powered on, the control signal IN, after being processed by the control signal generation circuit, controls the on / off state of the switching port device P11. In the power-off monitoring circuit, diode D1 generates a substrate potential P_bulk equivalent to VDD. When the power supply VDD is de-energized, P1, P2, P3, P4, N1, N2, N3, N4, and N5 in the control signal generation circuit are all in the off state, while P5 is in the on state. In the power-off monitoring circuit, P6 and P7 are in the on state, and P8... One chip in P9 is on, and another is on. Simultaneously, the state of D2 follows that of P8, and the state of D3 follows that of P9. P10 is on, D1 is reverse-cut off, and P11 is off. This ensures there are no leakage current paths between signal ports PIN1 and PIN2, PIN1 and VDD, and PIN2 and VDD, putting the entire circuit in a power-down isolation protection state. This reduces power consumption in systems using multi-chip backup and protects the integrated circuit chip from damage in the event of an abnormal power outage, thus improving system reliability. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a circuit structure with power failure isolation protection function according to the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] A circuit structure with power failure isolation protection function, such as Figure 1 As shown, it includes: a control signal generation circuit, port devices, and a power failure monitoring circuit;

[0019] The control signal generation circuit processes the control signal IN to generate control signals CP and IN+, which respectively control the on / off state of the port devices and the MOS transistor P10 in the power-off monitoring circuit.

[0020] Under the control of the gate signal CP, the port device transmits the signal from the PIN1 port to the PIN2 port or the signal from the PIN2 port to the PIN1 port, or keeps the PIN1 port and the PIN2 port in a high-impedance state, i.e., the port device is in an open state.

[0021] The power failure monitoring circuit is used to ensure that the substrate potential P_bulk of devices P4, P6, P7, P8, P9, and P10 follows the highest potential among the three signals VDD, PIN1, and PIN2. This ensures that the source-substrate PN and drain-substrate PN junctions of devices P4, P6, P7, P8, P9, and P10 are in a reverse-biased cutoff state. At the same time, when VDD is detected to be de-energized, the circuit can make the gate control signal CP potential and substrate potential of the port devices follow the highest potential among PIN1 and PIN2, ensuring that the port devices are in a shut-off and non-leakage state to achieve power failure isolation protection.

[0022] In this embodiment, the control signal generation circuit includes MOS transistors P1, P2, P3, P4, P5, N1, N2, N3, N4, and N5;

[0023] P1 is connected to the gate of N1 to receive the control signal IN. The source of P1 is connected to its substrate and connected to the power supply VDD. The source of N1 is connected to its substrate and grounded. P1 is connected to the drain of N1 and interconnected with the gates of P2 and N2. The source of P2 is connected to its substrate and connected to the power supply VDD. The source of N2 is connected to its substrate and grounded. The connection between the drains of P2 and N2 generates the control signal IN+ and interconnected with the gates of P3 and N3. The source of P3 is connected to its substrate and connected to the power supply VDD. N3's... The source is connected to its substrate and grounded. The drains of P3 and N3 are connected together and interconnected with the drains of P4 and N4. The gate of N4 is connected to the power supply VDD. The substrate of N4 is grounded. The gate of P4 is interconnected with the drains of N5 and P5. The source of P4 and N4 is connected to output signal CP. The substrate of P4 is connected to potential P_bulk. The gates of N5 and P5 are connected and connected to the power supply VDD. The source of N5 is connected to its substrate and grounded. The source of P5 is connected to its substrate and connected to the signal CP, port devices, and power failure monitoring circuit.

[0024] In this embodiment, the power failure monitoring circuit includes MOSFETs P6, P7, P8, P9, and P10, and diodes D1, D2, and D3.

[0025] The gates of P6 and P7 are connected to the power supply VDD. The source of P6 is connected to the potential PIN1, and the source of P7 is connected to the potential PIN2. The drain of P6 is connected to the source of P8 and the positive terminal of diode D2. The negative terminal of diode D2 is connected to the negative terminal of diode D3, the drain of P8, the drain of P9, and the source of P10. The drain of P7 is connected to the positive terminal of diode D3 and the source of P9. The gate of P9 is connected to the potential PIN1, and the gate of P8 is connected to the potential PIN2. The gate of P10 is connected to the control signal IN+ generated by the control signal generation circuit. The drain of P10 is connected to the port device. The positive terminal of diode D1 is connected to the power supply VDD, and the negative terminal of diode D1 generates a substrate potential P_bulk equivalent to the potential of the power supply VDD on the substrate of the MOS transistor.

[0026] In this embodiment, the port device includes a MOS transistor P11;

[0027] The gate of P11 receives the control signal CP, the drain is connected to PIN1, the source is connected to PIN2, and the substrate is connected to the drain of P10 in the power failure monitoring circuit.

[0028] Power outage isolation protection principle:

[0029] When the circuit is powered on normally, MOSFETs P4, N4, and N5 in the control signal generation circuit are always on, while P5 is always off. In the power-off monitoring circuit, P6, P7, P8, and P9 are always off, D2 and D3 are reverse-biased off, and D1 is forward-biased, generating a substrate potential P_bulk equivalent to VDD. At this time, the control signal IN, after being processed by the control signal generation circuit, generates the gate control signal CP for the control port device P11 and the gate signal IN+ for the control port device P10, thereby controlling the on and off states of P10 and P11.

[0030] When the circuit is powered off, P1, P2, P3, P4, N1, N2, N3, N4, and N5 in the control signal generation circuit are all in the off state, and P5 is in the on state; P6 and P7 in the power failure monitoring circuit are in the on state; and the potential of the control signal IN+ is 0.

[0031] Assume that the potential of port signal PIN1 is higher than that of port signal PIN2, i.e., V PIN1 >V PIN2 At this time, since the source-substrate equivalent diode of P6 is in a forward bias state, it will generate a substrate potential P_bulk equivalent to the potential of PIN1, i.e., V. P_bulk ≈V PIN1 Therefore, diode D1 is in reverse-biased cutoff state. Diodes D2 and D3 in the power-off monitoring circuit are fast-response diodes, ensuring that the control signal CP can quickly follow the highest potential in port signals PIN1 and PIN2. At this time, because V... PIN1 >V PIN2 And since the diode has a voltage drop, V CP ≈V PIN1 For P8 devices, their V S =V PIN1 >V G =V PIN2 Therefore, P8 is in the ON state; for device P9, its V S =V PIN2 <V G =V PIN1 Therefore, P9 is in the off state. The activation of P8 ensures that V... CP =V PIN1 Because of V IN+ =0, therefore P10 is in the on state. Thus, for port device P11, its V G =V B =V PIN1 Meanwhile, V GSA value of ≥0 ensures that the circuit is completely shut down. This eliminates leakage current paths between pins PIN1 and PIN2, between pin1 and VDD, and between pin2 and VDD, keeping the entire circuit in a power-off isolation protection state. This reduces power consumption in systems using multi-chip backup and protects the integrated circuit chip from damage in the event of an abnormal power outage, thus improving system reliability.

[0032] Similarly, when the potential of port signal PIN1 is lower than that of port signal PIN2, i.e., V PIN1 <V PIN2 In this way, there can be no leakage current path between PIN1 and PIN2, PIN1 and VDD, and PIN2 and VDD, so that the entire circuit is in a power-off isolation protection state, thereby reducing the power consumption of the system using the multi-chip backup method. At the same time, it protects the chip itself from damage in the event of abnormal power failure of the integrated circuit chip, thereby improving the reliability of the system.

[0033] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A circuit structure with power failure isolation protection function, characterized in that, include: Control signal generation circuit, port devices, and power failure monitoring circuit; The control signal generation circuit is used to process the control signal IN to generate control signals CP and IN+, which respectively control the on / off state of the port device and the MOS transistor P10 in the power-off monitoring circuit. Under the control of the gate signal CP, the port device transmits the signal from the PIN1 port to the PIN2 port or the signal from the PIN2 port to the PIN1 port, or keeps the PIN1 port and the PIN2 port in a high-impedance state, i.e., the port device is in an open state. The power failure monitoring circuit is used to ensure that the substrate potential P_bulk of devices P4, P6, P7, P8, P9, and P10 follows the highest potential among the three signals VDD, PIN1, and PIN2, so as to ensure that the source-substrate PN and drain-substrate PN junctions of devices P4, P6, P7, P8, P9, and P10 are in a reverse-biased cutoff state. At the same time, when VDD is detected to be de-energized, the gate control signal CP potential and substrate potential of the port device follow the highest potential among PIN1 and PIN2, so as to ensure that the port device is in a turn-off cutoff state without leakage current, thereby achieving power failure isolation protection. The control signal generation circuit includes MOS transistors P1, P2, P3, P4, P5, N1, N2, N3, N4, and N5; P1 is connected to the gate of N1 to receive the control signal IN. The source of P1 is connected to its substrate and connected to the power supply VDD. The source of N1 is connected to its substrate and grounded. P1 is connected to the drain of N1 and interconnected with the gates of P2 and N2. The source of P2 is connected to its substrate and connected to the power supply VDD. The source of N2 is connected to its substrate and grounded. The connection between the drains of P2 and N2 generates the control signal IN+ and interconnected with the gates of P3 and N3. The source of P3 is connected to its substrate and connected to the power supply VDD. N3's... The source is connected to its substrate and grounded. The drains of P3 and N3 are connected together and interconnected with the drains of P4 and N4. The gate of N4 is connected to the power supply VDD. The substrate of N4 is grounded. The gate of P4 is connected to the drains of N5 and P5. The source of P4 and N4 is connected to output signal CP. The substrate of P4 is connected to potential P_bulk. The gates of N5 and P5 are connected and connected to the power supply VDD. The source of N5 is connected to its substrate and grounded. The source of P5 is connected to its substrate and connected to the signal CP, port devices, and power failure monitoring circuit. The power failure monitoring circuit includes MOSFETs P6, P7, P8, P9, and P10, and diodes D1, D2, and D3. The gates of P6 and P7 are connected and connected to the power supply VDD. The source of P6 is connected to the potential PIN1, and the source of P7 is connected to the potential PIN2. The drain of P6 is connected to the source of P8 and the positive terminal of diode D2. The negative terminal of diode D2 is connected to the negative terminal of diode D3, the drain of P8, the drain of P9, and the source of P10. The drain of P7 is connected to the positive terminal of diode D3 and the source of P9. The gate of P9 is connected to the potential PIN1, and the gate of P8 is connected to the potential PIN2. The gate of P10 is connected to the control signal IN+ generated by the control signal generation circuit. The drain of P10 is connected to the port device. The positive terminal of diode D1 is connected to the power supply VDD. Through the negative terminal of diode D1, a substrate potential P_bulk equivalent to the potential of the power supply VDD is generated on the substrate of the MOS transistor. The port device includes a MOSFET P11; The gate of P11 receives the control signal CP, the drain is connected to PIN1, the source is connected to PIN2, and the substrate is connected to the drain of P10 in the power failure monitoring circuit.

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