Pixel design with reduced lofic reset and settling time

Abstract

Disclosed herein are pixel designs with reduced LOFIC reset and settling time. In one embodiment, a pixel cell includes a photosensor configured to photo generate image charge in response to incident light, a floating diffusion region for receiving the image charge from the photosensor, a transfer transistor coupled between the floating diffusion region and the photosensor to transfer the image charge to the floating diffusion region, and a first reset transistor coupled between the floating diffusion and a voltage source. The pixel cell further includes a capacitor having two terminals and a second reset transistor. A first terminal of the capacitor is coupled to the floating diffusion region. The second reset transistor is coupled between a second terminal of the capacitor and the voltage source.

Description

Technical Field

[0001] This disclosure generally relates to image sensors. For example, several embodiments of the present technology relate to pixel units with lateral overflow integrating capacitors (LOFICs), including pixel units with LOFIC auto-zeroing capability to reduce LOFIC reset and settling time. Background Technology

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, surveillance cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a desire to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through device architecture design and image acquisition and processing.

[0003] A typical image sensor operates in response to incident image light from an external scene. The image sensor includes a pixel array with photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate an image charge upon absorption. The image charge generated by the pixel light can be measured as an analog output image signal on a bit line that varies according to the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, and this image charge is read out as an analog image signal from the bit line and converted into a digital value to provide information representing the external scene. Summary of the Invention

[0004] One aspect of the present invention provides a pixel unit comprising: a photodetector configured to generate an image charge in response to incident light; a floating diffuser (FD) region for receiving the image charge from the photodetector; a transfer (TX) transistor coupled between the floating diffuser and the photodetector to transfer the image charge to the FD region; a first reset (RST1) transistor coupled between the FD region and a voltage source; a capacitor having two terminals, a first terminal of the capacitor coupled to the FD region; and a second reset (RST2) transistor coupled between the second terminal of the capacitor and the voltage source.

[0005] Another aspect of the present invention provides a pixel unit comprising: a photodetector configured to generate an image charge in response to incident light; a floating diffusion (FD) region for receiving the image charge from the photodetector; a capacitor having two terminals configured to receive an overflow charge from the photodetector when the image charge generated by the photodetector exceeds a threshold amount; and a circuit system that receives one or more control signals and selectively forms an electrical loop connecting the two terminals of the capacitor in response to the one or more control signals.

[0006] A further aspect of the invention provides an imaging system comprising: a row of pixel units, wherein each pixel unit of the row includes: (a) a photosensitive sensor configured to generate an image charge in response to incident light; (b) a capacitor having two terminals, the capacitor being configured to receive an overflow charge from the photosensitive sensor when the image charge generated from the photosensitive sensor exceeds a threshold amount; and (c) a first reset (RST1) transistor and a second reset (RST2) transistor, wherein the RST1 transistor is coupled between an FD region and a voltage source, wherein the RST2 transistor is coupled between the capacitor and the voltage source; and a control circuit system coupled to the row of pixel units, wherein the control circuit system is configured to generate one or more control signals to selectively cause an electrical short circuit between the two terminals of the capacitor.

[0007] One or more aspects of the present invention provide a method for operating a pixel unit, the method comprising: resetting a lateral overflow integral capacitor (LOFIC) of the pixel unit, wherein the LOFIC includes a first terminal coupled to a photodetector of the pixel unit to receive image charge from the photodetector, and wherein the LOFIC includes a second terminal, different from the first terminal and coupled to a power supply voltage via a reset transistor of the pixel unit, wherein resetting the LOFIC includes activating the reset transistor such that the second terminal of the LOFIC is pulled up toward the power supply voltage. Attached Figure Description

[0008] The following description, with reference to the accompanying drawings, outlines non-limiting and non-exhaustive embodiments of the present technology, wherein similar or analogous reference numerals are used throughout to refer to similar or analogous components unless otherwise specified.

[0009] Figure 1 This is a partial schematic block diagram of an imaging system configured according to various embodiments of the present technology.

[0010] Figure 2 These are partial schematic diagrams of pixel units and line control circuit systems configured according to various embodiments of the present technology.

[0011] Figure 3 This is a timing diagram illustrating methods of operating pixel units according to various embodiments of the present technology.

[0012] Figure 4 This is a timing diagram illustrating another method of operating pixel units according to various embodiments of the present technology.

[0013] Those skilled in the art will understand that the elements in the figures are for illustrative purposes and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to aid in understanding various aspects of the art. Furthermore, common but well-known elements or methods that are useful or necessary in commercially feasible embodiments are generally not described in the figures or in detail below to avoid unnecessarily obscuring the description of various aspects of the art. Detailed Implementation

[0014] This disclosure relates to pixel units with a LOFIC (Local Dynamic Range Controller). For example, several embodiments of the present technology relate to pixel units incorporated into a high dynamic range LOFIC, and the LOFIC can be selectively automatically zeroed to reduce LOFIC reset and settling time. Specific details are set forth in the following description to provide a thorough understanding of aspects of the present technology. However, those skilled in the art will recognize that the systems, apparatuses, and techniques described herein can be practiced without one or more of the specific details set forth herein, or can be practiced using other methods, components, materials, etc.

[0015] Throughout this specification, references to "example" or "embodiment" mean that a particular feature, structure, or characteristic described in connection with an example or embodiment is included in at least one example or embodiment of the present technology. Therefore, the use of the phrases "for example," "as an example," or "embodiment" herein does not necessarily refer to all the same example or embodiment, and is not necessarily limited to the specific example or embodiment discussed. Furthermore, the features, structures, or characteristics of the present technology described herein can be combined in any suitable manner to provide further examples or embodiments of the present technology.

[0016] For ease of description, spatial relative terms (e.g., “below,” “below,” “above,” “under,” “above,” “top,” “bottom,” “left,” “right,” “center,” “middle,” etc.) may be used herein to describe the relationship of an element or feature illustrated in the figures relative to one or more other elements or features. It will be understood that spatial relative terms are intended to cover different orientations of the apparatus or system in use or operation other than those depicted in the figures. For example, if the apparatus or system illustrated in the figures is rotated, turned, or flipped about a horizontal axis, then an element or feature described as “below,” “under,” or “below” one or more other elements or features may be oriented “above” one or more other elements or features. Therefore, the exemplary terms “below” or “below” are non-limiting and may cover orientations above and below. Furthermore or alternatively, the apparatus or system may be oriented in other ways as illustrated in the figures (e.g., rotated 90 degrees about a vertical axis, or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly. In addition, it will be understood that when an element is referred to as being "between" two other elements, it may be the only element between the two other elements, or there may be one or more intermediary elements.

[0017] Several technical terms are used throughout this specification. These terms have their general meanings in the fields from which they are derived, unless expressly defined herein or otherwise indicated by the context in which they are used. It should be noted that component names and symbols may be used interchangeably throughout this document (e.g., Si and silicon); however, they have the same meaning.

[0018] A. Overview

[0019] Many pixel cells incorporate lateral overflow integrating capacitors (LOFICs) to increase the full-well capacitance of the pixel cell and thereby enhance the high dynamic range capability of the corresponding image sensor. The LOFIC capacitance is positively correlated with the full-well capacitance. Therefore, as the capacitance of the LOFIC used in a pixel cell increases, the full-well capacitance of the pixel cell also increases. For this reason, higher LOFIC capacitance is generally desired.

[0020] However, as the capacitance of the LOFIC increases, the time required for LOFIC charging and / or resetting also increases. Furthermore, the LOFICs of pixel units arranged in rows of a pixel array are typically coupled to a pair of global row drivers (e.g., a global row pull-down driver and a global row pull-up driver) to facilitate charging and / or resetting the LOFICs. Therefore, as the capacitance of the LOFICs in a row of pixel units increases, the total capacitive load on the lines connecting the LOFICs to the global row drivers also increases, resulting in (a) longer row LOFIC charging and resetting times, and (b) a reduced likelihood that the global row drivers can charge and / or reset the LOFICs in the row within the time allocated by the image sensor. This problem is only exacerbated by the need for larger pixel arrays, as the increased number of pixel units per row further increases the total capacitive load on the lines connecting the LOFICs to the global row drivers. If the time allocated by the image sensor for resetting and stabilizing the LOFICs is insufficient, banding (e.g., image artifacts, horizontal fixed-pattern noise, etc.) may be observed in the resulting image. Therefore, in order to continue increasing the LOFIC capacitance in the pixel units described above while avoiding striping, it is necessary to increase the time allocated for charging and / or resetting the LOFIC of the pixel units in the row at the cost of a slower frame rate.

[0021] To address these issues, the pixel unit of this technology may include a reset transistor coupled between the LOFIC and the power supply voltage. For example, the pixel unit of this technology may include (a) a first reset transistor coupling the floating diffusion region to the power supply voltage, (b) a double floating diffusion (DFD) transistor coupling a first terminal of the LOFIC to the floating diffusion region, and / or (c) a second reset transistor coupling a second terminal of the LOFIC to the power supply voltage. The second terminal of the LOFIC may also be selectively coupled to a global row pull-down driver to facilitate charging of the LOFIC.

[0022] A second reset transistor can be activated to locally pull the second terminal of the LOFIC to the power supply voltage, thereby avoiding the use of a global row pull-up driver external to the pixel unit. Additionally, the first reset transistor, the second reset transistor, and / or the DFD transistor can be activated to locally reset the LOFIC and short the first and second terminals of the LOFIC together (thereby automatically zeroing the LOFIC). Because the LOFIC reset is performed locally, the LOFIC reset time is reduced compared to a LOFIC that is globally reset along with other LOFICs using a row driver. Furthermore, automatic zeroing of the LOFIC reduces the LOFIC settling time, enabling faster precharge and / or LOFIC readout operations (and therefore faster frame rates). As a result, this technique facilitates the use of LOFICs with larger capacitance and / or a larger number of pixel units per row without significant risks of violating timing specifications defined by the image sensor and / or without requiring larger precharge and / or LOFIC reset timing margins.

[0023] B. Selected embodiments of pixel designs with reduced LOFIC pixel reset and settling time, and phase Related systems, apparatus and methods

[0024] Figure 1 This is a partial schematic block diagram of an imaging system 100 configured according to various embodiments of the present technology. As shown, the imaging system 100 includes a pixel array 102, a readout circuitry system 106, functional logic 108, and a control circuitry system 110. The pixel array may consist of pixels arranged in rows (in... Figure 1 Individually identified as rows R1 to Ry and columns (in) Figure 1 Individually identified as multiple pixel units 104 (in columns C1 to Cx) Figure 1 Individually identified as a two-dimensional (2D) array of pixels P1 to Pn. Each pixel unit 104 is configured to acquire image charge in response to incident light received from an external scene, and to generate a corresponding analog image charge data signal based at least in part on the acquired image charge.

[0025] After each pixel unit 104 has acquired an image charge, the corresponding analog image charge data signal is read out from the pixel array 102 along the column bit line 112 and enters the readout circuit system 106. In some embodiments, the analog image charge data signal is read out from the pixel array 102 one row at a time, from pixel units 104. Alternatively, other suitable techniques are used to read out the analog image charge data signal from the pixel array 102, such as (a) using a serial readout technique to read out pixel units 104 sequentially one by one, or (b) using a parallel readout technique to read out all pixel units 104 or a subset of pixel units 104 (e.g., multiple rows) simultaneously.

[0026] When the analog image charge data signal is read into the readout circuit system 106, an analog-to-digital converter (ADC) 148 can be used to convert the analog image charge data signal into a digital value (digital representation). In some embodiments, the ADC 148 of the readout circuit system 106 has an adjustable gain 150, allowing the analog image charge data signal to be read from the pixel array 102 using multiple gain settings. Although in Figure 1 Not shown, but the readout circuitry system 106 may additionally or alternatively include an amplifier circuitry system, a column readout circuitry system, and / or other circuitry systems.

[0027] The digital representation of the analog image charge data signal can then be transferred from the readout circuitry 106 to the functional logic 108. In some embodiments, the functional logic 108 is configured to simply store the digital representation as image data. In other embodiments, the functional logic 108 may be configured to manipulate the image data in addition to storing it (e.g., by applying post-image effects such as cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, etc.). The image data can be used to render an image of an external scene (e.g., people, places, objects, etc. within the external scene), from which light incident on the pixel units 104 of the pixel array 102 is received.

[0028] As shown, control circuitry 110 is coupled to pixel array 102. In some embodiments, control circuitry 110 controls the operational characteristics of pixel array 102. For example, control circuitry 110 may generate a transfer gate signal and / or other control signals (e.g., a reset signal) for (a) controlling the transfer of image charge and / or other signals within each of pixel units 104 and / or (b) controlling the readout of analog image charge data signals from pixel array 102. As another example, control circuitry 110 may generate a shutter signal for controlling image acquisition. The shutter signal may be a global shutter signal for enabling all pixel units 104 of pixel array 102 to simultaneously capture corresponding image charges (and corresponding analog image charge data signals) during a single acquisition window. Alternatively, the shutter signal may be a rolling shutter signal, such that each row, column, or other group of pixel units 104 is sequentially enabled to capture corresponding image charges (and corresponding analog image charge data signals) during consecutive acquisition windows. In some embodiments, the shutter signal may establish the exposure time (e.g., defined as the length of time the shutter remains open, although the imaging system 100 may lack a physical shutter). The exposure time may be the same for each image frame, or the exposure time may vary across different image frames.

[0029] Figure 2 This is a partial schematic diagram of pixel unit 204 coupled to line control circuit system 210. Pixel unit 204 can be... Figure 1One of the pixel units 104 or another pixel unit of the present technology. Additionally or alternatively, the line control circuit system 210 may be... Figure 1 The control circuit system 110 or other control circuit systems of the present technology.

[0030] like Figure 2 As shown, pixel unit 204 includes a photoelectric sensor 214, a transfer transistor 222, a floating diffusion region 230, a source follower transistor 232, a row selection transistor 234, a first reset transistor 236, a second reset transistor 237, a dual floating diffusion (DFD) transistor 238, a lateral overflow integrating capacitor (LOFIC) 240, and a LOFIC transistor 242. The photoelectric sensor 214... Figure 2 The illustrated photodiode has an anode coupled to ground (e.g., a negative power rail or another reference voltage) and a cathode coupled to (a) a transfer transistor 222 and (b) a LOFIC transistor 242. In operation, Figure 1 The photoelectric sensor 214 is configured to generate an image charge in response to incident light received from an external scene. In other embodiments of the present invention, the photoelectric sensor 214 may be another suitable type of photoelectric sensor or photodetector (e.g., metal semiconductor metal (MSM) photodetector, phototransistor, photoconductive detector, or phototube).

[0031] Transfer transistor 222 couples floating diffusion region 230 to photosensor 214. More specifically, transfer transistor 222 includes a gate configured to receive transfer signal TX. When asserting transfer signal TX, transfer transistor 222 is configured to transfer image charge generated by photosensor 214 to floating diffusion region 230. In some embodiments, transfer transistor 222 may be omitted from pixel unit 204. Floating diffusion region 230 is further coupled to (a) DFD transistor 238, (b) first reset transistor 236, and (c) the gate of source follower transistor 232.

[0032] LOFIC transistor 242 couples photosensor 214 to first LOFIC node 243, which in turn couples to a first terminal of LOFIC 240. More specifically, LOFIC transistor 242 includes a gate coupled to a reference voltage (e.g., a positive power rail (VDD or PIXVDD) or another voltage). Therefore, LOFIC transistor 242 can transfer image charge generated by photosensor 214 to first LOFIC node 243.

[0033] DFD transistor 238 couples the first LOFIC node 243 to the floating diffusion region 230. More specifically, DFD transistor 238 includes a gate configured to receive the dual floating diffusion signal DFD. When asserting the dual floating diffusion signal DFD, DFD transistor 238 is configured to couple (a) the first terminal of LOFIC 240 and the first LOFIC node 243 to (b) the gates of the floating diffusion region 230, the first reset transistor 236, and the source follower transistor 232. In some embodiments, DFD transistor 238 may be omitted from pixel cell 204.

[0034] LOFIC 240 may be a high-density capacitor. For example, LOFIC 240 may be a three-dimensional (3D) metal-insulator-metal (MIM) capacitor. The insulator may be a dielectric material having a high dielectric constant (κ). In some embodiments, LOFIC 240 has a large capacitance (e.g., greater than 100 nanofarads (fF), such as approximately 300 fF or greater). In other embodiments, LOFIC 240 may have a relatively small capacitance (e.g., less than 100 fF). In any embodiment, LOFIC 240 may be employed in pixel unit 204 to extend the dynamic range of pixel unit 204. For example, when the image charge generated from photodetector 214 exceeds a predetermined amount (e.g., a maximum amount that floating diffusion region 230 can receive or store, or another threshold amount), LOFIC 240 may be configured to receive overflow charge from photodetector 212. As shown, the first terminal of LOBIC 240 is coupled to DFD transistor 238 and LOBIC transistor 242 via the first LOBIC node 243, and the second terminal of LOBIC 240 is coupled to the second reset transistor 237 and the horizontal control circuit system 210 via the second LOBIC node 245. The line connecting the horizontal control circuit system 210 to the second LOBIC node 245 and the second terminal of LOBIC 240 is commonly referred to as the voltage capacitive capacitance (VCAP) line.

[0035] A first reset transistor 236 is coupled between the floating diffusion region 230 and a power supply voltage (e.g., a positive power supply voltage (VDD or PIXVDD) or another reference voltage), and a second reset transistor 237 is coupled between a second terminal of the LOFIC 240 and a power supply voltage (e.g., between the second LOFIC node 245 and the power supply voltage). The gate of the first reset transistor 236 is configured to receive a first reset signal RST1, and the gate of the second reset transistor 237 is configured to receive a second reset signal RST2. As discussed in more detail below, the first reset signal RST1 and the second reset signal RST2 can be asserted to reset or stabilize the pixel cell 204 (e.g., to reset or stabilize the floating diffusion region 230 and / or the LOFIC 240). For example, when the first reset signal RST1 is asserted, the floating diffusion region 230 can be pulled up toward the power supply voltage (e.g., through the first reset transistor 236). As another example, when the second reset signal RST2 is asserted, the second LOFIC node 245 and the second terminal of LOFIC 240 can be pulled up toward the power supply voltage (e.g., via the second reset transistor 237). As yet another example, when the first reset signal RST1, the second reset signal RST2, and the double floating diffuse signal DFD are all asserted, the electrical circuit (e.g., extending from the first terminal of LOFIC 240 to the second terminal of LOFIC 240 via DFD transistor 238, the first reset transistor 236, and the second reset transistor 237) can connect or short-circuit the first and second terminals of LOFIC 240, and quickly stabilize LOFIC 240.

[0036] In some embodiments, the second reset transistor 237 may be shared among more than one pixel unit in the pixel array (e.g., Figure 2 (As shown in box 250, indicated by the dashed line). For example, in addition to the second terminal of the LOFIC of one or more other pixel units (not shown), the source of the second reset transistor 237 may also be coupled to the second terminal of the LOFIC 240 of pixel unit 204. Figure 2 One or more other pixel units sharing the second reset transistor 237 with pixel unit 204 may comprise one or more pixel units located in the same row as pixel unit 204 in the pixel array. Alternatively, one or more other pixel units sharing the second reset transistor 237 with pixel unit 204 may comprise one or more pixel units located in one or more rows of the pixel array different from the row containing pixel unit 204. One or more other pixel units sharing the second reset transistor 237 with pixel unit 204 may have the same or similar reset and / or readout timing as pixel unit 204. For example, the analog image charge data signals of one or more other pixel units and pixel unit 204 may be simultaneously reset and / or read out.

[0037] Figure 2 The source follower transistor 232 of pixel unit 204 is coupled to a voltage source and a row select transistor 234. The row select transistor 234 is coupled between the source follower transistor 232 and the column bit line 212. As shown, the row select transistor 234 is configured to receive a row select signal RS. In operation, the source follower transistor 232 is configured to output an analog image charge data signal to the column bit line 212 via the row select transistor 234 when the row select signal RS is asserted. The analog image charge data signal output to the column bit line 212 is at least partially based on the amount of image charge in the floating diffusion region 230.

[0038] Now for reference Figure 2 The line control circuit system 210 includes a line driver 226 and a switch 228. Figure 2 The diagram also shows the parasitic capacitance 227 of the line control circuitry system 210. In some embodiments, switch 228 is an enable transistor. In operation, switch 228 is configured to selectively couple line driver 226 to a second terminal of second LOFIC node 245 and LOFIC 240, at least in part, based on an enable signal EN (e.g., applied to the gate of the enable transistor). For example, when the enable signal EN is asserted, switch 228 may couple line driver 226 to the second terminal of second LOFIC node 245 and LOFIC 240. Continuing this example, when the enable signal EN is not asserted, switch 228 may decouple line driver 226 from the second terminal of second LOFIC node 245 and LOFIC 240.

[0039] Because the second terminals of the second LOFIC node 245 and LOFIC 240 can be pulled up toward the power supply voltage via the second reset transistor 237 when the second reset signal RST2 is asserted, the pixel unit 204 can avoid using a pull-up line driver in the line control circuit system 210. Therefore, in some embodiments, in parallel Figure 2 An imaging system with pixel unit 204 (e.g., Figure 1 The imaging system 100 may omit or lack the pull-up row driver in the row control circuitry system 210 coupled to the pixel unit 204. As a result, in some embodiments, Figure 2 The row driver 226 can be a simple voltage buffer or a pull-down row driver. In operation, the row driver 226 can be configured to pull the second terminal of the second LOFIC node 245 and / or the second terminal of the LOFIC 240 toward a ground voltage (e.g., a negative supply voltage or another reference voltage) when the row driver 226 is coupled to the second terminal of the second LOFIC node 245 and / or the second terminal of the LOFIC 240 via the switch 228.

[0040] Figure 3 This describes the operation of various embodiments according to the present technology. Figure 2 Timing diagram 360 for the method of pixel unit 204. (e.g.) Figure 3 As shown, timing diagram 360 is divided into four operations or stages, including pre-charge operation, integration operation, photodetector (PD) readout operation, and LOFIC (or capacitor) readout operation.

[0041] Let's refer to each other. Figure 2 and 3 A pre-charge operation is performed to reset pixel unit 204. More specifically, the first reset signal RST1, the second reset signal RST2, the dual floating diffuser signal DFD, and the transfer signal TX are each asserted, while the enable signal EN is not asserted. Therefore, pixel unit 204 is decoupled from the row driver 226 of the row control circuit system 210, and the first reset transistor 236, the second reset transistor 237, the DFD transistor 238, and the transfer transistor 222 are each activated. As a result, the floating diffuser region 230 and LOBIC 240 are locally pulled up toward the power supply voltage (e.g., without using a global row pull-up driver). In addition, an electrical loop (e.g., extending from the first terminal of LOBIC 240 to the second terminal of LOBIC 240 via the DFD transistor 238, the first reset transistor 236, and the second reset transistor 237) connects or shorts the first and second terminals of LOBIC 240 together. Therefore, it is expected that the charge will be redistributed between the first and second terminals of LOFIC 240 to quickly stabilize LOFIC 240 after or when LOFIC 240 is reset. It is also expected that no charge will leak to the power supply voltage or the line driver 226 during this process, and the line driver 226 will not be disturbed (e.g., because it is decoupled from pixel unit 204 via switch 228). Then, the transfer signal TX, the first reset signal RST1, the dual floating diffuse signal DFD, and the second reset signal RST2 are sequentially deasserted near the end of the precharge operation and before the integration operation begins.

[0042] An integration operation is performed to accumulate image charge in pixel unit 204. The duration of the integration period corresponds to the exposure time of pixel unit 204. During the integration operation, the enable signal EN is asserted, while each of the other signals is not asserted. Consequently, the line driver 226 of the line control circuitry system 210 is coupled to the second LOBIC node 245 and the second terminal of LOBIC 240 via switch 228, while the second reset transistor 237, DFD transistor 238, and first reset transistor 236 are turned off. Subsequently, the line driver 226 pulls the second LOBIC node 245 and the second terminal of LOBIC 240 toward ground voltage (e.g., a negative power rail or another reference voltage). In some embodiments, the line driver 226 experiences a relatively small capacitive load on the VCAP line that couples the line driver 226 to the second terminal of LOBIC 240, which is at least partly due to the capacitance of LOBIC 240 arranged in series with the parasitic capacitance (not shown) at the first LOBIC node 243. Figure 3 In the embodiment described herein, the enable signal EN is maintained as asserted when pixel unit 204 moves from integration operation to PD readout operation.

[0043] During the PD readout operation, the row selection signal RS (in) Figure 2 Shown in but Figure 3 (Not shown) is asserted to activate row selection transistor 234, and the analog image charge data signal corresponding to photodetector 214 is read from pixel cell 204 onto column line 212. In some embodiments, correlated double sampling (CDS) is used to read the analog image charge data signal corresponding to photodetector 214 onto column line 212. For example, the first reset signal RST1 is pulsed, while the second reset signal RST2, the double floating diffuser signal DFD, and the transfer signal TX are not asserted. During the pulse of the first reset signal RST1, the first reset transistor 236 is activated, and the floating diffuser region 230 is pulled up toward the power supply voltage. After the pulse of the first reset signal RST1, the reset value of the PD readout operation output from pixel cell 204 via row selection transistor 234 to column line 212 is determined by the readout circuitry system surrounding pixel cell 204 (e.g., Figure 1 The readout circuit system 106) samples and holds data, such as... Figure 3 The “SHR1” in the analog-to-digital signal ADC described herein indicates this.

[0044] Subsequently, the transfer signal TX is pulsed, while the first reset signal RST1, the second reset signal RST2, and the dual floating diffusion signal DFD are not asserted. During the pulse of the transfer signal TX, the transfer transistor 222 is activated, and the image charge generated by the photoelectric sensor 214 during the integration operation is transferred to the floating diffusion region 230. After the pulse of the transfer signal TX, the analog image charge data signal of the PD readout operation output from the pixel unit 204 via the row selection transistor 234 to the column line 212 is sampled and held by the readout circuit system surrounding the pixel unit 204, such as... Figure 3 The analog image charge data signal of the PD readout operation is indicated by "SHS1" in the analog-to-digital signal ADC described herein. This signal can be based at least partially on the amount of image charge in the floating diffusion region 230. Figure 3 In the embodiment described herein, the enable signal EN is then deasserted near the end of the PD readout operation to decouple the row driver 226 from the second LOFIC node 245 and the second end of the LOFIC 240.

[0045] During a LOFIC read operation, the row selection signal RS (in) Figure 2 Shown in but Figure 3 (Not shown) can remain asserted to activate row selection transistor 234, and the analog image charge data signal corresponding to LOFIC 240 and photodetector 214 can be read onto column line 212. In some embodiments, CDS is used to read the analog image charge data signal corresponding to LOFIC 240 and photodetector 214 onto column line 212. For example, a second reset signal RST2 is asserted to activate second reset transistor 237 and pull up the second LOFIC node 245 and the second terminal of LOFIC 240 toward the power supply voltage (e.g., without using a global row pull-up driver). Figure 3 As shown, when the enable signal EN is asserted, the second reset signal RST2 is never asserted. In other words, the assertion of the second reset signal RST2 does not overlap with the assertion of the enable signal EN, such that there is no time for the second LOFIC node 245 and the second terminal of LOFIC 240 to be actively coupled to (a) the row driver 226 and (b) the power supply voltage via the second reset transistor 237 via the switch 228.

[0046] After the second reset signal RST2 is asserted, the dual floating diffuse signal DFD and the transfer signal TX are asserted to activate DFD transistor 238 and transfer transistor 222, respectively. Consequently, image charge is transferred to the floating diffuse region 230, and the analog image charge data signal corresponding to LOFIC 240 and photodetector 214 is output to column line 212 via row select transistor 234. This analog image charge data signal is at least partially based on the amount of image charge in the floating diffuse region 230. The analog image charge data signal corresponding to LOFIC 240 and photodetector 214 is then sampled and held by the readout circuitry system surrounding pixel unit 204, such as... Figure 3 The “SHS2” in the analog-to-digital signal ADC described herein indicates this.

[0047] The first reset signal RST1 is then pulsed to reset LOFIC 240 and the floating diffusion region 230. More specifically, the first reset signal RST1 is pulsed, while the second reset signal RST2, the dual floating diffusion signal DFD, and the transfer signal TX are asserted. Therefore, during the pulse of the first reset signal RST1, LOFIC 240 and the floating diffusion region 230 are locally pulled up toward the power supply voltage (e.g., without using a global horizontal pull-up driver). Additionally, an electrical loop (e.g., extending from the first terminal of LOFIC 240 to the second terminal of LOFIC 240 via DFD transistor 238, the first reset transistor 236, and the second reset transistor 237) connects or shorts the first and second terminals of LOFIC 240 together. Thus, charge is expected to redistribute between the first and second terminals of LOFIC 240 to quickly stabilize the LOFIC. It is also anticipated that no charge leakage will occur to the power supply voltage or the row driver 226 during this process, and that the row driver 226 will not be disturbed (e.g., because it remains decoupled from pixel unit 204 via switch 228, and the enable signal EN is not asserted). After the pulsed first reset signal RST1, the reset value of the LOFIC readout operation output from pixel unit 204 via row select transistor 234 to column line 212 is sampled and held by the readout circuitry system surrounding pixel unit 204, such as... Figure 3 The "SHR2" in the analog-to-digital signal ADC described herein indicates that the transfer signal TX, the first reset signal RST1, the dual floating diffuse signal DFD, and the second reset signal RST2 are then sequentially deasserted at the end of the LOFIC readout operation.

[0048] Figure 4 This describes the operation of various embodiments according to the present technology. Figure 2Timing diagram 470 for another method of pixel unit 204. As shown, timing diagram 470 is similar to [previous method] except for the second reset signal RST2 and enable signal EN during integration and PD readout operations. Figure 3 The timing diagram is shown in 360°. Therefore, for the sake of brevity, it is omitted below. Figure 4 The pre-charge and LOFIC readout operations described herein are discussed in detail.

[0049] Figure 4 The integration operation illustrated in timing diagram 470 is largely similar to Figure 3 The integration operation is illustrated in timing diagram 360. For example, refer to [reference needed]. Figure 2 and 4 The enable signal EN is asserted at the very beginning of the integration operation, while none of the other signals are asserted. Therefore, the line driver 226 of the line control circuitry 210 is coupled to the second LOBIC node 245 and the second terminal of LOBIC 240 via switch 228, while the second reset transistor 237, DFD transistor 238, and first reset transistor 236 remain off. The line driver 226 then pulls the second LOBIC node 245 and the second terminal of LOBIC 240 down toward ground voltage (e.g., a negative power rail or another reference voltage). In some embodiments, the line driver 226 experiences a relatively small capacitive load on the VCAP line coupling the line driver 226 to the second terminal of LOBIC 240, at least in part due to the capacitance of LOBIC 240 arranged in series with the parasitic capacitance (not shown) at the first LOBIC node 243. Figure 3 The hold assertion illustrated in timing diagram 360 is compared to the enable signal EN that forms a contrast until the PD readout operation ends. Figure 4 The enable signal EN, as illustrated in timing diagram 470, is deasserted near the end of the integration operation and remains unasserted during the duration of the PD readout operation and the LOFIC readout operation.

[0050] During PD readout operation Figure 4 The second reset signal RST2, as illustrated in timing diagram 470, is asserted at the very beginning of the PD readout operation (e.g., simultaneously with the assertion or pulse of the first reset signal RST1), instead of as... Figure 3 As shown in timing diagram 360, the signal remains unassertified for the duration of the PD readout operation. The assertion of the second reset signal RST2 activates the second reset transistor 237 and pulls the second LOFIC node 245 and the second terminal of LOFIC 240 towards the power supply voltage (e.g., without using a global row pull-up driver). The second reset signal RST2 is then held asserted until the LOFIC readout operation ends. Similar to... Figure 3The timing diagram 360, in Figure 4 In timing diagram 470, the second reset signal RST2 is never asserted while the enable signal EN is asserted. In other words, the assertion of the second reset signal RST2 does not overlap with the assertion of the enable signal EN, such that there is no time for the second LOFIC node 245 and the second terminal of LOFIC 240 to be actively coupled to (a) the row driver 226 and (b) the power supply voltage via the second reset transistor 237.

[0051] Dual-floating diffused signal DFD in Figure 4 During the PD readout operation, the second reset signal RST2 remains unassertified, preventing the unexpected assertion that the second reset signal RST2 might otherwise alter the operation of pixel unit 204 during the PD readout operation. Therefore, during the PD readout operation, the row selection signal RS (in...) Figure 2 Shown in but Figure 4 (Not shown) is asserted to activate row select transistor 234, and pixel unit 204 outputs an analog image charge data signal corresponding to photodetector 214 to column line 212. In some embodiments, correlated double sampling (CDS) is used to read the analog image charge data signal corresponding to photodetector 214 onto column line 212. For example, the first reset signal RST1 is pulsed, while the dual floating diffuse signal DFD and transfer signal TX are not asserted. During the pulse of the first reset signal RST1, the first reset transistor 236 is activated, and the floating diffuse region 230 is pulled up toward the power supply voltage. After pulsed first reset signal RST1, the reset value of the PD readout operation output from pixel unit 204 to column line 212 via row select transistor 234 is sampled and held by the readout circuitry system surrounding pixel unit 204, such as Figure 4 The “SHR1” in the analog-to-digital signal ADC described herein indicates this.

[0052] Subsequently, the transfer signal TX is pulsed, while the first reset signal RST1 and the dual floating diffusion signal DFD are not asserted. During the pulse of the transfer signal TX, the transfer transistor 222 is activated, and the image charge generated by the photoelectric sensor 214 during the integration operation is transferred to the floating diffusion region 230. After the pulse of the transfer signal TX, the analog image charge data signal of the PD readout operation output from the pixel unit 204 via the row selection transistor 234 to the column line 212 is sampled and held by the readout circuit system surrounding the pixel unit 204, such as... Figure 4 The analog image charge data signal of the PD readout operation is indicated by "SHS1" in the analog-to-digital signal ADC described above. The image charge data signal can be based at least partially on the amount of image charge in the floating diffusion region 230. Then, pixel unit 204 continues to perform the operation described above. Figure 3The discussion of LOFIC read operations is consistent with the LOFIC read operations.

[0053] C. in conclusion

[0054] The above detailed description of embodiments of this technology is not intended to be exhaustive or to limit the technology to the precise forms disclosed above. Although specific embodiments and examples of this technology have been described above for illustrative purposes, as those skilled in the art will recognize, various equivalent modifications are possible within the scope of this technology. For example, although the steps are presented in the order given above, alternative embodiments may perform the steps in a different order. Furthermore, the various embodiments described herein may be combined to provide further embodiments.

[0055] As will be understood from the foregoing, for illustrative purposes, this document has described specific embodiments of the technology, but has not shown or described in detail well-known structures and functions to avoid unnecessarily obscuring the description of the embodiments of the technology. Where the context permits, singular or plural terms may also contain plural or singular terms respectively. Furthermore, when referring to a list of two or more items, unless the word “or” is explicitly limited to referring only to a single item excluding other items, its use in such a list should be interpreted as including (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Additionally, as used herein, the phrase “and / or” in “A and / or B” refers to only A, only B, and both A and B. Furthermore, the terms “comprising,” “including,” “having,” and “with” are used throughout to indicate that at least the stated features are included, such that no further number of the same features and / or other features of additional types are excluded. Furthermore, as used herein, the phrases “based on,” “depending on,” “as a result of,” and “in response to” should not be interpreted as a reference to a set of closed conditions. For example, without departing from the scope of this disclosure, an exemplary step described as “based on condition A” may be based on both condition A and condition B. In other words, as used herein, the phrase “based on” should be interpreted in the same way as the phrase “at least partially based on” or the phrase “at least partially based on”.

[0056] From the foregoing, it will be understood that various modifications can be made without departing from this disclosure or the present technology. For example, those skilled in the art will understand that the various components of the present technology can be further divided into sub-components, or the various components and functions of the present technology can be combined and integrated. Furthermore, certain aspects of the present technology described in the context of specific embodiments may be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the present technology have been described in the context of these embodiments, other embodiments may also exhibit such advantages, and not all embodiments must exhibit such advantages to fall within the scope of the present technology. Therefore, this disclosure and related technologies may cover other embodiments not explicitly shown or described herein.

Claims

1. A pixel cell, comprising: a photosensor configured to photo generate image charges in response to incident light; a floating diffusion (FD) region for receiving the image charges from the photosensor; a transfer (TX) transistor coupled between the FD region and the photosensor to transfer the image charges to the FD region; a first reset (RST1) transistor coupled between the FD region and a voltage source; a capacitor having two terminals, a first terminal of the capacitor coupled to the FD region; and a second reset (RST2) transistor coupled between a second terminal of the capacitor and the voltage source.

2. The pixel cell of claim 1, further comprising a double floating diffusion (DFD) transistor coupled between the first terminal of the capacitor and the FD region.

3. The pixel cell of claim 2, wherein the RST1 transistor, the RST2 transistor, and the DFD transistor are arranged such that when the RST1 transistor, the RST2 transistor, and the DFD transistor are simultaneously active, the two terminals of the capacitor are shorted.

4. The pixel cell of claim 1, wherein the second terminal of the capacitor is further coupled to a row driver.

5. The pixel cell of claim 4, wherein the second terminal of the capacitor is selectively coupled to the row driver via an enable (EN) transistor, and wherein the EN transistor and the RST2 transistor are configured such that the EN transistor and the RST2 transistor are never active at the same time.

6. The pixel cell of claim 4, wherein the second terminal of the capacitor is configured to be pulled down by the row driver.

7. The pixel cell of claim 6, wherein the second terminal of the capacitor is configured to be pulled up by the RST2 transistor.

8. The pixel cell of claim 1, wherein the RST2 transistor is further coupled to another capacitor of a different pixel cell.

9. The pixel cell of claim 1, further comprising: a source follower (SF) transistor coupled to the voltage source and having a gate coupled to the FD region; and a row select (RS) transistor coupled to the SF transistor and a bit line, wherein the SF transistor is coupled to output an analog image charge data signal to the bit line in response to the image charges in the FD region.

10. The pixel cell of claim 1, wherein the capacitor is a lateral overflow integration capacitor (LOFIC).

11. The pixel cell of claim 10, wherein the LOFIC is a metal-insulator-metal (MIM) type having an insulator material between two metal terminals.

12. The pixel cell of claim 11, wherein the insulator material is a high-k type.

13. The pixel cell of claim 1, wherein the pixel cell is included in a row of pixel cells of a pixel array, and wherein the RST2 transistor is shared between multiple rows that are read simultaneously. ​ ​ 14. The pixel cell of claim 1, further comprising a transistor coupling the photosensor to the first terminal of the capacitor, wherein the transistor includes a gate connected to a reference voltage.

15. A pixel cell, comprising: a photosensor configured to photo generate image charges in response to incident light; a floating diffusion (FD) region for receiving the image charges from the photosensor; a capacitor having two terminals, the capacitor configured to receive overflow charges from the photosensor when the image charges generated by the photosensor exceed a threshold amount; and circuitry that receives one or more control signals and selectively forms an electrical loop connecting the two terminals of the capacitor in response to the one or more control signals.

16. The pixel cell of claim 15, wherein the circuitry includes: a first reset (RST1) transistor coupled between the FD region and a voltage source; and a second reset (RST2) transistor coupled between a first terminal of the capacitor and the voltage source.

17. The pixel cell of claim 16, wherein the RST2 transistor is further coupled to another capacitor of a different pixel cell.

18. The pixel cell of claim 16, wherein the pixel cell is included in a row of a plurality of rows of pixel cells of a pixel array, and wherein the RST2 transistor is shared between a predetermined number of rows of the plurality of rows that are read simultaneously.

19. The pixel cell of claim 16, wherein the circuitry further includes a double floating diffusion (DFD) transistor coupled between the FD region and a second terminal of the capacitor.

20. The pixel cell of claim 16, wherein the first terminal of the capacitor is configured to be pulled up through the RST2 transistor.

21. The pixel cell of claim 15, wherein the one or more control signals are generated by control circuitry coupled to the pixel cell, and wherein, in response to the one or more control signals, the circuitry forms the electrical loop during a select moment during a pre-charge operation and / or a capacitor readout operation of the pixel cell.

22. The pixel cell of claim 21, wherein the pixel cell is selectively coupled to a row driver, and wherein the pixel cell is decoupled from the row driver when the circuitry forms the electrical loop.

23. The pixel cell of claim 22, wherein one of the two terminals of the capacitor is configured to be pulled down through the row driver.

24. The pixel cell of claim 22, further comprising a source follower transistor having a gate coupled to the FD region.

25. The pixel cell of claim 15, wherein the capacitor is coupled to a pull-down row driver but not to a pull-up row driver.

26. The pixel cell of claim 15, wherein the capacitor is a lateral overflow integration capacitor (LOFIC).

27. The pixel cell of claim 15, further comprising a transistor coupling one of the two terminals of the capacitor to the photosensor, wherein the transistor comprises a gate connected to a reference voltage.

28. The pixel cell of claim 15, further comprising a transfer (TX) transistor coupled between the FD region and the photosensor to transfer the image charge to the FD region.

29. An imaging system comprising: a row of pixel cells, wherein each pixel cell of the row includes: (a) a photosensor configured to photogenerate image charge in response to incident light; (b) a capacitor having two terminals, the capacitor configured to receive overflow charge from the photosensor when the image charge generated from the photosensor exceeds a threshold amount; and (c) a first reset (RST1) transistor and a second reset (RST2) transistor, wherein the RST1 transistor is coupled between a floating diffusion (FD) region and a voltage source, wherein the RST2 transistor is coupled between the capacitor and the voltage source; and control circuitry coupled to the row of pixel cells, wherein the control circuitry is configured to generate one or more control signals to selectively cause an electrical short between the two terminals of the capacitor.

30. The imaging system of claim 29, wherein the control circuitry selectively causes the electrical short in response to turning on the RST1 transistor and the RST2 transistor.

31. The imaging system of claim 29, wherein each pixel cell of the row further includes a double floating diffusion (DFD) transistor coupled between the FD region and the capacitor, and wherein the control circuitry causes the electrical short in response to turning on the RST1 transistor, the RST2 transistor, and the DFD transistor.

32. The imaging system of claim 29, wherein the imaging system further comprises a row driver coupled to the row of pixel cells by an enable (EN) transistor, and wherein the control circuitry is further configured to control the RST2 transistor and the EN transistor such that the RST2 transistor is never turned on when the EN transistor is turned on.

33. The imaging system of claim 32, wherein the row driver is a pull-down driver.

34. The imaging system of claim 33, wherein a pull-up row driver is not coupled to the capacitor of each pixel cell of the row of pixel cells.

35. The imaging system of claim 29, wherein the control circuitry is configured to selectively cause the electrical short during a pre-charge phase and / or a capacitor readout phase.

36. The imaging system of claim 29, wherein each pixel cell of the row further includes a transfer transistor coupled between the FD region and the photosensor. ​ 37. The imaging system of claim 29, wherein each pixel cell of the row further comprises a source follower transistor having a gate coupled to the FD region.

Images