Display substrate, manufacturing method thereof and display device

Abstract

A display substrate comprises a base substrate (101), the base substrate (101) comprises a display area (AA), the display area (AA) comprises a plurality of pixel areas (P); at least four stacked conductive layers (102, 103, 104 and 105) are located on the base substrate (101), any two adjacent conductive layers are insulated from each other, each conductive layer (102, 103, 104 and 105) comprises a conductive pattern located in each pixel area (P), the conductive patterns of any two adjacent conductive layers in the same pixel area (P) form a storage capacitor (such as Cst1, Cst2, Cst3), and in a direction perpendicular to the base substrate (101), the projections of at least four conductive layers (102, 103, 104 and 105) on the base substrate (101) overlap. A method for manufacturing a display substrate and a display device are also provided.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device. Background Art

[0002] In recent years, reflective displays represented by electrophoretic displays have been widely used as readers in the education market due to their advantages such as eye protection, low power consumption, readability in sunlight, and good flexibility. Summary of the invention

[0003] The display substrate, the manufacturing method thereof and the display device provided by the present disclosure are as follows:

[0004] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0005] A base substrate, the base substrate comprising a display area, the display area comprising a plurality of pixel areas;

[0006] At least four conductive layers are stacked and located on the base substrate. Any two adjacent conductive layers are insulated from each other. Each conductive layer includes a conductive pattern located in each pixel area. The conductive patterns of any two adjacent conductive layers in the same pixel area form a storage capacitor. In a direction perpendicular to the base substrate, the projections of the at least four conductive layers on the base substrate overlap.

[0007] In some embodiments, in the above display substrate provided by the embodiments of the present disclosure, the at least four conductive layers include a first conductive layer, a second conductive layer, a third conductive layer and a pixel electrode layer, wherein:

[0008] The first conductive layer includes a first conductive pattern, the second conductive layer includes a second conductive pattern, the third conductive layer includes a third conductive pattern, and the pixel electrode layer includes a pixel electrode;

[0009] The first conductive pattern and the second conductive pattern constitute a first storage capacitor, the second conductive pattern and the third conductive pattern constitute a second storage capacitor, the third conductive pattern and the pixel electrode constitute a third storage capacitor, and the first conductive pattern is electrically connected to the third conductive pattern, and the second conductive pattern is electrically connected to the pixel electrode.

[0010] In some embodiments, the above-mentioned display substrate provided in the embodiments of the present disclosure further includes a first insulating layer, a second insulating layer and a third insulating layer, wherein the first insulating layer is located between the first conductive layer and the second conductive layer, the second insulating layer is located between the second conductive layer and the third conductive layer, and the third insulating layer is located between the third conductive layer and the pixel electrode layer.

[0011] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the second insulating layer and the third insulating layer include through holes provided therethrough, and the pixel electrode is electrically connected to the second conductive pattern via the through holes.

[0012] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the third conductive pattern includes a hollow structure, and the orthographic projection of the hollow structure on the base substrate covers the orthographic projection of the through hole on the base substrate.

[0013] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the base substrate further includes a non-display area surrounding the display area;

[0014] The first conductive layer further includes a first connecting line, the first connecting line extends along a first direction, and the first connecting line is integrally arranged with the first conductive pattern;

[0015] The third conductive layer further includes a second connecting line, the second connecting line extends along a second direction, and the second connecting line is integrally arranged with the third conductive pattern, and the second direction is arranged to intersect with the first direction;

[0016] The pixel electrode layer further includes a wiring located in the non-display area, wherein the wiring surrounds the display area and is electrically connected to the first connection line and the second connection line respectively.

[0017] In some embodiments, the display substrate provided in the embodiments of the present disclosure further includes a transistor located in the pixel area, the gate of the transistor is located in the first conductive layer, and the first electrode and the second electrode of the transistor are located in the second conductive layer.

[0018] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the third conductive layer is metal, and the orthographic projection of the third conductive pattern on the base substrate at least covers the orthographic projection of the channel region of the transistor on the base substrate.

[0019] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the orthographic projection of the first conductive pattern on the base substrate half surrounds the orthographic projection of the transistor on the base substrate.

[0020] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the orthographic projection of the second conductive pattern on the base substrate overlaps with the orthographic projection of the first conductive pattern on the base substrate, and the second conductive pattern is integrally arranged with the first electrode of the transistor.

[0021] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the orthographic projection of the pixel electrode on the base substrate completely covers the orthographic projection of the transistor on the base substrate.

[0022] On the other hand, an embodiment of the present disclosure provides a display device, including a display substrate and an opposing substrate arranged opposite to each other, and a dimming layer located between the display substrate and the opposing substrate, wherein the display substrate is the above-mentioned display substrate provided in the embodiment of the present disclosure.

[0023] In some embodiments, in the above-mentioned display device provided by the embodiments of the present disclosure, the counter substrate includes a common electrode, and the common electrode, the first conductive pattern, and the third conductive pattern are loaded with the same electrical signal.

[0024] In some embodiments, in the above-mentioned display device provided by the embodiments of the present disclosure, the dimming layer is an electrophoretic layer or a liquid crystal layer.

[0025] On the other hand, an embodiment of the present disclosure provides a method for manufacturing the above-mentioned display substrate, comprising:

[0026] Providing a substrate, the substrate comprising a display area, the display area comprising a plurality of pixel areas;

[0027] At least four conductive layers are stacked on the base substrate, any two adjacent conductive layers are insulated from each other, each conductive layer includes a conductive pattern located in each pixel area, and the conductive patterns of any two adjacent conductive layers in the same pixel area constitute a storage capacitor, and in a direction perpendicular to the base substrate, the projections of the at least four conductive layers on the base substrate overlap.

[0028] In some embodiments, in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, at least four conductive layers are stacked and arranged on the base substrate, any two adjacent conductive layers are insulated from each other, each conductive layer includes a conductive pattern located in each pixel area, and the conductive patterns of any two adjacent conductive layers in the same pixel area constitute a storage capacitor, and in a direction perpendicular to the base substrate, the projections of the at least four conductive layers on the base substrate overlap, specifically including:

[0029] Forming a first conductive layer on the base substrate, wherein the first conductive layer includes a first conductive pattern located in the pixel area;

[0030] forming a first inorganic insulating layer on the first conductive layer;

[0031] forming a second conductive layer on the first inorganic insulating layer, wherein the second conductive layer comprises a second conductive pattern located in the pixel area, and the second conductive pattern and the first conductive pattern constitute a first storage capacitor;

[0032] forming a second inorganic insulating layer on the second conductive layer;

[0033] forming a third conductive layer on the second inorganic insulating layer, wherein the third conductive layer comprises a third conductive pattern located in the pixel area, and the third conductive pattern and the second conductive pattern constitute a second storage capacitor;

[0034] forming a third inorganic insulating layer on the third conductive layer, and forming a first through hole penetrating the third inorganic insulating layer and the second inorganic insulating layer in the pixel area by a single patterning process;

[0035] A pixel electrode layer is formed on the third inorganic insulating layer, wherein the pixel electrode layer includes a pixel electrode located in the pixel area, the pixel electrode and the third conductive pattern constitute a third storage capacitor, and the pixel electrode is electrically connected to the second conductive pattern through the first through hole.

[0036] In some embodiments, in the above manufacturing method provided in the embodiment of the present disclosure, after forming the second conductive layer on the first inorganic insulating layer and before forming the second inorganic insulating layer on the second conductive layer, the method further includes:

[0037] An organic insulating layer is formed on the second conductive layer. The organic insulating layer includes a second through hole located in the pixel area. The second through hole is conductively connected to the first through hole.

[0038] In some embodiments, in the above manufacturing method provided by the embodiments of the present disclosure, while forming the first conductive pattern located in the pixel area on the base substrate, the method further includes: forming a first connecting line extending along a first direction and integrally provided with the first conductive pattern on the first conductive layer;

[0039] Forming a first inorganic insulating layer on the first conductive layer specifically includes: forming a third through hole penetrating the first inorganic insulating layer in the non-display area;

[0040] While forming a second conductive pattern located in the pixel area on the first inorganic insulating layer, the method further includes: forming a second connecting line extending along a second direction and integrally arranged with the second conductive pattern on the second conductive layer, wherein the second direction intersects the first direction;

[0041] While forming a first through hole penetrating the third inorganic insulating layer and the second inorganic insulating layer in the pixel area, the invention further comprises: forming a fourth through hole penetrating the third inorganic insulating layer and the second inorganic insulating layer in the non-display area, and a fifth through hole penetrating only the third inorganic insulating layer in the non-display area, wherein the fourth through hole is conductively connected to the third through hole;

[0042] While forming a pixel electrode located in the pixel area on the third inorganic insulating layer, it also includes: forming a wiring located in the pixel electrode layer in the non-display area, the wiring is electrically connected to the first connecting line through the third through hole and the fourth through hole, and the wiring is electrically connected to the second connecting line through the fifth through hole.

[0043] In some embodiments, in the above manufacturing method provided in the embodiment of the present disclosure, after forming the second conductive layer on the first inorganic insulating layer and before forming the second inorganic insulating layer on the second conductive layer, the method further includes:

[0044] An organic insulating layer is formed on the second conductive layer, the organic insulating layer includes a second through hole located in the pixel area, and a sixth through hole located in the non-display area, the second through hole is conductively connected to the first through hole, and the sixth through hole is conductively connected to the third through hole and the fourth through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure;

[0046] Figure 2 For along Figure 1 Schematic diagram of four pixel areas;

[0047] Figure 3 for Figure 2 A schematic structural diagram of the first conductive layer;

[0048] Figure 4 for Figure 2 A schematic structural diagram of the second conductive layer;

[0049] Figure 5 for Figure 2 A schematic diagram of the structure of the third conductive layer;

[0050] Figure 6 for Figure 2 A schematic diagram of the structure of the pixel electrode layer;

[0051] Figure 7 for Figure 2 A schematic diagram of the structure of the active layer and the insulating layer;

[0052] Figure 8 For along Figure 2 A schematic cross-sectional view of the middle II line;

[0053] Fig. 9 For along Figure 2 Another schematic cross-section of the middle II line;

[0054] Fig.10 A schematic cross-sectional view of a display substrate in a non-display area provided by an embodiment of the present disclosure;

[0055] Fig.11 Another schematic cross-sectional view of a display substrate in a non-display area provided by an embodiment of the present disclosure;

[0056] Fig.12 is a cross-sectional schematic diagram of a display substrate in the related art;

[0057] Fig.13 A schematic diagram of a structure of a display device provided in an embodiment of the present disclosure;

[0058] Fig.14 A schematic diagram of another structure of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solution and advantages of the embodiment of the present disclosure clearer, the technical solution of the embodiment of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiment of the present disclosure. It should be noted that the size and shape of each figure in the drawings do not reflect the actual proportion, and the purpose is only to illustrate the content of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0060] Unless otherwise defined, the technical or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0061] With the development of display technology, the market demand for high-resolution (PPI) and full-color electronic paper (EPD) is becoming stronger and stronger. However, as the resolution increases, the pixel size becomes smaller and smaller, and the overlapping area of ​​the storage capacitor becomes smaller and smaller, so the storage capacitor becomes smaller and smaller. The two storage capacitors used in the related technology still cannot meet the EPD product's demand for holding voltage.

[0062] In order to solve the above technical problems existing in the related art, the present disclosure provides a display substrate, such as Figures 1 to 8 As shown, including:

[0063] A first base substrate 101, wherein the first base substrate 101 comprises a display area AA, and a plurality of pixel areas P are arranged in the display area AA;

[0064] At least four conductive layers (e.g., a first conductive layer 102, a second conductive layer 103, a third conductive layer 104, and a pixel electrode layer 105) are stacked and arranged on the first substrate 101. Any two adjacent conductive layers are insulated from each other. Each conductive layer includes a conductive pattern (e.g., a first conductive pattern 1021, a second conductive pattern 1031, a third conductive pattern 1041, and a pixel electrode 1051) located in each pixel region P. The conductive patterns of any two adjacent conductive layers in the same pixel region P form a storage capacitor (e.g., a first storage capacitor Cst 1 , the second storage capacitor Cst 2 , the third storage capacitor Cst 3 ), in a direction Z perpendicular to the base substrate, the projections of the at least four conductive layers mentioned above overlap on the first base substrate 101.

[0065] In the above-mentioned display substrate provided in the embodiment of the present disclosure, by setting conductive patterns in at least four conductive layers, and setting the conductive patterns of any two adjacent conductive layers to overlap with each other to form a storage capacitor, each pixel area P has at least three storage capacitors, thereby effectively increasing the capacitance value of each pixel area P, which is beneficial to maintaining voltage stability.

[0066] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, if Figures 2 to 8 As shown, the at least four conductive layers may include a first conductive layer 102, a second conductive layer 103, a third conductive layer 104 and a pixel electrode layer 105, wherein the first conductive layer 102 includes a first conductive pattern 1021, the second conductive layer 103 includes a second conductive pattern 1031, the third conductive layer 104 includes a third conductive pattern 1041, and the pixel electrode layer 105 includes a pixel electrode 1051. Figure 2The area surrounded by a thick solid line frame represents a pixel electrode 1051; the first conductive pattern 1021 and the second conductive pattern 1031 constitute a first storage capacitor Cst 1 The second conductive pattern 1031 and the third conductive pattern 1041 constitute a second storage capacitor Cst 2 The third conductive pattern 1041 and the pixel electrode 1051 constitute a third storage capacitor Cst 3 , and the first conductive pattern 1021 is electrically connected to the third conductive pattern 1041, and the second conductive pattern 1031 is electrically connected to the pixel electrode 1051, so that the first storage capacitor Cst 1 , the second storage capacitor Cst 2 , the third storage capacitor Cst 3 The three are connected in parallel, and the capacitance value in each pixel area P is the first storage capacitor Cst 1 The capacitance value of the second storage capacitor Cst 2 The capacitance value of the third storage capacitor Cst 3 The capacitance value of each pixel area P is effectively increased by adding the capacitance values ​​of the pixels.

[0067] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, if Figure 8 and Fig. 9 As shown, it may also include a first insulating layer 106, a second insulating layer 107 and a third insulating layer 108, wherein the first insulating layer 106 is located between the first conductive layer 102 and the second conductive layer 103, the second insulating layer 107 is located between the second conductive layer 103 and the third conductive layer 104, and the third insulating layer 108 is located between the third conductive layer 104 and the pixel electrode layer 105, so that the first conductive layer 102 and the second conductive layer 103 are insulated by the first insulating layer 106, the second conductive layer 103 and the third conductive layer 104 are insulated by the second insulating layer 107, and the third conductive layer 104 and the pixel electrode layer 105 are insulated by the third insulating layer 108.

[0068] Optionally, the first insulating layer 106 is a first inorganic insulating layer, the second insulating layer 107 is a second inorganic insulating layer 1071, and the third insulating layer 108 is a third inorganic insulating layer; or, the first insulating layer 106 is a first inorganic insulating layer, the third insulating layer 108 is a third inorganic insulating layer, and the second insulating layer 107 includes a second inorganic insulating layer 1071 and an organic insulating layer 1072 stacked together, and the second inorganic insulating layer 1071 is located between the organic insulating layer 1072 and the third insulating layer 108. The calculation formula for the capacitance value C is C=ε*s / d, where ε represents the dielectric constant of the insulating layer, S represents the facing area of ​​the two electrodes in the storage capacitor, and d is the thickness of the insulating layer. It can be seen from the capacitance calculation formula that the smaller the thickness of the insulating layer, the larger the capacitance value of the storage capacitor. Therefore, the second storage capacitor Cst 2 The capacitance value of the organic insulating layer 107 is larger when the second insulating layer 107 includes only the second inorganic insulating layer 1071 than when the second insulating layer 107 includes the second inorganic insulating layer 1071 and the organic insulating layer 1072 .

[0069] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, if Figure 8 and Fig. 9 As shown, the second insulating layer 107 and the third insulating layer 108 may include through holes. Figure 8 The middle through hole is a first through hole that penetrates the second inorganic insulating layer 1071 and the third insulating layer 108. 1 .exist Fig. 9 The through hole is connected by the first through hole h 1 and the second through hole h 2 Composition, wherein the first through hole h 1 The second through hole h penetrates the second inorganic insulating layer 1071 and the third insulating layer 108. 2 The pixel electrode 1051 passes through the organic insulating layer 1072. Figure 8 The first through hole h 1 ,or Fig. 9 The first through hole h 1 and the second through hole h 2 ) is electrically connected to the second conductive pattern 1031. Since the materials of the second inorganic insulating layer 1071 and the third insulating layer 108 are both inorganic insulating materials, a first through hole h that penetrates the second inorganic insulating layer 1071 and the third insulating layer 108 can be formed simultaneously through a single patterning (mask) process. 1 Compared with the solution of separately patterning the second inorganic insulating layer 1071 and the third insulating layer 108 to form through holes, a patterning process can be saved, which is beneficial to improving production efficiency and reducing production costs.

[0070] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, if Figure 8 and Fig. 9 As shown, in order to facilitate the electrical connection between the pixel electrode 1051 and the second conductive pattern 1031, a hollow structure K can be provided in the third conductive pattern 1041, and the orthographic projection of the hollow structure K on the first base substrate 101 covers the through hole (for example Figure 8 The first through hole h 1 ,or Fig. 9 The first through hole h 1 and the second through hole h 2 ) is an orthographic projection on the first substrate 101.

[0071] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, if Figures 1 to 3 , Figure 5 , Fig.10 and Fig.11 As shown, the first base substrate 101 may further include a non-display area BB surrounding the display area AA; the first conductive layer 102 may further include a first connecting line 1022, the first connecting line 1022 extends along the first direction X, and the first connecting line 1022 is integrally arranged with the first conductive pattern 1021; the third conductive layer 104 may further include a second connecting line 1042, the second connecting line 1042 extends along the second direction Y, and the second connecting line 1042 is integrally arranged with the third conductive pattern 1041, and the second direction Y is intersected with the first direction X; the pixel electrode layer 105 may further include a routing line 1052 located in the non-display area BB, the routing line 1052 surrounds the display area AA and is electrically connected to the first connecting line 1022 and the second connecting line 1042, respectively, so that the jumper connection between the first connecting line 1022 and the second connecting line 1042 is realized by the routing line 1052 in the pixel electrode layer 105, thereby realizing the electrical connection between the first conductive pattern 1021 and the third conductive pattern 1041.

[0072] Alternatively, if Fig.10 As shown, in the case where the second insulating layer 107 only includes the second inorganic insulating layer 1071, a third through hole h penetrating the first insulating layer 106 may be formed in the non-display area BB. 3 Then, a first through hole h is formed in the display area AA through the second inorganic insulating layer 1071 and the third insulating layer 108. 1 At the same time, a third through hole h is formed in the non-display area BB, penetrating the second inorganic insulating layer 1071 and the third insulating layer 108 and connecting with the third through hole h 3 The fourth through hole h 4 , and a fifth through hole h that only penetrates the third insulating layer 108 5 , so that the trace 1052 passes through the conductive third through hole h 3and the fourth through hole h 4 The wiring 1052 is electrically connected to the first connection line 1022 and passes through the fifth through hole h 5 Electrically connected to the second connection line 1042 .

[0073] Alternatively, if Fig.11 As shown, in the case where the second insulating layer 107 includes an organic insulating layer 1072 and a second inorganic insulating layer 1071 stacked, a third through hole h penetrating the first insulating layer 106 may be formed in the non-display area BB. 3 Then, a third through hole h is formed in the non-display area BB through the organic insulating layer 1072 and connected to the third through hole h 3 The sixth through hole h 6 ; Then, a first through hole h is formed in the display area AA through the second inorganic insulating layer 1071 and the third insulating layer 108 1 At the same time, a sixth through hole h is formed in the non-display area BB through the second inorganic insulating layer 1071 and the third insulating layer 108. 6 The fourth through hole h 4 , and a fifth through hole h that only penetrates the third insulating layer 108 5 , so that the trace 1052 passes through the conductive third through hole h 3 , the sixth through hole h 6 , and the fourth through hole h 4 The wiring 1052 is electrically connected to the first connection line 1022 and passes through the fifth through hole h 5 Electrically connected to the second connection line 1042 .

[0074] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, if Figure 3 , Figure 4 , Figure 8 and Fig. 9 As shown, a transistor TFT located in the pixel area P may also be included, the gate g of the transistor TFT may be located in the first conductive layer 102, and the first electrode d and the second electrode s of the transistor TFT may be located in the second conductive layer 103. By using the first conductive layer 102 to prepare the gate g and the first conductive pattern 1021, it is avoided to add a film layer of the first conductive pattern 1021 separately, and the preparation of the gate g and the first conductive pattern 1021 can be completed through a single patterning process, avoiding the addition of a patterning process of the first conductive pattern 1021 separately, thus, it is conducive to simplifying the manufacturing process and realizing a light and thin design. Based on similar reasons, by using the second conductive layer 103 to prepare the first electrode d, the second electrode s and the second conductive pattern 1031, it is also conducive to simplifying the manufacturing process and realizing a light and thin design.

[0075] In addition, the transistor TFT mentioned in the embodiment of the present disclosure may be a thin film transistor or a metal oxide semiconductor field effect transistor, which is not limited here. Moreover, the transistor TFT may be a P-type transistor or an N-type transistor. The transistor TFT may be a top-gate transistor or a bottom-gate transistor. The first electrode d and the second electrode s of the transistor TFT are the source and the drain, respectively. In practical applications, depending on the type of transistor and the input signal, the functions of the first electrode d and the second electrode s may be interchangeable without specific distinction.

[0076] Optionally, a gate line GL extending along the first direction X may be provided in the first conductive layer 102, and a data line DL extending along the second direction Y may be provided in the second conductive layer 103. The gate line GL and the data line DL intersect to define a pixel region P, and the conductive patterns of each conductive layer (e.g., the first conductive pattern 1021, the second conductive pattern 1031, the third conductive pattern 1041, and the pixel electrode 1051) may be at least partially located in the pixel region P. In some embodiments, in order to prevent the conductive patterns (e.g., the first conductive pattern 1021, the second conductive pattern 1031, the third conductive pattern 1041, and the pixel electrode 1051) from overlapping with the gate line GL and / or the data line DL to form an electric field affecting the electrophoretic layer, the conductive patterns of each conductive layer (e.g., the first conductive pattern 1021, the second conductive pattern 1031, the third conductive pattern 1041, and the pixel electrode 1051) are preferably all located in the pixel region P, such as Figure 2 shown.

[0077] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, if Figures 2 to 9 As shown, the material of the third conductive layer 104 may be metal, and the orthographic projection of the third conductive pattern 1041 on the first base substrate 101 may at least cover the orthographic projection of the channel region of the transistor TFT (i.e., the region between the first electrode d and the second electrode s) on the first base substrate 101. Optionally, the material of the third conductive layer 104 may be a light shielding metal (TPM), so that when the orthographic projection of the third conductive pattern 1041 on the first base substrate 101 at least covers the orthographic projection of the channel region of the transistor TFT (i.e., the region between the first electrode d and the second electrode s) on the first base substrate 101, light can be effectively blocked to prevent light from irradiating the channel region of the transistor TFT and generating leakage current, thereby ensuring the stability of the transistor TFT.

[0078] In some embodiments, in the above display device provided by the embodiments of the present disclosure, if Figures 2 to 9As shown, the orthographic projection of the first conductive pattern 1021 on the first substrate 101 half surrounds the orthographic projection of the transistor TFT on the first substrate 101, so that on the one hand, the area of ​​the first conductive pattern 1021 can be larger, so that the first conductive pattern 1021 and the second conductive pattern 1031 form a first storage capacitor Cst 1 On the other hand, it avoids the first conductive pattern 1021 and the transistor TFT from overlapping each other to cause coupling capacitance, so that the signal on the first conductive pattern 1021 and the signal on the transistor TFT interfere with each other.

[0079] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, if Figures 2 to 9 As shown, the orthographic projection of the second conductive pattern 1031 on the first base substrate 101 overlaps with the orthographic projection of the first conductive pattern 1021 on the first base substrate 101, so that a second storage capacitor Cst can be formed between the first conductive pattern 1021 and the second conductive pattern 1031. 2 Optionally, in order to make the second storage capacitor Cst 2 The capacitance value is relatively large, and the orthographic projection of the second conductive pattern 1031 on the first base substrate 101 can roughly coincide with the orthographic projection of the first conductive pattern 1021 on the first base substrate 101, that is, the two coincide exactly or are within the error range caused by factors such as manufacturing and measurement. In some embodiments, the second conductive pattern 1031 can be integrally provided with the first electrode d of the transistor, so that the signal of the transistor TFT is transmitted to the pixel electrode 1051 via the second conductive pattern 1031.

[0080] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, if Figures 2 to 9 As shown, the positive projection of the pixel electrode 1051 on the first substrate 101 can completely cover the positive projection of the transistor TFT on the first substrate 101, so that the pixel electrode 1051 and the third conductive pattern 1041 have a sufficiently large positive facing area to form a third storage capacitor Cst with a large capacitance value. 3 At the same time, the larger area of ​​the pixel electrode 1051 can better control the electrophoretic layer and improve the display quality.

[0081] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, if Figure 8 and Fig. 9 As shown, a buffer layer 109 may also be included. Other essential components of the display substrate are well understood by those skilled in the art, and are not described in detail herein, nor should they be used as limitations to the present disclosure.

[0082] like Fig.12As shown, in the related art, the storage capacitor of each pixel region P is composed of a fourth storage capacitor Cst 4 and the fifth storage capacitor Cst 5 The fourth storage capacitor Cst 4 The fourth conductive pattern C is provided in the same layer as the gate electrode g of the transistor TFT. 1 , and a fifth conductive pattern C disposed in the same layer as the first electrode d and the second electrode s of the transistor TFT 2 The fourth conductive pattern C 1 and the fifth conductive pattern C 2 A first insulating layer 106 is provided between the first and second storage capacitors Cst. 5 The fifth conductive pattern C is provided in the same layer as the first electrode d and the second electrode s of the transistor TFT. 2 , and a sixth conductive pattern C located in the third conductive layer 104 and the pixel electrode layer 105 3 The fifth conductive pattern C 2 The sixth conductive pattern C 3 A second inorganic insulating layer 1071 and an organic insulating layer 1072 are provided therebetween.

[0083] In addition, taking the size (pitch) of the pixel region P as 60 μm as an example, the present disclosure also provides Fig. 9 The storage capacitor of the display substrate is shown in FIG. Fig.12 The relevant data of the storage capacitor in the related art shown. Specifically, Table 1 shows the parameters of each insulating layer, where GI represents the first insulating layer 106, PVX1 represents the second inorganic insulating layer 1071, PVX2 represents the third insulating layer 108, and Resin represents the organic insulating layer 1072. Table 2 shows the comparative data of the storage capacitor. It can be seen from Table 2 that the total capacitance value of a pixel area P in the present disclosure is 0.7186pF, which is within the range of 0.6pF to 1pF required to maintain the voltage. And compared with the total capacitance value of 0.1746pF in the related art, it has increased by about 311.6%. Therefore, the present disclosure Fig. 9 The structure shown can effectively meet the requirement of maintaining voltage.

[0084] Table 1

[0085]

[0086] Table 2

[0087]

[0088] Based on the same inventive concept, an embodiment of the present disclosure provides a method for manufacturing the above-mentioned display substrate. Since the principle of solving the problem by the manufacturing method is similar to the principle of solving the problem by the above-mentioned display substrate, the implementation of the manufacturing method provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned display substrate provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0089] Specifically, the present disclosure provides a method for manufacturing the display substrate, comprising the following steps:

[0090] Provide a substrate, the substrate comprising a display area, the display area comprising a plurality of pixel areas;

[0091] At least four conductive layers are stacked on the base substrate, any two adjacent conductive layers are insulated from each other, each conductive layer includes a conductive pattern located in each pixel area, and the conductive patterns of any two adjacent conductive layers in the same pixel area constitute a storage capacitor. In a direction perpendicular to the base substrate, the projections of at least four conductive layers on the base substrate overlap.

[0092] In some embodiments, in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, at least four conductive layers are stacked on the base substrate, any two adjacent conductive layers are insulated from each other, each conductive layer includes a conductive pattern located in each pixel area, and the conductive patterns of any two adjacent conductive layers in the same pixel area constitute a storage capacitor. In the direction perpendicular to the base substrate, the projections of at least four conductive layers on the base substrate overlap, which can be specifically achieved in the following manner:

[0093] Forming a first conductive layer on the base substrate, the first conductive layer comprising a first conductive pattern located in the pixel area;

[0094] forming a first inorganic insulating layer on the first conductive layer;

[0095] forming a second conductive layer on the first inorganic insulating layer, wherein the second conductive layer comprises a second conductive pattern located in the pixel area, and the second conductive pattern and the first conductive pattern constitute a first storage capacitor;

[0096] forming a second inorganic insulating layer on the second conductive layer;

[0097] forming a third conductive layer on the second inorganic insulating layer, wherein the third conductive layer includes a third conductive pattern located in the pixel area, and the third conductive pattern and the second conductive pattern constitute a second storage capacitor;

[0098] forming a third inorganic insulating layer on the third conductive layer, and forming a first through hole penetrating the third inorganic insulating layer and the second inorganic insulating layer in the pixel area by a single patterning process;

[0099] A pixel electrode layer is formed on the third inorganic insulating layer, the pixel electrode layer includes a pixel electrode located in the pixel area, the pixel electrode and the third conductive pattern constitute a third storage capacitor, and the pixel electrode is electrically connected to the second conductive pattern through the first through hole.

[0100] In some embodiments, in the above-mentioned manufacturing method provided by the embodiment of the present disclosure, after forming the second conductive layer on the first inorganic insulating layer and before forming the second inorganic insulating layer on the second conductive layer, the following steps may be further performed:

[0101] An organic insulating layer is formed on the second conductive layer. The organic insulating layer includes a second through hole located in the pixel area. The second through hole is conductively connected to the first through hole, so that the pixel electrode is electrically connected to the second conductive pattern through the first through hole and the second through hole.

[0102] It should be noted that in the present disclosure, whether the first inorganic insulating layer, the second inorganic insulating layer, the third inorganic insulating layer or the organic insulating layer, all serve to provide insulation. Therefore, in some embodiments, the inorganic insulating layer in the present disclosure may be replaced by an organic insulating layer, and the organic insulating layer may also be replaced by an inorganic insulating layer, which is not specifically limited here. Furthermore, in order to reduce the number of masking operations, it is necessary to ensure that the third inorganic insulating layer and the second inorganic insulating layer are made of the same material, for example, both may be made of inorganic insulating materials, or both may be replaced by organic insulating materials.

[0103] In some embodiments, in the above manufacturing method provided by the embodiments of the present disclosure, while forming the first conductive pattern located in the pixel area on the base substrate, a first connecting line extending along the first direction and integrally provided with the first conductive pattern may also be formed in the first conductive layer;

[0104] Forming a first inorganic insulating layer on the first conductive layer can be achieved in the following manner: forming a third through hole penetrating the first inorganic insulating layer in the non-display area;

[0105] While forming a second conductive pattern located in the pixel area on the first inorganic insulating layer, a second connecting line extending along a second direction and integrally arranged with the second conductive pattern may also be formed on the second conductive layer, wherein the second direction intersects the first direction;

[0106] While forming a first through hole penetrating the third inorganic insulating layer and the second inorganic insulating layer in the pixel area, a fourth through hole penetrating the third inorganic insulating layer and the second inorganic insulating layer may be formed in the non-display area, and a fifth through hole penetrating only the third inorganic insulating layer in the non-display area, wherein the fourth through hole is conductively connected to the third through hole;

[0107] While forming a pixel electrode located in the pixel area on the third inorganic insulating layer, a wiring located in the pixel electrode layer can also be formed in the non-display area. The wiring is electrically connected to the first connecting line through the third through hole and the fourth through hole, and the wiring is electrically connected to the second connecting line through the fifth through hole.

[0108] In some embodiments, in the above-mentioned manufacturing method provided by the embodiment of the present disclosure, after forming the second conductive layer on the first inorganic insulating layer and before forming the second inorganic insulating layer on the second conductive layer, an organic insulating layer can also be formed on the second conductive layer, the organic insulating layer including a second through hole located in the pixel area, and a sixth through hole located in the non-display area, the second through hole is conductively connected to the first through hole, and the sixth through hole is conductively connected to the third through hole and the fourth through hole, so that the wiring is electrically connected to the first connecting line through the third through hole, the sixth through hole, and the fourth through hole, and the wiring is electrically connected to the second connecting line through the fifth through hole.

[0109] Based on the same inventive concept, an embodiment of the present disclosure provides a display device. Since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned display substrate, the implementation of the display device provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned display substrate provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0110] Specifically, an embodiment of the present disclosure provides a display device, such as Fig.12 and Fig.13 As shown, it includes a display substrate 001 and an opposite substrate 002 that are opposite to each other, and a dimming layer 003 located between the display substrate 001 and the opposite substrate 002, wherein the display substrate 001 is the above-mentioned display substrate provided in the embodiment of the present disclosure.

[0111] In some embodiments, in the above-mentioned display device provided by the embodiments of the present disclosure, the opposing substrate 002 may include a second base substrate 201, and a common electrode 202 located on the side of the second base substrate 201 facing the dimming layer 003. Optionally, the common electrode 202 may be electrically connected to the first conductive pattern 1021 and the third conductive pattern 1041 through conductive silver paste, so that the common electrode 202, the first conductive pattern 1021 and the third conductive pattern 1041 are loaded with the same common voltage electrical signal (Vcom).

[0112] In some embodiments, in the display device provided in the embodiments of the present disclosure, the dimming layer 003 may be an electrophoretic layer (eg Fig.13 and Fig.14 In the present disclosure, the dimming layer 003 is described as an electrophoretic layer. Specifically, Fig.13 and Fig.14As shown, the electrophoretic layer 003 may include: a plurality of electrophoretic particles 301, each of which may include: a particle body, and an electrophoretic liquid and charged particles located in the particle body, and the charged particles may include: black particles, white particles, and colored particles, etc. The driving of the electrophoretic particles includes: a reverse phase, an up and down shaking phase, and a writing phase. The purpose of the reverse phase is to maintain charge conservation, the up and down shaking phase is to eliminate the influence of the previous frame on the next frame, and the writing phase is based on the picture to be written. For example, for a black picture, the writing voltage is 15V, so the common voltage is generally around 0V. The scanning signal on the gate line DL gives a start voltage of 20V, and the data signal on the data line DL gives 15V, which is transmitted to the pixel electrode 1051 through the transistor TFT, so that the pixel electrode 1051 and the common electrode 202 form an electric field to drive the black particles to move upward. Generally, multiple frames of driving are required to make the electrophoretic particles 301 display uniform and stable black. Between multiple frames of driving, the storage capacitor plays a role in maintaining the pixel voltage. Generally, the larger the storage capacitor, the better the maintenance. However, too large a storage capacitor will affect the pixel charging, so the reader product is generally between 0.1pF and 1.2pF. When the power is turned off after several frames are written, the electrophoretic particles 301 can maintain their original position unchanged through the buoyancy and viscosity in the electrophoretic liquid, thereby saving power and using ambient light to display eye protection.

[0113] In some embodiments, the display device provided in the embodiment of the present disclosure may also include, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a user input unit, an interface unit, a memory, a processor, and a power supply. In addition, it can be understood by those skilled in the art that the above structure does not constitute a limitation on the display device provided in the embodiment of the present disclosure. In other words, the display device provided in the embodiment of the present disclosure may include more or less of the above components, or combine certain components, or arrange the components differently.

[0114] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A display substrate, wherein: include: A base substrate, the base substrate comprising a display area, the display area comprising a plurality of pixel areas; At least four conductive layers are stacked and located on the base substrate, any two adjacent conductive layers are insulated from each other, each conductive layer includes a conductive pattern located in each pixel area, and in a direction perpendicular to the base substrate, the projections of the at least four conductive layers on the base substrate overlap, The at least four conductive layers include a first conductive layer, a second conductive layer, a third conductive layer and a pixel electrode layer, wherein: The first conductive layer includes a first conductive pattern, the second conductive layer includes a second conductive pattern, the third conductive layer includes a third conductive pattern, and the pixel electrode layer includes a pixel electrode; The first conductive pattern and the second conductive pattern constitute a first storage capacitor, the second conductive pattern and the third conductive pattern constitute a second storage capacitor, the third conductive pattern and the pixel electrode constitute a third storage capacitor, and the first conductive pattern is electrically connected to the third conductive pattern, and the second conductive pattern is electrically connected to the pixel electrode; It also includes a transistor located in the pixel area, wherein the gate of the transistor is located in the first conductive layer, and the first electrode and the second electrode of the transistor are located in the second conductive layer; The orthographic projection of the first conductive pattern on the substrate half surrounds the orthographic projection of the transistor on the substrate; The orthographic projection of the pixel electrode on the base substrate completely covers the orthographic projection of the transistor on the base substrate.

2. The display substrate according to claim 1, wherein: It also includes a first insulating layer, a second insulating layer and a third insulating layer, wherein the first insulating layer is located between the first conductive layer and the second conductive layer, the second insulating layer is located between the second conductive layer and the third conductive layer, and the third insulating layer is located between the third conductive layer and the pixel electrode layer.

3. The display substrate according to claim 2, wherein: The second insulating layer and the third insulating layer include through holes extending therethrough, and the pixel electrode is electrically connected to the second conductive pattern via the through holes.

4. The display substrate according to claim 3, wherein: The third conductive pattern includes a hollow structure, and the orthographic projection of the hollow structure on the base substrate covers the orthographic projection of the through hole on the base substrate.

5. The display substrate according to any one of claims 1 to 4, wherein: The base substrate also includes a non-display area surrounding the display area; The first conductive layer further includes a first connecting line, the first connecting line extends along a first direction, and the first connecting line is integrally arranged with the first conductive pattern; The third conductive layer further includes a second connecting line, the second connecting line extends along a second direction, and the second connecting line is integrally arranged with the third conductive pattern, and the second direction is arranged to intersect with the first direction; The pixel electrode layer further includes a wiring located in the non-display area, wherein the wiring surrounds the display area and is electrically connected to the first connection line and the second connection line respectively.

6. The display substrate according to claim 1, wherein: The third conductive layer is metal, and the orthographic projection of the third conductive pattern on the substrate at least covers the orthographic projection of the channel region of the transistor on the substrate.

7. The display substrate according to claim 1, wherein: The orthographic projection of the second conductive pattern on the base substrate overlaps with the orthographic projection of the first conductive pattern on the base substrate, and the second conductive pattern is integrally arranged with the first electrode of the transistor.

8. A display device, wherein: The invention comprises a display substrate and an opposite substrate which are arranged opposite to each other, and a dimming layer located between the display substrate and the opposite substrate, wherein the display substrate is the display substrate according to any one of claims 1 to 7.

9. The display device according to claim 8, wherein: The opposite substrate includes a common electrode, and the common electrode, the first conductive pattern, and the third conductive pattern are loaded with the same electrical signal.

10. The display device according to claim 8 or 9, wherein: The dimming layer is an electrophoretic layer or a liquid crystal layer.

11. A method for manufacturing a display substrate according to any one of claims 1 to 7, wherein: include: Providing a substrate, the substrate comprising a display area, the display area comprising a plurality of pixel areas; Forming a first conductive layer on the base substrate, wherein the first conductive layer includes a first conductive pattern located in the pixel area; forming a first inorganic insulating layer on the first conductive layer; forming a second conductive layer on the first inorganic insulating layer, wherein the second conductive layer comprises a second conductive pattern located in the pixel area, and the second conductive pattern and the first conductive pattern constitute a first storage capacitor; forming a second inorganic insulating layer on the second conductive layer; forming a third conductive layer on the second inorganic insulating layer, wherein the third conductive layer comprises a third conductive pattern located in the pixel area, and the third conductive pattern and the second conductive pattern constitute a second storage capacitor; forming a third inorganic insulating layer on the third conductive layer, and forming a first through hole penetrating the third inorganic insulating layer and the second inorganic insulating layer in the pixel area by a single patterning process; forming a pixel electrode layer on the third inorganic insulating layer, wherein the pixel electrode layer includes a pixel electrode located in the pixel area, the pixel electrode and the third conductive pattern constitute a third storage capacitor, and the pixel electrode is electrically connected to the second conductive pattern through the first through hole; In a direction perpendicular to the base substrate, projections of the at least four conductive layers on the base substrate overlap; The display substrate further comprises a transistor located in the pixel area, a gate of the transistor is located in the first conductive layer, and a first electrode and a second electrode of the transistor are located in the second conductive layer; The orthographic projection of the first conductive pattern on the substrate half surrounds the orthographic projection of the transistor on the substrate; The orthographic projection of the pixel electrode on the base substrate completely covers the orthographic projection of the transistor on the base substrate.

12. The method according to claim 11, wherein: After forming a second conductive layer on the first inorganic insulating layer and before forming a second inorganic insulating layer on the second conductive layer, the method further includes: An organic insulating layer is formed on the second conductive layer. The organic insulating layer includes a second through hole located in the pixel area. The second through hole is conductively connected to the first through hole.

13. The method according to claim 11, wherein: While forming a first conductive pattern located in the pixel area on the base substrate, the method further includes: forming a first connecting line extending along a first direction and integrally provided with the first conductive pattern on the first conductive layer; Forming a first inorganic insulating layer on the first conductive layer specifically includes: forming a third through hole penetrating the first inorganic insulating layer in the non-display area; While forming a second conductive pattern located in the pixel area on the first inorganic insulating layer, the method further includes: forming a second connecting line extending along a second direction and integrally arranged with the second conductive pattern on the second conductive layer, wherein the second direction intersects the first direction; While forming a first through hole penetrating the third inorganic insulating layer and the second inorganic insulating layer in the pixel area, the invention further comprises: forming a fourth through hole penetrating the third inorganic insulating layer and the second inorganic insulating layer in the non-display area, and a fifth through hole penetrating only the third inorganic insulating layer in the non-display area, wherein the fourth through hole is conductively connected to the third through hole; While forming a pixel electrode located in the pixel area on the third inorganic insulating layer, it also includes: forming a wiring located in the pixel electrode layer in the non-display area, the wiring is electrically connected to the first connecting line through the third through hole and the fourth through hole, and the wiring is electrically connected to the second connecting line through the fifth through hole.

14. The method of claim 13, wherein: After forming a second conductive layer on the first inorganic insulating layer and before forming a second inorganic insulating layer on the second conductive layer, the method further includes: An organic insulating layer is formed on the second conductive layer, the organic insulating layer includes a second through hole located in the pixel area, and a sixth through hole located in the non-display area, the second through hole is conductively connected to the first through hole, and the sixth through hole is conductively connected to the third through hole and the fourth through hole.

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