Verification response method of consumable chip, verification method of consumable container

Abstract

The application provides a verification response method of a consumable chip and a verification method of a consumable container. The verification response method comprises the following steps: the consumable chip receives a verification instruction, determines a verification period of a verification response signal according to the verification instruction, and confirms a verification level of each verification period; a high-level signal is output in a verification period with an initial verification level being a high level, and a high-impedance state is set in at least one verification period with an initial verification level being a low level. The verification method of the consumable container comprises the following steps: a printing device sends a verification instruction to at least one consumable container; after the consumable chip of the consumable container receives the verification instruction, the verification response method of the consumable chip is performed; after the printing device receives the verification response signal sent by the consumable chip, the state of the consumable container is determined according to the received verification response signal. The application can simplify the control logic of the consumable chip in response to the verification instruction, reduce the difficulty in implementing the control logic of the consumable chip, and reduce the production cost.

Description

Technical Field

[0001] This invention relates to the technical field of printing equipment, and more specifically, to a verification response method for consumable chips on a printing device, and also to a verification method for consumable containers. Background Technology

[0002] Printing equipment, as a common office tool, provides great convenience for modern offices. Common printing equipment is divided into inkjet printers and laser printers. Inkjet printers use ink cartridges containing ink as consumable containers to spray ink onto paper to form the text or pattern to be printed on the paper; laser printers use toner cartridges containing toner as consumable containers to form the text or pattern to be printed on the medium.

[0003] See Figure 1 A color inkjet printing device has a housing 11. Figure 1 The inkjet printer shown omits the tray of the housing 11. The housing 11 houses the inkjet printer's mechanism 12 and includes a slide bar. The printing carriage 14 is mounted on a motor (…). Figure 1 Driven by the invisible component, it reciprocates along the slide bar. The printing carriage 14 contains the main control circuit board (…). Figure 1 (Not visible in the middle), the main control circuit board communicates with the mechanism 12 through the ribbon cable 13.

[0004] Multiple ink cartridges 15 are detachably mounted on the printing carriage 14, each containing ink of a different color. The structure of the ink cartridge 15 is as follows: Figure 2 As shown. The ink cartridge 15 has a housing 16, which forms a cavity for containing ink. The lower end of the cavity is provided with an ink outlet 17. The ink in the cavity flows out through the ink outlet 17 and supplies ink to the ink supply needle of the printing carriage 14.

[0005] A chip 18 is mounted on the outer wall of the cartridge body 16 of the ink cartridge 15. The chip 18 has a substrate, and one side of the substrate has multiple connection terminals 19 for electrical connection with the contact pins on the print carriage 14. The other side of the substrate has a memory (…). Figure 2 (Not visible in the image) Typically, this memory is a non-volatile memory, such as EEPROM or FLASH, which stores information related to the ink cartridge, including variable information and invariant information. Variable information is information that changes continuously with the printing operation, such as ink level, printing time, and number of sheets printed. Invariant information is information that does not change with the printing operation, such as ink cartridge model, applicable inkjet printer model, and ink color.

[0006] After ink cartridge 15 is installed into the print carriage 14 of the inkjet printer, the inkjet printer powers on the chip 18 and reads the data stored in the memory of the chip 18 to determine whether the ink cartridge 15 is the right model and whether there is enough ink remaining in the ink cartridge 15. Only after determining that the ink cartridge 15 is the right model and that there is enough ink in the ink cartridge 15 can the inkjet printer perform the printing operation.

[0007] Since the print carriage 14 typically houses multiple ink cartridges 15, the installation status of each cartridge 15 may differ. For example, some cartridges may be correctly installed, while others may not, preventing communication with the inkjet printer. Therefore, the inkjet printer needs to verify each cartridge 15, such as checking if it is correctly installed. Typically, the inkjet printer sends a verification command to each cartridge. Upon receiving the command, the cartridge must respond within a specified timeframe, sending a correct verification response signal within the designated verification period. Only when the inkjet printer receives a correct verification response signal from a cartridge within its designated verification period will it consider the cartridge correctly installed and proceed with subsequent communication operations. If the inkjet printer deems a cartridge incorrectly installed, it issues an alarm and cannot perform any further communication or printing operations.

[0008] A current inkjet printer communicates with each ink cartridge by sending a clock signal via a clock signal line, see [link to relevant documentation]. Figure 3 The clock signal SCK is a periodically changing square wave signal. Each ink cartridge chip communicates synchronously with the inkjet printer based on the clock signal SCK. When the inkjet printer sends a verification command, it sends the same level signal on the data signal line SDA for two consecutive transmission cycles. Each transmission cycle consists of nine clock cycles; for example, the first transmission cycle consists of nine clock cycles D1 to D9, and the second transmission cycle also consists of nine clock cycles D1 to D9. In the first transmission cycle, when the inkjet printer sends a verification command for the first color ink cartridge, the data signal SDA1 sent to the data signal line includes high-level signals in the first clock cycle D1, the eighth clock cycle D8, and the ninth clock cycle D9, and low-level signals in the other clock cycles. In the second transmission cycle, the inkjet printer also sends high-level signals in the first clock cycle D1, the eighth clock cycle D8, and the ninth clock cycle D9, and low-level signals in the other clock cycles. If the first color ink cartridge receives three high-level signals in three corresponding clock cycles D1, D8, and D9 within two consecutive transmission cycles, it is considered that the inkjet printer has sent a verification command for the first color ink cartridge, and a verification response signal needs to be sent within the specified verification period.

[0009] See Figure 4In the existing technical solution, the verification period corresponding to the first color ink cartridge is the latter half of the eighth clock cycle within the first response cycle and the entire period of the eighth clock cycle within the second response cycle. Based on half a clock cycle, the verification period corresponding to the first ink cartridge can include three verification periods, namely verification periods T1, T2, and T3. Among them, verification period T1 is the latter half of the eighth clock cycle within the first response cycle, verification period T2 is the first half of the eighth clock cycle within the second response cycle, and verification period T3 is the latter half of the eighth clock cycle within the second response cycle.

[0010] from Figure 4 It can be seen that during the first verification period T1, the ink cartridge needs to output a low-level signal to the data signal line; during the first verification period T2, the ink cartridge needs to output a high-level signal to the data signal line; and during the first verification period T3, the ink cartridge needs to output a low-level signal to the data signal line. During other time periods, since the inkjet printer does not detect the level of the data signal line SDA1, the ink cartridge does not need to output a level to the data signal line. At this time, the data signal line exhibits a high-impedance state, i.e. Figure 4 The area indicated by the dotted line. If the ink cartridge fails to output the corresponding level signal as described above, the inkjet printer will consider it incorrectly installed, affecting subsequent communication operations.

[0011] For the second color ink cartridge, the verification command sent by the inkjet printer is a high-level signal sent during the first transmission cycle of the data signal SDA2, the first clock cycle D1 of the second transmission cycle, the seventh clock cycle D7, and the ninth clock cycle D9. The three verification periods T1, T2, and T3 of the second color ink cartridge are the latter half of the seventh clock cycle in the first response cycle, the first half of the seventh clock cycle in the second response cycle, and the latter half of the seventh clock cycle in the second response cycle, respectively. The level signals of the three verification periods are low level, high level, and low level, respectively.

[0012] Similarly, for the third color ink cartridge, the verification command sent by the inkjet printer is a high-level signal sent during the first transmission cycle of data signal SDA3, the first clock cycle D1 of the second transmission cycle, the sixth clock cycle D6, and the ninth clock cycle D9. The three verification periods T1, T2, and T3 for the third color ink cartridge are the second half of the sixth clock cycle in the first response cycle, the first half of the sixth clock cycle in the second response cycle, and the second half of the sixth clock cycle in the second response cycle, respectively. Similarly, the level signals for the three verification periods are low level, high level, and low level, respectively.

[0013] Because the response cycle of each color ink cartridge immediately follows the second sending cycle of the inkjet printer—meaning the next cycle after the second sending cycle is the first response cycle for the ink cartridge—each ink cartridge needs to respond within a very short time, resulting in extremely short processing time for the ink cartridge chip. Furthermore, the verification levels sent by the ink cartridge chip in the two response cycles are not the same. This necessitates that the ink cartridge chip possess strong processing capabilities and the ability to respond to the verification commands from the inkjet printer within a very short time. To meet this requirement, a high-performance processor or complex logic circuitry needs to be configured on the ink cartridge chip, increasing the implementation difficulty and production cost of the ink cartridge chip. Summary of the Invention

[0014] The primary objective of this invention is to provide a consumable chip verification response method that reduces the implementation difficulty and production cost of ink cartridge chips.

[0015] A second objective of this invention is to provide a verification method for a consumable container that applies the above-described consumable chip verification response method.

[0016] To achieve the first objective mentioned above, the consumable chip verification response method provided by the present invention includes receiving a verification command for the consumable chip, determining a verification period of the verification response signal according to the verification command, and confirming the verification level of each verification period; outputting a high-level signal during a verification period in which the initial verification level is high, and setting the chip to a high-impedance state during at least one verification period in which the initial verification level is low.

[0017] Because the SPI bus used by inkjet printers has a pull-down resistor on the data signal line (meaning the data signal line is grounded through a very large pull-down resistor), setting the digital signal line to a high-impedance state actually results in a low-level state. Utilizing this characteristic, setting the verification period (when the initial verification level is low) to a high-impedance state ensures that the verification period is effectively low, thus meeting the verification requirements of inkjet printers for consumable chips.

[0018] In addition, since the consumable chip should also set the digital signal line to a high impedance state during the non-verification period of the response cycle, the consumable chip only needs to be set to two states, namely high-level signal output and high impedance state, and does not need to output a low-level signal throughout the entire response cycle. This simplifies the output state type of the consumable chip, thereby making the logic control of the consumable chip simpler, reducing the implementation difficulty of the consumable chip, and reducing its production cost.

[0019] A preferred embodiment is that there are two verification periods with an initial verification level of low; a low-level signal is output during the first verification period with an initial verification level of low, and a high-impedance state is set during the second verification period with an initial verification level of low; or a high-impedance state is set during the first verification period with an initial verification level of low, and a low-level signal is output during the second verification period with an initial verification level of low; or a high-impedance state is set during the first verification period with an initial verification level of low, and a high-impedance state is also set during the second verification period with an initial verification level of low.

[0020] Therefore, it can be seen that the control logic of the consumable chip is simple: outputting a low-level signal only during one verification period when the initial verification level is low, and setting it to a high-impedance state during the other verification period when the initial verification level is low.

[0021] A further approach is to make the verification period when the initial verification level is high the first half of the clock cycle of the verification period when the second initial verification level is low.

[0022] As can be seen, in the first response cycle, the consumable chip can be set to high impedance output, so that the consumable chip only outputs a non-high impedance signal during the verification period of the second response cycle, allowing the consumable chip more time to process the signal response.

[0023] A further approach is to reduce the clock signal line voltage during the high-impedance period. Even further, the clock signal line voltage is reduced only during the high-impedance period of the verification phase.

[0024] When the digital signal line is in a high-impedance state, a small voltage pulse signal will be induced on the digital signal line due to the presence of the clock signal. In order to reduce the interference caused by this pulse signal, the amplitude of the induced pulse signal can be reduced by lowering the voltage of the clock signal, thus avoiding affecting the detection of the inkjet printing equipment.

[0025] A further approach is to reduce the voltage of the clock signal line by lowering the voltage of the clock signal line but keeping it above a high-level threshold voltage.

[0026] Therefore, although the voltage of the clock signal line is reduced, it is still higher than the threshold voltage of the high level. The ink cartridge and inkjet printer can still recognize the high and low levels of the clock signal, thereby meeting the synchronization requirements of the inkjet printer and the ink cartridge.

[0027] Another consumable chip verification response method provided by the present invention includes the consumable chip receiving a verification command, and determining the verification period of the verification response signal according to the verification command, and confirming the verification level of each verification period; outputting a high-level signal during the verification period when the initial verification level is high, and outputting a low-level signal during the period other than the period when the initial verification level is high within the response cycle.

[0028] As can be seen from the above scheme, a low-level signal is output during the period other than the initial verification level being high during the response cycle. Therefore, the consumable chip only outputs a high-level signal or a low-level signal during the entire response cycle, without the need to set a high-impedance state. This simplifies the output state type of the consumable chip, making the logic control of the consumable chip simpler, reducing the implementation difficulty of the consumable chip, and reducing its production cost.

[0029] A preferred embodiment is that the verification period includes two sets of verification periods. The initial verification level of the first set of verification periods is a low-level signal, the initial verification level of the first verification period of the second set of verification periods is a high-level signal, and the initial verification level of the second verification period of the second set of verification periods is a low-level signal. The method includes: always outputting a low-level signal before the arrival of the second set of verification periods.

[0030] Therefore, it can be seen that the consumable chip outputs a low-level signal throughout the entire first response cycle, which allows the consumable chip a relatively long time to prepare for the output of a high-level signal. This is equivalent to the consumable chip having a long high-level preparation time, thereby reducing the logic control difficulty of the consumable chip.

[0031] Another consumable chip verification response method provided by the present invention includes the consumable chip receiving a verification command; and determining the verification period of the verification response signal according to the verification command, and confirming the verification level of each verification period; wherein, the verification period includes two sets of verification periods, the first set of verification periods is located in a first response cycle, the second set of verification periods is located in a second response cycle, the initial verification level of the first set of verification periods is a low level signal, the initial verification level of the first verification period of the second set of verification periods is a high level signal, and the initial verification level of the second verification period of the second set of verification periods is a low level signal; the method includes: outputting a high level signal in the half-clock cycle before the first set of verification periods, outputting a low level signal or a high impedance state in the first set of verification periods, outputting a high level signal in the first verification period of the second set of verification periods, and outputting a low level signal or a high impedance state in the second verification period of the second set of verification periods.

[0032] As can be seen from the above scheme, a high-level signal is also output in the half-clock cycle before the first verification period, so that the clock cycles corresponding to the verification period of the two response cycles output a high-level signal and a low-level signal, that is, the level signals output by the two response cycles are exactly the same, and the control logic of the consumable chip is very simple.

[0033] A preferred embodiment is that the first set of verification time periods in the first response cycle matches the second set of verification time periods in the second response cycle. The method includes ensuring that the level signal output in the first response cycle is the same as the level signal output in the second response cycle.

[0034] Another consumable chip verification response method provided by the present invention includes the consumable chip receiving a verification command, and determining a verification period of the verification response signal according to the verification command; acquiring a clock signal and inverting the clock signal, and outputting the inverted clock signal to the data signal line at least during the verification period.

[0035] Since the signal that the consumable chip needs to output to the data signal line is opposite to the clock signal during the verification period, the verification of the consumable container can be achieved by inverting the clock signal and outputting it directly to the data signal line. Moreover, the control logic of the consumable chip is very simple.

[0036] A preferred embodiment is that outputting the inverted clock signal to the data signal line at least during the verification period includes: determining the response period according to the verification command, and outputting the inverted clock signal to the data signal line during the response period.

[0037] Another consumable chip verification response method provided by the present invention includes: the consumable chip receiving a verification command; determining the verification period of the verification response signal according to the verification command, and confirming the verification level of each verification period; wherein, the verification period includes two sets of verification periods, the first set of verification periods is located in the first response cycle, the second set of verification periods is located in the second response cycle, the initial verification level of the first set of verification periods is a low level signal, the initial verification level of the first verification period of the second set of verification periods is a high level signal, and the initial verification level of the second verification period of the second set of verification periods is a low level signal; the method includes: after the first clock cycle of the second response cycle and before the arrival of the first verification period of the second set of verification periods, outputting a high level signal to the data signal line, and keeping the voltage on the data signal line above the threshold voltage confirmed as high level during the first verification period of the second set of verification periods.

[0038] A preferred approach is to continuously output a high-level signal to the data signal line after the first clock cycle of the second response cycle and before the first verification period of the second verification period, until the end of the second verification period of the second verification period.

[0039] An alternative approach is to output a high-level signal to the data signal line after the first clock cycle of the second response cycle, and set the data signal line to a high-impedance state before the arrival of the first verification period of the second verification period, until the arrival of the second verification period of the second verification period.

[0040] As can be seen from the above scheme, by setting the level of the data signal line to high level in advance before the arrival of the second verification period, there is no need to monitor the arrival time of the second verification period. This can reduce the need to complete two level switchings in a very short time, thereby reducing the calculation requirements of the controller and the production cost of consumable chips.

[0041] To achieve the second objective mentioned above, the present invention provides a method for verifying consumable containers, which includes a printing device sending a verification command to at least one consumable container; and, after receiving the verification command, the consumable chip of the consumable container executes the aforementioned verification response method for the consumable chip; and after receiving the verification response signal sent by the consumable chip, the printing device determines the state of the consumable container based on the received verification response signal.

[0042] As can be seen from the above scheme, each consumable chip sends a verification level in the above manner. After receiving the verification level, the printing device can confirm whether the received verification level is correct, thereby completing the verification of the consumable container.

[0043] A preferred approach is to use two or more containers, with each consumable chip having a different verification period within its response cycle.

[0044] Since the corresponding verification period within the response cycle of each consumable chip is different, the printing device can determine whether the consumable chip is correctly responding to the signal sent by the inkjet printer based on the time period during which each consumable chip sends a verification level, thereby realizing the verification of multiple consumable containers. Attached Figure Description

[0045] Figure 1 This is a structural diagram of an existing inkjet printing device.

[0046] Figure 2 This is a structural diagram of an existing ink cartridge.

[0047] Figure 3 This is a waveform timing diagram of existing inkjet printing equipment sending verification commands.

[0048] Figure 4 This is a waveform timing diagram of the verification response signal sent by the existing consumable chip.

[0049] Figure 5This is a waveform timing diagram of the verification response signal sent by the consumable chip in the first embodiment of the verification response method of the consumable chip of the present invention.

[0050] Figure 6 This is a waveform timing diagram of the consumable chip sending a verification response signal according to the second embodiment of the verification response method of the consumable chip of the present invention.

[0051] Figure 7 This is a waveform timing diagram of the consumable chip sending a verification response signal according to the third embodiment of the verification response method of the consumable chip of the present invention.

[0052] Figure 8 This is a waveform timing diagram of the consumable chip sending a verification response signal according to the fourth embodiment of the verification response method of the consumable chip of the present invention.

[0053] Figure 9 This is a waveform timing diagram of the consumable chip sending a verification response signal according to the fifth embodiment of the verification response method for the consumable chip of the present invention.

[0054] Figure 10 This is a circuit diagram of the consumable chip in the sixth embodiment of the verification response method for the consumable chip of the present invention.

[0055] Figure 11 This is a waveform timing diagram of the verification response signal sent by the consumable chip in the sixth embodiment of the verification response method of the consumable chip of the present invention.

[0056] Figure 12 This is a waveform timing diagram of the consumable chip sending a verification response signal according to the seventh embodiment of the verification response method of the consumable chip of the present invention.

[0057] Figure 13 This is a waveform timing diagram of the consumable chip sending a verification response signal according to the eighth embodiment of the verification response method of the consumable chip of the present invention.

[0058] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0059] The consumable chip verification response method of the present invention can be applied to printing equipment such as inkjet printing equipment or laser printing equipment. For example, the consumable chip is an ink cartridge chip installed on the side wall of the ink cartridge. Multiple ink cartridge chips can be installed on the inkjet printing equipment. Preferably, the inkjet printing equipment and the ink cartridge chip communicate with each other via a serial bus.

[0060] First embodiment:

[0061] In this embodiment, the consumable container is a removable ink cartridge that can be installed into the inkjet printer. The ink cartridge contains an ink cartridge chip, which serves as the consumable chip. One surface of the ink cartridge chip has multiple connection terminals, including clock terminals, data terminals, power terminals, chip select terminals, and ground terminals. The print carriage of the inkjet printer has a stylus holder with multiple stylus pins. The connection terminals of the ink cartridge chip can be electrically connected to the stylus pins. The inkjet printer communicates with multiple ink cartridge chips serially via an SPI bus. For example, the serial bus has clock signal lines and data signal lines. The inkjet printer outputs a clock signal SCK to the clock signal line. Each ink cartridge chip receives the clock signal through its respective clock terminal and communicates synchronously with the inkjet printer under the clock signal.

[0062] In addition, each color ink cartridge chip transmits data signals to the inkjet printer via a data signal line. For example, the data signal between the inkjet printer and the first color ink cartridge is SDA1, the data signal between the inkjet printer and the second color ink cartridge is SDA2, the data signal between the inkjet printer and the third color ink cartridge is SDA3, and so on.

[0063] It should be noted that SDA1, SDA2, and SDA3 mentioned above can be the same data signal line. In the diagram, SDA1, SDA2, and SDA3 represent signals on the data signal line during different time periods. That is, the signal used by the inkjet printer to communicate with the first color ink cartridge on the data signal line during the first time period is SDA1. Similarly, the signal used by the inkjet printer to communicate with the second color ink cartridge on the data signal line during the second time period is SDA2, and the signal used by the inkjet printer to communicate with the third color ink cartridge on the data signal line during the third time period is SDA3. At the same time, SDA1, SDA2, and SDA3 mentioned above can be different data signal lines. Different color ink cartridges are connected to the inkjet printer through different data signal lines, and the inkjet printer communicates with different color ink cartridges synchronously or asynchronously.

[0064] After the ink cartridges are installed on the printing carriage, the inkjet printer needs to verify the installation of each cartridge, that is, to determine whether each cartridge is installed correctly. Specifically, the inkjet printer sends verification commands to each cartridge chip, for example, sending a high-level signal in the preset clock cycle of the first sending cycle and a high-level signal in the preset clock cycle of the second sending cycle. Usually, the preset clock cycles of the two sending cycles are the same. Figure 3 As shown, for the first color ink cartridge chip, the preset clock cycle is the eighth clock cycle D8, for the second color ink cartridge chip, the preset clock cycle is the seventh clock cycle D7, and so on.

[0065] After receiving the corresponding verification command, the ink cartridge chip needs to respond within a specified time, that is, output a verification response signal to the inkjet printer. As mentioned earlier, the first color ink cartridge needs to output a low-level signal in the second half of the eighth clock cycle D8 of the first response cycle, and output a high-level signal in the first half of the eighth clock cycle D8 of the second response cycle, and output a low-level signal in the second half of the eighth clock cycle D8 of the second response cycle.

[0066] Therefore, the cartridge chip needs to determine the verification period corresponding to the current verification instruction based on the received verification instruction. For example, the second half of the eighth clock cycle D8 of the first response cycle is the first verification period T1, the first half of the eighth clock cycle D8 of the second response cycle is the second verification period T2, and the second half of the eighth clock cycle D8 of the second response cycle is the second verification period T3.

[0067] In addition, the cartridge chip needs to determine the verification level for each verification period. For example, it should output a low-level signal in the first verification period T1, a high-level signal in the second verification period T2, and a low-level signal in the third verification period T3. Therefore, the first verification period T1 and the third verification period T3 are verification periods with an initial verification level of low, and the second verification period T2 is a verification period with an initial verification level of high. During the other periods of the first and second response cycles, the inkjet printer does not detect the signal on the data signal line. Therefore, the cartridge chip can not apply any signal to the data signal line, and at this time, the data signal line presents a high-impedance state. However, due to the large resistance between the data signal line and ground, the data signal line usually exhibits a low-level state when the cartridge chip does not apply a level.

[0068] Because the verification response signal has complex requirements for the verification level in each verification period, for example, the verification level corresponding to the first response cycle and the second response cycle are not the same, and the first response cycle is the next cycle after the second transmission cycle, that is, the ink cartridge chip needs to respond immediately after receiving the verification command, which puts very high demands on the control logic of the ink cartridge chip.

[0069] It should be noted that the inkjet printer applies a low-level signal to the data signal line during the first clock cycle D1 of the first response cycle and the second response cycle to indicate the start of the first response cycle or the second response cycle.

[0070] For simplification of control logic, see Figure 5In this embodiment, a high-impedance state is output during the verification periods when the initial verification level is low, i.e., the first verification period T1 and the second verification period T3. A high-level signal is output only during the verification periods when the initial verification level is high, i.e., only the second verification period T2. Thus, when the inkjet printer verifies the cartridge chip, if it receives a low-level signal in the first verification period T1, a high-level signal in the second verification period T2, and a low-level signal in the third verification period T3, it considers the cartridge to be correctly installed and the cartridge has passed verification.

[0071] Similarly, for the second cartridge, the verification periods are the seventh clock cycle (D7) of the first and second response cycles, respectively. The high-impedance state is only output during the second verification period (T2), and remains high during the other periods of the first and second response cycles. The third cartridge uses the same processing method.

[0072] In this way, the ink cartridge chip does not need to perform any operation during the first response cycle. It only needs to output a high level during the second verification period T2 of the second response cycle. It does not need to output any digital signals during other periods, that is, it is configured as a high impedance state. The control logic of the ink cartridge chip is very simple and has low requirements for the computing power of the ink cartridge chip. If logic circuits are used to implement logic control, the implementation difficulty of logic circuits can be simplified, thereby reducing the production cost of ink cartridge chips.

[0073] Second embodiment:

[0074] See Figure 6 Unlike the first embodiment, this embodiment outputs a low-level signal in the third verification period T3 of the second response cycle, and a high-impedance state in the first verification period T1 of the first response cycle. Thus, the inkjet printer receives a low-level signal, a high-level signal, and a low-level signal respectively in the three verification periods T1, T2, and T3, allowing the cartridge chip to pass verification.

[0075] from Figure 6 As can be seen, the cartridge chip is in a high-impedance state for the entire first response cycle, meaning it does not need to output signals to the data signal line. It only outputs high-level and low-level signals sequentially during the eighth clock cycle (D8) of the second response cycle. Specifically, it outputs a high-level signal only during the second verification period (T2) and a low-level signal during the third verification period (T3). This allows the cartridge chip a longer response time after receiving the verification command, eliminating the need for any processing during the first response cycle. This reduces the performance requirements of the cartridge chip, simplifies logic control, lowers the complexity of logic control implementation, and helps reduce production costs.

[0076] In addition, the low-level output during the third verification period T3, compared to the high-impedance output during the third verification period T3, can promptly eliminate the charge remaining on the data signal line during the second verification period T2, and avoid the situation where the chip outputs a high-impedance state during the third verification period T3, but is mistakenly interpreted as a high level by the inkjet printing device.

[0077] Of course, in other implementations, a low-level signal can be output during the first verification period T1, while the signal is set to a high-impedance state during the third verification period T3, and the ink cartridge chip can also pass the verification of the inkjet printing device.

[0078] Third embodiment:

[0079] See Figure 7 Unlike the second embodiment, in this embodiment, the cartridge chip consistently outputs a low-level signal to the data signal line before the second verification period T2, outputs a high-level signal during the second verification period T2, outputs a low-level signal during the third verification period T3, and can output a low-level signal or be set to a high-impedance state after the third verification period T3 ends. In this way, the inkjet printer receives low-level, high-level, and low-level signals respectively during the three verification periods T1, T2, and T3, allowing the cartridge chip to pass the verification.

[0080] As can be understood, this embodiment divides the three verification periods into two groups. The first group of verification periods is the verification period of the first response cycle, i.e., verification period T1, and the second group of verification periods is the verification period of the second response cycle, i.e., verification periods T2 and T3. Therefore, the initial verification level of the first group of verification periods is a low-level signal, the initial verification level of the first verification period of the second group of verification periods is a high-level signal, and the initial verification level of the second verification period of the second group of verification periods is a low-level signal.

[0081] As can be seen, before the second verification period T2, the signal output by the cartridge chip is fixed, that is, it always outputs a low-level signal. In other words, before the arrival of the second verification period, the cartridge chip always outputs a low-level signal to the data signal line. In this way, after the second transmission cycle ends, the cartridge chip only needs to output a low-level signal for the entire first response cycle, without needing to calculate which period is the first verification period T1, thus reducing the difficulty of logic control.

[0082] Fourth embodiment:

[0083] See Figure 8In this embodiment, the signals output in the first and second response cycles are the same. This embodiment also divides the three verification periods into two groups: the first group is the verification period of the first response cycle, i.e., verification period T1; the second group is the verification period of the first response cycle, i.e., verification periods T2 and T3. Furthermore, the period of the first group of verification periods in the first response cycle matches the period of the second verification period of the second group in the second response cycle. That is, the first group of verification periods is located in the eighth clock cycle D8 of the first response cycle, and the second verification period of the second group of verification periods is also located in the eighth clock cycle D8 of the second response cycle.

[0084] Since the second set of verification periods requires both high-level and low-level signals, a high-level signal needs to be output in the verification cycle preceding the first set of verification periods. Specifically, a high-level signal should be output in the first half of the eighth clock cycle (D8) of the first response cycle, and a low-level signal should be output in the first verification period (T1). Additionally, a high-level signal should be output in the first verification period (T2) of the second set of verification periods, and a low-level signal should be output in the second verification period (T3) of the second set of verification periods.

[0085] from Figure 8 As can be seen, the signals output to the data signal line by the ink cartridge chip in the first and second response cycles are the same: a high-level signal and a low-level signal are output respectively during two time periods in the eighth clock cycle D8. Thus, the output signal level of the ink cartridge chip is identical in both response cycles, requiring only the use of the same output signal rule, resulting in relatively simple control logic.

[0086] Of course, in other implementations, the first verification period T1 of the first response cycle can output a high-impedance state, and correspondingly, the third verification period T3 of the second response cycle also outputs a high-impedance state.

[0087] Fifth embodiment:

[0088] Since the clock signal line and data signal line of the SPI bus are adjacent, when the data signal line is in a high impedance state, a high-frequency pulse signal will be generated on the clock signal line, which will induce an interference signal on the data signal line. The frequency of this interference signal is the same as that of the clock signal, but the amplitude is very low, for example, only 0.4V. Since the high-level threshold voltage of inkjet printers is usually above 1V, this interference signal usually does not affect the signal on the data signal line.

[0089] However, if the inkjet printer is subjected to external electromagnetic interference, the interference signal generated on the data signal line may be incorrectly identified by the inkjet printer, that is, the interference signal may be identified as a high-level signal. To avoid this situation, in this embodiment, if a high-impedance state is output during the verification response of the ink cartridge chip, the voltage of the clock signal is adjusted, for example, by temporarily reducing the high-level voltage value of the clock signal.

[0090] See Figure 9 Under normal circumstances, the clock signal SCK has a voltage of 3.3V when it is high. However, during verification periods that require a high-impedance state, the clock signal voltage is reduced. For example, during the peripheral moments of the first verification period T1, such as the previous clock cycle D7 and the current clock cycle D8 of the first verification period T1, the clock signal SCK voltage is reduced. Similarly, during the peripheral moments of the third verification period T3, such as the previous clock cycle D7 and the current clock cycle D8 of the third verification period T3, the clock signal SCK voltage is reduced.

[0091] However, if the clock signal voltage is too low, the cartridge chip will be unable to recognize the clock signal, affecting communication between the cartridge and the inkjet printer. To avoid this problem, the voltage of the reduced clock signal needs to be higher than the high-level threshold voltage. For example, if the high-level threshold voltage is 1.2V, then the voltage of the reduced clock signal at its high level must be at least higher than 1.2V, preferably 1.5V. This allows the cartridge chip to correctly recognize the clock signal sent by the inkjet printer while avoiding the formation of excessively high-amplitude interference signals in a high-impedance state.

[0092] Of course, in other embodiments, the clock signal voltage is reduced during all periods that need to be set to a high impedance state in both the first and second response cycles.

[0093] There are several ways to reduce the voltage when the clock signal SCK is high. For example, an LDO (low dropout linear regulator) can be connected to the clock signal line to clamp the 3.3V high-level voltage to around 1.5V. Many existing technologies have been described, so they will not be elaborated here.

[0094] Sixth embodiment:

[0095] See Figure 10In the ink cartridge chip provided in this embodiment, the circuit responsible for responding to the verification command of the inkjet printing device is provided with a main control unit 21, a first MOS transistor Q1, and a first inverter NOT1. The control terminal of the first MOS transistor Q1 is connected to the main control unit 21 of the ink cartridge chip, the drain of the first MOS transistor Q1 is connected to the clock signal line, the source of the first MOS transistor Q1 is connected to the input terminal of the first inverter NOT1, and the output terminal of the first inverter NOT1 is connected to the data signal line.

[0096] After receiving continuous verification commands from the inkjet printer, the ink cartridge chip controls the first MOSFET Q1 to be turned on. At this time, the signal on the clock signal line is inverted by the first inverter NOT1 and output to the data signal line. The timing diagram is as follows. Figure 11 As shown. From Figure 11 As can be seen, since the inkjet printer outputs a low level in both the first clock cycle (D1) and the first clock cycle (D1) of the second clock cycle, even if the inverter NOT1 outputs a high level during the latter half of the first clock cycle (D1), the inkjet printer will pull the level low, ultimately resulting in... Figure 11 The timing diagram shown.

[0097] Since inkjet printers only detect the level on the data signal line during specific verification periods T1, T2, and T3 of a specific clock cycle, and do not detect the level on the data signal line at other times, in this embodiment, the clock signal line is inverted and output to the data signal line, and low-level signals, high-level signals, and low-level signals are output in the three verification periods T1, T2, and T3, respectively, so that the ink cartridge chip can also pass the verification of the inkjet printer.

[0098] After the verification is completed, that is, after the second response cycle ends, the ink cartridge chip controls the first MOSFET Q1 to be in the off state. The signal on the clock signal line is no longer inverted and output to the data signal line. The ink cartridge chip begins to conduct normal data communication with the inkjet printer.

[0099] It should be noted that the time for the ink cartridge chip to control the on and off states of the first MOSFET Q1 can be selected at other times. For example, it can be set to turn on at any time between the clock cycles D2 and D8 of the first response cycle, or it can be set to turn off at any time between the clock cycle D8 of the second response cycle and the start of the next communication.

[0100] In this way, the ink cartridge chip only needs to turn on the first MOSFET Q1 after receiving the verification command from the inkjet printer and turn it off after the second response cycle. No output operation is required during the intermediate period. The control logic of the ink cartridge chip is very simple, requiring low computational power. If logic circuits are used to implement the logic control, the implementation difficulty of the logic circuits can be simplified, thereby reducing the production cost of the ink cartridge chip. Even if the inkjet printer needs to check the installation status of all color ink cartridge chips within two response cycles due to firmware upgrades—that is, all color ink cartridge chips need to respond during the corresponding verification periods D3 to D8 within the two response cycles—the ink cartridge chip provided in this embodiment can still be applied to such upgraded inkjet printers.

[0101] Seventh embodiment:

[0102] In the first embodiment, a high-level signal and a high-impedance state need to be output during the second verification period. For example, during the eighth clock cycle D8 of the second response cycle, a high-level signal needs to be output in the first half of the cycle, while a high-impedance state is required in the second half. However, during the third verification period T3, the signal collected by the inkjet printer may not be low. This is because, during the third verification period T3, although the data signal line SDA will slowly discharge under the action of the large-value pull-down resistor inside the inkjet printer, causing the voltage of the data signal line SDA to gradually decrease, the clock signal line CLK is a high-level signal during the third verification period T3, with a voltage value typically of 3.3V. Therefore, the high-level state on the clock signal line CLK will also affect the discharge effect of the data signal line SDA. Moreover, the resistance values ​​of the pull-down resistors inside different inkjet printers will also differ. Therefore, under the combined influence of these factors, the level state of the data signal line SDA may be unstable during the third verification period T3, resulting in the signal collected by the inkjet printer not being low. If the inkjet printer determines that the ink cartridge is not in a low-level state during the third verification period T3, it considers the ink cartridge to be incorrectly installed.

[0103] Furthermore, in the second, third, and fourth embodiments, a high-level signal and a low-level signal need to be output respectively during the second verification period. For example, in the eighth clock cycle D8 of the second response cycle, a high-level signal needs to be output in the first half of the cycle, and a low-level signal needs to be output in the second half of the cycle. Thus, for ink cartridge chips using a microcontroller as the main controller, since the installation detection command sent to the inkjet printer is responded to in software, that is, after the microcontroller detects the falling edge of the second verification period T2 for the corresponding color, it outputs a high-level signal to the data signal line SDA. After outputting the high level, it needs to immediately detect whether the rising edge of the third verification period T3 has arrived. After the rising edge of the third verification period T3 arrives, it outputs a low-level signal to the data signal line SDA. In other words, the microcontroller needs to monitor two edge signals within one clock cycle and perform two signal switching operations to output two levels, which places high demands on the operating speed of the microcontroller.

[0104] To address the above issues, this embodiment outputs a high-level signal before the arrival of the second verification period T2, and outputs a low-level signal during the third verification period T3. For details, see [link to documentation]. Figure 12 After the first clock cycle D1 of the second response cycle, a high-level signal is output to the data signal line SDA1, and the high-level signal is maintained until the arrival of the third verification period T3. That is, after the high-level signal is output in the first clock cycle D1, the high-level signal is maintained before the arrival of the second verification period T2. It is not necessary to monitor whether the falling edge of the second verification period T2 arrives, but only whether the rising edge of the third verification period T3 arrives. After the rising edge of the third verification period T3 arrives, a low-level signal is output immediately.

[0105] Therefore, in this embodiment, after the first clock cycle D1 of the second response cycle and before the arrival of the second verification period T2, a high-level signal is output to the data signal line SDA1 in advance, and maintained until the end of the second verification period T2.

[0106] In this way, on the one hand, outputting a low-level signal instead of a high-impedance state during the third verification period T3 can prevent the inkjet printer from detecting a high-level signal and thinking that the ink cartridge is not installed correctly. On the other hand, the microcontroller does not need to monitor the falling and rising edges of the two verification periods T2 and T3 in a very short time. It only needs to monitor the rising edge of the third verification period T3. Moreover, the level signal only switches once during the eighth clock cycle D8, which requires a lower processing speed from the microcontroller and can be implemented using a low-cost microcontroller.

[0107] It should be noted that in this embodiment, the high-level output can begin at any time after the first clock cycle D1 of the second response cycle and before the arrival of the second verification period T2. Taking the ink cartridge chip color BK as an example, since a high-level signal needs to be acquired during the first half of the eighth clock cycle D8 of the second response cycle, the high-level output can occur at any time between the second clock cycle D2 and the seventh clock cycle D7 of the second response cycle, as long as the high level is maintained until the rising edge of the eighth clock cycle D8 arrives.

[0108] Eighth embodiment:

[0109] This embodiment is a further improvement on the seventh embodiment. For details, please refer to [link / reference]. Figure 13 After the first clock cycle D1 of the second response cycle, a high-level signal is output to the data signal line SDA1. However, the high-level signal is not maintained until the arrival of the third verification period T3, but terminates before the arrival of the second verification period T2 and is set to a high-impedance state. Furthermore, the high-impedance state is maintained until the arrival of the third verification period T3, that is, once the rising edge of the third verification period T3 is detected, a low-level signal is immediately output to the data signal line SDA1.

[0110] Since the data signal line maintains a high level signal for a period of time after the first clock cycle D1 of the second response cycle, the voltage of the data signal line SDA1 does not immediately decrease after switching to a high impedance state, but gradually decreases during the discharge process. Figure 13 As shown by the dashed line. Therefore, during the second verification period T2, even if the data signal line is in a high-impedance state, the data signal line SDA1 still has a high voltage, which is still higher than the high-level detection threshold of the inkjet printer, for example, higher than 1.5V. Therefore, the inkjet printer will still detect a high-level signal and will still consider the ink cartridge to be correctly installed.

[0111] It should be noted that in this embodiment, the high-level output can begin at any time after the first clock cycle D1 of the second response cycle and before the arrival of the second verification period T2. Taking the ink cartridge chip color BK as an example, since a high-level signal needs to be acquired during the first half of the eighth clock cycle D8 of the second response cycle, the high-level output can occur at any time between the second clock cycle D2 and the seventh clock cycle D7 of the second response cycle. The termination time of the high-level output can be determined based on the actual measured circuit parameters, such as the resistance value of the pull-down resistor and the capacitance value of the parasitic capacitance inside different models of inkjet printers, to ensure that the voltage acquired by the inkjet printer is above the threshold voltage during the second verification period T2. Preferably, the high-level signal output should stop at least 1 / 2 clock cycle before the arrival of the second verification period T2, so that the microcontroller has sufficient interval time to output a low-level signal during the third verification period T3.

[0112] In this way, since the microcontroller does not need to monitor the falling and rising edges of the two verification periods T2 and T3 in a very short time, it only needs to monitor the rising edge of the third verification period T3. Furthermore, during the time period of the eighth clock cycle D8, it only needs to output a low-level signal during the third verification period T3. This reduces the requirements for the microcontroller's processing speed and allows it to be implemented using a low-cost microcontroller.

[0113] It should be noted that in this embodiment, a suitable high-level termination time can be selected according to the actual circuit parameters, so that a low-level signal does not need to be output during the third verification period T3, but the current high-impedance state can be maintained. That is, according to the discharge curve of the data signal line SDA1, the high-level signal is terminated before the arrival of the second verification period T2, so that during the second verification period T2, the voltage on the data signal line SDA1 is maintained above the threshold voltage for high-level detection, allowing the inkjet printer to detect a high-level signal; while in the third verification period T3, the voltage on the data signal line SDA1 drops below the threshold voltage, allowing the inkjet printer to detect a low-level signal. Combining the methods used in embodiments one to three, maintaining a high-impedance state during the first verification period T1, the ink cartridge chip only needs to output a high level once before the second verification period T2 during the entire response period of the inkjet printer's installation detection command, greatly simplifying the control logic.

[0114] As can be seen, the present invention can simplify the response logic of the ink cartridge chip to the verification command, and the ink cartridge chip can use simple control logic to deal with the verification command, thereby reducing the implementation difficulty of the ink cartridge chip.

[0115] Finally, it should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. Verification response methods for consumable chips, including: Consumable chip receives verification command; Its features are: The verification period of the verification response signal is determined according to the verification instruction, and the verification level of each verification period is confirmed. Output a high-level signal during the verification period when the initial verification level is high, and set to a high-impedance state during at least one verification period when the initial verification level is low; The number of verification periods in which the initial verification level is low is two; During the first verification period when the initial verification level is low, a low-level signal is output; during the second verification period when the initial verification level is low, a high-impedance state is set. During the first verification period when the initial verification level is low, the signal is set to a high impedance state; during the second verification period when the initial verification level is low, a low-level signal is output. The first verification period when the initial verification level is low is set to a high impedance state, and the second verification period when the initial verification level is low is also set to a high impedance state.

2. The verification response method for consumable chips according to claim 1, characterized in that: The verification period in which the initial verification level is high is the first half of the clock cycle of the second verification period in which the initial verification level is low.

3. The verification response method for consumable chips according to claim 1, characterized in that: During the period when the clock signal line is set to a high impedance state, the voltage is reduced.

4. The verification response method for consumable chips according to claim 3, characterized in that: The voltage of the clock signal line is reduced only during the period when the verification period is set to a high impedance state.

5. The verification response method for consumable chips according to claim 3, characterized in that: Reducing the voltage of the clock signal line includes: reducing the voltage of the clock signal line but above a high-level threshold voltage.

6. Verification response methods for consumable chips, including: Consumable chip receives verification command; Its features are: The verification period of the verification response signal is determined according to the verification instruction, and the verification level of each verification period is confirmed. During the verification period when the initial verification level is high, a high-level signal is output; during the response period when the initial verification level is not high, a low-level signal is output. Furthermore, the verification period includes two sets of verification periods. The initial verification level of the first set of verification periods is a low-level signal, the initial verification level of the first verification period of the second set of verification periods is a high-level signal, and the initial verification level of the second verification period of the second set of verification periods is a low-level signal. The method includes: always outputting a low-level signal before the arrival of the second verification period.

7. Verification response methods for consumable chips, including: Consumable chip receives verification command; Its features are: The verification period of the verification response signal is determined according to the verification instruction, and the verification level of each verification period is confirmed. The verification period includes two sets of verification periods. The first set of verification periods is located in the first response cycle, and the second set of verification periods is located in the second response cycle. The initial verification level of the first set of verification periods is a low-level signal, the initial verification level of the first verification period of the second set of verification periods is a high-level signal, and the initial verification level of the second verification period of the second set of verification periods is a low-level signal. The method includes: outputting a high-level signal for half a clock cycle before the first verification period, outputting a low-level signal or a high-impedance state during the first verification period, outputting a high-level signal during the first verification period of the second verification period, and outputting a low-level signal or a high-impedance state during the second verification period of the second verification period.

8. The verification response method for consumable chips according to claim 7, characterized in that: The first set of verification time periods in the first response cycle matches the second set of verification time periods in the second response cycle.

9. The verification response method for consumable chips according to claim 8, characterized in that: The method includes: the level signal output in the first response cycle is the same as the level signal output in the second response cycle.

10. Verification response methods for consumable chips, including: Consumable chip receives verification command; Its features are: The verification period of the verification response signal is determined according to the verification instruction, and the verification level of each verification period is confirmed. The verification period includes two sets of verification periods. The first set of verification periods is located in the first response cycle, and the second set of verification periods is located in the second response cycle. The initial verification level of the first set of verification periods is a low-level signal, the initial verification level of the first verification period of the second set of verification periods is a high-level signal, and the initial verification level of the second verification period of the second set of verification periods is a low-level signal. The method includes: after the first clock cycle of the second response cycle and before the first verification period of the second set of verification periods arrives, outputting a high-level signal to the data signal line, and ensuring that the voltage on the data signal line is maintained above the threshold voltage for confirmation of a high level during the first verification period of the second set of verification periods.

11. The verification response method for consumable chips according to claim 10, characterized in that: After the first clock cycle of the second response cycle and before the first verification period of the second verification period arrives, a high-level signal is continuously output to the data signal line until the end of the second verification period of the second verification period.

12. The verification response method for consumable chips according to claim 10, characterized in that: After the first clock cycle of the second response cycle, a high-level signal is output to the data signal line. Before the first verification period of the second verification period arrives, the data signal line is set to a high-impedance state until the second verification period of the second verification period arrives.

13. Verification response methods for consumable chips, including: Consumable chip receives verification command; Its features are: The verification period for the verification response signal is determined according to the verification instruction; Acquire a clock signal and invert the clock signal, and output the inverted clock signal to the data signal line at least during the verification period.

14. The verification response method for consumable chips according to claim 13, characterized in that: Outputting the inverted clock signal to the data signal line at least during the verification period includes: The response period is determined according to the verification command, and the inverted clock signal is output to the data signal line during the response period.

15. Validation methods for consumable containers, including: The printing device sends a verification command to at least one consumable container; Its features are: After receiving the verification command, the consumable chip in the consumable container executes the verification response method for the consumable chip as described in any one of claims 1 to 14. After receiving the verification response signal sent by the consumable chip, the printing device determines the state of the consumable container based on the received verification response signal.

16. The verification method for consumable containers according to claim 15, characterized in that: The number of containers is two or more, and the verification period corresponding to the response cycle of each consumable chip is different.

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