Word line drive circuit and word line driver, storage device

Abstract

This disclosure relates to a word line driving circuit, a word line driver, and a memory device. The word line driving circuit includes: at least two sub-word line drivers, each sub-word line driver being connected to a main word line and a sub-word line, the main word line being used to provide an enable signal; each sub-word line driver includes a holding transistor, a first terminal and a second terminal of the holding transistor being respectively connected to different sub-word lines, and the gate of the holding transistor receiving a second driving signal; the sub-word line driver is configured to, in response to a first driving signal and an enable signal, provide a first driving signal to a selected sub-word line, the selected sub-word line being a sub-word line connected to either the first terminal or the second terminal of the holding transistor; and, in response to the first driving signal, the enable signal, and the second driving signal, turn on the first terminal and the second terminal of the holding transistor. This disclosure is beneficial for reducing the layout area of ​​the word line driving circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a word line driving circuit, a word line driver, and a storage device. Background Technology

[0002] Memory is a common semiconductor structure. As the size of semiconductor structures continues to shrink, more memory can be integrated onto a chip, thus contributing to increased product capacity. In dynamic random access memory (DRAM), data needs to be written to / read from memory cells using word lines and bit lines, and operation is based on the voltage applied to the word lines.

[0003] As DRAM capacity increases, the number of memory cells connected to a word line increases, and the distance between word lines decreases, potentially leading to speed latency issues. To improve word line voltage latency, a word line can be divided into multiple sub-word lines, and each sub-word line can be driven using a sub-word-line driver (SWD). The sub-word-line driver can be integrated into the word line driving circuit.

[0004] However, the current word line driver circuits have a large layout area, resulting in low memory integration density. Summary of the Invention

[0005] This disclosure provides a word line driving circuit, a word line driver, and a storage device, which at least helps to reduce the layout area of ​​the word line driving circuit.

[0006] This disclosure provides a word line driving circuit, including: at least two sub-word line drivers, each sub-word line driver being connected to a main word line and a sub-word line, the main word line being used to provide an enable signal; each sub-word line driver including a holding transistor, a first terminal and a second terminal of the holding transistor being respectively connected to different sub-word lines, the gate of the holding transistor receiving a second driving signal; the sub-word line drivers are configured to, in response to a first driving signal and an enable signal, provide a first driving signal to a selected sub-word line, the selected sub-word line being a sub-word line connected to either the first terminal or the second terminal of the holding transistor; and, in response to the first driving signal, the enable signal, and the second driving signal, turn on the first terminal and the second terminal of the holding transistor.

[0007] In some embodiments, the same main word line is connected to at least two sub-word line drivers, and the same main word line corresponds to at least two sub-word lines; the two sub-word lines connected to the first end and the second end respectively correspond to the same main word line.

[0008] In some embodiments, at least two main word line drivers are connected to different main word lines, and the different main word lines correspond to different sub-word lines; the two sub-word lines connected to the first end and the second end correspond to different main word lines.

[0009] In some embodiments, the holding transistor includes an NMOS transistor.

[0010] In some embodiments, the sub-word line driver includes: a pull-up transistor with its gate connected to the main word line, its source receiving a first drive signal, and its drain connected to the sub-word line and a first or second terminal of a holding transistor; and a pull-down transistor with its gate connected to the main word line, its drain connected to the drain of the pull-up transistor, and its source receiving a third drive signal.

[0011] In some embodiments, the pull-up transistor includes a PMOS transistor; the pull-down transistor includes an NMOS transistor.

[0012] Accordingly, this disclosure also provides a word line driver, comprising: a PMOS region including a plurality of first active regions extending along a first direction, the first active regions including a first channel region and first source regions and first drain regions respectively located on opposite sides of the first channel region; an NMOS region arranged along a second direction with the PMOS region, including a plurality of second active regions extending along the first direction, the second active regions including a second channel region and second source regions and second drain regions respectively located on opposite sides of the second channel region, the second active regions further including a third channel region and third source regions and third drain regions respectively located on opposite sides of the third channel region; and a first gate, each first gate extending along the second direction. The transistor extends and covers multiple first channel regions and multiple second channel regions. The first gate is electrically connected to the main word line. The first gate, the first source region, and the first drain region constitute a pull-up transistor, and the first gate, the second source region, and the second drain region constitute a pull-down transistor. Multiple second gates are included, each covering a corresponding third channel region. The second gate, the third source region, and the third drain region constitute a holding transistor. The first drain region of a pull-up transistor is electrically connected to the second drain region of a pull-down transistor and is electrically connected to the corresponding sub-word line. The third drain region of the same holding transistor is electrically connected to the second drain region of a pull-down transistor, and the third source region is electrically connected to the second drain region of another pull-down transistor.

[0013] In some embodiments, each first gate includes: at least two extensions spaced apart along a first direction, extending along a second direction and covering a plurality of first channel regions and a plurality of second channel regions; and a connecting portion connecting the extensions arranged adjacent to each other along the first direction.

[0014] In some embodiments, the connecting portion covers the area between adjacent first active regions, and also covers the area between the first active region and the second active region.

[0015] In some embodiments, along the first direction, the distance between adjacent extensions of the NMOS region is greater than the distance between adjacent extensions of a portion of the PMOS region, and the second gate is located between the adjacent extensions.

[0016] In some embodiments, the PMOS region includes: a first PMOS region and a second PMOS region arranged along a second direction, the second PMOS region being located between the first PMOS region and the NMOS region; two extensions of the same first gate cover the same first active region of the first PMOS region, and the two extensions also respectively cover two first active regions of the second PMOS region arranged along a first direction; wherein, along the first direction, the distance between adjacent extensions of the first PMOS region is smaller than the distance between adjacent extensions of the second PMOS region.

[0017] In some embodiments, along the first direction, the distance between adjacent extensions of the NMOS region is less than the distance between adjacent extensions of a portion of the PMOS region, and the second gate is located outside the region enclosed by the two extensions.

[0018] In some embodiments, the PMOS region includes: a first PMOS region and a second PMOS region arranged along a second direction, the second PMOS region being located between the first PMOS region and the NMOS region; two extensions of the same first gate cover the same first active region of the second PMOS region, and the two extensions also respectively cover two first active regions of the first PMOS region arranged along a first direction; wherein, along the first direction, the distance between adjacent extensions of the first PMOS region is greater than the distance between adjacent extensions of the second PMOS region.

[0019] In some embodiments, the third channel region and at least one second channel region belong to the same second active region.

[0020] In some embodiments, the second drain region of a pull-down transistor corresponding to the same first gate is shared with the third drain region of a holding transistor, and the second drain region of another pull-down transistor corresponding to the same first gate is shared with the third source region of the same holding transistor.

[0021] In some embodiments, the second drain region of a pull-down transistor corresponding to a first gate is shared with the third drain region of a holding transistor, and the second drain region of a pull-down transistor corresponding to another first gate is shared with the third source region of the same holding transistor.

[0022] In some embodiments, each first gate covers 4×N first channel regions and 4×N second channel regions, and each first gate forms a pull-up transistor and a pull-down transistor that are electrically connected to 2×N holding transistors; wherein, N is a positive integer greater than or equal to 1.

[0023] In some embodiments, the plurality of first active regions include: at least two first active regions disposed near the NMOS region, the two first active regions being spaced apart along a first direction and having a spacer region, wherein the second gate and the spacer region are disposed opposite each other along a second direction.

[0024] Accordingly, embodiments of this disclosure also provide a storage device, including: a storage cell array including a plurality of storage cells connected to a plurality of sub-word lines and a plurality of bit lines; a word line driving circuit provided in any of the above; or a word line driver provided in any of the above.

[0025] The technical solution provided in this disclosure has the following advantages:

[0026] The word line driving circuit provided in this disclosure includes at least two sub-word line drivers. Each sub-word line driver is connected to a main word line and a sub-word line, enabling the sub-word line driver to drive the sub-word line based on an enable signal received from the main word line. Each sub-word line driver includes a holding transistor, with its first and second ends connected to different sub-word lines, meaning two sub-word lines share the same holding transistor. The sub-word line driver can respond to a first driving signal and an enable signal to drive the sub-word line connected to one end of the holding transistor. The holding transistor can also maintain the sub-word line connected to the other end of the holding transistor in an unselected state based on the first driving signal, the enable signal, and the second driving signal. In other words, by setting two sub-word lines to share a single holding transistor, one sub-word line connected to one end of the holding transistor can be driven while the other sub-word line connected to the other end of the holding transistor is in an unselected state. This reduces the area occupied by the word line driving circuit while maintaining its performance, thereby reducing the layout area of ​​the word line driving circuit. Attached Figure Description

[0027] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0028] Figure 1 This is a circuit diagram of a word line driving circuit;

[0029] Figure 2 This is a diagram of a sub-word line system architecture;

[0030] Figure 3 A circuit diagram of a word line driving circuit provided for an embodiment of this disclosure;

[0031] Figure 4 A circuit diagram of another word line driving circuit provided in an embodiment of this disclosure;

[0032] Figure 5 A circuit diagram of yet another word line driving circuit provided in an embodiment of this disclosure;

[0033] Figure 6 A circuit diagram of yet another word line driving circuit provided in an embodiment of this disclosure;

[0034] Figure 7 A timing diagram of each signal in a word line driving circuit provided in an embodiment of this disclosure;

[0035] Figure 8 A schematic diagram of the layout structure of a first word line driver provided in an embodiment of this disclosure;

[0036] Figure 9 A schematic diagram of the layout structure of a second word line driver provided in an embodiment of this disclosure;

[0037] Figure 10 A schematic diagram of the layout structure of a third word line driver provided in an embodiment of this disclosure;

[0038] Figure 11 A schematic diagram of the layout structure of a fourth word line driver provided in an embodiment of this disclosure;

[0039] Figure 12 This is a schematic diagram of the layout structure of a fifth word line driver provided in an embodiment of this disclosure. Detailed Implementation

[0040] As is known from the background technology, current word line driver circuits suffer from a large layout area. Analysis reveals that one reason for this large layout area is the reference... Figure 1 as well as Figure 2Currently, word line driving circuits include at least one sub-word line driver, which is connected to a main word line MWLb and a sub-word line WL. The sub-word line driver also includes a holding transistor, with one end connected to the sub-word line WL and the other end coupled to a low level VKK. The sub-word line driver receives an enable signal and a drive signal PXID, and provides the drive signal PXID to the sub-word line WL, thereby driving the sub-word line WL. When sub-word line WL is not needed, the first and second ends of the holding transistor can be turned on in response to the enable signal, drive signal PXID, and drive signal PXIB, causing the first end of the holding transistor to be coupled to a low level VKK, thereby pulling the sub-word line WL connected to the first end of the holding transistor to a low level VKK, thus turning off the sub-word line WL. In other words, one holding transistor is used to control only one sub-word line, keeping the sub-word line in an unselected state. (Reference) Figure 2 As can be seen, when there are two main word lines in the word line driver circuit, denoted as MWLb1 and MWLb2 respectively, and each main word line corresponds to two sub-word line drivers SWD respectively, and each holding transistor is electrically connected to a sub-word line (multiple sub-word lines are denoted as WL0 to WL15 in the figure), the sub-word line drivers respond to the corresponding drive signal PXIB and the corresponding drive signal PXID respectively, thereby controlling the shutdown of the sub-word line. This will occupy a lot of space in the word line driver circuit layout.

[0041] This disclosure provides a word line driving circuit, a word line driver, and a storage device. The word line driving circuit includes at least two word line drivers, each connected to a main word line and a sub-word line. The first and second terminals of the holding transistor in the sub-word line driver are respectively connected to two sub-word lines, meaning the two sub-word lines share the same holding transistor. When a sub-word line connected to one end of the holding transistor is driven, the holding transistor can keep the sub-word line connected to the other end of the holding transistor in an unselected state. This reduces the area occupied by the word line driving circuit and the layout area of ​​the sub-word line driving circuit while maintaining the performance of the word line driving circuit.

[0042] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0043] Figure 3 A circuit diagram of a word line driving circuit provided in an embodiment of this disclosure.

[0044] refer to Figures 3 to 6The word line driving circuit includes: at least two sub-word line drivers 100, each sub-word line driver 100 being connected to a main word line MWL and a sub-word line, the main word line MWL being used to provide an enable signal; each sub-word line driver 100 includes a holding transistor 101, the first and second terminals of the holding transistor 101 being respectively connected to different sub-word lines, the gate of the holding transistor 101 receiving a second driving signal; the sub-word line driver 100 is configured to, in response to a first driving signal PXID and an enable signal, provide a first driving signal PXID to a selected sub-word line, the selected sub-word line being a sub-word line connected to either the first or second terminal of the holding transistor 101; and, in response to the first driving signal PXID, the enable signal, and the second driving signal PXIB, turn on the first and second terminals of the holding transistor 101.

[0045] The first and second terminals of the holding transistor 101 are respectively connected to two different sub-word lines, meaning that the two sub-word lines share the same holding transistor 101. When the word line driver responds to the first drive signal PXID and the enable signal, it provides the first drive signal PXID to the selected sub-word line, thereby selecting the sub-word line connected to the first or second terminal of the holding transistor 101, while the other sub-word line connected to the holding transistor 101 is not selected. When the word line driver responds to the first drive signal PXID, the enable signal, and the second drive signal PXIB, it turns on the first and second terminals of the holding transistor 101, thereby pulling the level of the selected sub-word line to match the level of the unselected sub-word line, thus turning off the selected word line. That is, when the sub-word line connected to one end of the holding transistor 101 is driven, the holding transistor 101 can make the sub-word line connected to the other end of the holding transistor 101 unselected, thereby reducing the area occupied by the word line driving circuit and the layout area of ​​the sub-word driving circuit while keeping the performance of the word line driving circuit unchanged.

[0046] refer to Figure 3 as well as Figure 4 In some embodiments, the same main word line MWL is connected to at least two sub-word line drivers 100, and the same main word line MWL corresponds to at least two sub-word lines; the two sub-word lines connected to the first end and the second end each correspond to the same main word line MWL. That is, the enable signal provided by the same main word line MWL can be used to drive multiple corresponding sub-word lines. Figure 4As shown, one main word line (MWL) can be connected to eight sub-word line drivers (100), and one main word line (MWL) corresponds to eight sub-word lines. Furthermore, one main word line (MWL) corresponds to only four holding transistors (101), meaning one main word line (MWL) can share four holding transistors (101). When there are two main word lines (MWL), a total of 16 sub-word lines can be driven, while only eight holding transistors (101) are required. Compared to one main word line (MWL) corresponding to eight holding transistors (101), this significantly reduces the area occupied by the sub-word line drivers (100), thereby greatly reducing the layout area of ​​the word line driving circuit.

[0047] refer to Figure 5 as well as Figure 6 In other embodiments, at least two main word line (MWL) drivers are connected to different main word lines (MWL), and the different main word lines (MWL) correspond to different sub-word lines; the two sub-word lines connected to the first and second ends correspond to different main word lines (MWL). Figure 6 As shown, there can be two main word lines (MWLs). Each main word line (MWL) is connected to eight sub-word line drivers (100), and each main word line (MWL) corresponds to eight holding transistors (101). Two sub-word line drivers (100) connected to different main word lines (MWLs) share the same holding transistor (101), resulting in the two main word lines (MWLs) sharing a total of eight holding transistors (101). In other words, the two main word lines (MWLs) can drive a total of 16 sub-word lines, while the number of holding transistors (101) remains only eight. This reduces the number of holding transistors (101) in each sub-word line driver (100), thus reducing the layout area of ​​the word line driving circuit.

[0048] It is understandable that, regardless of how many sub-word line drivers 100 a main word line MWL is connected to, and whether a main word line MWL shares 4 holding transistors 101 or two main word lines MWL share 8 holding transistors 101, in a sub-word line driving circuit, only one sub-word line can be driven at any given time, and the remaining sub-word lines are in an unselected state.

[0049] The sub-word line driver 100 can activate or precharge a selected sub-word line in response to an enable signal provided by the main word line MWL and a first drive signal PXID and a second drive signal PXIB input to the sub-word line driver 100. The enable signal, the first drive signal PXID, and the second drive signal PXIB can be provided by external circuitry. In some embodiments, the first drive signal PXID can be a high voltage level, and the sub-word line driver 100 can drive the sub-word line with a high voltage. Correspondingly, when a high voltage level is used to drive the sub-word line, a low voltage level can be used to turn off the sub-word line.

[0050] refer to Figure 3 as well as Figure 5Since a sub-word line driver 100 is connected to a sub-word line, and a holding transistor 101 is connected to two different sub-word lines respectively, in the word line driving circuit, the number of sub-word line drivers 100 is twice the number of holding transistors 101, that is, the two sub-word lines connected to a holding transistor 101 are also connected to two sub-word line drivers 100 respectively.

[0051] It is worth noting that in the word line driving circuit, when one word line driver drives its connected sub-word line, the sub-word lines connected to the remaining sub-word line drivers 100 are all in an unselected state. That is, only one sub-word line can be selected at a time in the word line driving circuit. Therefore, when a sub-word line connected to either the first or second terminal of the holding transistor 101 is selected, the sub-word line connected to the other terminal is unselected. Thus, when the first and second terminals of the holding transistor 101 are turned on, the voltage level of the sub-word line connected to the first terminal of the holding transistor 101 will be pulled down to match the voltage level of the sub-word line connected to the second terminal of the holding transistor 101. This allows the voltage level of the selected sub-word line to be pulled down to match the voltage level of the unselected sub-word line, thus putting the selected sub-word line in a closed state.

[0052] In some embodiments, the holding transistor 101 includes an NMOS transistor. The second drive signal PXIB can be a high-level signal. The holding transistor 101 turns on in response to the high-level signal, thereby turning on its first and second terminals. When the first and second terminals are turned on, the levels of the two sub-word lines connected to the first and second terminals are consistent. Specifically, when the sub-word line connected to the first terminal of the holding transistor 101 is selected, the sub-word line connected to the second terminal of the holding transistor 101 is in an unselected state. If the sub-word line is driven in response to a high voltage level, the node of the first terminal of the holding transistor 101 is at a high voltage level, and the node of the second terminal is at a low voltage level. When the first and second terminals of the holding transistor 101 are turned on, the level of the node of the first terminal of the holding transistor 101 is pulled down to be consistent with the level of the node of the second terminal, that is, the node of the first terminal of the holding transistor 101 has a negative voltage level, which is equivalent to pre-charging the sub-word line connected to the first terminal of the holding transistor 101 with a negative voltage, ensuring that the sub-word line connected to the first terminal of the transistor is turned off.

[0053] It is not difficult to see that in this embodiment of the present disclosure, since the first and second ends of the holding transistor 101 are respectively connected to two sub-word lines, when the first and second ends of the holding transistor 101 are turned on, the level of the node at the first end is consistent with the level of the node at the second end, that is, the voltage of the selected word line is consistent with the voltage of the unselected word line, thereby ensuring that the selected word line can be turned off.

[0054] In some embodiments, the sub-word line driver 100 includes: a pull-up transistor 102, with its gate connected to the main word line MWL, its source receiving a first drive signal PXID, and its drain connected to the sub-word line and a first or second terminal of a holding transistor 101; and a pull-down transistor 103, with its gate connected to the main word line MWL, its drain connected to the drain of the pull-up transistor 102, and its source receiving a third drive signal VKK. The pull-up transistor 102, in response to an enable signal and the first drive signal PXID, pulls the sub-word line up to the level of the first drive signal PXID, and the sub-word line is driven in response to the first drive signal PXID. The pull-down transistor 103, in response to an enable signal, pulls the sub-word line down to the level of the third drive signal VKK, and the sub-word line is turned off in response to the third drive signal VKK. In some embodiments, the first drive signal PXID can be high, and the third drive signal VKK can be low; for example, the voltage of the third drive signal VKK can be 0 or less than 0.

[0055] Specifically, when the sub-word line driver 100 drives the sub-word line, the gate of the pull-up transistor 102 is turned on in response to the enable signal, and the first drive signal PXID is transmitted from the source to the drain of the pull-up transistor 102. Since the drain of the pull-up transistor 102 is connected to the sub-word line, the first drive signal PXID is transmitted from the drain of the pull-up transistor 102 to the sub-word line, thereby pulling up the level of the sub-word line to the level of the first drive signal PXID.

[0056] When the sub-word line driver 100 turns off the sub-word line, the gate of the pull-down transistor 103 turns on in response to the enable signal. The third drive signal VKK is transmitted from the source of the pull-down transistor 103 to the drain. The drain of the pull-down transistor 103 is connected to the drain of the pull-up transistor 102, and the drain of the pull-up transistor 102 is connected to the sub-word line. This causes the third drive signal VKK to be transmitted from the drain of the pull-down transistor 103 to the sub-word line, thereby pulling down the level of the sub-word line to the third drive signal VKK.

[0057] It is worth noting that, due to potential instability of the enable signal or the third drive signal VKK, or due to external noise interference affecting the word line driving circuit, the sub-word line level may not be less than 0. Therefore, relying solely on the third drive signal VKK may not be sufficient to completely turn off the sub-word line. However, in this embodiment, since the first and second terminals of the holding transistor 101 are connected to two different sub-word lines, when the first and second terminals of the holding transistor 101 are turned on, the voltage of the selected word line will be pulled down to match the voltage of the unselected word line. That is, the holding transistor 101 can couple the voltage of the selected word line to a negative voltage level, thereby turning it off. Therefore, regardless of how the levels of the enable signal or the third drive signal VKK change, the unselected word line can maintain a stable voltage value.

[0058] In some embodiments, the pull-up transistor 102 includes a PMOS transistor; the pull-down transistor 103 includes an NMOS transistor. That is, the pull-up transistor 102 turns on in response to a low-level signal, and the pull-down transistor 103 turns on in response to a high-level signal, so that the pull-up transistor 102 and the pull-down transistor 103 can operate independently and control the driving and turning off of the sub-word line respectively.

[0059] Specifically, when pull-up transistor 102 is a PMOS transistor and pull-down transistor 103 is an NMOS transistor, the word line drive circuit works as follows:

[0060] The two sub-word line drivers 100 are respectively designated as the second sub-word line driver and the second sub-word line driver. The sub-word line connected to the first terminal of the holding transistor 101 is designated as the first sub-word line WL1, and the sub-word line connected to the second terminal of the holding transistor 101 is designated as the second sub-word line WL2. The first sub-word line WL1 is connected to the second sub-word line driver, and the second sub-word line WL2 is connected to the second sub-word line driver.

[0061] The second sub-word line driver drives the first sub-word line WL1. At this time, the second sub-word line WL2 is in an unselected state.

[0062] The second sub-word line driver drives the first sub-word line WL1 in response to a low-level enable signal, a high-level first drive signal PXID, and a low-level second drive signal PXIB. Specifically, the pull-up transistor 102 is turned on in response to the low-level enable signal, and the high-level first drive signal PXID is transmitted from the source of the pull-up transistor 102 to the drain of the pull-up transistor 102. At the same time, the holding transistor 101 is turned off in response to the low-level second drive signal PXIB, so that the level of the first sub-word line WL1 is pulled up to the first drive signal PXID, has a high level, and is thus driven.

[0063] The second sub-word line driver shuts down the first sub-word line WL1 in response to a high-level enable signal, a low-level first drive signal PXID, and a high-level second drive signal PXIB. Pull-down transistor 103 turns on in response to a high-level enable signal, and pull-up transistor 102 turns off in response to a low-level enable signal. The third drive signal VKK is transmitted from the source to the drain of pull-down transistor 103, causing the level of the first sub-word line WL1 to be pulled down to a low level by the third drive signal VKK. Simultaneously, holding transistor 101 turns on in response to a high-level second drive signal PXIB, ensuring that the level of the first sub-word line WL1 matches the level of the second sub-word line WL2. Since the second sub-word line WL2 is in an unselected state, the first sub-word line WL1 is ensured to be turned off, thus becoming unselected.

[0064] The principle of driving the second sub-word line WL2 and turning off the sub-word line is the same as that of the second sub-word line driver, and will not be repeated below. It is worth noting that since the second sub-word line driver and the second sub-word line driver correspond to the same holding transistor 101, when it is necessary to turn off the selected second sub-word line WL2, the first and second terminals of the holding transistor 101 can be turned on to pull the level of the second sub-word line WL2 down to the level of the first sub-word line WL1, thereby turning off the second sub-word line WL2. In other words, a holding transistor 101 can be connected to two different sub-word lines to control the turning off of both sub-word lines.

[0065] refer to Figure 3 In some embodiments, the second sub-word line driver and the second sub-word line driver are connected to the same main word line MWL. In this case, when the main word line MWL receives an enable signal, the gates of the upper and lower transistors of the second sub-word line driver and the gate of the pull-up transistor 102 of the second sub-word line driver will simultaneously receive the enable signal from the main word line MWL. Considering that only one sub-word line can be driven, the level of the first driving signal PXID received by the source of the pull-up transistor 102 of the second sub-word line driver can be set to be different from the level of the first driving signal PXID received by the source of the pull-up transistor 102 of the second sub-word line driver, to prevent two sub-word lines from being turned on simultaneously.

[0066] refer to Figure 5 In some embodiments, the second sub-word line driver and the second sub-word line driver are respectively connected to different main word lines MWL. For example, the first word line driver is connected to the first main word line MWL1, and the second word line driver is connected to the second main word line MWL2, so that the first word line driver and the second word line driver can drive the connected sub-word lines respectively in response to the enable signal from the first main word line MWL1 and the enable signal from the second main word line MWL2.

[0067] refer to Figure 7 , Figure 7 This is a timing diagram of each signal in a word line driving circuit provided in an embodiment of the present disclosure.

[0068] When driving the sub-word line, the level of the first driving signal PXID is first pulled high. At the same time as the level of the first driving signal PXID is pulled high, the level of the second driving signal PXIB is pulled low. Then the level of the enable signal is pulled low, thereby driving the sub-word line.

[0069] When the sub-word line is turned off, the level of the first drive signal PXID is first pulled low. After the level of the first drive signal PXID has been pulled low for a period of time, the level of the second drive signal PXIB is pulled high. That is, the level of the second drive signal PXIB is pulled high later than the level of the first drive signal PXID. When the second drive signal PXIB is high, the holding transistor is kept in the off state. In this way, the holding transistor can be kept off for a longer period of time, which can slow down the aging rate of the holding transistor.

[0070] In the word line driving circuit provided in the above-disclosed embodiments, the word line driving circuit includes at least two word line drivers, and each word line driver is connected to a main word line (MWL) and a sub-word line. The first and second terminals of the holding transistor 101 in the sub-word line driver 100 are respectively connected to two sub-word lines, meaning that the two sub-word lines share the same holding transistor 101. When a sub-word line connected to one end of the holding transistor 101 is driven, the holding transistor 101 can keep the sub-word line connected to the other end of the holding transistor 101 in an unselected state, thereby reducing the area occupied by the word line driving circuit and the layout area of ​​the sub-word line driving circuit while maintaining the performance of the word line driving circuit.

[0071] Accordingly, this disclosure also provides a word line driver, which can be used to form the word line driving circuit provided in the previous embodiment. The word line driver provided in this disclosure will be described in detail below.

[0072] refer to Figure 8The word line driver includes: a PMOS region 10, including a plurality of first active regions 110 extending along a first direction X, each first active region 110 including a first channel region and a first source region 12 and a first drain region 13 located on opposite sides of the first channel region; an NMOS region 11, arranged with the PMOS region 10 along a second direction Y, including a plurality of second active regions 120 extending along the first direction X, each second active region 120 including a second channel region 14 and a second source region 15 and a second drain region 16 located on opposite sides of the second channel region 14, the second active region 120 also including a third channel region and a third source region 17 and a third drain region located on opposite sides of the third channel region; and a first gate 130, each first gate 130 extending along the second direction Y and covering a plurality of A first channel region and multiple second channel regions 14; a first gate 130 electrically connected to the main word line MWL; the first gate 130, the first source region 12, and the first drain region 13 constitute a pull-up transistor; the first gate 130, the second source region 15, and the second drain region 16 constitute a pull-down transistor; multiple second gates 140, each second gate 140 covering a corresponding third channel region; the second gate 140, the third source region 17, and the third drain region constitute a holding transistor; wherein, the first drain region 13 of a pull-up transistor is electrically connected to the second drain region 16 of a pull-down transistor and is electrically connected to the corresponding sub-word line; the third drain region of the same holding transistor is electrically connected to the second drain region 16 of a pull-down transistor, and the third source region 17 is electrically connected to the second drain region 16 of another pull-down transistor.

[0073] PMOS region 10 is used to form PMOS transistors, with pull-up transistors located in PMOS region 10, meaning the pull-up transistors are PMOS transistors. NMOS region 11 is used to form NMOS transistors, with pull-down transistors located in NMOS region 11, making the pull-down transistors NMOS transistors. First drain region 13 is used to form the drain of the pull-up transistor, and second drain region 16 is used to form the drain of the pull-down transistor. The first drain region 13 of the pull-up transistor 102 is electrically connected to the second drain region 16 of the pull-down transistor, and both the first drain region 13 and the second drain region 16 are also electrically connected to a sub-word line. Thus, the drive signal for driving the sub-word line can be transmitted from the source of the pull-up transistor to the drain of the pull-up transistor and input to the sub-word line to control the sub-word line drive; the drive signal for turning off the sub-word line can be transmitted from the source of the pull-down transistor to the drain of the pull-down transistor and input to the sub-word line to control the sub-word line turn off. Furthermore, since pull-up transistors and pull-down transistors are different types of transistors, when a pull-up transistor is on, the pull-down transistor is off, allowing the pull-up transistor to be used to drive the sub-word line; conversely, when a pull-down transistor is on, the pull-up transistor is off, allowing the pull-down transistor to be used to drive the sub-word line. In other words, pull-up transistors and pull-down transistors can be used to drive and turn off the sub-word line, respectively.

[0074] It is understood that a pull-up transistor and a pull-down transistor can be used to form a sub-word driver for driving and turning off a sub-word line. Since the pull-up transistor and the pull-down transistor are different types of transistors, with the pull-up transistor located in the PMOS region 10 and the pull-down transistor located in the NMOS region 11, in some embodiments, a metal layer may also be included for electrically connecting the first drain region 13 of the pull-up transistor and the second drain region 16 of the pull-down transistor.

[0075] refer to Figure 8 In some embodiments, when there are 8 first drain regions 13 and 8 second drain regions 16, the first drain regions 13 located in the PMOS region 10 are labeled as (1), (2), (3), (4), (5), (6), (7), and (8), respectively; and the second drain regions 16 located in the NMOS region 11 are labeled as (1), (2), (3), (4), (5), (6), (7), and (8), respectively. When the first drain regions 13 and the second drain regions 16 are electrically connected using metal layers, the metal layers can be configured to connect the first drain regions 13 and the second drain regions 16 with the same label. For example, the metal layers can electrically connect the first drain region 13 labeled (1) in the PMOS region 10 and the second drain region 16 labeled (1) in the NMOS region 11. In this way, when multiple metal layers are connected to the first drain regions 13 and the second drain regions 16, the extension direction of the multiple metal layers is consistent, that is, they extend along the second direction Y, which helps to simplify the complexity of the layout. In other embodiments, a metal layer may be provided to connect a first drain region 13 and a second drain region 16 with different markings. For example, the metal layer may be electrically connected to the first drain region 13 marked (1) in the PMOS region 10 and the second drain region 16 marked (2) in the NMOS region 11, as long as the metal layer connects one first drain region 13 to one second drain region 16.

[0076] Specifically, in some embodiments, the metal layer can be electrically connected to the first drain region 13 and the second drain region 16 via conductive plugs.

[0077] The first gate 130 can serve as the main word line MWL, and also as the gate of multiple pull-up transistors and pull-down transistors, thereby enabling the multiple pull-up transistors and pull-down transistors to drive multiple sub-word lines in response to the enable signal provided by the first gate 130.

[0078] The third drain region is used as the drain of the holding transistor, and the third source region 17 is used as the source of the holding transistor. The third source region 17 and the third drain region of the same holding transistor are electrically connected to the second drain regions 16 of two different pull-down transistors, respectively. That is, the source and drain of the same holding transistor are connected to the drains of two different pull-down transistors. Since the drains of the two different pull-down transistors are also connected to two different sub-word lines, the source and drain of the same holding transistor are also electrically connected to two different sub-word lines. In this way, a holding transistor can maintain the voltage stability of two different sub-word lines. This is because, at any given time, the word line driver can only drive one sub-word line. For example, if the number of sub-word lines is two, when one of the sub-word lines connected to the holding transistor is selected, the other sub-word line is in an unselected state. When it is necessary to turn off the selected sub-word line, the source and drain of the holding transistor are turned on, so that the level of the selected sub-word line is pulled to the same level as the unselected sub-word line, thereby ensuring that the selected sub-word line can be completely turned off.

[0079] Compared to using a holding transistor to control one sub-word line, in this embodiment of the disclosure, the source and drain of a holding transistor are electrically connected to two sub-word lines respectively, thereby controlling two sub-word lines. This greatly reduces the number of holding transistors in the word line driver, and thus reduces the layout area of ​​the word line driver.

[0080] In some embodiments, each first gate 130 includes: at least two extensions spaced apart along a first direction X, extending along a second direction Y and covering a plurality of first channel regions and a plurality of second channel regions 14; and a connecting portion 131 connected to the adjacent extensions arranged along the first direction X. The two extensions cover the plurality of first channel regions and the plurality of second channel regions 14, such that one first gate 130 is electrically connected to the plurality of first channel regions and the plurality of second channel regions 14 for controlling the conduction of a plurality of pull-up transistors, thereby allowing the pull-up transistors to be used to drive and turn off sub-word lines, respectively. The connecting portion 131 connects the adjacent extensions along the first direction X, such that two spaced-apart extensions are electrically connected to form a main word line MWL for controlling the conduction of the plurality of pull-up transistors and the second pull-down transistors.

[0081] In some embodiments, the material of the first gate 130 may include at least one of polysilicon or metal.

[0082] In some embodiments, the connection portion 131 covers the area between adjacent first active regions 110, and also covers the area between the first active region 110 and the second active region 120. Compared to the connection portion 131 only covering the area between the first active region 110 and the second active region 120, the connection portion 131 covers the area between both the first active region 110 and the second active region 120, thereby increasing the volume of the connection portion 131 and reducing its resistance. This helps to reduce signal delay and improve the performance of the word line driver.

[0083] Specifically, in some embodiments, when there are multiple first active regions 110, the connecting portion 131 can cover the area between each adjacent first active region 110, or it can only cover the area between one of the adjacent first active regions 110.

[0084] In other embodiments, the connecting portion 131 may only cover the area between the first active region 110 and the second active region 120, thereby reducing process complexity and saving material for forming the connecting portion 131.

[0085] refer to Figure 8 In some embodiments, along the first direction X, the distance between adjacent extensions of the NMOS region 11 is greater than the distance between adjacent extensions of a portion of the PMOS region 10, and the second gate 140 is located between adjacent extensions. That is, the distance between adjacent extensions of the portion of the PMOS region 10 is smaller, reducing the area occupied by the second gate 140, thereby helping to reduce the layout area of ​​the word line driver. The extensions located on both sides of the second gate 140 can serve as the gates of two different pull-up transistors, while the third drain region of the holding transistor and the third source region 17 of the holding transistor are electrically connected to the second drain regions 16 of the two different pull-down transistors, respectively. Therefore, when the second gate 140 is located between the two extensions, it is beneficial to form an electrical connection between the holding transistor and the second drain regions 16 of the different pull-down transistors on both sides, improving the rationality of the layout.

[0086] The extensions located on both sides of the second gate 140 belong to the same first gate 130. This means that the same main word line is connected to two sub-word line drivers, and the two sub-word line drivers share the same holding transistor; that is, one main word line corresponds to only one holding transistor. For details, please refer to the corresponding circuit diagram. Figure 3 as well as Figure 4Each main word line (MWL) is connected to at least two sub-word line drivers 100, and each main word line (MWL) corresponds to at least two sub-word lines. The two sub-word lines connected to the first and second ends each correspond to the same main word line (MWL). When there are eight sub-word line drivers 100, one main word line (MWL) can be connected to eight sub-word line drivers 100, and one main word line (MWL) corresponds to eight sub-word lines. Two sub-word lines share one sub-word line driver 100, meaning that one main word line (MWL) corresponds to only four holding transistors 101. Thus, when there are two main word lines (MWL), 16 sub-word lines can be driven, while only eight holding transistors 101 are needed, thereby greatly reducing the layout area of ​​the word line drivers.

[0087] Specifically, when the second gate 140 is located between two adjacent extensions, the principle of the word line driver driving the sub-word line and turning off the sub-word line can be as follows: taking the first gate 130 as the gate of two pull-up transistors and the gate of two pull-down transistors as an example, wherein the two pull-up transistors are respectively referred to as the first pull-up transistor and the second pull-up transistor, and the pull-down transistors are respectively referred to as the first pull-down transistor and the second pull-down transistor, wherein the first pull-down transistor is electrically connected to the source of the holding transistor 101, and the second pull-down transistor is electrically connected to the drain of the holding transistor.

[0088] The principle of driving the sub-word line connected to the first pull-up transistor is as follows: an enable signal is input to the first gate 130, and the gates of the first pull-up transistor and the second pull-up transistor are turned on in response to the enable signal. The holding transistor is turned off in response to the low-level second drive signal PXIB. The source of the first pull-up transistor is input to the high-level first drive signal PXID, and the source of the second pull-up transistor is input to the low-level first drive signal PXID, thereby making the sub-word line connected to the first pull-up transistor have a high level and be driven, and the sub-word line connected to the second pull-up transistor have a low level and be turned off.

[0089] The principle for closing the sub-word line connected to the first pull-up transistor is as follows: an enable signal is input to the first gate 130, and the gates of the first pull-down transistor and the second pull-down transistor are turned on in response to the enable signal. The holding transistor is turned on in response to the high-level second drive signal PXIB. The source of the first pull-down transistor is input to the low-level third drive signal VKK, thereby making the sub-word line connected to the drain of the first pull-down transistor have a low level. Since the source and drain of the holding transistor are connected to different pull-down transistors, the level of the sub-word line connected to the first pull-down transistor is pulled down to the level of the sub-word line connected to the second pull-down transistor, thereby turning off the sub-word line connected to the first pull-down transistor.

[0090] The process of driving the sub-word line connected to the second pull-down transistor and turning off the sub-word line connected to the second pull-down transistor is the same as the process described above, and will not be repeated here.

[0091] In some embodiments, each first gate 130 covers 4×N first channel regions and 4×N second channel regions 14. Each first gate 130 forms a pull-up transistor and a pull-down transistor, which are electrically connected to 2×N holding transistors; where N is a positive integer greater than or equal to 1. That is, the number of first channel regions and the number of second channel regions 14 are kept equal, such that the number of pull-up transistors is the same as the number of pull-down transistors. Each pull-up transistor and pull-down transistor 103 constitute a sub-word line driver. The number of holding transistors is half the number of pull-up transistors or pull-down transistors 103, allowing two sub-word line drivers to share a single holding transistor. This helps reduce the number of holding transistors in the word line driver, thereby reducing the layout area of ​​the word line driver.

[0092] Specifically, refer to Figure 8 as well as Figure 4 In some embodiments, N is 2, and there are 2 extensions, wherein one extension covers 4 first channel regions, and one extension also covers 4 second channel regions 14. Based on this, there are 8 pull-up transistors 102 and 8 pull-down transistors 103, forming 8 sub-word line drivers 100. Each sub-word line driver 100 corresponds to one sub-word line. There are 4 holding transistors 101, that is, one holding transistor 101 is used to control 2 sub-word lines, thereby making one main word line MWL formed by the first gate 130 used to control 8 sub-word lines. When there are 2 first gates 130, two main word lines MWL are used to control 8 sub-word lines.

[0093] In other embodiments, reference is made to... Figure 9 N can be 3, and there are 3 extensions, where one extension covers 4 first channel regions and one extension also covers 4 second channel regions 14. Based on this, there are 12 pull-up transistors and 12 pull-down transistors, forming 12 sub-word line drivers. Each sub-word line driver corresponds to one sub-word line. There are 6 holding transistors, that is, one holding transistor is used to control 2 sub-word lines, so that one main word line formed by the first gate 130 is used to control 12 sub-word lines. When the number of first gates 130 is 2, two main word lines are used to control 24 sub-word lines.

[0094] In some embodiments, the PMOS region 10 includes a first PMOS region 21 and a second PMOS region 22 arranged along a second direction Y, the second PMOS region 22 being located between the first PMOS region 21 and the NMOS region 11; two extensions of the same first gate 130 cover the same first active region 110 of the first PMOS region 21, and the two extensions also respectively cover two first active regions 110 of the second PMOS region 22 arranged along a first direction X; wherein, along the first direction X, the distance between adjacent extensions of the first PMOS region 21 is smaller than the distance between adjacent extensions of the second PMOS region 22.

[0095] Two extensions of the same first gate 130 cover the same first active region 110 of the first PMOS region 21, such that the two extensions of the formed first gate 130 are electrically connected to the same first active region 110 of the first PMOS region 21, thereby forming two pull-up transistors. The two extensions respectively cover two first active regions 110 of the second PMOS region 22 arranged along the first direction X, such that the two extensions are electrically connected to the two first active regions 110 respectively, forming two pull-up transistors. Since the two extensions of the first gate 130 are located on the same active region, the distance between adjacent extensions of the first PMOS region 21 is small, thereby reducing the area occupied by the first gate 130 and thus reducing the layout area.

[0096] Specifically, in some embodiments, in the first active region 110 of the first PMOS region 21, each extension covers a first channel region, and a first source region 12 is located between two first extensions for inputting a first drive signal PXID. A first drain region 13 is located on the side of the channel region away from the first extension and is used to form a pull-up transistor. The number of first source regions 12 located between two first extensions can be one, and the number of first drain regions 13 can be two, meaning that two pull-up transistors share the same first source region 12. This helps to improve the integration density of the formed word line driver and further reduce the layout area.

[0097] In the first active region 110 of the second PMOS region 22, each extension covers a first channel region, and the first source region 12 and the first drain region 13 are located on both sides of the first channel region. The first drain region 13 can be located between two extensions, and the first source region 12 can also serve as the source of a pull-up transistor corresponding to another first gate 130. Thus, when there are multiple first gates 130, the overall size of the active region can be reduced, resulting in a smaller layout area.

[0098] refer to Figure 10In some embodiments, along the first direction X, the distance between adjacent extensions of the NMOS region 11 is smaller than the distance between adjacent extensions of a portion of the PMOS region 10, and the second gate 140 is located outside the region enclosed by the two extensions. Thus, when multiple spaced-apart first gates 130 are present, the distance between the extensions of different first gates 130 in the NMOS region 11 is larger, providing more space for forming the second gate 140. The extensions located on both sides of the second gate 140 are used as gates for two different pull-up transistors, and since the extensions on both sides of the second gate 140 belong to different first gates 130, the same holding transistor formed corresponds to different main word lines (MWL).

[0099] The corresponding circuit diagram can be referenced. Figure 5 as well as Figure 6 Two sub-word line drivers 100 connected to different main word lines (MWL) share the same holding transistor 101. When the same main word line (MWL) is connected to eight different sub-word line drivers 100, one main word line (MWL) corresponds to eight holding transistors 101, and the two main word lines (MWL) share eight holding transistors 101. That is, the two main word lines (MWL) can drive a total of 16 sub-word lines, while the number of holding transistors 101 is still only eight, thereby reducing the number of holding transistors 101 in the sub-word line driver 100 and reducing the layout area of ​​the word line driving circuit. When a sub-word line driver 100 connected to two different main word lines (MWL) drives its connected sub-word lines, it can drive its connected sub-word lines in response to the enable signals from the different main word lines (MWL).

[0100] In some embodiments, the PMOS region 10 includes a first PMOS region 21 and a second PMOS region 22 arranged along a second direction Y, the second PMOS region 22 being located between the first PMOS region 21 and the NMOS region 11; two extensions of the same first gate 130 cover the same first active region 110 of the second PMOS region 22, and the two extensions also respectively cover two first active regions 110 of the first PMOS region 21 arranged along a first direction X; wherein, along the first direction X, the distance between adjacent extensions of the first PMOS region 21 is greater than the distance between adjacent extensions of the second PMOS region 22. That is, along the direction from the first PMOS region 21 to the second PMOS region 22, the distance between two extensions of the same first gate 130 tends to decrease, and since the distance between two extensions of the same first gate 130 in the NMOS region 11 adjacent to the second PMOS is also small, the orientation of the two extensions located in the second PMOS region 22 can be similar to or the same as the orientation of the two extensions located in the NMOS region 11, which helps to reduce the complexity of the layout design.

[0101] Specifically, in the first active region 110 of the first PMOS region 21, each extension covers a first channel region, and the first source region 12 and the first drain region 13 are located on both sides of the first channel region. The first drain region 13 can be located between two extensions, and the first source region 12 can also serve as the source of a pull-up transistor formed by another first gate 130. Thus, when there are multiple first gates 130, the overall size of the active region can be reduced, resulting in a smaller layout area.

[0102] In the first active region 110 of the second PMOS region 22, each extension covers a first channel region. A first source region 12 is located between two first extensions and is used to input a first drive signal PXID. A first drain region 13 is located on the side of the channel region away from the first extension and is used to form a pull-up transistor. The number of first source regions 12 located between two first extensions can be one, and the number of first drain regions 13 can be two, meaning that two pull-up transistors share the same first source region 12. This helps to improve the integration density of the formed word line driver and further reduce the layout area.

[0103] refer to Figure 10 In some embodiments, a connection portion 131 is provided between two extensions of the same first gate 130. The connection portion 131 is located in the second PMOS region 22, between two adjacent first active regions 110, and also between adjacent first active regions 110 and second active regions 120. In this way, not only can the volume of the first gate 130 be increased, but also, since the distance between two adjacent extensions in the second PMOS region 22 is small, the length of the connection portion 131 can be set to be smaller, thereby reducing the delay when the electrical signal lens connection portion 131 transmits.

[0104] refer to Figure 11 In other embodiments, the connection portion 131 may also be located between two adjacent first active regions 110 in the first PMOS region 21, which can further increase the volume of the first gate 130, thereby reducing the resistance of the first gate 130 and improving the transmission of electrical signals.

[0105] In some embodiments, the third channel region and at least one second channel region 14 belong to the same second active region 120. Both the third channel region and the second channel region 14 are located in the NMOS region 11, that is, the doped ion type in the second active region 120 corresponding to the third channel region is the same as the doped ion type in the second active region 120 corresponding to the second channel region 14. Therefore, setting the third channel region and the second channel region 14 to share the same second active region 120 not only helps to simplify the process flow, but also saves space in the second active region 120, improves the integration density of the word line driver layout structure, and reduces the area of ​​the layout structure.

[0106] Specifically, refer to Figure 8 In some embodiments, when the second gate 140 is located between adjacent extensions of the same first gate 130, the second drain region 16 of a pull-down transistor corresponding to the same first gate 130 is shared with the third drain region of a holding transistor, and the second drain region 16 of another pull-down transistor corresponding to the same first gate 130 is shared with the third source region 17 of the same holding transistor. The second gate 140 covers the surface of the third channel region so that the formed second gate 140 is electrically connected to the third channel region. The second gate 140 serves as the gate of the holding transistor, and the third drain regions and the third source regions 17 on both sides of the third channel region serve as the drain and source of the holding transistor, respectively. The two extensions located on both sides of the second gate 140 serve as the gates of two different pull-down transistors to provide a third drive signal VKK. The third drain region can serve as the drain of one of the pull-down transistors, and the third source region 17 can serve as the drain of the other pull-down transistor. The second source regions 15 of the two pull-down transistors are located on the side of the extension away from the third gate and serve as the source of the pull-down transistor. In some embodiments, the second source region 15 can also serve as the source of a pull-down transistor corresponding to another first gate 130. That is, the second drain region 16 of the same pull-down transistor is shared with the third drain region of the holding transistor, and the second source region 15 is shared with the second source region 15 of the pull-down transistor corresponding to another first gate 130. In this way, the occupied area of ​​the second active region 120 can be greatly reduced, thereby improving the integration density of the word line driver.

[0107] refer to Figure 10In other embodiments, when the second gate 140 is located outside the region enclosed by the two extensions, i.e., when the second gate 140 is located between two adjacent first gates 130, the second drain region 16 of the pull-down transistor 103 corresponding to one first gate 130 is shared with the third drain region of the holding transistor 101, and the second drain region 16 of the pull-down transistor 103 corresponding to the other first gate 130 is shared with the third source region 17 of the same holding transistor 101. The two extensions located on both sides of the second gate 140 belong to different first gates 130 and are used to form different pull-down transistors, i.e., the holding transistor is electrically connected to the pull-down transistors corresponding to the two different first gates 130. The third drain region located on one side of the third channel region can serve as the drain of one pull-down transistor corresponding to a first gate 130, and the third source region 17 located on the other side of the third channel region can serve as the drain of another pull-down transistor corresponding to a first gate 130. In this embodiment, the second source region 15 of the pull-down transistors corresponding to the two different first gates 130 is located on the side of the extension away from the second gate 140. In some embodiments, the two adjacent pull-down transistors corresponding to the same first gate 130 can also share the second source region 15, thereby reducing the occupied area of ​​the second active region 120 and thus reducing the layout area of ​​the word line driver.

[0108] It is understandable that when two active regions with different doping types are adjacent, a punch-through effect (Hot-Electron-Induced Punchthrough, HEIP) will occur. Specifically, when the circuit formed by the two active regions with different doping types is an analog circuit, their potentials may be different. When the potential difference between the two active regions is large enough, the depletion region of the active region will expand outward, thereby forming a punch-through current between the two active regions and generating electrical interference. Based on this, in some embodiments, the plurality of first active regions 110 include: at least two first active regions 110 disposed near the NMOS region 11, the two first active regions 110 being spaced apart along a first direction X and having a spacer region, wherein the second gate 140 is disposed opposite to the spacer region along a second direction Y. That is, the extension direction of the second gate 140 is the same as the extension direction of the spacer region, and the second gate 140 is located on the extension line of the spacer region. The second gate 140 is used to cover the third channel region, i.e., the third channel region is opposite to the spacer region. The spacer region is used to form an isolation structure between two spaced-apart first active regions 110. Therefore, the second gate 140 is positioned directly opposite the isolation structure, so that the third channel region of the second source region 15 is not adjacent to the first channel region of the first source region, which helps to improve the punch-through effect.

[0109] In the word line driver provided in the above embodiment, the third source region 17 and the third drain region of the same holding transistor are electrically connected to the second drain regions 16 of two different pull-down transistors, respectively. That is, the source and drain of the same holding transistor are connected to the drains of two different pull-down transistors. Since the drains of the two different pull-down transistors are also connected to two different sub-word lines, one holding transistor 101 is used to control two sub-word lines. Compared to one holding transistor being used to control one sub-word line, the number of holding transistors in the word line driver can be greatly reduced, thereby reducing the layout area of ​​the word line driver.

[0110] Accordingly, embodiments of this disclosure also provide a storage device, including: a storage cell array including a plurality of storage cells connected to a plurality of sub-word lines and a plurality of bit lines; a word line driving circuit provided in any of the above embodiments; or a word line driver provided in any of the above embodiments. In some embodiments, the storage cells may be DRAM storage cells.

[0111] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A word line drive circuit characterized by comprising: include: At least two sub-word line drivers, each of the sub-word line drivers being connected to a main word line and a sub-word line, the main word line being used to provide an enable signal; The sub-word line driver includes a holding transistor, the first and second ends of which are respectively connected to different sub-word lines, and the gate of the holding transistor receives a second driving signal; The sub-word line driver is configured to, in response to a first drive signal and an enable signal, provide the first drive signal to a selected sub-word line, wherein the selected sub-word line is a sub-word line connected to a first terminal or a second terminal of the holding transistor; and, in response to the first drive signal, the enable signal, and the second drive signal, turn on the first terminal and the second terminal of the holding transistor. In this configuration, the same main word line is connected to at least two sub-word line drivers, and the same main word line corresponds to at least two sub-word lines; the two sub-word lines connected to the first end and the second end respectively correspond to the same main word line. The sub-word line driver includes: A pull-up transistor has its gate connected to the main word line, its source receiving the first drive signal, and its drain connected to the sub-word line and either the first or second terminal of the holding transistor. The pull-down transistor has its gate connected to the main word line, its drain connected to the drain of the pull-up transistor, and its source receiving the third drive signal.

2. The word line driving circuit as described in claim 1, characterized in that, The holding transistor includes an NMOS transistor.

3. The word line drive circuit of claim 1, wherein, The pull-up transistor includes a PMOS transistor; the pull-down transistor includes an NMOS transistor.

4. A word line driver, according to any one of claims 1-3, characterized in that, include: The PMOS region includes a plurality of first active regions extending along a first direction, wherein the first active region includes a first channel region and a first source region and a first drain region located on opposite sides of the first channel region. The NMOS region, arranged along the second direction with the PMOS region, includes a plurality of second active regions extending along the first direction. The second active region includes a second channel region and a second source region and a second drain region located on opposite sides of the second channel region. The second active region also includes a third channel region and a third source region and a third drain region located on opposite sides of the third channel region. A first gate, each of the first gates extending along the second direction and covering a plurality of first channel regions and a plurality of second channel regions, the first gate being electrically connected to the main word line, the first gate, the first source region and the first drain region constituting a pull-up transistor, and the first gate, the second source region and the second drain region constituting a pull-down transistor. A plurality of second gates, each second gate covering a corresponding third channel region, the second gate, the third source region and the third drain region constituting a holding transistor; The first drain region of one of the pull-up transistors is electrically connected to the second drain region of one of the pull-down transistors, and is also electrically connected to the corresponding sub-word line. The third drain region of the same holding transistor is electrically connected to the second drain region of a pull-down transistor, and the third source region is electrically connected to the second drain region of another pull-down transistor; Wherein, the third channel region and at least one of the second channel regions belong to the same second active region; In this configuration, the second drain region of one pull-down transistor corresponding to the same first gate is shared with the third drain region of the holding transistor, and the second drain region of another pull-down transistor corresponding to the same first gate is shared with the third source region of the same holding transistor.

5. The word line driver of claim 4, wherein, Each of the first gates includes: At least two extensions spaced apart along the first direction extend along the second direction and cover a plurality of first channel regions and a plurality of second channel regions; A connecting portion, which connects to the extensions arranged adjacent to each other along the first direction.

6. The word line driver as claimed in claim 5, characterized in that, The connecting portion covers the area between adjacent first active regions, and also covers the area between the first active region and the second active region.

7. The word line driver of claim 5, wherein, Along the first direction, the distance between adjacent extensions of the NMOS region is greater than the distance between adjacent extensions of a portion of the PMOS region, and the second gate is located between adjacent extensions.

8. The word line driver of claim 7, wherein, The PMOS region includes: A first PMOS region and a second PMOS region are arranged along the second direction, wherein the second PMOS region is located between the first PMOS region and the NMOS region; The two extensions of the same first gate cover the same first active region of the first PMOS region, and the two extensions also respectively cover the two first active regions of the second PMOS region arranged along the first direction; Wherein, along the first direction, the distance between adjacent extensions of the first PMOS region is less than the distance between adjacent extensions of the second PMOS region.

9. The word line driver of claim 5, wherein, Along the first direction, the distance between adjacent extensions of the NMOS region is less than the distance between adjacent extensions of a portion of the PMOS region, and the second gate is located outside the region enclosed by the two extensions.

10. The word line driver of claim 8, wherein, The PMOS region includes: A first PMOS region and a second PMOS region are arranged along the second direction, wherein the second PMOS region is located between the first PMOS region and the NMOS region; The two extensions of the same first gate cover the same first active region of the second PMOS region, and the two extensions also respectively cover the two first active regions of the first PMOS region arranged along the first direction; Wherein, along the first direction, the distance between adjacent extensions of the first PMOS region is greater than the distance between adjacent extensions of the second PMOS region.

11. The word line driver of claim 4, wherein, Each of the first gates covers 4×N first channel regions and 4×N second channel regions, and the pull-up transistors and pull-down transistors formed by each of the first gates are electrically connected to 2×N holding transistors; wherein N is a positive integer greater than or equal to 1.

12. The word line driver of claim 4, wherein, The plurality of first active regions include: at least two first active regions disposed near the NMOS region, the two first active regions being spaced apart along the first direction and having a spacer region, wherein the second gate and the spacer region are disposed opposite each other along the second direction.

13. A memory device, comprising: include: A memory cell array comprising multiple memory cells connected to multiple subword lines and multiple bit lines. ； The word line driving circuit as described in any one of claims 1-3, or the word line driver as described in any one of claims 4-12.

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