Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method forms a gate dielectric layer and a work function layer on the gate dielectric layer in the gate trench, the first through trench and the second through trench in sequence, and then forms a protective layer conformally covering the work function layer, which can effectively prevent the top of the gate dielectric layer from being damaged in the subsequent removal of the shielding layer of the first device area, so as to improve the performance of the formed gate dielectric layer, and accordingly improve the performance of the formed semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are evolving towards higher device density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor material, are currently widely used. Therefore, as the device density and integration of semiconductor transistors increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirement of proportionally shrinking transistor dimensions, semiconductor manufacturing processes have gradually transitioned from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. GAA transistors include vertical and horizontal types. In a GAA transistor, the gate surrounds the channel region from all sides. Compared to planar transistors, GAA transistors offer stronger control over the channel and better suppress short-channel effects.

[0004] As device dimensions continue to shrink, improving the quality of the resulting fully enclosed gate transistors has become an urgent problem to be solved. Summary of the Invention

[0005] The problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To address the above problems, the present invention provides a method for forming a semiconductor structure, comprising:

[0007] A substrate is provided having adjacent first device regions and second device regions, and one or more stacked channel stacks, gate structures spanning the channel stacks, and dielectric layers located between the gate structures are formed on the substrates of the first device regions and the second device regions. The channel stacks include a sacrificial layer and a channel layer located on the sacrificial layer.

[0008] Remove the gate structure and form a gate trench in the dielectric layer;

[0009] Remove the sacrificial layer exposed by the gate trench to form a first through trench and a suspended first channel layer located in the first device region, and a second through trench and a suspended second channel layer located in the second device region;

[0010] A gate dielectric layer is formed at the bottom and sidewalls of the gate trench, and the gate dielectric layer also surrounds the first channel layer and the second trench layer;

[0011] Form a conformally conformal work function layer covering the gate dielectric layer;

[0012] A conformal protective layer is formed over the work function layer;

[0013] A shielding layer is formed on the dielectric layer, and the shielding layer further fills the gate trench, the first through trench and the second through trench;

[0014] Remove the shielding layer from the first device area;

[0015] Using the remaining masking layer as a mask, the protective layer and work function layer of the first device region are etched and removed sequentially to expose the gate dielectric layer of the first device region.

[0016] Optionally, the gate dielectric layer is a high-k gate dielectric layer, and the protective layer is made of aluminum oxide.

[0017] Optionally, the thickness of the protective layer is 3nm to 5nm.

[0018] Optionally, the process for forming the protective layer is atomic layer deposition.

[0019] Optionally, the step of removing the masking layer of the first device region includes: forming a patterned hard mask layer on the masking layer; and using the patterned hard mask layer as a mask, etching away the masking layer of the first device region.

[0020] Optionally, the material of the hard mask layer is aluminum oxide.

[0021] Optionally, the thickness of the hard mask layer is 30nm to 50nm.

[0022] Optionally, the process of etching away the shielding layer of the first device region is a dry etching process.

[0023] Optionally, after exposing the gate dielectric layer of the first device region, the method further includes:

[0024] Remove the remaining shielding layer;

[0025] After removing the shielding layer, remove the protective layer of the second device area.

[0026] Optionally, the process for removing the remaining shielding layer is an ashing process.

[0027] Optionally, the first device region is used to form a first type of transistor, and the second device region is used to form a second type of transistor, wherein the first type of transistor and the second type of transistor have different doping types.

[0028] Optionally, the first type of transistor is an NMOS transistor, and the second type of transistor is a PMOS transistor.

[0029] Optionally, before removing the gate structure, the method further includes:

[0030] Etch the channel stack on both sides of the gate structure of the first device region to form a first groove in the channel stack on both sides of the gate structure of the first device region.

[0031] The channel stack on both sides of the gate structure of the second device region is etched to form a second groove exposed in the channel stack on both sides of the gate structure of the second device region.

[0032] A first source / drain doped layer is formed within the first groove;

[0033] A second source / drain doped layer is formed within the second groove.

[0034] Optionally, the step of forming the first groove and the second groove includes:

[0035] A first sidewall layer is formed on the channel stack on both sides of the gate structure of the first device region, and a second sidewall layer is formed on the channel stack on both sides of the gate structure of the second device region; using the gate structure, the first sidewall layer and the second sidewall layer as a mask, the channel layers on both sides of the gate structure are etched to form the first groove and the second groove.

[0036] Optionally, the process for forming the first groove and the second groove includes an anisotropic dry etching process.

[0037] Optionally, the materials of the first sidewall layer and the second sidewall layer include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0038] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0039] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having adjacent first device regions and second device regions, wherein one or more stacked channel layers, a gate structure spanning the channel layers, and a dielectric layer located between the gate structures are formed on the substrate of the first device regions and the second device regions, the channel layers including a sacrificial layer and a channel layer located on the sacrificial layer; removing the gate structure to form a gate trench in the dielectric layer; removing the sacrificial layer exposed by the gate trench to form a first through-hole located in the first device region and a suspended first channel layer and a position... A second through trench and a suspended second channel layer are formed in the second device region; a gate dielectric layer is formed at the bottom and sidewalls of the gate trench, the gate dielectric layer also surrounding the first channel layer and the second trench layer; a conformal work function layer is formed covering the gate dielectric layer; a conformal protective layer is formed covering the work function layer; a shielding layer is formed on the dielectric layer, the shielding layer also filling the gate trench, the first through trench and the second through trench; the shielding layer of the first device region is removed; using the remaining shielding layer as a mask, the protective layer and the work function layer of the first device region are sequentially etched away to expose the gate dielectric layer of the first device region.

[0040] As can be seen, after the gate dielectric layer and the work function layer on the gate dielectric layer are formed sequentially in the gate trench, the first through trench and the second through trench, a conformal protective layer covering the work function layer is formed. This can effectively prevent the top of the gate dielectric layer from being damaged during the subsequent removal of the shielding layer of the first device region, thus improving the performance of the formed gate dielectric layer and correspondingly improving the performance of the formed semiconductor structure. Attached Figure Description

[0041] Figures 1 to 19 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0042] As is known from the background art, the fully enclosed gate transistors formed by existing methods have the problem of low performance.

[0043] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate having adjacent first device regions and second device regions, wherein one or more stacked channel layers, a gate structure spanning the channel layers, and a dielectric layer located between the gate structures are formed on the substrate of the first device regions and the second device regions; the channel layers include a sacrificial layer and a channel layer located on the sacrificial layer; removing the gate structure to form a gate trench in the dielectric layer; and removing the sacrificial layer exposed by the gate trench to form a first through-hole located in the first device region and a suspended first channel. The first device region is formed with a first trench and a second channel layer located in the second device region; a gate dielectric layer is formed at the bottom and sidewalls of the gate trench, the gate dielectric layer also surrounding the first channel layer and the second trench layer; a conformal work function layer is formed covering the gate dielectric layer; a conformal protective layer is formed covering the work function layer; a shielding layer is formed on the dielectric layer, the shielding layer also filling the gate trench, the first channel and the second channel; the shielding layer of the first device region is removed; using the remaining shielding layer as a mask, the protective layer and the work function layer of the first device region are sequentially etched away to expose the gate dielectric layer of the first device region.

[0044] As can be seen, after the gate dielectric layer and the work function layer on the gate dielectric layer are formed sequentially in the gate trench, the first through trench and the second through trench, a conformal protective layer covering the work function layer is formed. This can effectively prevent the top of the gate dielectric layer from being damaged during the subsequent removal of the shielding layer of the first device region, thus improving the performance of the formed gate dielectric layer and correspondingly improving the performance of the formed semiconductor structure.

[0045] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] Figures 1 to 19 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0047] See Figure 1 A substrate (not shown) is provided, the substrate having an adjacent first device region I and a second device region II, the substrate including a substrate 10 and a first fin 11 protruding on the substrate 10 of the first device region I and a second fin 12 protruding on the substrate 10 of the second device region II.

[0048] The substrate provides a process platform for forming transistors with a gate-all-around (GAA) structure.

[0049] In this embodiment, the substrate has a three-dimensional structure. Specifically, the substrate includes a substrate 10 and a first fin 11 and a second fin 12 protruding from the substrate 10.

[0050] In this embodiment, substrate 10 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. Furthermore, the substrate material may also be a material suitable for process requirements or easy to integrate.

[0051] The first device region I is used to form a first type of transistor, and the second device region II is used to form a second type of transistor. The first type of transistor and the second type of transistor have different doping types. Here, "first type" and "second type" refer to the doping types of the transistor, that is, the doping types of the source and drain doping layers in the transistor.

[0052] In this embodiment, the first device region I is used to form an NMOS transistor, and the second device region II is used to form a PMOS transistor. In other embodiments, the first device region can also be used to form a PMOS transistor, and the second device region can also be used to form an NMOS transistor.

[0053] In this embodiment, the materials of the first fin 11 and the second fin 12 are the same as the material of the substrate 10. Specifically, the materials of the first fin 11 and the second fin 12 are silicon.

[0054] Accordingly, the steps of forming substrate 10, first fin 11 and second fin 12 include: providing an initial substrate; forming a fin mask on the initial substrate; using the fin mask as a mask, etching a portion of the initial substrate to form substrate 10 and first fin 11 and second fin 12 located on substrate 10.

[0055] See Figure 2 A channel stack 20 is formed on the substrate 10, covering one or more stacks of the first fin 11 and the second fin 12. The channel stack 20 includes a sacrificial layer 21 and a channel layer 22 located on the sacrificial layer 21.

[0056] The channel stack 20 provides a basis for the subsequent formation of a channel layer suspended above the first device region I and the second device region II.

[0057] Specifically, the sacrificial layer 21 is used to support the channel layer 22, thereby providing a process basis for the subsequent floating of the channel layer 22 in the first device region I and the second device region II, and occupying part of the space for the subsequent formation of the first device gate and the second device gate.

[0058] In order to effectively reduce the impact of the removal process of the sacrificial layer 21 on the channel layer 22 during the subsequent removal process, the sacrificial layer 21 should be made of a material with a higher etching selectivity rate than the channel layer 22. In this embodiment, the material of the sacrificial layer 21 is silicon-germanium, and the material of the channel layer 22 is silicon.

[0059] In this embodiment, the channel stack 20 is formed on the substrate 10 and covers the first fin 11 and the second fin 12, so as to provide a basis for the subsequent formation of the channel layer suspended on the first fin 11 and the second fin 12.

[0060] The step of forming the channel stack 20 includes: forming one or more stacked channel material stacks (not shown) on a substrate 10, the channel material stacks further covering a first fin 11 and a second fin 12, the channel material stacks including a sacrificial material layer (not shown) and a channel material layer (not shown) located on the sacrificial material layer; and patterning the channel material stacks to form one or more stacked channel stacks 20 located on the first fin 11 and the second fin 12.

[0061] In this embodiment, there are three channel stacks 20, and correspondingly, three channel material stacks. In other embodiments, the number of channel stacks can be more or less.

[0062] In this embodiment, the channel material stack is formed on the substrate 10 and the first fin 11 and the second fin 12 by an epitaxial growth process. The epitaxial growth process can form a sacrificial material layer and a channel material layer of good quality, so that the formation quality of the sacrificial layer 21 and the channel layer 22 is also relatively good. The channel of the formed gate-enclosed transistor is located in high-quality material, which is beneficial to improving device performance.

[0063] See Figure 4 In this embodiment, after forming the channel stack 20, the method further includes forming a gate structure 30 on the substrate 10 that spans the first fin 11, the second fin 12 and the channel stack 20.

[0064] The gate structure 30 occupies space for the subsequent formation of the gate of the first device and the gate of the second device.

[0065] In this embodiment, the gate structure 30 covers part of the sidewall of the first fin 11 of the first device region I, part of the sidewall of the second fin 12 of the second device region II, and part of the top and sidewall of the channel stack 20.

[0066] In this embodiment, the gate structure 30 is a single-layer structure. Specifically, the gate structure 30 includes a dummy gate layer, which covers part of the sidewall of the first fin 11 of the first device region I, part of the sidewall of the second fin 12 of the second device region II, and part of the top and sidewall of the channel stack 20.

[0067] Specifically, the steps of forming the gate structure 30 include: forming a dummy gate material layer (not shown) that spans the channel stack 20; forming a gate mask layer (not shown) on the surface of the dummy gate material layer; and etching the dummy gate material layer using the gate mask layer as a mask until the channel stack 20 is exposed to form the gate structure 30.

[0068] In this embodiment, the dummy gate layer is made of polycrystalline silicon. In other embodiments, the dummy gate layer may be made of one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or amorphous carbon.

[0069] In this embodiment, the process for forming the dummy gate material layer is chemical vapor deposition. In other embodiments, the process for forming the dummy gate material layer can also be physical vapor deposition, atomic layer deposition, or high-temperature furnace tube deposition, etc.

[0070] In this embodiment, the material of the gate mask layer is silicon nitride.

[0071] In this embodiment, the process for forming the gate mask layer is chemical vapor deposition. In other embodiments, the process for forming the gate mask layer can also be at least one of physical vapor deposition and atomic layer deposition.

[0072] In other embodiments, the gate structure may also be a stacked structure. Specifically, the gate structure includes a dummy gate oxide layer and a dummy gate layer located on the dummy gate oxide layer. In this embodiment, the dummy gate oxide layer also conformally covers the exposed channel stacked surface of the dummy gate layer. The material of the dummy gate oxide layer is silicon oxide or silicon oxynitride.

[0073] In this embodiment, the gate mask layer is removed after the gate structure is formed. In other embodiments, the gate mask layer can be retained after the gate structure is formed to protect the top of the gate structure in subsequent processes.

[0074] See Figure 5 In this embodiment, after forming the gate structure 30, the method further includes: forming a first sidewall layer 41 on the channel stack 20 on both sides of the gate structure 30 in the first device region I, and forming a second sidewall layer 42 on the channel stack 20 on both sides of the gate structure 30 in the second device region II; using the gate structure 30, the first sidewall layer 41 and the second sidewall layer 42 as masks, etching the channel layers on both sides of the gate structure 30 to form a first groove 51 located in the channel stack 20 on both sides of the gate structure 30 in the first device region I and a second groove 52 located in the channel stack 20 on both sides of the gate structure 30 in the second device region II.

[0075] The first sidewall layer 41 and the second sidewall layer 42 are used as etching masks for subsequent etching processes to define the formation areas of the subsequent first source / drain doped layer and the second source / drain doped layer. The first sidewall layer 41 and the second sidewall layer 42 are also used to protect the sidewalls of the gate structure 30 in subsequent processes.

[0076] The materials of the first sidewall layer 41 and the second sidewall layer 42 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the materials of the first sidewall layer 41 and the second sidewall layer 42 are silicon nitride.

[0077] In other embodiments, the first sidewall layer and the second sidewall layer can also be stacked structures.

[0078] The first groove 51 is used to provide space for the subsequent formation of the first source / drain doped layer, and the second groove 52 is used to provide space for the subsequent formation of the second source / drain doped layer.

[0079] In this embodiment, the etching process for the channel stack 20 on both sides of the gate structure 30 is a dry etching process. The dry etching process is easy to achieve anisotropic etching and has good profile control, which is beneficial to improving the morphological quality of the formed first groove 51 and second groove 52, and also beneficial to improving etching efficiency.

[0080] After the first groove 51 and the second groove 52 are formed, the sidewall of the channel layer 22 and the sidewall of the sidewall 50 are flush with each other in a direction perpendicular to the sidewall of the gate structure 30.

[0081] See Figure 6 In this embodiment, after forming the first groove 51 and the second groove 52, the method further includes: etching a sacrificial layer 21 of a portion of the exposed thickness of the sidewalls of the first groove 51 and the second groove 52 along a preset direction to form a first trench and a second trench, respectively. The first trench is surrounded by the adjacent channel layer 22 on the first fin 11 and the remaining sacrificial layer 21, or the first trench is surrounded by the first fin 11, the channel layer 22 adjacent to the first fin 11 and the remaining sacrificial layer 21. The second trench is surrounded by the adjacent channel layer 22 on the second fin 12 and the remaining sacrificial layer 21, or the second trench is surrounded by the second fin 12, the channel layer 22 adjacent to the second fin 12 and the remaining sacrificial layer 21. A first inner wall layer 71 is formed in the first trench, and a second inner wall layer 72 is formed in the second trench. The preset direction is a direction parallel to the substrate 100 and perpendicular to the extension direction of the gate structure.

[0082] In this embodiment, a wet etching process is used to etch the exposed portion of the sacrificial layer 21 on the sidewalls of the first groove 51 and the second groove 52. The wet etching process is an isotropic etching process, which allows the sacrificial layer 21 to be etched and removed along a direction perpendicular to the sidewalls of the gate structure 30. Furthermore, the wet etching process easily achieves a large etching selectivity, which helps reduce the difficulty of etching the sacrificial layer 21 and minimizes damage to other film structures.

[0083] In this embodiment, the sacrificial layer 21 is made of silicon-germanium, and the channel layer 11 is made of silicon. The exposed sacrificial layer 21 is wet-etched using hydrogen chloride (HCl) vapor. The etching rate of hydrogen chloride vapor on silicon-germanium is much greater than that on silicon. Therefore, using hydrogen chloride vapor to etch the exposed sacrificial layer 21 in the first groove 51 and the second groove 52 can effectively reduce the probability of damage to the channel layer 22.

[0084] The first inner wall layer 71 serves as an inner spacer, covering the sidewall of the first device gate at the location of the remaining sacrificial layer 11 subsequently formed in the first device region I. It can isolate the first source / drain doped layer from the first device gate and increase the distance between the subsequent first device gate and the first source / drain doped layer, thereby reducing the parasitic capacitance between the first device gate and the first source / drain doped layer and improving the performance of the formed semiconductor structure.

[0085] The second inner wall layer 72 is used to cover the sidewall of the second device gate subsequently formed at the location of the remaining sacrificial layer 21. It can isolate the second source / drain doped layer from the second device gate and increase the distance between the subsequently formed second device gate and the second source / drain doped layer, thereby reducing the parasitic capacitance between the second device gate and the second source / drain doped layer and improving the performance of the formed semiconductor structure.

[0086] The first inner wall layer 71 and the second inner wall layer 72 are made of dielectric materials. Specifically, the materials of the first inner wall layer 71 and the second inner wall layer 72 include silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric materials, or ultra-low-k dielectric materials. In this embodiment, the materials of the first inner wall layer 71 and the second inner wall layer 72 are silicon oxide. Silicon oxide is a commonly used dielectric material in semiconductor processes, which is beneficial for improving process compatibility and reducing process costs.

[0087] In this embodiment, the first inner wall layer 71 and the second inner wall layer 72 are formed in the same process step.

[0088] Specifically, the steps of forming the first inner wall layer 71 and the second inner wall layer 72 include: forming an inner wall film (not shown) that conformally covers the top and sidewalls of the gate structure 30, the bottom and sidewalls of the first groove 51, and the bottom and sidewalls of the second groove 52; removing the inner wall film on the exposed channel layer 22 of the top and sidewalls of the gate structure 30, the bottom and sidewalls of the first groove 51, and the exposed channel layer 22 of the bottom and sidewalls of the second groove 52, retaining the inner wall film on the exposed sacrificial layer 21 of the sidewall of the first groove 51 as the first inner wall layer 71, and retaining the inner wall film on the exposed sacrificial layer 21 of the sidewall of the second groove 52 as the second inner wall layer 72.

[0089] In this embodiment, an atomic layer deposition (ALD) process is used to form the inner wall film. The ALD process has good step coverage capability, which is beneficial to improve the conformal coverage capability of the inner wall film on the top and sidewalls of the gate structure 30, the bottom and sidewalls of the first groove 51, and the bottom and sidewalls of the trench of the second groove 52. Furthermore, the ALD process is also beneficial to precisely control the thickness of the formed inner wall film.

[0090] In other embodiments, other deposition processes with better filling performance can also be used to form the inner wall film, such as low-pressure chemical vapor deposition (LPCVD), etc., which are not limited here.

[0091] In this embodiment, anisotropic etching and isotropic etching processes are sequentially used to etch the inner wall film, thereby removing the inner wall film exposed on the top and sidewalls of the gate structure 30, the bottom and sidewalls of the first groove 51, and the bottom and sidewalls of the second groove 52. The inner wall film located in the first groove is difficult to remove due to obstruction by adjacent channel layers 22, or by the first fin 11 and adjacent channel layers 22. Similarly, the inner wall film located in the second groove is difficult to remove due to obstruction by adjacent channel layers 22, or by the second fin 11 and adjacent channel layers 22. Therefore, the inner wall film on the sidewalls of the sacrificial layer 21 exposed on the sidewalls of the first groove 51 and the second groove 52 can be retained, forming the first inner wall layer 71 and the second inner wall layer 72, respectively.

[0092] Please continue reading Figure 6 In this embodiment, after forming the first inner wall layer 71 and the second inner wall layer 72, the method further includes: forming a first source / drain doped layer 61 in the first groove 51 and forming a second source / drain doped layer 62 in the second groove 52.

[0093] The first source / drain doped layer 61 and the second source / drain doped layer 62 are used to provide carrier sources when the device is in operation.

[0094] In this embodiment, the steps of forming the first source / drain doped layer 61 and the second source / drain doped layer 62 include: forming a first stress layer and a second stress layer in the first groove 51 and the second groove 52 respectively using an epitaxial growth process, and performing a first in-situ self-doping and a second in-situ self-doping respectively during the formation of the first stress layer and the second stress layer to form the first source / drain doped layer 61 and the second source / drain doped layer 62.

[0095] The first source / drain doped layer 61 includes a first stress layer, thereby providing tensile stress to the channel during device operation, which is beneficial to improving the carrier mobility of the second type of transistor.

[0096] The material of the second source / drain doped layer 62 includes a second stress layer, thereby providing compressive stress to the channel when the device is in operation, which is beneficial to improving the carrier mobility of the second type of transistor.

[0097] In this embodiment, the material of the first stress layer is silicon or silicon-germanium, and the doping ions in the first stress layer are N-type ions; the material of the second stress layer is silicon or silicon carbide, and the doping ions in the second stress layer are P-type ions.

[0098] In this embodiment, the top surfaces of the first source / drain doped layer 61 and the second source / drain doped layer 62 are flush with the top surface of the channel stack 20. In other embodiments, the top surfaces of the first source / drain doped layer and the second source / drain doped layer may also be higher than the top surface of the channel stack, and correspondingly, the first source / drain doped layer and the second source / drain doped layer also cover part of the sidewall of the sidewall layer.

[0099] See Figure 7 A dielectric layer 80 covering the first source / drain doped layer 61 and the second source / drain doped layer 62 is formed on the substrate 10 on the side of the gate structure 30. The top surface of the dielectric layer 80 is flush with the top surface of the gate structure 30. The gate structure 30 is removed, and a gate trench 31 exposing the channel stack 20 is formed in the dielectric layer 80.

[0100] The dielectric layer 80 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the material of the dielectric layer 80 is silicon oxide. In other embodiments, the material of the dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0101] Specifically, the step of forming dielectric layer 80 includes: forming a dielectric material layer (not shown) on substrate 10 that covers channel stack 20, gate structure 30, first source / drain doped layer 61 and second source / drain doped layer 62; planarizing the dielectric material layer until the top surface of gate structure 30 is exposed to form dielectric layer 80.

[0102] In this embodiment, a dry etching process is used to remove the gate structure 30.

[0103] The gate trench 31 provides a spatial location for the subsequent formation of the first device gate and the second device gate, and provides a basis for removing the sacrificial layer 21 of the first device region I and the second device region II.

[0104] See Figure 8 Remove the sacrificial layer 21 exposed by the gate trench 31 to form a first through trench 32 and a suspended first channel layer 321 located in the first device region I, and a second through trench 33 and a suspended second channel layer 322 located in the second device region II.

[0105] The first channel layer 321 is used to provide a conductive channel when the first type of transistor is operating, and the second channel layer 322 is used to provide a conductive channel when the second type of transistor is operating.

[0106] In this embodiment, a wet etching process is used to remove the sacrificial layer 21 exposed in the gate trench 31.

[0107] After removing the sacrificial layer 21 exposed in the gate trench 31, the channel layers 22 of the first device region I and the second device region II exposed in the gate trench 31 form a suspended first channel layer 321 and a suspended second channel layer 322, respectively.

[0108] In this embodiment, the sacrificial layer 21 is made of silicon germanium and the channel layer 22 is made of silicon. Therefore, the sacrificial layer 21 exposed in the gate trench 31 is removed by hydrogen chloride vapor.

[0109] The first source / drain doped layer 61 and the second source / drain doped layer 62 are formed before the sacrificial layer 21 of the first device region I and the second device region II is removed. Therefore, after the sacrificial layer 21 exposed by the gate trench 31 is removed, along the extension direction of the channel layer 11, the two ends of the first channel layer 321 are connected to the first source / drain doped layer 61, and the two ends of the second channel layer 322 are connected to the second source / drain doped layer 62, so that the first channel layer 22 and the second channel layer 322 are suspended in the gate trench 31, thereby providing a basis for the subsequent formation of the first device gate and the second device gate with a fully enclosed structure.

[0110] Accordingly, after removing the sacrificial layer 21 of the first device region I and the second device region II, a first through-slot 32 located in the first device region I and a second through-slot 33 located in the second device region II are formed.

[0111] Specifically, the first through-slot 32 is formed by the first fin 11, the channel layer 22 located on the first fin 11, and the first source / drain doped layer 61, or the first through-slot 32 is formed by the adjacent channel layer 22 and the first source / drain doped layer 61, and the first through-slot 32 is connected to the gate trench 31.

[0112] The second through trench 33 is formed by the second fin 12, the channel layer 22 located on the second fin 12, and the second source / drain doped layer 62. Alternatively, the second through trench 33 is formed by the adjacent channel layer 22 and the second source / drain doped layer 62, and the second through trench 33 is connected to the gate trench 31.

[0113] See Figure 9 A gate dielectric layer 91 is formed at the bottom and sidewalls of the gate trench 31, and the gate dielectric layer 91 also surrounds the first channel layer 321 and the second channel layer 322.

[0114] The gate dielectric layer 91 is used to achieve electrical isolation between the subsequently formed gate electrode layer and the channel.

[0115] In this embodiment, the gate dielectric layer 91 is a high-k gate dielectric layer, meaning that the material of the gate dielectric layer 91 is a high-k gate dielectric material. Specifically, the high-k gate dielectric material is a dielectric material with a dielectric constant greater than 3.9. Specifically, the high-k gate dielectric material includes one or more of hafnium dioxide (HfO2), zirconium dioxide (ZrO2), hafnium oxide silicate (HfSiO), and hafnium silicate nitride (HfSiON).

[0116] The gate dielectric layer 91 can be a single-layer structure or a multilayer structure. In this embodiment, the gate dielectric layer 91 is a single-layer structure. Specifically, the material of the gate dielectric layer 91 is hafnium dioxide.

[0117] In this embodiment, the gate dielectric layer 91 is located on the upper surface, lower surface and side surface of the first channel layer 321 and the second channel layer 322, and the gate dielectric layer 91 also covers part of the top and part of the sidewall of the first fin 11 and the second fin 12.

[0118] The steps of forming the gate dielectric layer 91 include: forming an initial gate dielectric layer at the bottom and sidewalls of the gate trench 31, the initial gate dielectric layer also surrounding the first channel layer 321 and the second channel layer 322 and also formed on the dielectric layer 80; planarizing the initial gate dielectric layer; removing the initial gate dielectric layer on the dielectric layer 80 to form the gate dielectric layer 91.

[0119] The process for forming the initial gate dielectric layer includes deposition processes. Specifically, deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0120] In this embodiment, atomic layer deposition (ALD) is used to form the initial gate dielectric layer. ALD processes operate at relatively low temperatures, which helps to minimize the impact on device performance. Furthermore, ALD has excellent step coverage capabilities, which improves the thickness uniformity of the formed initial gate dielectric layer and enhances its conformal coverage.

[0121] See Figure 10 This forms the first initial work function layer 92 of the conformal cover gate dielectric layer 91.

[0122] The first initial work function layer 92 is used to form a part of the second work function layer located in the second device region II.

[0123] The material of the first initial work function layer 92 includes one or more of titanium nitride, tantalum nitride, silicon tantalum nitride, titanium silicon nitride, tantalum carbide, titanium aluminide, tantalum carbide, aluminum, and titanium carbide. In this embodiment, the material of the first initial work function layer 92 is titanium nitride.

[0124] In this embodiment, an atomic layer deposition (ALD) process is used to form the first initial work function layer 92. ALD has excellent step coverage capability, which helps improve the conformal coverage of the first initial work function layer 92 on the gate dielectric layer 91. Furthermore, ALD allows for precise control of the thickness of the formed first initial work function layer 92.

[0125] See Figure 11 A protective layer 93 is formed that conformally covers the first initial work function layer 92.

[0126] The protective layer 93 is used to protect the gate dielectric layer 91 and the first initial work function layer 92 during the subsequent removal of the shielding layer formed on the protective layer 93.

[0127] Specifically, the presence of the protective layer 93 can prevent the subsequent removal of the shielding layer from damaging the gate dielectric layer 91 and the first initial work function layer 92, thus improving the quality of the formed gate dielectric layer 91 and the first initial work function layer 92, and thereby improving the formation quality of the formed semiconductor structure.

[0128] In this embodiment, the material of the protective layer 93 is aluminum oxide (Al2O3).

[0129] The subsequent step also includes the removal of the protective layer 93. Using aluminum oxide as the protective layer 93 allows for the removal of the protective layer 93 using an alkaline etching solution, which shortens the removal time. The process of removing the protective layer 93 causes less damage to other film layers, thereby improving the quality of the formed semiconductor structure.

[0130] The thickness of the protective layer 93 should not be too large or too small. If the thickness of the protective layer 93 is too small, it will not be able to provide adequate protection for the top of the gate dielectric layer 91 and the first initial work function layer 92 during the subsequent removal of the shielding layer; if the thickness of the protective layer 93 is too large, it will correspondingly increase the time and difficulty of removing the protective layer 93, and will not be conducive to cost savings. Therefore, in this embodiment, the thickness of the protective layer 93 is 3nm to 5nm.

[0131] See Figure 12 A shielding layer 94 is formed on the dielectric layer 80, and the shielding layer 94 also fills the gate trench 31, the first through trench 32 and the second through trench 33.

[0132] The shielding layer 94 is used to define the pattern, position and thickness of the first work function layer formed in the first device region I and the second work function layer formed in the second device region II.

[0133] Specifically, the masking layer 94 of the first device region I is first removed, and the protective layer 93 and the first initial work function layer 92 of the first device region I are removed using the remaining masking layer 94 as a mask. Then, the masking layer 94 and the protective layer 93 on the second device region II are removed, so that the first initial work function layer 92 on the second device region II becomes part of the second work function layer. Subsequently, a second initial work function layer is formed on the first initial work function layer 92 on the second device region II. The second initial work function layer is also located on the gate dielectric layer 91 of the first device region I, so that the second initial work function layer on the gate dielectric layer 91 of the first device region I forms the first work function layer, and the first initial work function layer 92 and the second initial work function layer on the second device region II together form the second work function layer.

[0134] In this embodiment, the material of the shielding layer 94 is a bottom anti-reflective coating (BARC) material. In other embodiments, the material of the shielding layer may also be one or more of spin-on carbon (SOC) material, photoresist, dielectric anti-reflective coating (DARC) material, and organic dielectric layer (ODL) material.

[0135] The steps of forming the shielding layer 94 include: forming a shielding material layer (not shown in the figure) covering the first device region I, the second device region II and the dielectric layer 80; planarizing the shielding material layer so that the top surface of the shielding material layer is flush with each other to form the shielding layer 94.

[0136] In this embodiment, a spin coating process is used to form a masking material layer.

[0137] In this embodiment, the planarization process for the masking material layer is chemical mechanical polishing. In other embodiments, the planarization process for the masking material layer can also be etching back, etc.

[0138] See Figure 13 and 14 Remove the masking layer 94 from the first device region I.

[0139] Remove the shielding layer 94 of the first device region I to expose the protective layer 93 of the first device region I, thereby providing a basis for the subsequent removal of the protective layer 93 and the first initial work function layer 92 of the first device region I.

[0140] The step of removing the masking layer 94 of the first device region I includes: forming a patterned hard mask layer 95 on the masking layer 94; and using the patterned hard mask layer 95 as a mask, etching to remove the masking layer 94 of the first device region I.

[0141] In this embodiment, the process for forming the patterned hard mask layer 95 includes deposition, photolithography, and etching processes.

[0142] In this embodiment, the process of etching away the masking layer 94 of the first device region I using a patterned hard mask layer 95 as a mask is a dry etching process.

[0143] In this embodiment, after etching away the masking layer 94 of the first device region I, the remaining hard mask layer 95 is removed. Therefore, the hard mask layer 95 is made of an easily removable material. In this embodiment, the material of the hard mask layer 95 is aluminum oxide.

[0144] Alumina is an easily removable material, which can reduce the time required to remove the hard mask layer 95 in subsequent processes, thereby avoiding damage to other film layers caused by prolonged etching processes. Moreover, since the hard mask layer 95 and the protective layer 93 are made of the same material, they can be removed in the same process, thus saving process costs and improving work efficiency.

[0145] In this embodiment, during the process of removing the shielding layer 94 of the first device region I, the protective layer 93 can protect the gate dielectric layer 91 below it, so that the gate dielectric layer 91 is not damaged during the etching of the shielding layer 94 of the first device region I, thereby improving the morphological quality of the gate dielectric layer 91 and enhancing the performance of the formed semiconductor structure.

[0146] See Figure 15 Using the remaining shielding layer 94 as a mask, the protective layer 93 and the first initial work function layer 92 of the first device region I are removed sequentially.

[0147] The protective layer 93 and the first initial work function layer 92 of the first device region I are removed sequentially to expose the gate dielectric layer 91 of the first device region I, so as to provide a basis for the subsequent formation of the first work function layer located on the gate dielectric layer 91 of the first device region I.

[0148] In this embodiment, the process for removing the protective layer 93 of the first device region I is a wet etching process.

[0149] Specifically, the protective layer 93 is made of aluminum oxide, and the etching solution used is ammonia (NH4.H2O). As an alkaline etching solution, ammonia can quickly remove the protective layer 93, reduce etching time and difficulty, and minimize damage to other film layers.

[0150] As mentioned above, the protective layer 93 and the hard mask layer 95 of the first device region I are both made of aluminum oxide. Both are removed in the same wet etching process, which simplifies the process operation and saves process costs.

[0151] In this embodiment, after removing the protective layer 93 of the first device region I, a wet etching process is used to remove the first initial work function layer 92 located in the first device region I.

[0152] In this embodiment, the material of the first initial work function layer 92 is titanium nitride, and the etching solution used to remove the first initial work function layer 92 located in the first device region I is hydrogen peroxide (H2O2). In other embodiments, other suitable etching solutions can also be used to etch and remove the first initial work function layer 92 of the first device region I, such as nitric acid, phosphoric acid, etc.

[0153] See Figure 16 In this embodiment, after removing the protective layer 93 and the first initial work function layer 92 of the first device region I, the semiconductor structure formation method further includes removing the remaining shielding layer 94.

[0154] Remove the remaining shielding layer 94 to expose the protective layer 93 of the second device region II.

[0155] In this embodiment, the shielding layer 94 is a bottom anti-reflective layer, and correspondingly, the process for removing the remaining shielding layer 94 is an ashing process. In other embodiments, the shielding layer can also be made of other suitable materials, and correspondingly, other suitable removal processes can be used to remove the remaining shielding layer.

[0156] The remaining first initial work function layer 92 in the second device region II is located below the protective layer 93, so that during the removal of the remaining shielding layer 94, the protective layer 93 can protect the top of the first initial work function layer 92 below it, thereby preventing the removal process of the remaining shielding layer 94 from protecting the first initial work function layer 92 in the second device region II. Subsequently, the first initial work function layer 92 on the second device region II becomes part of the second work function layer, which helps to improve the performance of the formed second work function layer.

[0157] See Figure 17 In this embodiment, after removing the remaining shielding layer 94, the semiconductor structure formation method further includes removing the protective layer 93 of the second device region II.

[0158] The protective layer 93 of the second device region II is removed, exposing the first initial work function layer 92 of the second device region II. The exposed first initial work function layer 92 of the second device region II is part of the second work function layer formed in the second device region II.

[0159] After removing the protective layer 93 of the second device region, a second initial work function layer is formed on the first initial work function layer 92 of the second device region II. The first initial work function layer 92 and the second initial work function layer of the second device region II together serve as the second work function layer.

[0160] In this embodiment, ammonia water is used to remove the protective layer 93 of the second device region II.

[0161] See Figure 18 In this embodiment, after removing the protective layer 93 of the second device region II, the semiconductor structure formation method further includes: forming a second initial work function layer 96 covering the high-k gate dielectric layer 91 and the first initial work function layer 92 of the first device region I.

[0162] After forming the second initial work function layer 96, the second initial work function layer 96 located in the first device region I serves as the first work function layer, which is used to adjust the threshold voltage of the NMOS transistor when it is operating. Simultaneously, the second initial work function layer 96 and the first initial work function layer 92 located in the second device region II serve as the second work function layer, which is used to adjust the threshold voltage of the PMOS transistor when it is operating.

[0163] The material of the second initial work function layer 96 includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, tantalum carbide, aluminum, and titanium aluminide. In this embodiment, the material of the third initial work function layer 95 is titanium nitride.

[0164] In this embodiment, the process for forming the second initial work function layer 96 is an atomic layer deposition process.

[0165] As described above, the first work function layer is composed of a second initial work function layer 96 located in the first device region I, while the second work function layer is composed of a second initial work function layer 96 located in the second device region II and a first initial work function layer 92 located in the second device region II. Therefore, the thickness of the first work function layer is less than that of the second work function layer. In other embodiments, the thickness of the first work function layer may be greater than or equal to the thickness of the second work function layer, which is not limited here.

[0166] See Figure 19 In this embodiment, after forming the second initial work function layer 96, the semiconductor structure formation method further includes: forming a gate electrode layer filled with gate trench 31, first through trench 32 and second through trench 33 on the first work function layer and the second work function layer, and forming a first metal gate 101 located in the first device region I and a second metal gate 102 located in the second device region II.

[0167] The first metal gate 101 spans the first fin 11 and the first channel layer 321 and also surrounds the first channel layer 32, and the second metal gate spans the second fin 12 and the second channel layer 322 and also surrounds the second channel layer 322.

[0168] The first metal gate 101 is used to control the opening or closing of the conductive channel of the first type of transistor when the device is working, and the second metal gate 102 is used to control the opening or closing of the conductive channel of the second type of transistor when the device is working.

[0169] In this embodiment, the gate trench 31 is connected to the first through trench 32 and the second through trench 33. Therefore, after the gate electrode layer is formed in the gate trench 31, the gate electrode layer is also located in the first through trench 32 and the second through trench 33, so that the gate electrode layer can surround the first channel layer 321 and the second channel layer 322 from all sides. That is, the gold gate electrode layer can cover the upper surface, lower surface and side surface of the first channel layer 321 and the second channel layer 322, and the gate electrode layer also covers part of the top of the substrate 10.

[0170] In this embodiment, the gate electrode layer is made of tungsten (W). In other embodiments, the gate electrode may also be made of conductive materials such as aluminum (Al), copper (Cu), mercury (Ag), gold (Au), platinum (Pt), nickel (Ni), or titanium (Ti).

[0171] The steps of forming the first metal gate and the second metal gate include: forming an initial gate electrode layer that fills the gate trench 31, the first through trench 32 and the second through trench 33, the initial gate electrode layer also covering the top surface of the dielectric layer 80; planarizing the initial gate electrode layer; removing the initial gate electrode layer located on the dielectric layer 80; and forming the first metal gate 101 and the second metal gate 102.

[0172] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having adjacent first device regions and second device regions, and the substrate includes a substrate, one or more stacked channel stacks on the substrates of the first device regions and the second device regions, a gate structure across the channel stacks, and a dielectric layer between the gate structures, the channel stacks including a sacrificial layer and a channel layer on the sacrificial layer; Remove the gate structure and form a gate trench in the dielectric layer that exposes the channel stack; Remove the sacrificial layer exposed by the gate trench to form a first through trench and a suspended first channel layer located in the first device region, and a second through trench and a suspended second channel layer located in the second device region; A gate dielectric layer is formed at the bottom and sidewalls of the gate trench, and the gate dielectric layer also surrounds the first channel layer and the second channel layer; Form a conformally conformal work function layer covering the gate dielectric layer; A conformal protective layer is formed over the work function layer; A shielding layer is formed on the dielectric layer, and the shielding layer further fills the gate trench, the first through trench and the second through trench; Remove the shielding layer from the first device area; Using the remaining masking layer as a mask, the protective layer and work function layer of the first device region are etched and removed sequentially to expose the gate dielectric layer of the first device region.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The gate dielectric layer is a high-k gate dielectric layer, and the protective layer is made of aluminum oxide.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The thickness of the protective layer is 3nm to 5nm.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The process for forming the protective layer is atomic layer deposition.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The step of removing the masking layer of the first device region includes: forming a patterned hard mask layer on the masking layer; and using the patterned hard mask layer as a mask, etching away the masking layer of the first device region.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The material of the hard mask layer is aluminum oxide.

7. The method for forming a semiconductor structure according to claim 5, characterized in that, The thickness of the hard mask layer is 30nm to 50nm.

8. The method for forming a semiconductor structure according to claim 5, characterized in that, The process of etching away the masking layer in the first device region is a dry etching process.

9. The method for forming a semiconductor structure according to claim 5, characterized in that, After exposing the gate dielectric layer of the first device region, the method further includes: Remove the remaining shielding layer; After removing the shielding layer, remove the protective layer of the second device area.

10. The method for forming a semiconductor structure according to claim 5, characterized in that, The process for removing the remaining shielding layer is an ashing process.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, The first device region is used to form a first type of transistor, and the second device region is used to form a second type of transistor. The first type of transistor and the second type of transistor have different doping types.

12. The method for forming a semiconductor structure according to claim 11, characterized in that, The first type of transistor is an NMOS transistor, and the second type of transistor is a PMOS transistor.

13. The method for forming a semiconductor structure according to claim 2, characterized in that, Before removing the gate structure, the method further includes: Etch the channel stack on both sides of the gate structure of the first device region to form a first groove in the channel stack on both sides of the gate structure of the first device region. The channel stack on both sides of the gate structure of the second device region is etched to form a second groove exposed in the channel stack on both sides of the gate structure of the second device region. A first source / drain doped layer is formed within the first groove; A second source / drain doped layer is formed within the second groove.

14. The method for forming a semiconductor structure according to claim 13, characterized in that, The steps of forming the first groove and the second groove include: A first sidewall layer is formed on the channel stack on both sides of the gate structure of the first device region, and a second sidewall layer is formed on the channel stack on both sides of the gate structure of the second device region; using the gate structure, the first sidewall layer and the second sidewall layer as a mask, the channel layers on both sides of the gate structure are etched to form the first groove and the second groove.

15. The method for forming a semiconductor structure according to claim 14, characterized in that, The process for forming the first groove and the second groove includes anisotropic dry etching process.

16. The method for forming a semiconductor structure according to claim 14, characterized in that, The materials of the first sidewall layer and the second sidewall layer include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

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