Semiconductor structure and method of making the same, memory

Abstract

The embodiments of the present disclosure disclose a semiconductor structure, a manufacturing method thereof and a memory, wherein the semiconductor structure comprises a substrate, a plurality of active pillars above the substrate, a storage structure, and a plurality of transistors; the plurality of active pillars are arranged in an array along a first direction and a second direction; each of the active pillars comprises a first sub-active pillar and a second sub-active pillar above the first sub-active pillar; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; the material of the first sub-active pillar comprises a first element, and the resistivity of the first sub-active pillar containing the first element in the material is less than that of the first sub-active pillar not containing the first element in the material; the storage structure covers the sidewall of the first sub-active pillar; and the channel structure of each of the transistors is located in the second sub-active pillar, and the extension direction of the channel structure is the same as that of the second sub-active pillar.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method, and a memory. Background Technology

[0002] The memory array architecture of Dynamic Random Access Memory (DRAM) consists of an array of memory cells (i.e., 1T1C memory cells) each containing one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.

[0003] As the size of dynamic random access memory (DRAM) continues to shrink, the size of its memory cells also shrinks. Ensuring the performance of these memory cells has become a pressing issue. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for fabricating the same, and a memory.

[0005] According to a first aspect of this disclosure, a semiconductor structure is provided, comprising: a substrate, a plurality of active pillars located above the substrate, a memory structure, and a plurality of transistors;

[0006] The plurality of active pillars are arranged in an array along a first direction and a second direction; each active pillar includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; the material of the first sub-active pillar contains a first element, and the resistivity of the first sub-active pillar containing the first element in the material is less than the resistivity of the first sub-active pillar that does not contain the first element in the material;

[0007] The storage structure covers the sidewall of the first sub-active column;

[0008] The channel structure of each transistor is located within the second sub-active pillar, and the extension direction of the channel structure is the same as the extension direction of the second sub-active pillar.

[0009] In the above scheme, the first element includes an N-type dopant or a P-type dopant, and the material of the first sub-active pillar includes a semiconductor material; or, the first element includes a metal element, and the material of the first sub-active pillar includes a compound of the metal element.

[0010] In the above scheme, the substrate includes an isolation structure, and a plurality of the active pillars are located on the isolation structure.

[0011] In the above scheme, the storage structure includes:

[0012] A first electrode layer, the first electrode layer covering the sidewall of the first sub-active pillar;

[0013] A dielectric layer, at least covering the sidewalls of the first electrode layer;

[0014] The second electrode layer is located in the gap of the dielectric layer and covers the surface of the dielectric layer.

[0015] In the above scheme, the semiconductor structure further includes: a first protective layer surrounding the top sidewall of the second sub-active pillar;

[0016] The first protective layer includes a plurality of first protective pillars and a plurality of second protective pillars;

[0017] Each of the first protective posts is located between the tops of two adjacent second sub-active posts in the first direction and covers the two opposite sidewalls of the two adjacent second sub-active posts;

[0018] Each of the second protective posts extends along the first direction, covering the sidewall of the top of the second sub-active post that is not covered by the first protective post, and also covering the sidewall of the first protective post.

[0019] In the above scheme, the diameter of the middle part of the second sub-active column is smaller than the diameter of the top of the second sub-active column and / or the diameter of the bottom of the second sub-active column;

[0020] The transistor includes: a gate oxide layer disposed around the second sub-active pillar, a gate disposed around the gate oxide layer, and a source and a drain disposed at two opposite ends of the second active pillar, wherein the side of the gate away from the gate oxide layer is flush with the sidewall of the second guard pillar away from the gate oxide layer.

[0021] In the above scheme, the semiconductor structure further includes:

[0022] Multiple bit lines are located on the transistor and electrically connected to the top of the second sub-active pillar.

[0023] According to a second aspect of this disclosure, a memory is provided, comprising: one or more semiconductor structures as described in any of the above embodiments of this disclosure.

[0024] According to a third aspect of this disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:

[0025] A substrate is provided on which a plurality of active pillars are formed in an array along a first direction and a second direction; each active pillar includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;

[0026] Add a first element to the first sub-active column, and the resistivity of the first sub-active column containing the first element in the material is less than the resistivity of the first sub-active column not containing the first element in the material;

[0027] A storage structure is formed at least on the sidewall of the first active column;

[0028] Multiple transistors are formed, wherein the channel structure of the transistors is located within the second sub-active pillar, and the extension direction of the channel structure is the same as the extension direction of the second sub-active pillar.

[0029] In the above scheme,

[0030] The first element includes an N-type or P-type dopant element. Adding the first element to the first sub-active column includes: adding an N-type or P-type dopant element to the first sub-active column through diffusion or ion implantation processes.

[0031] or,

[0032] The first element includes a metal element. Adding the first element to the first sub-active pillar includes: forming a metal layer containing the metal element covering the sidewall of the first sub-active pillar; and using an annealing process to react the metal layer and the first sub-active pillar to form a metal compound.

[0033] In the above scheme, a plurality of active pillars are formed on the substrate in an array along a first direction and a second direction, including:

[0034] A plurality of semiconductor pillars are formed on the substrate in an array along a first direction and a second direction; each semiconductor pillar includes a first portion, a second portion located on the first portion, and a third portion located on the second portion;

[0035] A support layer is formed covering the top surface of the third part;

[0036] A second protective layer is formed that at least covers the sidewalls of the third part;

[0037] The semiconductor pillar is subjected to an oxidation treatment so that the first part is completely oxidized into an oxide pillar and the surface of the second part is oxidized into an oxide layer;

[0038] Remove the oxide layer from the surface of the second part to obtain the first sub-active pillar;

[0039] After the storage structure is formed, the support layer and the second protective layer are removed to obtain the second sub-active column.

[0040] In the above scheme, a plurality of semiconductor pillars are formed on the substrate in an array along a first direction and a second direction, including:

[0041] Provide semiconductor substrates;

[0042] Multiple first grooves spaced apart along a first direction and multiple second grooves spaced apart along a second direction are formed in the substrate;

[0043] The bottom of each of the first trenches and / or the second trenches is enlarged to form the plurality of semiconductor pillars.

[0044] In the above scheme, forming the support layer includes:

[0045] The first insulating material is filled between the plurality of semiconductor pillars to obtain a first insulating layer;

[0046] A second insulating material is deposited, which covers the top surface of the first insulating layer and the semiconductor pillar to obtain the second insulating layer;

[0047] A portion of the second insulating layer is removed along the second direction to form a first shallow trench, the bottom surface of the first shallow trench being flush with the top surface of the semiconductor pillar, and the first insulating material being filled into the first shallow trench.

[0048] A portion of the second insulating layer is removed along the first direction to form a second shallow trench, the bottom surface of the second shallow trench being flush with the top surface of the semiconductor pillar and exposing the top surface of the semiconductor pillar; the second insulating material is then filled into the second shallow trench.

[0049] The second insulating layer that has not been removed and the second shallow trench filled with the second insulating material constitute the support layer.

[0050] In the above scheme, forming the second protective layer includes:

[0051] A portion of the first insulating material is removed to form a third shallow trench; the bottom surface of the third shallow trench is flush with the bottom surface of the third portion, exposing the sidewalls of the third portion;

[0052] A sacrificial material is deposited, which at least covers the sidewall of the third part, to obtain the second protective layer.

[0053] In the above scheme, forming a storage structure at least on the sidewall of the first sub-active column includes:

[0054] A first conductive layer is formed covering the sidewall of the first sub-active pillar;

[0055] A dielectric layer is formed that at least covers the sidewalls of the first conductive layer;

[0056] A second conductive layer is formed in the gaps of the dielectric layer.

[0057] In the above scheme, after forming the storage structure, the method further includes: forming a first protective layer around the top sidewall of the second sub-active column;

[0058] The formation of the first protective layer includes:

[0059] A first insulating material is formed between the second sub-active pillars;

[0060] A portion of the first insulating material at the top of the second sub-active post is removed to form a plurality of first grooves, each of the first grooves exposing two opposing sidewalls at the top of two adjacent second sub-active posts in a first direction;

[0061] The first groove is filled to form a plurality of first protective pillars;

[0062] Remove the remaining first insulating material from the top of the second sub-active post to form a plurality of second grooves extending along the first direction;

[0063] Multiple second protective pillars are formed on the sidewall of the second groove, and the first protective pillar and the second protective pillar together constitute the first protective layer.

[0064] In the above scheme, forming a transistor includes:

[0065] After the first protective layer is formed, the first insulating material corresponding to the middle part of the second sub-active post is removed to expose the sidewall of the middle part of the second sub-active post.

[0066] A gate oxide layer is formed covering the sidewall of the middle part of the second sub-active pillar;

[0067] A gate is formed covering the gate oxide layer;

[0068] The source and drain are formed at the bottom and top of the second active pillar, respectively;

[0069] An isolation structure is formed between the second protective pillars and between the gate.

[0070] In the above scheme, the gate forming the gate oxide layer includes:

[0071] The gaps in the gate oxide layer are filled with gate conductive material;

[0072] Using the first protective layer as a mask layer, a portion of the gate conductive material is removed, and the remaining gate conductive material forms the gate.

[0073] In the above scheme,

[0074] Before forming the gate oxide layer, the sidewall of the middle part of the second sub-active pillar is removed to form a second sub-active pillar with a recess and a recessed space corresponding to the recess; in the recessed space, at least a gate oxide layer surrounding the recess is formed.

[0075] This disclosure discloses a method for fabricating a semiconductor structure: forming multiple active pillars on a substrate, each active pillar including a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar; adding a first element to the first sub-active pillar, wherein the resistivity of the first sub-active pillar containing the first element is less than the resistivity of the first sub-active pillar not containing the first element; forming a memory structure on the sidewall of the first sub-active pillar; and forming a channel structure of the transistor located within the second sub-active pillar. This disclosure utilizes the addition of a first element to the first sub-active pillar to reduce its resistivity, thereby reducing the resistance between the first sub-active pillar and the memory structure, thus reducing signal transmission delay and ultimately improving the performance of the semiconductor structure. Furthermore, forming the memory structure and the transistor on the same active pillar reduces the difficulty of aligning the memory cell and the transistor, thereby reducing process complexity. Attached Figure Description

[0076] Figure 1 This is a schematic diagram of the circuit connection of a DRAM transistor provided in an embodiment of this disclosure;

[0077] Figure 2 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0078] Figures 3 to 31 This is a three-dimensional structural diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of the present disclosure.

[0079] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0080] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0081] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0082] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0083] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0084] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0085] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0086] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0087] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only.

[0088] However, it should be noted that the following description of dynamic random access memory is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.

[0089] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements for ions and leakage current in dynamic random access memory, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.

[0090] In some embodiments of this disclosure, whether planar transistors or buried transistors, the dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0091] Figure 1 This is a schematic diagram of a control circuit using a 1T1C architecture provided in an embodiment of this disclosure; as shown... Figure 1 As shown, the drain of transistor T is electrically connected to the bit line (BL), the source region of transistor T is electrically connected to one of the electrode plates of capacitor C, and the other electrode plate of capacitor C can be connected to a reference voltage, which can be ground voltage or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0092] However, in order to achieve the miniaturization of memory, the size of dynamic random access memory is constantly shrinking, and the resistance between capacitors and transistors in memory cells is getting larger and larger, affecting the signal transmission of memory cells; at the same time, the size of capacitors is also shrinking, which makes the process of aligning capacitors and transistors increasingly difficult.

[0093] In view of this, and to solve one or more of the above problems, this disclosure provides a method for fabricating a semiconductor structure. Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 2 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:

[0094] S201. A substrate is provided, on which a plurality of active pillars are formed in an array along a first direction and a second direction; each active pillar includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;

[0095] S202. Add a first element to the first sub-active column, and the resistivity of the first sub-active column containing the first element in the material is less than the resistivity of the first sub-active column not containing the first element in the material.

[0096] S203, A storage structure is formed at least on the sidewall of the first sub-active column;

[0097] S204. A plurality of transistors are formed, wherein the channel structure of the transistors is located within the second sub-active pillar, and the extension direction of the channel structure is the same as the extension direction of the second sub-active pillar.

[0098] It should be understood that Figure 2 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 2 The steps shown can be adjusted in order according to actual needs.

[0099] Herein and in the following text, the first direction and the second direction refer to two orthogonal directions parallel to the top surface of the substrate; the third direction is the direction perpendicular to the top surface of the substrate, that is, the third direction is the extension direction of the active pillar; wherein, the top surface of the substrate can be understood as a plane perpendicular to the extension direction of the active pillar.

[0100] In some embodiments, the angle between the first direction and the second direction ranges from 0 to 90 degrees. In some specific embodiments, the first direction may be perpendicular to the second direction. It is understood that the angle between the first direction and the second direction establishes the positional relationship of the array arrangement of the semiconductor pillars along the first direction and the second direction.

[0101] For example, the first direction is represented by the X direction in the figure; the second direction is represented by the Y direction in the figure; and the third direction is represented by the Z direction in the figure.

[0102] Figures 3 to 31 This is a three-dimensional structural schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure. The following is in conjunction with… Figure 2 , Figures 3 to 31 The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0103] Execute step S201, refer to Figures 3 to 14 This forms multiple active pillars.

[0104] In some embodiments, forming a plurality of active pillars arranged in an array along a first direction and a second direction on the substrate includes the following steps:

[0105] a. A plurality of semiconductor pillars are formed on the substrate in an array along a first direction and a second direction; each semiconductor pillar includes a first portion, a second portion located on the first portion, and a third portion located on the second portion;

[0106] b. Form a support layer covering the top surface of the third part;

[0107] c. Form a second protective layer that at least covers the sidewalls of the third part;

[0108] d. The semiconductor pillar is subjected to an oxidation treatment so that the first part is completely oxidized into an oxide pillar and the surface of the second part is oxidized into an oxide layer;

[0109] e. Remove the oxide layer from the surface of the second part to obtain the first sub-active pillar;

[0110] f. After forming the storage structure, remove the support layer and the second protective layer to obtain the second sub-active column.

[0111] Perform step a, refer to Figures 3 to 6 This forms multiple semiconductor pillars.

[0112] In some embodiments, a plurality of semiconductor pillars arranged in an array along a first direction and a second direction are formed on the substrate, including:

[0113] Provide semiconductor substrates;

[0114] Multiple first grooves spaced apart along a first direction and multiple second grooves spaced apart along a second direction are formed in the substrate;

[0115] The bottom of each of the first trenches and / or the second trenches is enlarged to form the plurality of semiconductor pillars.

[0116] refer to Figure 3 The material of the semiconductor substrate 100 may include silicon (Si), germanium (Ge), silicon germanide (SiGe), etc.

[0117] refer to Figure 3 The top surface of the semiconductor substrate 100 is first etched using a photolithography-etching (LE) process to form a plurality of first trenches T1 spaced apart along a first direction in the semiconductor substrate; here, each of the first trenches T1 extends along a second direction. The first trenches T1 divide the semiconductor substrate 100 into a plurality of semiconductor strips 102.

[0118] Here, the first trench T1 is located in the semiconductor substrate, that is, the depth of the first trench T1 along the third direction is less than the thickness of the semiconductor substrate 100 along the third direction.

[0119] The first etching includes, but is not limited to, dry plasma etching processes.

[0120] In some embodiments, the first trench T1 includes, but is not limited to, a shallow trench isolation (STI) structure.

[0121] refer to Figure 4 A first insulating material 201 is formed in the first trench T1; wherein the top surface of the first insulating material 201 is substantially flush with the top surface of the semiconductor substrate 100; here, the first insulating material 201 serves as a support.

[0122] In some embodiments, the constituent materials of the first insulating material 201 include, but are not limited to, silicon oxide (SiO2).

[0123] The methods for forming the first insulating material 201 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and other processes.

[0124] In some embodiments, the first trench T1 includes, but is not limited to, a shallow trench isolation (STI) structure.

[0125] refer to Figure 5 The top surface of the semiconductor substrate 100 is etched a second time using a photolithography-etching process to form a plurality of second trenches T2 spaced apart along a second direction in the semiconductor substrate 100; here, each second trench T2 extends along a first direction. The second trenches T2 divide each semiconductor strip 102 into a plurality of semiconductor pillars 103.

[0126] Here, the second trench T2 is located in the semiconductor substrate, that is, the depth of the second trench T2 along the third direction is less than the thickness of the semiconductor substrate 100 along the third direction.

[0127] The second etching process includes, but is not limited to, dry plasma etching.

[0128] In some embodiments, the second trench T2 includes, but is not limited to, a shallow trench isolation structure.

[0129] Continue to refer to Figure 5 The bottom of each second trench T3 is enlarged; here, the enlargement process can be understood as etching the bottom of the second trench T2 along the second direction, so that the diameter of the bottom of the second trench T2 along the second direction is greater than the diameter of the top of the corresponding trench along the second direction.

[0130] The etching process used here may include wet etching process, dry etching process, etc.

[0131] For example, in the wet etching process, an etchant is introduced into the bottom of the second trench T2, and the diameter of the bottom of the second trench T2 along the Y-axis is increased by the anisotropic etching of the etchant.

[0132] For example, in the dry etching process, lateral etching is performed by controlling plasma to form a trench structure with an increased diameter at the bottom of the second trench T2.

[0133] In practical applications, the bottom of each first groove T1 can also be enlarged during the formation of the first groove T1; here, the enlargement of the bottom of each second groove T2 is taken as an example.

[0134] In some embodiments, the enlargement process for the bottom of each of the first trenches and / or the second trenches employs, but is not limited to, the BOSCH etching process.

[0135] For example, continue to refer to Figure 5 First, use a normal etching process to form a trench with a consistent width along the third direction. For example, use a shallow trench isolation process to form a second trench (the trench shape at this time can be referenced). Figure 3 (Understanding the morphology of the first trench), then using the BOSCH etching process, the bottom of the second trench is enlarged to form a shape like... Figure 5 The bottom of the third groove is enlarged, as shown.

[0136] In practical applications, the depth of the second groove T2 along the third direction can be the same as or different from the depth of the first groove T1 along the third direction. For example, the depth of the second groove T2 along the third direction is substantially the same as the depth of the first groove T1 along the third direction. This reduces the need for adjustments to process parameters during manufacturing and lowers the complexity of the process.

[0137] In this embodiment of the disclosure, after the process of enlarging the bottom of each of the first trench T1 and / or the second trench T2, the etching process etches the bottom regions of a plurality of cubic pillars located on the substrate 101, reducing the size of the bottom regions of the cubic pillars, thereby forming the active pillars 103. (Refer to...) Figure 5 .

[0138] It should be noted that each of the semiconductor pillars 103 is still a single unit, comprising a first portion 1031, a second portion 1032 located on the first portion, and a third portion 1033 located on the second portion. The first portion 1031, the second portion 1032, and the third portion 1033 in each semiconductor pillar 103 are only used to divide the semiconductor pillar 103 into regions along the extension direction of the semiconductor pillar 103, and do not mean that the first portion 1031, the second portion 1032, and the third portion 1033 can be separate or have different structures with obvious stacking interfaces.

[0139] In some embodiments, the maximum diameter of the first portion 1031 along the first direction is less than the minimum diameter of the second portion 1032 along the first direction; and / or, the maximum diameter of the first portion 1031 along the second direction is less than the minimum diameter of the second portion 1032 along the second direction.

[0140] For example, when the second trench T2 is enlarged, the maximum diameter of the first portion 1031 of the semiconductor pillar along the Y-axis is smaller than the minimum diameter of the second portion 1032 of the semiconductor pillar along the Y-axis.

[0141] In this embodiment of the disclosure, by forming the semiconductor pillars with a smaller bottom diameter, it is beneficial to oxidize the plurality of semiconductor pillars to form active pillars in subsequent process steps, so that a corresponding oxide pillar is set between each active pillar and the substrate, so that the memory structure (e.g., capacitor) formed on part of the sidewall of the active pillar can be isolated, thereby reducing the existence of leakage problems in the memory structure (e.g., capacitor) during use.

[0142] refer to Figure 6 A first insulating material 201 is formed in the second trench; wherein the top surface of the first insulating material 201 is substantially flush with the top surface of the semiconductor substrate 100.

[0143] In some embodiments, the constituent materials of the first insulating material 201 include, but are not limited to, silicon oxide (SiO2).

[0144] The methods for forming the first insulating material 201 include, but are not limited to, processes such as PVD and CVD.

[0145] Furthermore, after the second trench T2 is filled with the first insulating material 201, the top surfaces of the first insulating material 201 and the semiconductor pillar 103 are subjected to chemical mechanical polishing (CMP) to make the top surfaces of the first insulating material 201 and the semiconductor pillar 103 flush.

[0146] Perform step b, refer to Figures 7 to 11 This forms a supporting layer.

[0147] In some embodiments, forming the support layer includes:

[0148] The first insulating material is filled between the plurality of semiconductor pillars to obtain a first insulating layer;

[0149] A second insulating material is deposited, which covers the top surface of the first insulating layer and the semiconductor pillar to obtain the second insulating layer;

[0150] A portion of the second insulating layer is removed along the second direction to form a first shallow trench, the bottom surface of the first shallow trench being flush with the top surface of the semiconductor pillar, and the first insulating material being filled into the first shallow trench.

[0151] A portion of the second insulating layer is removed along the first direction to form a second shallow trench, the bottom surface of the second shallow trench being flush with the top surface of the semiconductor pillar and exposing the top surface of the semiconductor pillar; the second insulating material is then filled into the second shallow trench.

[0152] The second insulating layer that has not been removed and the second shallow trench filled with the second insulating material constitute the support layer.

[0153] refer to Figure 7 The spaces between the plurality of semiconductor pillars 103 are filled with the first insulating material 201 (reference). Figure 6 ), thus obtaining the first insulating layer 211.

[0154] Continue to refer to Figure 7 A second insulating material is deposited, which covers the top surface of the first insulating layer 211 and the semiconductor pillar 103 to obtain the second insulating layer 212.

[0155] Here, the methods for forming the second insulating layer 212 include, but are not limited to, processes such as PVD and CVD.

[0156] Here, the material of the second insulating layer 212 may be different from the material of the first insulating layer 211. For example, the constituent materials of the second insulating layer 212 include, but are not limited to, silicon nitride or carbon; the constituent materials of the first insulating layer 211 include, but are not limited to, silicon oxide.

[0157] refer to Figure 8 A first shallow trench ST1 is formed by removing part of the second insulating layer 212 along the second direction through a photolithography-etching process. The bottom surface of the first shallow trench ST1 is flush with the top surface of the semiconductor pillar 103.

[0158] Here, the first shallow trench ST1 does not expose the top surface of the semiconductor pillar 103.

[0159] refer to Figure 9 The first insulating material 201 is filled into the first shallow trench ST1 by processes including but not limited to PVD and CVD.

[0160] Here, the first insulating material 201 is made of the same material as the first insulating layer 211. For example, the constituent materials of the first insulating material 201 include, but are not limited to, silicon oxide.

[0161] refer to Figure 10 A portion of the second insulating layer 212 and a portion of the first insulating material 201 are removed along the first direction by photolithography-etching process to form a second shallow trench ST2. The bottom surface of the second shallow trench ST2 is flush with the top surface of the semiconductor pillar 103.

[0162] Here, the second shallow trench ST2 exposes the top surface of the semiconductor pillar 103.

[0163] refer to Figure 11 The second insulating material 202 is filled into the second shallow trench ST2 using processes including but not limited to PVD and CVD. The remaining second insulating layer 212 and the second insulating material 202 filling the second shallow trench constitute the support layer 2121.

[0164] Here, the second insulating material 202 is made of the same material as the second insulating layer 212, but not of the same material as the first insulating material 201. The constituent materials of the second insulating material 202 include, but are not limited to, silicon nitride or carbon; the constituent materials of the first insulating material 201 include, but are not limited to, silicon oxide.

[0165] Thus, the support layer 2121 protects the top surface of the active pillar 103; simultaneously, the support layer 2121 covering the top surface of the active pillar 103 forms a mesh structure, which facilitates effective support for the semiconductor pillar 103. In other words, the support layer 2121 both protects the top surface of the active pillar 103 and supports the multiple semiconductor pillars 103 arranged in the array, thereby facilitating the formation of a stable semiconductor structure.

[0166] Perform step c, refer to Figures 12 to 14 This forms a second protective layer.

[0167] In some embodiments, forming the second protective layer includes:

[0168] A portion of the first insulating material is removed to form a third shallow trench; the bottom surface of the third shallow trench is flush with the bottom surface of the third portion, exposing the sidewalls of the third portion;

[0169] A sacrificial material is deposited, which at least covers the sidewall of the third part, to obtain the second protective layer.

[0170] refer to Figure 12 A portion of the first insulating material 201 is removed using an etching process to form a third shallow trench ST3; the bottom surface of the third shallow trench ST3 is flush with the bottom surface of the third part 1033, exposing the sidewall of the third part 1033.

[0171] The etching process used here may include dry etching, etc.

[0172] For example, in the dry etching process, using the support layer 2121 as a mask, the first insulating material 201 between the grids of the support layer 2121 is etched along the Z-axis direction (refer to...). Figure 11 ), and the first insulating material 201 between the third part 1033 (reference) Figure 11 This forms the third shallow trench ST3.

[0173] refer to Figure 13 Sacrificial material 203 is deposited in the third shallow trench ST3 through processes including but not limited to PVD and CVD. The sacrificial material 203 covers the sidewalls, bottom surface, and exposed bottom surface of the support layer 2121 of the third shallow trench ST3.

[0174] Here, the material of the sacrificial material 203 is different from the material of the first insulating material 201. For example, the sacrificial material 203 may be composed of, but is not limited to, silicon nitride or carbon; the first insulating layer 211 may be composed of, but is not limited to, silicon oxide.

[0175] refer to Figure 14 The sacrificial material 203 covering the bottom surface of the third shallow trench ST3 (see reference) is removed by an etching process. Figure 13 The sacrificial material is retained to at least cover the sidewalls of the third part 1033, thus obtaining the second protective layer 213.

[0176] The etching process used here may include wet etching process, dry etching process, etc.

[0177] For example, in the dry etching process, longitudinal etching is performed by controlling plasma to remove the sacrificial material 203 covering the bottom surface of the third shallow trench ST3, while at least the sacrificial material 203 covering the sidewalls of the third portion 1033 is retained.

[0178] Thus, the second protective layer covering the sidewalls of the third portion 1033 reduces unnecessary contamination of the third portion 1033 during subsequent manufacturing processes. It should be noted that the third portion 1033 is used to form the channel structure of the transistor in subsequent processes. It is understood that the channel structure has a crucial impact on the performance of the semiconductor structure. By covering the sidewalls of the third portion 1033 with the second protective layer and the top surface of the third portion 1033 with the support layer 2121, contamination of the third portion 1033 in subsequent processes is avoided, preventing unnecessary defects in the transistor's channel structure.

[0179] Perform steps d and e, refer to Figures 15 to 18 This forms the first active column.

[0180] refer to Figure 15 The remaining first insulating material 201 covering the active pillars 103 is removed using an etching process (see reference). Figure 14 This exposes the sidewalls of the portion 1031, the sidewalls of the second portion 1032, and the top surface of a portion of the substrate 101.

[0181] The etching process used here may include wet etching process, dry etching process, etc.

[0182] refer to Figure 16 For the semiconductor pillar 103 (reference) Figure 15 The first part 1031 (reference) is subjected to oxidation treatment to make the oxidation treatment so that the oxidation treatment is performed on the first part 1031 (reference) Figure 15 ) is completely oxidized into oxide column 104, and the second part 1032 (refer to Figure 15 The surface of the ) is oxidized into an oxide layer 106.

[0183] For example, the semiconductor pillar 103 is oxidized by an oxidation process, such that the first portion 1031 is completely oxidized into an oxide pillar 104, and the surface of the exposed second portion 1032 of the semiconductor pillar is oxidized into an oxide layer 106. At the same time, the top surface of the substrate 101 is also oxidized to form a substrate oxide layer 105.

[0184] Here, the oxide pillar 104 and the oxide layer 106 are made of the same material. Exemplarily, the constituent materials of the oxide pillar 104 and the oxide layer 106 include, but are not limited to, silicon oxide.

[0185] It should be noted that, after the aforementioned enlargement process of the second trench T2, the transition portion between the bottom of the semiconductor pillar 103 and the substrate 101, namely the first portion 1031, is smaller in size and more easily oxidized. Meanwhile, the second portion 1032 is relatively larger and only its surface is oxidized.

[0186] After the semiconductor pillar 103 is oxidized, the third part 1033 (reference) Figure 15 The unoxidized portion of the second part 1032, namely the active pillar 401 and the substrate 101, is electrically isolated by the oxide pillar 104 to prevent leakage defects between the active pillar 401 and the substrate 101.

[0187] Here and below, each active column 401 is still a whole, including a first sub-active column 402 and a second sub-active column 403 located on the first sub-active column 402; the first sub-active column 402 and the second sub-active column 403 in each active column 401 are only used to divide the active column 401 into regions along the extension direction of the active column 401, and do not mean that the first sub-active column 402 and the second sub-active column 403 can be separated or have different structures with obvious stacking interfaces.

[0188] It is understandable that when the semiconductor pillar 103 is oxidized to form the active pillar 401, the first sub-active pillar 402 and the second sub-active pillar 403 are formed simultaneously.

[0189] Here and below, each of the second sub-active pillars 403 remains a single unit. The second sub-active pillar 403 includes a second sub-active pillar bottom 4033, a second sub-active pillar middle portion 4032 located on the second sub-active pillar bottom 4033, and a second sub-active pillar top portion 4031 located on the second sub-active pillar middle portion 4032; the second sub-active pillar bottom 4033, the second sub-active pillar middle portion 4032, and the second sub-active pillar top portion 4031 in each second sub-active pillar 403 are only used to divide the second sub-active pillar 403 into regions along the extension direction of the second sub-active pillar 403, and do not mean that the second sub-active pillar bottom 4033, the second sub-active pillar middle portion 4032, and the second sub-active pillar top portion 4031 can be separate or have different structures with obvious stacking interfaces.

[0190] refer to Figure 17 The first insulating material 201 is filled in the gap between the oxide layer and the oxide pillar, and in the gap between the second protective layer 213 and the grid-like gap between the support layer 2121.

[0191] Here, the method of filling the first insulating material 201 includes, but is not limited to, processes such as PVD and CVD.

[0192] First insulating material 201 and oxide column 104 (reference) Figure 16 Oxide layer 106 (reference) Figure 16The materials used in these components may be the same or different. For example, the first insulating material 201 may be composed of, but is not limited to, silicon oxide. For example, the first insulating material 201, oxide pillar 104, and oxide layer 106 may be composed of the same material; here, they are all represented by the first insulating material 201.

[0193] In practical applications, a first insulating material 201 can be filled between multiple oxide pillars 104, between multiple active pillars 401, and in the grid-like gaps of the support layer 2121, so that the first insulating material 201 is flush with the top surface of the support layer 2121.

[0194] refer to Figure 18 The first insulating material 201 in the grid gaps of the support layer 2121 and in the gaps of the second protective layer 213 is removed by an etching process, and the first insulating material 201 between the first sub-active pillars 402 is also removed, exposing the sidewalls of the first sub-active pillars 402; at the same time, the first insulating material that is not removed and remains on the substrate 101 becomes the isolation structure 107.

[0195] In some specific embodiments, the first sub-active post 402 can extend deep into the isolation structure 107 and penetrate the isolation structure 107 along its extending direction. The bottom of the first sub-active post 402 has a portion extending into the isolation structure 107, which provides stable support for the first sub-active post 402. The etching process used here can include wet etching, dry etching, etc.

[0196] Combination Figure 16 and Figure 18 The first insulating material 201 between the multiple oxide pillars 104, together with the oxide pillars 104 and the substrate oxide layer 105, constitutes the isolation structure 107 on the substrate 101.

[0197] For example, the constituent materials of the isolation structure 107 include, but are not limited to, silicon oxide. The isolation structure 107 can improve the functionality of devices mounted on it (e.g., the first sub-active pillar 402, hereinafter referred to as...). Figure 21 The leakage problem between the storage structure 315 and the substrate 101.

[0198] Perform step f, refer to Figures 20 to 21 This forms the second active column.

[0199] refer to Figures 20 to 21 After the storage structure 315 is formed, the support layer 2121 and the second protective layer 213 are removed to obtain the second sub-active column 403.

[0200] In practical applications, refer to Figure 20 The dielectric layer filling the gap between the second sub-active pillars 403 needs to be removed, leaving only the second sub-active pillars 403.

[0201] For example, the support layer 2121 is filled in the gap between the second sub-active pillars 403, and during the formation of the storage structure 315, the portion of the first electrode layer 3151, dielectric layer 3152, and second electrode layer 3153 filled between the support layers 2121 needs to be removed.

[0202] Here, an etching process is used to remove the support layer 2121; the portion of the first electrode layer 3151, dielectric layer 3152, and second electrode layer 3153 filling the space between the support layers 2121 is removed, leaving at least the storage structure 315 covering the sidewall of the first sub-active pillar 402; and the second protective layer 213 covering the sidewall of the second sub-active pillar 403 is removed.

[0203] The etching process used here may include wet etching process, dry etching process, etc.

[0204] For example, in the dry etching process, longitudinal etching is performed by controlling plasma to remove the dielectric layer filling the gap between the second sub-active pillars 403, thereby forming the second sub-active pillars 403 and exposing the sidewalls and top surface of the second sub-active pillars 403.

[0205] It is understandable that, in the formation of active column 401 (refer to the above) Figure 16 At that time, the first sub-active pillar 402 and the second sub-active pillar 403 have been formed simultaneously; here, it is only necessary to remove the dielectric layer filling the gap between the second sub-active pillar 403 (refer to the above). Figures 20 to 21 This exposes the sidewalls and top surface of the second sub-active pillar 403, facilitating subsequent process steps to form the channel structure CH, source S, and drain D of the transistor 400 within the second sub-active pillar 403, and to form the gate 405 and gate oxide layer 404 around the second sub-active pillar 403 (see below). Figure 31 ).

[0206] In this embodiment, multiple active pillars are formed on a substrate, each active pillar including a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar. In subsequent process steps, memory cells are formed on the sidewalls of the first sub-active pillar, and the channel structure, source, and drain of a transistor are formed within the second sub-active pillar, with a gate and gate oxide layer formed around the second sub-active pillar. In other words, forming the memory structure and transistor on the same active pillar reduces the difficulty of aligning the memory cells and transistors, thereby reducing process complexity.

[0207] Execute step S202 and continue referring to... Figure 18 Add the first element to the first sub-active column.

[0208] In some embodiments,

[0209] The first element includes an N-type or P-type dopant element. Adding the first element to the first sub-active column includes: adding an N-type or P-type dopant element to the first sub-active column through diffusion or ion implantation processes.

[0210] or,

[0211] The first element includes a metal element. Adding the first element to the first sub-active pillar includes: forming a metal layer containing the metal element covering the sidewall of the first sub-active pillar; and using a rapid thermal annealing process to react the metal layer and the first sub-active pillar to form a metal compound.

[0212] Continue to refer to Figure 18 In some embodiments, the first element may include an N-type or P-type dopant element, and the first dopant element is incorporated into the first sub-active pillar 402 from the sidewall of the first sub-active pillar 402 using a gas phase diffusion process.

[0213] Here, the N-type doping element may include at least one of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc.; the P-type doping element may include at least one of boron (B), gallium (Ga), indium (In), etc.

[0214] For example, the first element includes phosphorus. A gas-phase diffusion process is used, where a phosphorus-containing gas is introduced at a temperature of 800°C-1200°C. The gas contacts the sidewall of the first sub-active column 402, initially forming a thin layer of phosphorus-containing medium on the surface of the sidewall of the first sub-active column 402. At the temperature of 800°C-1200°C, the phosphorus in the thin layer diffuses into the interior of the first sub-active column 402, increasing the phosphorus content in the first sub-active column 402. The first sub-active column 402 with added phosphorus has a lower resistivity compared to the first sub-active column 402 without phosphorus.

[0215] In practical applications, transistors with different conductivity types can also be used (see below). Figure 31 In the transistor 400, the first element is determined to include an N-type or P-type dopant element. For example, if the transistor structure is an N-type transistor, the first element is an N-type dopant element, such as phosphorus, arsenic, or antimony; if the transistor structure is a P-type transistor, the first element is a P-type dopant element, such as boron, gallium, or indium.

[0216] Continue to refer to Figure 18 In other embodiments, the first element may include a metal element, and a metal layer containing the metal element is formed by a thin film deposition process covering the sidewall of the first sub-active pillar 402. An annealing process, such as rapid thermal annealing (RTP), is then used to react the metal layer with the first sub-active pillar 402 to form a metal compound.

[0217] Here, the constituent materials of the metallic elements include at least one of cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), silver (Ag), and gold (Au).

[0218] For example, the first element includes cobalt. A cobalt-containing metal layer is formed covering the sidewall of the first sub-active pillar 402 using a thin-film deposition process. A rapid thermal annealing process is then used to react the cobalt-containing metal layer with the first sub-active pillar 402 to form a cobalt compound. The addition of cobalt to the first sub-active pillar 402, forming a cobalt compound, results in a lower resistivity for the first sub-active pillar 402 with added cobalt compared to the first sub-active pillar 402 without cobalt.

[0219] In practical applications, the degree of reaction between the metal layer and the first sub-active pillar can be controlled by adjusting the parameters of the thin film deposition process and / or rapid thermal annealing process, thereby controlling the morphology of the formed metal compound. For example, the metal layer may react only with the surface of the first sub-active pillar, and the surface layer of the first sub-active pillar may form the metal compound; alternatively, the metal layer may react completely with the first sub-active pillar, and the entire first sub-active pillar may form the metal compound.

[0220] In this embodiment, the resistivity of the first sub-active pillar is reduced by adding a first element to the first sub-active pillar, thereby reducing the resistance between the first sub-active pillar and the memory structure, thus reducing the signal transmission delay and ultimately improving the performance of the semiconductor structure.

[0221] Execute step S203, refer to Figures 19 to 20 This forms a storage structure.

[0222] In some embodiments, forming a storage structure at least on the sidewall of the first sub-active column includes:

[0223] A first conductive layer is formed covering the sidewall of the first sub-active pillar;

[0224] A dielectric layer is formed that at least covers the sidewalls of the first conductive layer;

[0225] A second conductive layer is formed in the gaps of the dielectric layer.

[0226] refer to Figure 19 A first conductive layer 3151 is formed covering the sidewall of the first sub-active pillar 402;

[0227] Here, the first conductive layer is used as the lower electrode of the capacitor; the dielectric layer is used as the dielectric of the capacitor; and the second conductive layer is used as the upper electrode of the capacitor.

[0228] In some specific embodiments, the constituent materials of the first conductive layer 3151 may include, but are not limited to, ruthenium (Ru), ruthenium oxide (RuO), and titanium nitride (TiN).

[0229] In this embodiment of the disclosure, a first conductive layer can be formed on the sidewall of the first sub-active pillar by a selective deposition process, or by other deposition processes.

[0230] The selective deposition process refers to the selective deposition of the first conductive layer on the sidewall of the first active post. Other deposition processes include, but are not limited to, PVD, CVD, and ALD.

[0231] In some specific embodiments, forming the first conductive layer 3151 covering the sidewall of the first sub-active pillar 402 includes:

[0232] A first conductive layer 3151 is formed covering the sidewall of the first sub-active pillar 402 by a selective deposition process.

[0233] refer to Figure 20 A dielectric layer 3152 is formed that at least covers the sidewalls of the first conductive layer 3151; a second conductive layer 3153 is formed in the gaps of the dielectric layer 3152.

[0234] The dielectric layer is composed of high-k dielectric materials, which generally refer to materials with a dielectric constant higher than 3.9, and are usually significantly higher than this value. In some specific examples, the dielectric layer material may include, but is not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), strontium titanate (SrTiO3), etc.

[0235] In some specific embodiments, the constituent materials of the second conductive layer may include, but are not limited to, ruthenium, ruthenium oxide, and titanium nitride.

[0236] Here, the methods for forming the second conductive layer include, but are not limited to, processes such as PVD and CVD.

[0237] It should be noted that the method for forming the first conductive layer and the second electrode layer in the above embodiments can also be understood as forming a conductive layer-to-conductive layer (CoC) using a selective deposition process; here, the selective deposition process includes, but is not limited to, the ALD process.

[0238] In this embodiment of the present disclosure, during the formation of the first conductive layer using a selective deposition process, the material used to form the first conductive layer can be formed only on the sidewalls of the first sub-active pillar, or on other selected materials, and not on the top surface of the isolation structure. This ensures isolation between the first electrode layers, preventing mutual interference; furthermore, it avoids void problems that occur during the formation of the first conductive layer using other processes, thereby improving the reliability of the semiconductor structure.

[0239] Execute step S204, refer to Figures 22 to 31 This forms multiple transistors.

[0240] In some embodiments, after forming the storage structure, the method further includes: forming a first protective layer around the top sidewall of the second sub-active column;

[0241] The formation of the first protective layer includes:

[0242] A first insulating material is formed between the second sub-active pillars;

[0243] A portion of the first insulating material at the top of the second sub-active post is removed to form a plurality of first grooves, each of the first grooves exposing two opposing sidewalls at the top of two adjacent second sub-active posts in a first direction;

[0244] The first groove is filled to form a plurality of first protective pillars;

[0245] Remove the remaining first insulating material from the top of the second sub-active post to form a plurality of second grooves extending along the first direction;

[0246] Multiple second protective pillars are formed on the sidewall of the second groove, and the first protective pillar and the second protective pillar together constitute the first protective layer.

[0247] refer to Figure 22 A first insulating material 201 is formed between the second sub-active pillars 403; wherein the top surface of the first insulating material 201 is flush with the top surface of the second sub-active pillars 403.

[0248] Furthermore, the top surfaces of the first insulating material 201 and the second sub-active pillar 403 are polished to make the top surfaces of the first insulating material 201 and the semiconductor pillar 103 flush.

[0249] Here, the constituent materials of the first insulating material 201 include, but are not limited to, silicon oxide.

[0250] The methods for forming the first insulating material 201 include, but are not limited to, processes such as PVD, CVD, and ALD.

[0251] refer to Figure 23 A portion of the first insulating material on the top 4031 of the second sub-active pillar is removed using a photolithography-etching process, forming a plurality of first grooves R1 arranged in an array along the first and second directions. Each first groove R1 exposes two opposing sidewalls of two adjacent tops 4031 of the second sub-active pillars in the first direction, and the bottom surface of each first groove R1 is substantially flush with the bottom surface of the top 4031 of the second sub-active pillar. In other words, the depth of the first groove R1 along the third direction is substantially equivalent to the thickness of the top 4031 of the second sub-active pillar along the third direction.

[0252] The first etching includes, but is not limited to, dry plasma etching processes.

[0253] refer to Figure 24The first groove R1 is filled with a second insulating material to form a plurality of first protective pillars 2211; wherein the top surface of the first protective pillar 2211 is substantially flush with the top surface of the second sub-active pillar top 4031; here, the first protective pillar 2211 is used to protect the sidewall of the second sub-active pillar top 4031.

[0254] Here, the methods for forming the material of the first protective pillar 2211 include, but are not limited to, processes such as PVD and CVD.

[0255] Here, the composition of the first protective post 2211 may be different from that of the first insulating material 201. For example, the composition of the first protective post 2211 may include, but is not limited to, silicon nitride or carbon; the composition of the first insulating material 201 may include, but is not limited to, silicon oxide.

[0256] In some embodiments, the formation of the first protective post 2211 employs a process including but not limited to shallow trench isolation.

[0257] refer to Figure 25 The remaining first insulating material 201 on the top 4031 of the second sub-active pillar is removed by etching, forming a plurality of second grooves R2 extending along the first direction. Each second groove R2 exposes at least the other sidewalls of the top 4031 of the second sub-active pillar that are not covered by the first protective pillar 2211 (which can be understood as the two opposite sidewalls of two adjacent tops 4031 of the second sub-active pillar in the second direction), and the bottom surface of each second groove R2 is substantially flush with the bottom surface of the top 4031 of the second sub-active pillar. That is, the depth of the second groove R2 along the third direction is substantially equivalent to the thickness of the top 4031 of the second sub-active pillar along the third direction.

[0258] The first etching includes, but is not limited to, dry plasma etching processes.

[0259] refer to Figure 26 The second protective column 2212 is formed by the spacer process.

[0260] A second insulating material is deposited on the sidewalls and bottom surface of the second groove R2 using processes including but not limited to PVD and CVD, while a second insulating material is also deposited on the top surface of the first protective pillar 2211 and the top surface of the second sub-active pillar 4031.

[0261] The second insulating material on the bottom surface of the second groove R2 is removed by an etching process, and the second insulating material on the top surface of the first protective post 2211 and the top surface of the second sub-active post top 4031 is also removed, leaving the second insulating material on the sidewalls of the second groove, forming a plurality of second protective posts 2212. Each second protective post 2212 extends along a first direction to protect the sidewalls of the second sub-active post top 4031. Here, the first protective post 2211 and the second protective post 2212 together constitute the first protective layer 221, which surrounds the second sub-active post top 4031, protecting all the sidewalls of the second sub-active post top 4031.

[0262] Here, the composition of the second protective post 2212 may be different from that of the first insulating material 201. For example, the composition of the second protective post 2212 may include, but is not limited to, silicon nitride or carbon; the composition of the first insulating material 201 may include, but is not limited to, silicon oxide.

[0263] In some embodiments, the formation of the second protective pillar 2212 employs processes including dry etching.

[0264] For example, in the dry etching process, longitudinal etching is performed by controlling plasma to remove the second insulating material on the bottom surface of the second groove R2, and at the same time remove the second insulating material on the top surface of the first protective pillar 2211 and the top surface of the second sub-active pillar 4031, while retaining the second insulating material on the sidewall of the second groove to form the second protective pillar 2212.

[0265] In this embodiment, the second protective pillar 2212, formed by the sidewall process, protects the sidewall of the top 4031 of the second sub-active pillar and can also serve as a mask for forming the gate 405 (see below). Figure 30 The second protective pillar 2212, formed through the sidewall process, serves as a mask, allowing for further miniaturization of the mask size based on existing photolithography processes, enabling the formation of smaller semiconductor structures. Using the first protective layer as a mask reduces one photolithography step, thereby reducing process cost and complexity. Since the second protective pillar formed through the sidewall process is self-aligned based on the second sub-active pillar, it improves the gate formation in subsequent processes (see below). Figure 30 The alignment accuracy and process window.

[0266] In some embodiments, forming a transistor includes:

[0267] After the first protective layer is formed, the first insulating material corresponding to the middle part of the second sub-active post is removed to expose the sidewall of the middle part of the second sub-active post.

[0268] A gate oxide layer is formed covering the sidewall of the middle part of the second sub-active pillar;

[0269] A gate is formed covering the gate oxide layer;

[0270] The source and drain are formed at the bottom and top of the second active pillar, respectively;

[0271] An isolation structure is formed between the second protective pillars and between the gate.

[0272] refer to Figure 27 After the first protective layer 221 is formed, while the first protective layer 221 protects all the sidewalls of the top 4031 of the second sub-active column, the first insulating material 201 corresponding to the middle part 4032 of the second sub-active column is removed to expose the sidewalls of the middle part 4032 of the second sub-active column; and here the top surface of the first insulating material 201 that has not been removed is basically flush with the bottom surface of the middle part 4032 of the second sub-active column, that is, the depth of the first insulating material 201 that has not been removed along the third direction is basically equivalent to the thickness of the bottom 4033 of the second sub-active column along the third direction.

[0273] The etching process used here may include wet etching process, dry etching process, etc.

[0274] For example, a wet etching process is used to isotropically remove the first insulating material between the middle portions 4032 of the second sub-active pillars, exposing the sidewalls of the middle portions 4032 of the second sub-active pillars; and the remaining first insulating material 201 covers the sidewalls of the bottom portion 4033 of the second sub-active pillars.

[0275] refer to Figure 29 A gate oxide layer 404 is formed covering the sidewall of the middle portion 4032 of the second sub-active pillar.

[0276] The gate oxide layer 404 can be formed around the sidewall of the middle portion 4032 of the second sub-active pillar by in-situ oxidation of the sidewall of the middle portion 4032 of the second sub-active pillar.

[0277] A gate oxide layer 404 can also be deposited on the sidewall surrounding the middle portion 4032 of each second sub-active pillar using an ALD process.

[0278] Here, the material of the gate oxide layer 404 includes, but is not limited to, silicon oxide.

[0279] refer to Figure 30A gate 405 is formed covering the gate oxide layer.

[0280] In some embodiments, forming the gate 405 covering the gate oxide layer 404 includes:

[0281] Gate conductive material is filled into the gaps of the gate oxide layer 404;

[0282] Using the first protective layer 221 as a mask layer, a portion of the gate conductive material is removed, and the remaining gate conductive material forms the gate 405.

[0283] Gate conductive material is filled into the gaps of the gate oxide layer 404 using processes such as electro-chemical plating (ECP), PVD, and CVD. In practical applications, the gate conductive material can also fill the gaps between the first protective layers 221, and the top surface of the gate conductive material is flush with the top surface of the second sub-active pillar 4031.

[0284] Here, the constituent materials of the gate conductive material include at least one of cobalt, nickel, tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, aluminum copper, silver and gold.

[0285] Using the first protective layer 221 as a mask layer, a portion of the gate conductive material is removed using processes including wet etching and dry etching. The remaining gate conductive material forms a plurality of gates 405 arranged along the second direction. Each gate 405 extends along the first direction, physically connecting the gates of each transistor in each row of transistors arranged along the second direction; and adjacent gates 405 arranged along the second direction are isolated from each other.

[0286] In some embodiments, the side of the gate 405 away from the gate oxide layer 404 is flush with the sidewall of the second guard pillar 2212 away from the gate oxide layer.

[0287] For example, in the dry etching process, vertical etching is performed by controlling plasma to remove part of the gate conductive material and form the gate 405.

[0288] Since the first protective layer 221 is used as a mask layer, the side of the gate 405 away from the gate oxide layer 404 along the second direction is substantially flush with the sidewall of the second protective pillar 2212 away from the gate oxide layer 404 along the extension direction of the second sub-active pillar 403.

[0289] In this embodiment, since the second protective pillar formed by the sidewall process can have a further miniaturized size based on the existing photolithography process, the first protective layer also has a further miniaturized size. Using the first protective layer as a mask, a smaller gate size and / or a smaller spacing between gates can be formed. At the same time, using the first protective layer as a mask can reduce one photolithography process step, thereby reducing process cost and difficulty. Furthermore, since the self-aligned second protective pillar formed by the sidewall process can improve the alignment accuracy and process window of the formed gate.

[0290] refer to Figure 31 The gate isolation structure 406 is formed by filling at least two adjacent gates 405 with a first insulating material through processes such as PVD and CVD. In practical applications, the first insulating material can also be filled in the gaps between the first protective layers 221. The top surface of the first insulating material is flush with the top surface of the second sub-active pillar top 4031. The formed gate isolation structure 406 will space the gates 405 of two adjacent rows of transistors 400 arranged along the second direction.

[0291] It is understood that here, each of the second sub-active pillars 403 remains a single unit. The bottom 4033, middle 4032, and top 4031 of each second sub-active pillar 403 are only used to divide the second sub-active pillar 403 into regions along its extension direction. The middle 4032 of the second sub-active pillar is used to form the channel structure CH of the transistor 400; the top 4031 of the second sub-active pillar is used to form the drain D or source S of the transistor 400; and the bottom 4033 of the second sub-active pillar is used to form the source S or drain D of the transistor.

[0292] In some embodiments, refer to the above Figure 28 Before forming the gate oxide layer, the sidewall of the middle portion 4032 of the second sub-active pillar is removed to form a second sub-active pillar 403 with a recess and a recessed space R3 corresponding to the recess; refer to the above. Figure 29 In the recessed space R3, at least a gate oxide layer 404 is formed surrounding the recess.

[0293] Here, the etching process used to form the second sub-active pillar 403 with the concave portion may include wet etching process, dry etching process, etc.

[0294] For example, a wet etching process is used to isotropically remove the surface material of the middle part 4032 of the second sub-active pillar to form the recessed space R3.

[0295] Here, the diameter of the middle part 4032 of the second sub-active column is smaller than the diameter of the top part 4031 of the second sub-active column and / or the diameter of the bottom part 4033 of the second sub-active column.

[0296] In this embodiment of the present disclosure, by forming a structure with a recess in the middle of the second sub-active pillar, more space can be reserved for the formation of the gate surrounding the middle of the second sub-active pillar in subsequent process steps. More space means that the gate has more gate material and has lower resistance, resulting in better electrical performance of the gate.

[0297] Continue to refer to Figures 30 to 31 The transistor 400 is formed by: a gate oxide layer 404 disposed around the second active pillar, a gate 405 disposed around the gate oxide layer 404, and a source S and a drain D disposed at two opposite ends of the second active pillar 403, wherein the side of the gate 405 away from the gate oxide layer 404 is flush with the sidewall of the second guard pillar 2212 away from the gate oxide layer 405.

[0298] Here, the gate shape differs in different types of transistors; for example, refer to... Figure 31 In a columnar gate transistor, the gate is formed in a columnar shape on one side of the channel region; in a semi-around gate transistor, the gate partially surrounds the channel region; in a gate all around (GAA) transistor, the gate completely surrounds the channel region.

[0299] The transistor types in the embodiments of this disclosure may include, but are not limited to, the types described above. Preferably, refer to... Figure 31 The transistor is a fully surround gate transistor 400.

[0300] It should be noted that the gate structure here includes the gate (G) and the gate oxide layer; the gate oxide layer is located between the gate and the channel region, and is used to electrically isolate the channel region and the gate, thereby reducing the hot carrier effect of the transistor.

[0301] Here, the gate material may include metals and / or polysilicon, etc. The gate oxide layer material may include, but is not limited to, silicon oxide.

[0302] In some embodiments, the gate formation method includes, but is not limited to, PVD, CVD, ALD, etc. The gate oxide layer formation method includes, but is not limited to, in-situ oxidation.

[0303] The source and drain are formed at opposite ends of the second active post.

[0304] In some specific embodiments, the methods for forming the source and drain include, but are not limited to, ion implantation and diffusion processes.

[0305] It should be noted that the positions of the source and drain at opposite ends of the second active post can be interchanged; in practice, the selection and setting can be made according to actual needs.

[0306] It is understood that the memory in the above embodiment is a transistor-capacitor (TOC) structure, which further includes multiple bit lines located on the transistor and electrically contacting the top of the second part.

[0307] Therefore, in some embodiments, the method further includes forming a bit line BL on the transistor.

[0308] Here, the constituent materials of the bit line BL include at least one of cobalt, nickel, tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, aluminum copper, silver and gold.

[0309] It is understood that the bit line BL is used to perform read or write operations on the transistor when the transistor is turned on.

[0310] Here, placing the bit line BL above the transistor and treating the bit line BL as a metal bit line can reduce resistance and simplify the manufacturing process; it is also more compatible with the circuit design of the memory.

[0311] In the various embodiments proposed in this disclosure, a plurality of active pillars are formed on a substrate, each active pillar including a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar. A first element is added to the first sub-active pillar, and the resistivity of the first sub-active pillar containing the first element is less than the resistivity of the first sub-active pillar not containing the first element. A memory structure is then formed on the sidewall of the first sub-active pillar; and a channel structure of the transistor is formed within the second sub-active pillar. In the embodiments of this disclosure, adding a first element to the first sub-active pillar reduces the resistivity of the first sub-active pillar, thereby reducing the resistance between the first sub-active pillar and the memory structure, thereby reducing signal transmission delay and ultimately improving the performance of the semiconductor structure. Furthermore, forming the memory structure and the transistor on the same active pillar reduces the difficulty of aligning the memory cell and the transistor, thereby reducing the process complexity.

[0312] According to another aspect of this disclosure, the semiconductor structure provided in the embodiments of this disclosure includes: a substrate, a plurality of active pillars located above the substrate, a memory structure, and a plurality of transistors;

[0313] The plurality of active pillars are arranged in an array along a first direction and a second direction; each active pillar includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; the material of the first sub-active pillar contains a first element, and the resistivity of the first sub-active pillar containing the first element in the material is less than the resistivity of the first sub-active pillar that does not contain the first element in the material;

[0314] The storage structure covers the sidewall of the first sub-active column;

[0315] The channel structure of each transistor is located within the second sub-active pillar, and the extension direction of the channel structure is the same as the extension direction of the second sub-active pillar.

[0316] In some embodiments, the first element includes an N-type dopant or a P-type dopant, and the material of the first sub-active pillar includes a semiconductor material; or, the first element includes a metal element, and the material of the first sub-active pillar includes a compound of the metal element.

[0317] In some embodiments, the substrate includes an isolation structure on which a plurality of the active pillars are located.

[0318] In some embodiments, the storage structure includes:

[0319] A first electrode layer, the first electrode layer covering the sidewall of the first sub-active pillar;

[0320] A dielectric layer, at least covering the sidewalls of the first electrode layer;

[0321] The second electrode layer is located in the gap of the dielectric layer and covers the surface of the dielectric layer.

[0322] In some embodiments, the semiconductor structure further includes: a first protective layer surrounding the top sidewall of the second sub-active pillar;

[0323] The first protective layer includes a plurality of first protective pillars and a plurality of second protective pillars;

[0324] Each of the first protective posts is located between the tops of two adjacent second sub-active posts in the first direction and covers the two opposite sidewalls of the two adjacent second sub-active posts;

[0325] Each of the second protective posts extends along the first direction, covering the sidewall of the top of the second sub-active post that is not covered by the first protective post, and also covering the sidewall of the first protective post.

[0326] In some embodiments, the diameter of the middle part of the second sub-active column is smaller than the diameter of the top of the second sub-active column and / or the diameter of the bottom of the second sub-active column;

[0327] The transistor includes: a gate oxide layer disposed around the second sub-active pillar, a gate disposed around the gate oxide layer, and a source and a drain disposed at two opposite ends of the second active pillar, wherein the side of the gate away from the gate oxide layer is flush with the sidewall of the second guard pillar away from the gate oxide layer.

[0328] In some embodiments, the semiconductor structure further includes:

[0329] Multiple bit lines are located on the transistor and electrically connected to the top of the second sub-active pillar.

[0330] The semiconductor structure provided in this disclosure is similar to the semiconductor structure manufactured by the manufacturing method of the semiconductor structure in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0331] According to another aspect of this disclosure, a memory is provided, comprising: one or more semiconductor structures as described in any of the above embodiments of this disclosure.

[0332] Based on this, in this embodiment, the resistivity of the first sub-active pillar is reduced by adding a first element to the first sub-active pillar, thereby reducing the resistance between the first sub-active pillar and the memory structure, thus reducing signal transmission delay and ultimately improving the performance of the semiconductor structure. Furthermore, forming the memory structure and transistors on the same active pillar reduces the difficulty of aligning the memory cells and transistors, thereby reducing process complexity.

[0333] In some embodiments, the memory includes DRAM.

[0334] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0335] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, multiple active pillars located above the substrate, a memory structure, and multiple transistors; The plurality of active pillars are arranged in an array along a first direction and a second direction; each active pillar includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; the material of the first sub-active pillar contains a first element, and the resistivity of the first sub-active pillar containing the first element in the material is less than the resistivity of the first sub-active pillar that does not contain the first element in the material; The storage structure covers the sidewall of the first sub-active column; The channel structure of each transistor is located within the second sub-active pillar, and the extension direction of the channel structure is the same as the extension direction of the second sub-active pillar. The semiconductor structure further includes: a first protective layer surrounding the top sidewall of the second sub-active pillar; The first protective layer includes a plurality of first protective pillars and a plurality of second protective pillars; Each of the first protective posts is located between the tops of two adjacent second sub-active posts in the first direction and covers the two opposite sidewalls of the two adjacent second sub-active posts; Each of the second protective posts extends along the first direction, covering the sidewall of the top of the second sub-active post that is not covered by the first protective post, and also covering the sidewall of the first protective post.

2. The semiconductor structure according to claim 1, characterized in that, The first element includes an N-type dopant or a P-type dopant, and the material of the first sub-active pillar includes a semiconductor material; or, the first element includes a metal element, and the material of the first sub-active pillar includes a compound of the metal element.

3. The semiconductor structure according to claim 1, characterized in that, The substrate includes an isolation structure, and a plurality of the active pillars are located on the isolation structure.

4. The semiconductor structure according to claim 1, characterized in that, The storage structure includes: A first electrode layer, the first electrode layer covering the sidewall of the first sub-active pillar; A dielectric layer, at least covering the sidewalls of the first electrode layer; The second electrode layer is located in the gap of the dielectric layer and covers the surface of the dielectric layer.

5. The semiconductor structure according to claim 1, characterized in that, The diameter of the middle part of the second sub-active column is smaller than the diameter of the top of the second sub-active column and / or the diameter of the bottom of the second sub-active column; The transistor includes: a gate oxide layer disposed around the second sub-active pillar, a gate disposed around the gate oxide layer, and a source and a drain disposed at two opposite ends of the second sub-active pillar, wherein the side of the gate away from the gate oxide layer is flush with the sidewall of the second guard pillar away from the gate oxide layer.

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: Multiple bit lines are located on the transistor and electrically connected to the top of the second sub-active pillar.

7. A memory, characterized in that, include: One or more semiconductor structures as described in any one of claims 1 to 6.

8. A method for fabricating a semiconductor structure, characterized in that, The method includes: A substrate is provided on which a plurality of active pillars are formed in an array along a first direction and a second direction; each active pillar includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; Add a first element to the first sub-active column, and the resistivity of the first sub-active column containing the first element in the material is less than the resistivity of the first sub-active column not containing the first element in the material; A storage structure is formed at least on the sidewall of the first active column; Multiple transistors are formed, wherein the channel structure of the transistors is located within the second sub-active pillar, and the extension direction of the channel structure is the same as the extension direction of the second sub-active pillar; The plurality of active pillars are formed on the substrate in an array along a first direction and a second direction, including: A plurality of semiconductor pillars are formed on the substrate in an array along a first direction and a second direction; each semiconductor pillar includes a first portion, a second portion located on the first portion, and a third portion located on the second portion; A support layer is formed covering the top surface of the third part; A second protective layer is formed that at least covers the sidewalls of the third part; The semiconductor pillar is subjected to an oxidation treatment so that the first part is completely oxidized into an oxide pillar and the surface of the second part is oxidized into an oxide layer; Remove the oxide layer from the surface of the second part to obtain the first sub-active pillar; After the storage structure is formed, the support layer and the second protective layer are removed to obtain the second sub-active column.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The first element includes an N-type or P-type dopant element. Adding the first element to the first sub-active pillar includes: adding an N-type or P-type dopant element to the first sub-active pillar through diffusion or ion implantation processes. or, The first element includes a metal element. Adding the first element to the first sub-active pillar includes: forming a metal layer containing the metal element covering the sidewall of the first sub-active pillar; and using an annealing process to react the metal layer and the first sub-active pillar to form a metal compound.

10. The method for fabricating a semiconductor structure according to claim 8, characterized in that, A plurality of semiconductor pillars are formed on the substrate in an array along a first direction and a second direction, including: Provide semiconductor substrates; Multiple first grooves spaced apart along a first direction and multiple second grooves spaced apart along a second direction are formed in the substrate; The bottom of each of the first trenches and / or the second trenches is enlarged to form the plurality of semiconductor pillars.

11. The method for fabricating a semiconductor structure according to claim 8, characterized in that, A support layer is formed to cover the top surface of the third part, comprising: A first insulating layer is obtained by filling the spaces between the plurality of semiconductor pillars with a first insulating material. A second insulating material is deposited, which covers the top surface of the first insulating layer and the semiconductor pillar to obtain a second insulating layer; A portion of the second insulating layer is removed along the second direction to form a first shallow trench, the bottom surface of the first shallow trench being flush with the top surface of the semiconductor pillar, and the first insulating material being filled into the first shallow trench. A portion of the second insulating layer is removed along the first direction to form a second shallow trench, the bottom surface of the second shallow trench being flush with the top surface of the semiconductor pillar and exposing the top surface of the semiconductor pillar; the second insulating material is then filled into the second shallow trench. The second insulating layer that was not removed and the second insulating material filling the second shallow trench constitute the support layer.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, Forming a second protective layer that at least covers the sidewall of the third portion, comprising: A portion of the first insulating material is removed to form a third shallow trench; the bottom surface of the third shallow trench is flush with the bottom surface of the third portion, exposing the sidewalls of the third portion; A sacrificial material is deposited, which at least covers the sidewall of the third part, to obtain the second protective layer.

13. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The formation of a storage structure at least on the sidewall of the first sub-active column includes: A first conductive layer is formed covering the sidewall of the first sub-active pillar; A dielectric layer is formed that at least covers the sidewalls of the first conductive layer; A second conductive layer is formed in the gaps of the dielectric layer.

14. The method for fabricating a semiconductor structure according to claim 8, characterized in that, After forming the storage structure, the method further includes: forming a first protective layer around the top sidewall of the second sub-active pillar; The formation of a first protective layer around the top sidewall of the second active column includes: A first insulating material is formed between the second sub-active pillars; A portion of the first insulating material at the top of the second sub-active post is removed to form a plurality of first grooves, each of the first grooves exposing two opposing sidewalls at the top of two adjacent second sub-active posts in a first direction; The first groove is filled to form a plurality of first protective pillars; Remove the remaining first insulating material from the top of the second sub-active post to form a plurality of second grooves extending along the first direction; Multiple second protective pillars are formed on the sidewall of the second groove, and the first protective pillar and the second protective pillar together constitute the first protective layer.

15. The method for fabricating a semiconductor structure according to claim 14, characterized in that, Multiple transistors are formed, including: After the first protective layer is formed, the first insulating material corresponding to the middle part of the second sub-active post is removed to expose the sidewall of the middle part of the second sub-active post. A gate oxide layer is formed covering the sidewall of the middle part of the second sub-active pillar; A gate is formed covering the gate oxide layer; The source and drain are formed at the bottom and top of the second active pillar, respectively; An isolation structure is formed between the second protective pillars and between the gate.

16. The method for fabricating a semiconductor structure according to claim 15, characterized in that, The gate forming the gate covering the gate oxide layer includes: The gaps in the gate oxide layer are filled with gate conductive material; Using the first protective layer as a mask layer, a portion of the gate conductive material is removed, and the remaining gate conductive material forms the gate.

17. The method for fabricating a semiconductor structure according to claim 15, characterized in that, Before forming the gate oxide layer, the sidewall of the middle part of the second sub-active pillar is removed to form a second sub-active pillar with a recess and a recessed space corresponding to the recess; in the recessed space, at least a gate oxide layer surrounding the recess is formed.

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