Semiconductor structure and method of making the same, memory

Abstract

The embodiments of the present disclosure disclose a semiconductor structure, a manufacturing method thereof and a memory, wherein the semiconductor structure comprises a plurality of first semiconductor columns, a plurality of second semiconductor columns, a first support layer and a storage structure; the plurality of first semiconductor columns are arranged in an array along a first direction and a second direction; the first direction and the second direction are both perpendicular to the extension direction of the first semiconductor column, and the first direction and the second direction intersect; the first support layer covers the top sidewall of the plurality of first semiconductor columns; each second semiconductor column is located on a corresponding first semiconductor column; and the storage structure at least surrounds the sidewalls of the plurality of first semiconductor columns and the plurality of second semiconductor columns.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method, and a memory. Background Technology

[0002] The memory array architecture of Dynamic Random Access Memory (DRAM) consists of an array of memory cells (i.e., 1T1C memory cells) each containing one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.

[0003] As the size of dynamic random access memory (DRAM) continues to shrink, the size of capacitors also shrinks. Ensuring the performance of capacitors in DRAM has become a pressing issue.

[0004] Public content

[0005] In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for fabricating the same, and a memory.

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0007] Multiple first semiconductor pillars, multiple second semiconductor pillars, a first support layer, and a memory structure; wherein,

[0008] The plurality of first semiconductor pillars are arranged in an array along a first direction and a second direction; both the first direction and the second direction are perpendicular to the extension direction of the first semiconductor pillars, and the first direction and the second direction intersect each other;

[0009] The first support layer covers the top sidewalls of the plurality of first semiconductor pillars;

[0010] Each of the second semiconductor pillars is located on a corresponding first semiconductor pillar; the memory structure surrounds at least the sidewalls of the plurality of first semiconductor pillars and the plurality of second semiconductor pillars.

[0011] In the above scheme, the first support layer includes: a plurality of first support columns and a plurality of second support columns; wherein,

[0012] Each of the first support pillars is located between the tops of two adjacent first semiconductor pillars along the first direction, each of the second support pillars is located between the tops of two adjacent first semiconductor pillars along the second direction, and the first support layer covers a portion of the top sidewall of the first semiconductor pillar.

[0013] In the above scheme, the storage structure includes:

[0014] Multiple first electrodes; each first electrode covers at least a portion of the sidewall of a first semiconductor pillar that is not covered by the first support layer, and also covers the sidewall of a corresponding second semiconductor pillar;

[0015] Multiple dielectric layers; each of the dielectric layers covers at least one sidewall of the first electrode, one sidewall of the first support post, and one sidewall of the second support post;

[0016] The second electrode is located in the gap between the plurality of first semiconductor pillars and the plurality of second semiconductor pillars and covers the plurality of dielectric layers.

[0017] In the above scheme, the semiconductor structure further includes:

[0018] Multiple oxide pillars, each of the first semiconductor pillars being located on the top surface of a corresponding oxide pillar;

[0019] A sacrificial layer is located in the gaps between the plurality of oxide pillars;

[0020] The dielectric layer also covers the top surface of the sacrificial layer.

[0021] In the above scheme, the semiconductor structure further includes:

[0022] Multiple transistors; the channel structure of each transistor is located on the upper part of the second semiconductor pillar, and the extension direction of the channel structure is perpendicular to the plane containing the first direction and the second direction;

[0023] The transistor includes:

[0024] The gate structure is at least surrounding a portion of the upper sidewall of the second semiconductor pillar, and the source and drain are respectively disposed on the upper part of the second semiconductor pillar and located at both ends of the channel structure.

[0025] According to another aspect of this disclosure, a memory is provided, comprising: one or more semiconductor structures as described in any of the above embodiments of this disclosure.

[0026] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:

[0027] A first semiconductor substrate is provided, and a first active layer is formed on the first semiconductor substrate. The first active layer includes a plurality of first semiconductor pillars arranged in an array along a first direction and a second direction. The first direction and the second direction are both perpendicular to the extension direction of the first semiconductor pillars, and the first direction and the second direction intersect each other.

[0028] A first support layer is formed on top of the first active layer;

[0029] A second semiconductor substrate is formed on the first active layer and the first support layer;

[0030] A portion of the second semiconductor substrate is removed to form a second active layer, the second active layer comprising a plurality of second semiconductor pillars; each second semiconductor pillar is located on the top surface of a corresponding first semiconductor pillar;

[0031] A second support layer is formed on top of the second active layer;

[0032] A memory structure is formed on the sidewalls of a plurality of first semiconductor pillars and a plurality of second semiconductor pillars.

[0033] In the above scheme, the method further includes: forming a first insulating layer in the gaps between the plurality of first semiconductor pillars before forming the first support layer;

[0034] Forming the first support layer includes:

[0035] A portion of the first insulating layer is removed to form a plurality of first grooves;

[0036] A first support column is formed in the first groove;

[0037] A portion of the first insulating layer is removed to form a plurality of second grooves;

[0038] A second support column is formed in the second groove;

[0039] The first support pillar and the second support pillar together constitute the first support layer. Each first support pillar is located between the tops of two adjacent first semiconductor pillars along the first direction, and each second support pillar is located between the tops of two adjacent first semiconductor pillars along the second direction. The first support layer covers a portion of the top sidewall of the first semiconductor pillar.

[0040] In the above scheme, forming the second semiconductor substrate includes:

[0041] Remove part of the first insulating layer and part of the first support layer to expose part of the sidewall at the top of the first semiconductor pillar;

[0042] The second semiconductor substrate is formed on the first semiconductor pillar using an epitaxial growth process.

[0043] The method in the above scheme further includes:

[0044] Before forming the second support layer, a second insulating layer is formed in the gaps between the plurality of second semiconductor pillars;

[0045] Forming the second support layer includes:

[0046] Part of the second insulating layer is removed to form multiple third grooves;

[0047] A third support column is formed in the third groove;

[0048] Part of the second insulating layer is removed to form a plurality of fourth grooves;

[0049] A fourth support column is formed in the fourth groove;

[0050] The third support pillar and the fourth support pillar together constitute the second support layer. Each third support pillar is located between the tops of two adjacent second semiconductor pillars along the first direction, and each fourth support pillar is located between the tops of two adjacent second semiconductor pillars along the second direction. The second support layer covers a portion of the top sidewall of the second semiconductor pillar.

[0051] In the above scheme, forming the storage structure includes:

[0052] Completely remove the remaining first insulating layer and the remaining second insulating layer;

[0053] The exposed surfaces of the first semiconductor pillar and the second semiconductor pillar are subjected to an oxidation treatment to form a first oxide layer;

[0054] Sacrificial material is formed in the gaps of the first oxide layer;

[0055] Remove the second support layer and the first oxide layer to form a first filling region surrounding the first semiconductor pillar and the second semiconductor pillar;

[0056] A first electrode is formed by filling the first filled region with conductive material.

[0057] Remove the sacrificial material between the first electrodes to form a second filling region;

[0058] A dielectric layer and a second electrode are sequentially formed in the second filled region.

[0059] In the above scheme, before removing the second support layer, the first oxide layer located on the sidewall at the top of the second semiconductor pillar is removed to form a third filling region, and the sacrificial material is formed in the third filling region to form a third support layer at the top of the second semiconductor pillar.

[0060] In the above scheme, while forming the first electrode, the conductive material is formed in the third and fourth grooves to form a fourth support layer on top of the second semiconductor pillar.

[0061] In the above scheme, forming the first active layer includes:

[0062] Multiple first trenches spaced apart along a first direction and multiple second trenches spaced apart along a second direction are formed in the first semiconductor substrate; wherein the first trenches and the second trenches divide the first semiconductor substrate into multiple first semiconductor pillars;

[0063] The bottom of each of the first trenches and / or the second trenches is enlarged such that the formed first semiconductor pillar includes a first portion and a second portion located on the first portion; the maximum diameter of the first portion is smaller than the minimum diameter of the second portion.

[0064] In the above scheme, while the first oxide layer is formed, the first portion is completely oxidized into oxide pillars; while sacrificial material is formed in the gaps of the first oxide layer, the sacrificial material is also formed in the gaps of the oxide pillars; and when the sacrificial material between the first electrodes is removed, the sacrificial material located between the oxide pillars is retained to form a sacrificial layer, and the oxide pillars and the sacrificial layer form a bottom support layer.

[0065] The method in the above scheme further includes:

[0066] Remove the fourth support layer and part of the memory structure located on the upper part of the second semiconductor pillar to expose the upper sidewall of the second semiconductor pillar;

[0067] A gate structure is formed on at least one side of the upper sidewall.

[0068] This disclosure provides a semiconductor structure and its fabrication method, as well as a memory. The fabrication method of the semiconductor structure includes: providing a first semiconductor substrate; forming a first active layer on the first semiconductor substrate, the first active layer including a plurality of first semiconductor pillars arranged in an array along a first direction and a second direction; the first direction and the second direction are both perpendicular to the extension direction of the first semiconductor pillars and intersect each other; forming a first support layer on top of the first active layer; forming a second semiconductor substrate on the first active layer and the first support layer; removing a portion of the second semiconductor substrate to form a second active layer, the second active layer including a plurality of second semiconductor pillars; each second semiconductor pillar being located on the top surface of a corresponding first semiconductor pillar; forming a second support layer on top of the second active layer; and forming a memory structure on the sidewalls of the plurality of first semiconductor pillars and the plurality of second semiconductor pillars. In this embodiment of the present disclosure, by first forming a first semiconductor pillar on a first semiconductor substrate and forming a first support layer on top of the first semiconductor pillar, and then forming a second semiconductor pillar on the first semiconductor pillar and forming a second support layer on top of the second semiconductor pillar, a storage structure with a large storage capacity can be formed in the gap between the tall semiconductor pillars. At the same time, the first support layer and the second support layer can support the first semiconductor pillar and the second semiconductor pillar, so that the tall semiconductor pillars can be formed without collapsing, thereby obtaining a high-capacity and high-strength semiconductor structure. Attached Figure Description

[0069] Figure 1 This is a schematic diagram of the circuit connection of a DRAM transistor provided in an embodiment of this disclosure;

[0070] Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0071] Figures 3-30 This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation

[0072] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0073] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0074] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0075] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0076] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0077] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0078] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0079] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only.

[0080] However, it should be noted that the following description of dynamic random access memory is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.

[0081] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements for ions and leakage current in dynamic random access memory, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.

[0082] In some embodiments of this disclosure, regardless of whether it is a planar transistor, a recessed gate array transistor, a buried transistor, or a vertical gate transistor, the dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0083] Figure 1 This is a circuit connection diagram of a 1T1C architecture provided in an embodiment of this disclosure; as shown... Figure 1 As shown, the drain of transistor T is electrically connected to the bit line (BL), and the source of transistor T is electrically connected to one of the electrode plates of capacitor C. The other electrode plate of capacitor C can be connected to a reference voltage, which can be ground or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0084] However, with the development of memory, the size of dynamic random access memory is constantly shrinking and the storage capacity of memory is constantly increasing, which makes the process of forming capacitors increasingly difficult and poses a risk of collapse.

[0085] In view of this, in order to solve one or more of the above problems, this disclosure provides a method for fabricating a semiconductor structure that can improve the collapse problem. Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 2 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:

[0086] S100: A first semiconductor substrate is provided, and a first active layer is formed on the first semiconductor substrate. The first active layer includes a plurality of first semiconductor pillars arranged in an array along a first direction and a second direction. The first direction and the second direction are both perpendicular to the extension direction of the first semiconductor pillars, and the first direction and the second direction intersect each other.

[0087] S200: A first support layer is formed on top of the first active layer;

[0088] S300: A second semiconductor substrate is formed on the first active layer and the first support layer;

[0089] S400: A portion of the second semiconductor substrate is removed to form a second active layer, the second active layer comprising a plurality of second semiconductor pillars; each second semiconductor pillar is located on the top surface of a corresponding first semiconductor pillar;

[0090] S500: A second support layer is formed on top of the second active layer;

[0091] S600: A memory structure is formed on the sidewalls of a plurality of first semiconductor pillars and a plurality of second semiconductor pillars.

[0092] It should be understood that Figure 2 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 2 The steps shown can be adjusted in order according to actual needs. Figures 3 to 30 This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure. It should be noted that... Figures 3 to 30 This is a schematic diagram illustrating the complete manufacturing process of a semiconductor structure. Unmarked parts in some of the accompanying drawings can be shared. The following section combines... Figure 2 , Figures 3 to 30The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0093] In step S100, a first active layer consisting of a plurality of first semiconductor pillars 102 is formed on the first semiconductor substrate 101.

[0094] In some embodiments, forming the first active layer includes:

[0095] Multiple first trenches 118 spaced apart along a first direction and multiple second trenches 119 spaced apart along a second direction are formed in the first semiconductor substrate 101; wherein the first trenches 118 and the second trenches 119 divide the first semiconductor substrate 101 into multiple first semiconductor pillars 102.

[0096] The bottom of each of the first trench 118 and / or the second trench 119 is enlarged such that the formed first semiconductor pillar 102 includes a first portion 102-1 and a second portion 102-2 located on the first portion 102-1; the maximum diameter of the first portion 102-1 is smaller than the minimum diameter of the second portion 102-2.

[0097] In some specific examples, the first semiconductor substrate 101 includes, but is not limited to, a substrate, which may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0098] The following is combined Figures 3-6 The formation process of the first semiconductor pillar 102 is described in detail.

[0099] like Figure 3 As shown, a first etching is performed on the surface of the first semiconductor substrate 101 to form a plurality of first trenches 118 spaced apart along a first direction in the first semiconductor substrate 101. Here, each of the first trenches 118 extends along a second direction.

[0100] Here, the first direction is parallel to the surface of the first semiconductor substrate 101; the second direction intersects the first direction and is parallel to the surface of the first semiconductor substrate 101. The third direction is the extension direction of the first semiconductor pillar 102, and the third direction is perpendicular to the surface of the first semiconductor substrate 101.

[0101] Here, the first direction intersects with the second direction, which can be understood as the angle between the first direction and the second direction being 0-90 degrees.

[0102] To clearly describe this disclosure, the following embodiments are illustrated using the example of a first direction being perpendicular to a second direction. For example, the first direction is... Figure 3 The X-axis direction is shown in the figure; the second direction is Figure 3 The Y-axis direction is shown in the figure; the third direction is Figure 3 The Z-axis direction is shown in the figure. However, it should be noted that the description of the direction in the following embodiments is for illustrative purposes only and is not intended to limit the scope of this disclosure.

[0103] In some specific examples, the first trench 118 includes, but is not limited to, a shallow trench isolation (STI) structure.

[0104] In some specific examples, the methods for forming the first trench 118 include, but are not limited to, dry plasma etching processes.

[0105] like Figure 4 As shown, a first insulating layer 106 is formed in the first trench 118; wherein, the top surface of the first insulating layer 106 is substantially flush with the top surface of the first semiconductor substrate 101; here, the first insulating layer 106 serves as a support.

[0106] It should be noted that the term "basic flush" in this disclosure can be understood as "approximately flush"; it is also understood that misalignment or non-flushness caused by process errors during the manufacturing process of memory is also included within the scope of "basic flush".

[0107] In some specific examples, the constituent materials of the first insulating layer 106 include, but are not limited to, silicon oxide (SiO2).

[0108] In some specific examples, the methods for forming the first insulating layer 106 include, but are not limited to, processes such as PVD, CVD, and ALD.

[0109] like Figure 5 As shown, a second etching is performed on a first semiconductor substrate 101 on which a first insulating layer 106 is formed to form a plurality of second trenches 119 in the first semiconductor substrate 101; wherein the plurality of second trenches 119 are spaced apart along a second direction, and each second trench 119 extends along a first direction; that is, the first trench 118 and the second trench 119 intersect.

[0110] In some specific examples, when the first direction is perpendicular to the second direction, the first groove 118 and the second groove 119 are perpendicular to each other.

[0111] In some specific examples, a plurality of first grooves 118 are spaced apart along the X-axis; and each first groove 118 extends along the Y-axis; a plurality of second grooves 119 are spaced apart along the Y-axis; and each second groove 119 extends along the X-axis.

[0112] In some specific examples, the methods for forming the second trench 119 include, but are not limited to, dry plasma etching processes.

[0113] In some specific examples, the second trench 119 includes, but is not limited to, shallow trench isolation (STI) structures.

[0114] Here, the first trench 118 and the second trench 119 divide the first semiconductor substrate 101 into a plurality of first semiconductor pillars 102 arranged in an array along the first direction and the second direction.

[0115] In some specific examples, a grid-like mask layer can also be formed on the surface of the first semiconductor substrate 101. The grid-like mask layer is used as a mask to etch the first semiconductor substrate 101, while forming the first trench 118 and the second trench 119, so as to form a plurality of first semiconductor pillars 102 arranged in an array along the first direction and the second direction in the first semiconductor substrate 101.

[0116] Next, as Figure 5 As shown, the bottom of each of the first trenches 118 and / or the second trenches 119 is enlarged; here, the enlargement process can be understood as etching the bottom of the first trench 118 along a first direction; and / or etching the bottom of the second trench 119 along a second direction, such that the diameter of the bottom of the first trench 118 and / or the second trench 119 along the first direction is greater than the diameter of the top of the corresponding trench along the first direction.

[0117] And / or,

[0118] The bottom diameter of the first groove 118 and / or the second groove 119 along the second direction is greater than the top diameter of the corresponding groove along the second direction.

[0119] In some specific examples, the etching process used may include wet etching, dry etching, etc.

[0120] For example, in the wet etching process, an etchant is introduced into the bottom of the first trench 118 and / or the second trench 119, and the diameter of the bottom of the first trench 118 and / or the second trench 119 along the X-axis is increased by the anisotropic etching of the etchant; and / or, the diameter of the bottom of the first trench 118 and / or the second trench 119 along the Y-axis is increased.

[0121] For example, in the dry etching process, lateral etching is performed by controlling plasma to form a trench structure with an enlarged diameter at the bottom of the first trench 118 and / or the second trench 119.

[0122] In this embodiment of the disclosure, after the process of enlarging the bottom of each of the first trench 118 and / or the second trench 119, the etching process causes the bottom regions of the plurality of first semiconductor pillars 102 located on the first semiconductor substrate 101 to be etched, thereby reducing the size of the bottom regions of the first semiconductor pillars 102.

[0123] In other words, the first semiconductor pillar 102 includes a first portion 102-1 and a second portion 102-2 located on the first portion 102-1; here, the second portion 102-2 of the first semiconductor pillar 102 is located on the first portion 102-1 of the first semiconductor pillar 102.

[0124] For example, when only the first trench 118 is enlarged, the maximum diameter of the first portion 102-1 of the first semiconductor pillar 102 along the X-axis is smaller than the minimum diameter of the second portion 102-2 of the first semiconductor pillar 102 along the X-axis.

[0125] For example, when only the second trench 119 is enlarged, the maximum diameter of the first portion 102-1 of the first semiconductor pillar 102 along the Y-axis is smaller than the minimum diameter of the second portion 102-2 of the first semiconductor pillar 102 along the Y-axis.

[0126] For example, when both the first trench 118 and the second trench 119 are enlarged, the maximum diameter of the first portion 102-1 of the first semiconductor pillar 102 along the X-axis is smaller than the minimum diameter of the second portion 102-2 of the first semiconductor pillar 102 along the X-axis; and the maximum diameter of the first portion 102-1 of the first semiconductor pillar 102 along the Y-axis is smaller than the minimum diameter of the second portion 102-2 of the first semiconductor pillar 102 along the Y-axis.

[0127] Preferably, both the first trench 118 and the second trench 119 are enlarged to reduce the size of the first portion 102-1 of the first semiconductor pillar 102.

[0128] For example, the maximum diameter of the first part 102-1 can be understood as Figure 5 The diameter at the contact point between the first portion 102-1 and the second portion 102-2 of the first semiconductor pillar 102; the minimum diameter of the second portion 102-2 can be understood as the smallest region within the second portion 102-2 of the first semiconductor pillar 102; Reference Figure 5The upper and lower portions of the second part 102-2 of the first semiconductor pillar 102 have the same dimensions, that is, the minimum diameter and the maximum diameter of the second part 102-2 of the first semiconductor pillar 102 are the same.

[0129] Next, as Figure 6 As shown, a first insulating layer 106 is formed in the second trench 119; the top surface of the first insulating layer 106 is substantially flush with the top surface of the first semiconductor substrate 101. The first insulating material serves as a support.

[0130] It should be noted that the order in which the first trench 118 and the second trench 119 are formed, and the first insulating layer 106 is formed by filling the first insulating material in the first trench 118 and the second trench 119, can be selected according to the actual situation. In some other specific embodiments, the first trench 118 and the second trench 119 can be formed first, and then the first insulating layer 106 can be formed in the first trench 118 and the second trench 119.

[0131] In step S200, as Figures 7 to 10 As shown, the first support layer 109 is mainly formed on top of the first active layer.

[0132] In some embodiments, the method further includes: forming a first insulating layer 106 in the gaps between the plurality of first semiconductor pillars 102 before forming the first support layer 109 (e.g., ...). Figure 6 (as shown);

[0133] The first support layer 109 is formed by:

[0134] A portion of the first insulating layer 106 is removed to form a plurality of first grooves 107;

[0135] A first support post 109-1 is formed in the first groove 107;

[0136] A portion of the first insulating layer 106 is removed to form a plurality of second grooves 108;

[0137] A second support column 109-2 is formed in the second groove 108;

[0138] The first support pillar 109-1 and the second support pillar 109-2 together constitute the first support layer 109. Each first support pillar 109-1 is located between the tops of two adjacent first semiconductor pillars 102 along the first direction, and each second support pillar 109-2 is located between the tops of two adjacent first semiconductor pillars 102 along the second direction. The first support layer 109 covers part of the top sidewall of the first semiconductor pillar 102.

[0139] like Figure 7As shown, a portion of the first insulating layer 106 at the top of the first semiconductor pillar 102 is removed to form a plurality of first grooves 107. Each first groove 107 is located between the tops of two adjacent first semiconductor pillars 102 along the second direction. The plurality of first grooves 107 are spaced apart along the X-axis direction, and each first groove 107 extends along the Y-axis direction.

[0140] In some specific examples, the methods for removing a portion of the first insulating layer 106 at the top of the first semiconductor pillar 102 include, but are not limited to, dry etching processes and wet etching processes.

[0141] Next, as Figure 8 As shown, a first support column 109-1 is formed in the first groove 107.

[0142] In some specific examples, the methods for forming the first support column 109-1 include, but are not limited to, processes such as PVD, CVD, and ALD.

[0143] Here, the material of the first support column 109-1 includes, but is not limited to, silicon nitride.

[0144] Next, as Figure 9 As shown, a portion of the first insulating layer 106 at the top of the first semiconductor pillar 102 is removed to form a plurality of second grooves 108. Each second groove 108 is located between the tops of two adjacent first semiconductor pillars 102 along a first direction. The plurality of second grooves 108 are spaced apart along the Y-axis direction, and each second groove 108 extends along the X-axis direction.

[0145] Next, as Figure 10 As shown, a second support column 109-2 is formed in the second groove 108.

[0146] In some specific examples, the methods for forming the second support column 109-2 include, but are not limited to, processes such as PVD, CVD, and ALD.

[0147] Here, the first support column 109-1 and the second support column 109-2 may be made of the same or different materials.

[0148] In some specific examples, after the first support layer 109 is formed in the first groove 107 and the second groove 108, the first support layer 109 is further planarized so that the first support layer 109 is flush with the top surface of the first semiconductor pillar 102.

[0149] In some specific examples, the planarization process includes, but is not limited to, chemical mechanical polishing (CMP).

[0150] Here, the first support column 109-1 and the second support column 109-2 together constitute the first support layer 109, as shown below. Figure 10 As shown, the first support layer 109 has a mesh structure and covers part of the top sidewall of the first semiconductor pillar 102.

[0151] In other specific examples, a mesh-like mask layer can also be formed on the first semiconductor pillar 102, and the mesh-like mask layer can be used as a mask to etch the first insulating layer 106, while forming the first groove 107 and the second groove 108. While forming the first support pillar 109-1 in the first groove 107, the second support pillar 109-2 is formed in the second groove 108.

[0152] Here, the first support layer 109 covers a portion of the top sidewall of the first semiconductor pillar 102. This can be understood as the first support pillar 109-1 covering a portion of the top sidewall of the first semiconductor pillar 102, and / or the second support pillar 109-2 covering a portion of the top sidewall of the first semiconductor pillar 102. In other words, at least a portion of the first support layer 109 covers a portion of the top sidewall of the first semiconductor pillar 102; the first support layer 109 must cover the top sidewall of the first semiconductor pillar 102, but cannot completely cover it. Understandably, firstly, the first support layer 109 can only support the first semiconductor pillar 102 if it covers the top sidewall of the first semiconductor pillar 102. The more the first support layer 109 covers the top sidewall of the first semiconductor pillar 102, the better the support effect. Secondly, if the first support layer 109 completely covers the sidewall of the first semiconductor pillar 102, then when the memory structure 105 is formed in the subsequent process, the material of the first electrode can only fill the gap of the second semiconductor pillar 104, and cannot fill the gap of the first semiconductor pillar 102 downwards.

[0153] Understandably, with the increasing demands for memory density, the aspect ratio of the first semiconductor pillar 102 is constantly increasing, which increases the risk of collapse during the formation of the first semiconductor pillar 102. In this embodiment, at least a portion of the first support layer 109 covers part of the top sidewall of the first semiconductor pillar 102, thereby connecting multiple first semiconductor pillars 102 to each other. This provides support for the first semiconductor pillars 102 during subsequent process steps when the first insulating layer 106 is removed, making the first semiconductor pillars 102 with their large aspect ratio less prone to collapse.

[0154] The process of forming a first semiconductor pillar 102 on a first semiconductor substrate 101 has been described above. In practical applications, the storage capacity of the memory structure formed in the gap between semiconductor pillars of a certain height may not be sufficient, and it is necessary to further increase the height of the semiconductor pillars to form a memory structure with a larger capacity in the gap between the increased semiconductor pillars. However, increasing the height of the semiconductor pillars makes them more prone to collapse. In order to further solve the above-mentioned collapse problem, the embodiments of this disclosure also propose the following technical solutions.

[0155] In step S300, the second semiconductor substrate 103 is mainly formed.

[0156] In some embodiments, forming the second semiconductor substrate 103 includes:

[0157] Remove part of the first support layer 109 and part of the first insulating layer 106 to expose part of the sidewall at the top of the first semiconductor pillar 102;

[0158] The second semiconductor substrate 103 is formed on the first semiconductor pillar 102, the remaining first support layer 109 and the remaining first insulating layer 106 using an epitaxial growth process.

[0159] like Figure 11 As shown, the first insulating layer 106 at the top of the first semiconductor pillar 102 is removed, exposing a portion of the sidewall at the top of the first semiconductor pillar 102.

[0160] In some embodiments, the method for removing the first insulating layer 106 on top of the first semiconductor pillar 102 includes, but is not limited to, dry etching process and wet etching process.

[0161] Next, as Figure 12 As shown, a second semiconductor substrate 103 is formed on the first semiconductor pillar 102 and the first support layer 109.

[0162] In some specific examples, the methods for forming the second semiconductor substrate 103 include, but are not limited to, epitaxial growth processes.

[0163] It is understood that the purpose of removing the first insulating layer 106 at the top of the first semiconductor pillar 102 and exposing part of the sidewall at the top of the first semiconductor pillar 102 in the above embodiment is mainly to make it easier to form the second semiconductor substrate 103 by epitaxial growth.

[0164] In some specific examples, the material of the first semiconductor substrate 101 may include elemental semiconductor materials (e.g., silicon, germanium, etc.), composite semiconductor materials (e.g., germanium-silicon, etc.), etc. The material of the second semiconductor substrate 103 may be the same as or different from the material of the first semiconductor substrate 101.

[0165] In step S400, the main task is to form a second active layer consisting of a plurality of second semiconductor pillars 104.

[0166] like Figure 13 As shown, a plurality of second semiconductor pillars 104 are formed, each second semiconductor pillar 104 being located on the top surface of a corresponding first semiconductor pillar 102. A second insulating layer 110 is formed in the gaps between the second semiconductor pillars 104.

[0167] Here, the material of the second insulating layer 110 includes, but is not limited to, silicon oxide. The material of the second insulating layer 110 may be the same as or different from that of the first insulating layer 106.

[0168] Here, the process of forming the second semiconductor pillar 104 on the first semiconductor pillar 102 is similar to the process of forming the first semiconductor pillar 102 in the previous embodiment, and will not be described again here.

[0169] In step S500, as Figure 14 As shown, the main structure is the formation of the second support layer 114.

[0170] In some embodiments, the method further includes:

[0171] Before forming the second support layer 114, a second insulating layer 110 is formed in the gaps between the plurality of second semiconductor pillars 104;

[0172] The second support layer 114 is formed by:

[0173] A portion of the second insulating layer 110 is removed to form a plurality of third grooves;

[0174] A third support column 114-1 is formed in the third groove;

[0175] A portion of the second insulating layer 110 is removed to form a plurality of fourth grooves;

[0176] A fourth support post 114-2 is formed in the fourth groove;

[0177] The third support pillar 114-1 and the fourth support pillar 114-2 together constitute the second support layer 114. Each third support pillar 114-1 is located between the tops of two adjacent second semiconductor pillars 104 along the first direction, and each fourth support pillar 114-2 is located between the tops of two adjacent second semiconductor pillars 104 along the second direction. The second support layer 114 covers part of the top sidewall of the second semiconductor pillars 104.

[0178] Here, the material of the second support layer 114 includes, but is not limited to, silicon nitride. The material of the second support layer 114 may be the same as or different from that of the first support layer 109.

[0179] Here, the process of forming the second support layer 114 on top of the second active layer is similar to the process of forming the first support layer 109 on top of the first active layer in the previous embodiment, and will not be described again here.

[0180] Understandably, the second support layer 114 here supports the second semiconductor pillar 104, so that the second semiconductor pillar 104 is not easy to collapse after the first insulating layer 106 and the second insulating layer 110 are removed in subsequent processes.

[0181] In step S600, as Figures 15-27 As shown, the main structure is the storage structure 105.

[0182] In some embodiments, the storage structure 105 includes:

[0183] Completely remove the remaining first insulating layer 106 and the remaining second insulating layer 110;

[0184] The exposed surfaces of the first semiconductor pillar 102 and the second semiconductor pillar 104 are oxidized to form a first oxide layer 115.

[0185] Sacrificial material 117 is formed in the gaps of the first oxide layer 115;

[0186] Remove the second support layer 114 and the first oxide layer 115 to form a first filling region surrounding the first semiconductor pillar 102 and the second semiconductor pillar 104;

[0187] A first electrode 105-1 is formed by filling the first filling region with conductive material.

[0188] Remove the sacrificial material 117 between the first electrodes 105-1 to form a second filling region;

[0189] A dielectric layer 105-2 and a second electrode 105-3 are sequentially formed in the second filling region.

[0190] In some embodiments, while the first oxide layer 115 is formed, the first portion 102-1 is completely oxidized into oxide pillars 122; while sacrificial material 117 is formed in the gaps of the first oxide layer 115, the sacrificial material 117 is also formed in the gaps of the oxide pillars 122; and when the sacrificial material 117 between the first electrodes 105-1 is removed, the sacrificial material 117 located between the oxide pillars 122 is retained to form a sacrificial layer 123, and the oxide pillars 122 and the sacrificial layer 123 form a bottom support layer.

[0191] In some embodiments, before removing the second support layer 114, the first oxide layer 115 located on the sidewall at the top of the second semiconductor pillar 104 is removed to form a third filling region, and the sacrificial material 117 is formed in the third filling region to form a third support layer 120 at the top of the second semiconductor pillar 104.

[0192] In some embodiments, while forming the first electrode 105-1, the conductive material is formed in the third and fourth grooves to form a fourth support layer 121 on top of the second semiconductor pillar 104.

[0193] like Figure 15 As shown, the remaining first insulating layer 106 and the remaining second insulating layer 110 are completely removed.

[0194] In some specific examples, the methods for completely removing the remaining first insulating layer 106 and the remaining second insulating layer 110 include, but are not limited to, dry etching processes and wet etching processes.

[0195] Next, as Figure 16 As shown, the exposed surfaces of the first semiconductor pillar 102 and the second semiconductor pillar 104 are oxidized by an oxidation process, such as a thermal oxidation process, so that the first part 102-1 of the first semiconductor pillar 102 is completely oxidized into an oxide pillar 122, the surface of the second part 102-2 of the exposed first semiconductor pillar 102 and the surface of the exposed second semiconductor pillar 104 are oxidized into a first oxide layer 115, and at the same time, the surface of the first semiconductor substrate 101 is also oxidized to form a second oxide layer 116.

[0196] Understandably, the second oxide layer 116 and oxide pillars 122 formed here enable the capacitor formed in subsequent processes to be isolated from the bottom first semiconductor substrate 101, thereby improving the leakage problem at the bottom of the capacitor.

[0197] Here, the first oxide layer 115, the second oxide layer 116, and the oxide pillar 122 are made of the same material. For example, the constituent materials of the first oxide layer 115, the second oxide layer 116, and the oxide pillar 122 include, but are not limited to, silicon oxide.

[0198] In some specific examples, the materials of the first oxide layer 115, the second oxide layer 116, and the oxide pillar 122 may be the same as or different from the material of the first insulating layer 106. The materials of the first oxide layer 115, the second oxide layer 116, and the oxide pillar 122 may be the same as or different from the material of the second insulating layer 110.

[0199] To more clearly illustrate the changes at the top of the first semiconductor pillar 102 during the manufacturing process, Figure 17 , Figure 19, Figure 23 , Figure 25 A cross-sectional schematic diagram of the top of the first semiconductor pillar 102 is shown separately.

[0200] like Figure 16 as well as Figure 17 As shown, during the oxidation process of the first semiconductor pillar 102 and the second semiconductor pillar 104, since the top of the first semiconductor pillar 102 and the top of the second semiconductor pillar 104 are partially covered by the first support layer 109 and the second support layer 114, only the uncovered part of the sidewall of the first semiconductor pillar 102 and the part of the sidewall of the second semiconductor pillar 104 are oxidized into the first oxide layer 115.

[0201] It should be noted that, in the foregoing embodiments, after enlarging the first trench 118 and / or the second trench 119, the first portion 102-1 of the first semiconductor pillar 102 is smaller in size and easier to be completely oxidized. Moreover, when the first portion 102-1 of the first semiconductor pillar 102 is oxidized, only the surface of the second portion 102-2 of the first semiconductor pillar 102 is oxidized.

[0202] Next, as Figure 18 as well as Figure 19 As shown, sacrificial material 117 is formed in the gaps of the first oxide layer 115 and the gaps of the oxide pillars 122.

[0203] In some specific examples, the methods for forming the sacrificial material 117 include, but are not limited to, PVD, CVD, and ALD.

[0204] In some specific examples, the material of the sacrificial material 117 formed includes, but is not limited to, polycrystalline silicon and carbon.

[0205] Regarding the selection of the material of the sacrificial material 117, firstly, it is necessary to consider that the sacrificial material 117 has a certain etching selectivity relative to the first oxide layer 115, so that the sacrificial material 117 can be retained when the first oxide layer 115 is removed in the subsequent process; secondly, it is necessary to consider that the sacrificial material 117 has a certain etching selectivity relative to the material of the first electrode 105-1 formed in the subsequent process, so that the impact on the already formed first electrode 105-1 is reduced when the sacrificial material 117 is removed to form the sacrificial layer 123 in the subsequent process; thirdly, the sacrificial material 117 needs to be easy to remove in the subsequent process.

[0206] Next, as Figure 20As shown, the first oxide layer 115 located on the sidewall at the top of the second semiconductor pillar 104 is removed to form a third filling region. A sacrificial material 117 is formed in the third filling region to form a third support layer 120 on the top of the second semiconductor pillar 104. Specifically, the second support layer 120 can be as follows: Figure 20 The sacrificial material shown in the dashed box can specifically be as follows: Figure 20 The image shows the sacrificial material in the regions surrounding the four corners of the second semiconductor pillar.

[0207] In some specific examples, the methods for removing the first oxide layer 115 located on the sidewall at the top of the second semiconductor pillar 104 include, but are not limited to, dry etching processes and wet etching processes.

[0208] In some specific examples, the methods for forming the sacrificial material 117 in the third filling region include, but are not limited to, PVD, CVD, and ALD.

[0209] It should be noted that when the first oxide layer 115 on the sidewall at the top of the second semiconductor pillar 104 is removed, the first oxide layer 115 on the sidewall at the top of the first semiconductor pillar 102 is not removed.

[0210] Understandably, if the first oxide layer 115 on the sidewall at the top of the second semiconductor pillar 104 is not removed first to form the third support layer 120, but instead all of the first oxide layer 115 is removed together, then the sacrificial material 117 formed in the gaps of the second semiconductor pillars 104 in the aforementioned embodiment will separate from the formed sacrificial material 117 after all the first oxide layer 115 is removed. Furthermore, after the second support layer 114 is removed in subsequent processes, multiple second semiconductor pillars 104 will lose their support, posing a risk of collapse. Therefore, forming the third support layer 120 as a top support first can further improve the collapse problem.

[0211] Next, as Figure 21 As shown, the second support layer 114 is removed to form the third groove 112 and the fourth groove 113.

[0212] Here, the methods for removing the second support layer 114 include, but are not limited to, dry etching process and wet etching process.

[0213] Next, as Figure 22 as well as Figure 23 As shown, the remaining first oxide layer 115 in the gap between the first semiconductor pillar 102 and the second semiconductor pillar 104 is removed.

[0214] Here, after removing the remaining first oxide layer 115 from the gap between the second support layer 114 and the first semiconductor pillar 102 and the second semiconductor pillar 104, a first filling region 127 is formed around the first semiconductor pillar 102 and the second semiconductor pillar 104. Figure 23 The area at the top of the first semiconductor pillar, which surrounds the four corners of the first semiconductor pillar, is also part of the first filling area 127.

[0215] In some specific examples, the methods for removing the remaining first oxide layer 115 include, but are not limited to, dry etching processes and wet etching processes.

[0216] Next, as Figure 24 as well as Figure 25 As shown, a first electrode 105-1 is formed by filling a conductive material in the first filling region 127. Specifically, conductive material may be filled in the gaps between the third groove 112, the fourth groove 113, the first semiconductor pillar 102, and the gaps in the portion of the second semiconductor pillar 104 excluding the top. The conductive material filled in the third groove 112 and the fourth groove 113 forms a fourth support layer 121. The conductive material filled in the gaps between the first semiconductor pillar 102 and the gaps in the portion of the second semiconductor pillar 104 excluding the top forms the first electrode 105-1. Figure 25 The first filling region 127, which surrounds the four corners of the first semiconductor pillar and is shown in the figure, also has the first electrode 105-1 formed.

[0217] Understandably, the fourth support layer 121 formed here can play a supporting role, improving the problem of the first semiconductor pillar 102 and the second semiconductor pillar 104 losing support and thus collapsing after the removal of the sacrificial material 117 in subsequent process steps.

[0218] Here, the first electrode 105-1 is used as the lower electrode of the capacitor.

[0219] In some specific examples, the constituent materials of the first electrode 105-1 may include, but are not limited to, ruthenium (Ru), ruthenium oxide (RuO), and titanium nitride (TiN).

[0220] In some specific examples, the methods for forming the first electrode 105-1 include, but are not limited to, PVD, CVD, and ALD.

[0221] It is understood that in this embodiment of the present disclosure, after removing the first oxide layer 115, a first filling region 127 is formed. This first filling region 127 surrounds the first semiconductor pillar 102 and the second semiconductor pillar 104. The material for forming the first electrode 105-1 is directly filled into the first filling region 127, thereby forming the first electrode 105-1. The multiple first electrodes 105-1 formed are separated from each other. The conventional method involves directly depositing the material for the first electrode 105-1 in the first trench 118 and second trench 119 in the gap of the first semiconductor pillar 102 to form multiple first electrodes 105-1. This makes it impossible for the bottoms of the multiple first electrodes 105-1 to be separated from each other, resulting in mutual interference between the first electrodes 105-1. However, the solution in this embodiment of the present disclosure allows the first electrodes 105-1 to be separated from each other, thereby improving the problem of mutual interference between the multiple first electrodes 105-1.

[0222] Next, as Figure 26 As shown, the sacrificial material 117 between the first electrodes 105-1 is removed to form a second filling region 128. During the removal of the sacrificial material 117 between the first electrodes 105-1, the sacrificial material 117 located between the oxide pillars 122 is retained to form a sacrificial layer 123, and the oxide pillars 122 and the sacrificial layer 123 form a bottom support layer. Furthermore, during the removal of the sacrificial material 117 between the first electrodes 105-1, the sacrificial material 117 between the fourth support layers 121 is also removed simultaneously.

[0223] In some specific examples, the methods for removing the sacrificial material 117 include, but are not limited to, wet etching and dry etching processes. For example, when removing the sacrificial material 117 between the first electrodes 105-1 using an etching process, the etching time can be controlled to etch only the sacrificial material 117 between the first electrodes 105-1 and between the fourth support layer 121, while the sacrificial material 117 in the gaps between the oxide pillars 122 is retained.

[0224] Next, as Figure 27 As shown, a dielectric layer 105-2 and a second electrode 105-3 are sequentially formed in the second filling region 128.

[0225] Here, dielectric layer 105-2 is used as the dielectric of the capacitor.

[0226] Here, the constituent materials of the dielectric layer 105-2 include high-k dielectric materials, which generally refer to materials with a dielectric constant higher than 3.9, and are usually significantly higher than this value. In some specific examples, the material of the dielectric layer 105-2 may include, but is not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), strontium titanate (SrTiO3), etc.

[0227] In some specific embodiments, the constituent materials of the second electrode 105-3 may include, but are not limited to, ruthenium, ruthenium oxide, and titanium nitride.

[0228] Here, the methods for forming the second electrode 105-3 include, but are not limited to, processes such as PVD and CVD.

[0229] It is understood that in this embodiment of the present disclosure, the semiconductor pillar is formed in two stages, namely, the first semiconductor pillar 102 is formed first, and the second semiconductor pillar 104 is formed. After the first semiconductor pillar 102 and the second semiconductor pillar 104 are formed, the memory structure 105 is formed in the gap between the first semiconductor pillar 102 and the second semiconductor pillar. This can improve the collapse problem that occurs when the semiconductor pillar is formed in one stage.

[0230] The above describes forming semiconductor pillars in two stages. In some specific examples, semiconductor pillars can also be formed in three or more stages. In practical applications, the specific number of formations can be selected by balancing saving process time and improving the collapse problem area.

[0231] In some embodiments, the method further includes: forming a third semiconductor substrate on the first semiconductor pillar 102 and the first support layer 109 before forming the second semiconductor substrate 103;

[0232] A portion of the third semiconductor substrate is removed to form a third active layer, the third active layer comprising a plurality of third semiconductor pillars; each of the third semiconductor pillars is located on the top surface of a corresponding first semiconductor pillar 102;

[0233] A fifth support layer is formed on top of the third active layer, and the fifth support layer covers the top sidewall of the third semiconductor pillar;

[0234] A memory structure 105 is formed on the sidewalls of a plurality of first semiconductor pillars 102 and a plurality of second semiconductor pillars 104, including:

[0235] A memory structure 105 is formed on the sidewalls of a plurality of first semiconductor pillars 102, a plurality of second semiconductor pillars 104 and a plurality of third semiconductor pillars.

[0236] Next, a transistor is formed on the upper sidewall of the second semiconductor pillar 104, and a bit line is formed that is electrically connected to one of the source and drain of the transistor. The capacitor in the semiconductor structure is electrically connected to the other of the source and drain of the transistor.

[0237] In some embodiments, the method further includes:

[0238] Remove the fourth support layer 121 and part of the storage structure 105 located on the upper part of the second semiconductor pillar 104 to expose the upper sidewall of the second semiconductor pillar 104.

[0239] A gate structure 124 is formed on at least one side of the upper sidewall.

[0240] like Figure 27 As shown, the fourth support layer 121 and part of the storage structure 105 located on the upper part of the second semiconductor pillar 104 are removed, exposing the upper sidewall of the second semiconductor pillar 104.

[0241] In some specific examples, the methods for the fourth support layer 121 and the portion of the memory structure 105 located above the second semiconductor pillar 104 include, but are not limited to, dry etching processes and wet etching processes.

[0242] like Figure 28 As shown, a third insulating layer 111 is formed between the second semiconductor pillars 104 with exposed sidewalls. The height of the third insulating layer 111 in a third direction is lower than the height of the second semiconductor pillars 104 in a third direction.

[0243] like Figure 29 as well as Figure 30 As shown, a gate oxide layer 125 and a gate 126 are formed on the exposed sidewall of the second semiconductor pillar 104.

[0244] Here, the shape of the gate 126 varies in different types of transistors; for example, in a pillar gate transistor, the gate 126 is formed in a pillar shape on one side of the channel region; in a semi-around gate transistor, the gate 126 partially surrounds the channel region; in a gate all around (GAA) gate transistor, the gate 126 completely surrounds the channel region.

[0245] The transistor types in this disclosure may include, but are not limited to, the types described above. Preferably, the transistor type is a full-around gate transistor.

[0246] It should be noted that the gate structure 124 here includes a gate 126 and a gate oxide layer; wherein, the gate oxide layer is located between the gate 126 and the channel region, and is used to electrically isolate the channel region and the gate 126, thereby reducing the hot carrier effect of the transistor.

[0247] Here, the material of the gate 126 may include metal or polysilicon, etc. The material of the gate oxide layer may include, but is not limited to, silicon oxide.

[0248] In some specific examples, the methods for forming the gate 126 include, but are not limited to, PVD, CVD, ALD, etc. The methods for forming the gate oxide layer include, but are not limited to, in-situ oxidation.

[0249] In some specific examples, the method further includes forming a source and a drain at three opposite ends on the upper part of the second semiconductor pillar 104. Methods for forming the source and drain include, but are not limited to, doping and diffusion processes.

[0250] It should be noted that the positions of the source and drain at opposite ends on the upper part of the second semiconductor pillar 104 can be interchanged; in practice, the selection and setting can be made according to actual needs.

[0251] In some embodiments, the method further includes:

[0252] Multiple bit lines are formed on the second semiconductor pillar 104; the multiple bit lines are electrically contacted with the top of the second semiconductor pillar 104.

[0253] It is understood that the memory in the above embodiment is a transistor-capacitor (TOC) structure, which further includes multiple bit lines located on the transistor and electrically contacting the top of the second semiconductor pillar 104.

[0254] It is understood that the bit line BL is used to perform read or write operations on the transistor when the transistor is turned on.

[0255] Here, placing the bit line BL above the transistor and treating the bit line BL as a metal bit line can reduce resistance and simplify the manufacturing process; it is also more compatible with the circuit design of the memory.

[0256] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a first semiconductor substrate 101; forming a first active layer on the first semiconductor substrate 101, the first active layer including a plurality of first semiconductor pillars 102 arranged in an array along a first direction and a second direction; the first direction and the second direction are both perpendicular to the extension direction of the first semiconductor pillars 102, and the first direction and the second direction intersect; forming a first support layer 109 on top of the first active layer; forming a second semiconductor substrate 103 on the first active layer and the first support layer 109; removing a portion of the second semiconductor substrate 103 to form a second active layer, the second active layer including a plurality of second semiconductor pillars 104; each second semiconductor pillar 104 being located on the top surface of a corresponding first semiconductor pillar 102; forming a second support layer 114 on top of the second active layer; and forming a memory structure 105 on the sidewalls of the plurality of first semiconductor pillars 102 and the plurality of second semiconductor pillars 104. In this embodiment of the present disclosure, by first forming a first semiconductor pillar on a first semiconductor substrate and forming a first support layer on top of the first semiconductor pillar, and then forming a second semiconductor pillar on the first semiconductor pillar and forming a second support layer on top of the second semiconductor pillar, a storage structure with a large storage capacity can be formed in the gap between the tall semiconductor pillars. At the same time, the first support layer and the second support layer can support the first semiconductor pillar and the second semiconductor pillar, so that the tall semiconductor pillars can be formed without collapsing, thereby obtaining a high-capacity and high-strength semiconductor structure.

[0257] According to another aspect of this disclosure, embodiments of this disclosure further provide a semiconductor structure, including:

[0258] Multiple first semiconductor pillars, multiple second semiconductor pillars, a first support layer, and a memory structure; wherein,

[0259] The plurality of first semiconductor pillars are arranged in an array along a first direction and a second direction; both the first direction and the second direction are perpendicular to the extension direction of the first semiconductor pillars, and the first direction and the second direction intersect each other;

[0260] The first support layer covers the top sidewalls of the plurality of first semiconductor pillars;

[0261] Each of the second semiconductor pillars is located on a corresponding first semiconductor pillar; the memory structure surrounds at least the sidewalls of the plurality of first semiconductor pillars and the plurality of second semiconductor pillars.

[0262] In some embodiments, the first support layer includes: a plurality of first support columns and a plurality of second support columns; wherein...

[0263] Each of the first support pillars is located between the tops of two adjacent first semiconductor pillars along the first direction, each of the second support pillars is located between the tops of two adjacent first semiconductor pillars along the second direction, and the first support layer covers a portion of the top sidewall of the first semiconductor pillar.

[0264] In some embodiments, the storage structure includes:

[0265] Multiple first electrodes; each first electrode covers at least a portion of the sidewall of a first semiconductor pillar that is not covered by the first support layer, and also covers the sidewall of a corresponding second semiconductor pillar;

[0266] Multiple dielectric layers; each of the dielectric layers covers at least one sidewall of the first electrode, one sidewall of the first support post, and one sidewall of the second support post;

[0267] The second electrode is located in the gap between the plurality of first semiconductor pillars and the plurality of second semiconductor pillars and covers the plurality of dielectric layers.

[0268] In some embodiments, the semiconductor structure further includes:

[0269] Multiple oxide pillars, each of the first semiconductor pillars being located on the top surface of a corresponding oxide pillar;

[0270] A sacrificial layer is located in the gaps between the plurality of oxide pillars;

[0271] The dielectric layer also covers the top surface of the sacrificial layer.

[0272] In some embodiments, the semiconductor structure further includes:

[0273] Multiple transistors; the channel structure of each transistor is located on the upper part of the second semiconductor pillar, and the extension direction of the channel structure is perpendicular to the plane containing the first direction and the second direction;

[0274] The transistor includes:

[0275] The gate structure is at least surrounding a portion of the upper sidewall of the second semiconductor pillar, and the source and drain are respectively disposed on the upper part of the second semiconductor pillar and located at both ends of the channel structure.

[0276] In some embodiments, the semiconductor structure further includes: a plurality of third semiconductor pillars and a fifth support layer; wherein,

[0277] Each of the third semiconductor pillars is located on a corresponding first semiconductor pillar, and each of the second semiconductor pillars is located on a corresponding third semiconductor pillar;

[0278] The fifth support layer covers the top sidewall of the third semiconductor pillar;

[0279] The storage structure also surrounds the sidewalls of the plurality of third semiconductor pillars.

[0280] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory comprising: one or more semiconductor structures as described in any of the embodiments described above in this disclosure.

[0281] The semiconductor structure and memory provided in the above embodiments have been described in detail in the method section, and will not be repeated here.

[0282] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0283] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0284] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple first semiconductor pillars, multiple second semiconductor pillars, a first support layer, and a memory structure; wherein, The plurality of first semiconductor pillars are arranged in an array along a first direction and a second direction; both the first direction and the second direction are perpendicular to the extension direction of the first semiconductor pillars, and the first direction and the second direction intersect each other; The first support layer covers the top sidewalls of the plurality of first semiconductor pillars; Each of the second semiconductor pillars is located on a corresponding first semiconductor pillar; the memory structure surrounds at least the sidewalls of the plurality of first semiconductor pillars and the plurality of second semiconductor pillars; The first support layer includes: a plurality of first support columns and a plurality of second support columns; wherein, Each of the first support pillars is located between the tops of two adjacent first semiconductor pillars along the first direction, each of the second support pillars is located between the tops of two adjacent first semiconductor pillars along the second direction, and the first support layer covers a portion of the top sidewall of the first semiconductor pillar.

2. The semiconductor structure according to claim 1, characterized in that, The storage structure includes: Multiple first electrodes; each first electrode covers at least a portion of the sidewall of a first semiconductor pillar that is not covered by the first support layer, and also covers the sidewall of a corresponding second semiconductor pillar; Multiple dielectric layers; each of the dielectric layers covers at least one sidewall of the first electrode, one sidewall of the first support post, and one sidewall of the second support post; The second electrode is located in the gap between the plurality of first semiconductor pillars and the plurality of second semiconductor pillars and covers the plurality of dielectric layers.

3. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure also includes: Multiple oxide pillars, each of the first semiconductor pillars being located on the top surface of a corresponding oxide pillar; A sacrificial layer is located in the gaps between the plurality of oxide pillars; The dielectric layer also covers the top surface of the sacrificial layer.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: Multiple transistors; the channel structure of each transistor is located on the upper part of the second semiconductor pillar, and the extension direction of the channel structure is perpendicular to the plane containing the first direction and the second direction; The transistor includes: The gate structure is at least surrounding a portion of the upper sidewall of the second semiconductor pillar, and the source and drain are respectively disposed on the upper part of the second semiconductor pillar and located at both ends of the channel structure.

5. A memory, characterized in that, include: At least one semiconductor structure as described in any one of claims 1 to 4.

6. A method for fabricating a semiconductor structure, characterized in that, The method includes: A first semiconductor substrate is provided, and a first active layer is formed on the first semiconductor substrate. The first active layer includes a plurality of first semiconductor pillars arranged in an array along a first direction and a second direction. The first direction and the second direction are both perpendicular to the extension direction of the first semiconductor pillars, and the first direction and the second direction intersect each other. A first support layer is formed on top of the first active layer; A second semiconductor substrate is formed on the first active layer and the first support layer; A portion of the second semiconductor substrate is removed to form a second active layer, the second active layer comprising a plurality of second semiconductor pillars; each second semiconductor pillar is located on the top surface of a corresponding first semiconductor pillar; A second support layer is formed on top of the second active layer; A memory structure is formed on the sidewalls of a plurality of first semiconductor pillars and a plurality of second semiconductor pillars; The method further includes: forming a first insulating layer in the gaps between the plurality of first semiconductor pillars before forming the first support layer; Forming the first support layer includes: A portion of the first insulating layer is removed to form a plurality of first grooves; A first support column is formed in the first groove; A portion of the first insulating layer is removed to form a plurality of second grooves; A second support column is formed in the second groove; The first support pillar and the second support pillar together constitute the first support layer. Each first support pillar is located between the tops of two adjacent first semiconductor pillars along the first direction, and each second support pillar is located between the tops of two adjacent first semiconductor pillars along the second direction. The first support layer covers a portion of the top sidewall of the first semiconductor pillar.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, Forming the second semiconductor substrate includes: Remove part of the first support layer and part of the first insulating layer to expose part of the sidewall at the top of the first semiconductor pillar; The second semiconductor substrate is formed on the first semiconductor pillar using an epitaxial growth process.

8. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The method further includes: Before forming the second support layer, a second insulating layer is formed in the gaps between the plurality of second semiconductor pillars; Forming the second support layer includes: Part of the second insulating layer is removed to form multiple third grooves; A third support column is formed in the third groove; A portion of the second insulating layer is removed to form multiple fourth grooves; A fourth support column is formed in the fourth groove; The third support pillar and the fourth support pillar together constitute the second support layer. Each third support pillar is located between the tops of two adjacent second semiconductor pillars along the first direction, and each fourth support pillar is located between the tops of two adjacent second semiconductor pillars along the second direction. The second support layer covers a portion of the top sidewall of the second semiconductor pillar.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, Forming the storage structure includes: Completely remove the remaining first insulating layer and the remaining second insulating layer; The exposed surfaces of the first semiconductor pillar and the second semiconductor pillar are subjected to an oxidation treatment to form a first oxide layer; Sacrificial material is formed in the gaps of the first oxide layer; Remove the second support layer and the first oxide layer to form a first filling region surrounding the first semiconductor pillar and the second semiconductor pillar; A first electrode is formed by filling the first filled region with conductive material. Remove the sacrificial material between the first electrodes to form a second filling region; A dielectric layer and a second electrode are sequentially formed in the second filled region.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, Before removing the second support layer, the first oxide layer on the sidewall at the top of the second semiconductor pillar is removed to form a third filling region, and the sacrificial material is formed in the third filling region to form a third support layer at the top of the second semiconductor pillar.

11. The method for fabricating a semiconductor structure according to claim 9, characterized in that, While forming the first electrode, the conductive material is formed in the third and fourth grooves to form a fourth support layer on top of the second semiconductor pillar.

12. The method for fabricating a semiconductor structure according to claim 9, characterized in that, Forming the first active layer includes: Multiple first trenches spaced apart along a first direction and multiple second trenches spaced apart along a second direction are formed in the first semiconductor substrate; wherein the first trenches and the second trenches divide the first semiconductor substrate into multiple first semiconductor pillars; The bottom of each of the first trenches and / or the second trenches is enlarged such that the formed first semiconductor pillar includes a first portion and a second portion located on the first portion; the maximum diameter of the first portion is smaller than the minimum diameter of the second portion.

13. The method for fabricating a semiconductor structure according to claim 12, characterized in that, While the first oxide layer is being formed, the first portion is completely oxidized into oxide pillars; while sacrificial material is being formed in the gaps of the first oxide layer, the sacrificial material is also being formed in the gaps of the oxide pillars; and when the sacrificial material between the first electrodes is being removed, the sacrificial material located between the oxide pillars is retained to form a sacrificial layer, and the oxide pillars and the sacrificial layer form a bottom support layer.

14. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The method further includes: Remove the fourth support layer and part of the memory structure located on the upper part of the second semiconductor pillar to expose the upper sidewall of the second semiconductor pillar; A gate structure is formed on at least one side of the upper sidewall.

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