Memory device and operating method thereof for performing a multiply-add operation

Abstract

This disclosure provides a memory device and an operational method thereof for performing multiply-accumulate operations. The memory device includes: at least one memory string, multiple data lines, and a serial line. The memory string includes multiple memory cells. Each memory cell has multiple stored values. The multiple data lines are respectively connected to the multiple memory cells to receive multiple data signals. The multiple data signals have multiple input values. When the multiple data signals are input to the multiple memory cells, multiple nodes between the multiple memory cells are at the same voltage level. The serial line is connected to at least one memory string to receive a sensing signal and obtain a measured value. The measured value represents the sum of the products of these input values ​​and these stored values. The multiple data signals and the sensing signal are received at different times.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and its operation method, and more particularly to a memory device and its operation method for performing multiply-accumulate operations. Background Technology

[0002] With the development of artificial intelligence (AI) technology, in-memory computing has been widely applied in various electronic devices. In memory devices that perform multiplication and addition operations, the input voltage of each memory string is affected by the body effect, resulting in a deviation and making it impossible to obtain the correct product and result from the memory string. Therefore, there is an urgent need to improve the problems of body effect and input voltage deviation. Summary of the Invention

[0003] This disclosure provides a memory device and an operating method therefor performing multiply-accumulate operations. When a data signal is input to a memory cell, the nodes between memory cells can maintain the same voltage level. Therefore, the data signal input to the memory cell will not be offset, and the product of the input value and the stored value can be correctly read from the memory string. Furthermore, the product of the neural network operation can be directly passed to the next layer. In this way, the computational efficiency and output capability of the neural network can be significantly improved.

[0004] According to one aspect of this disclosure, a memory device is provided, comprising: at least one memory string, a plurality of data lines, and a serial line. The memory string includes a plurality of memory cells. Each memory cell has a plurality of stored values. The plurality of data lines are respectively connected to the plurality of memory cells to receive a plurality of data signals. The plurality of data signals have a plurality of input values. When the plurality of data signals are input to the plurality of memory cells, the plurality of nodes between the plurality of memory cells are at the same voltage level. The serial line is connected to at least one memory string to receive a sensing signal and obtain a measured value. The measured value represents the sum of the products of the plurality of input values ​​and the plurality of stored values. The plurality of data signals and the sensing signal are received at different times.

[0005] According to another aspect of this disclosure, a method for operating a memory device is provided to perform a multiply-accumulate operation. The method includes: inputting multiple data signals to at least one memory string. The multiple data signals have multiple input values. The memory string includes multiple memory cells. The multiple memory cells include multiple stored values. Multiple nodes between the multiple memory cells are at the same voltage level. Applying a sensing signal to the at least one memory string to obtain a measured value. The measured value represents the sum of a product of the multiple input values ​​and the multiple stored values. The step of inputting the multiple data signals and the step of applying the sensing signal are performed at different times.

[0006] To provide a better understanding of the above and other aspects of this disclosure, the following embodiments are described in detail with reference to the accompanying drawings. Attached Figure Description

[0007] Figure 1A and Figure 1B An example illustrates a memory device and its operation method according to an embodiment;

[0008] Figure 2A and Figure 2B The illustration depicts a memory device and its operation method according to an embodiment;

[0009] Figure 3 A flowchart illustrating an operation method of a memory device according to an embodiment is provided;

[0010] Figure 4A and Figure 4B An illustration is provided according to one embodiment. Figure 1A , 1B Detailed design drawings of the memory device;

[0011] Figure 5A and Figure 5B An illustration is provided according to one embodiment. Figure 2A and 2B Detailed design drawings of the memory device;

[0012] Figure 6A A detailed design diagram of a storage cell according to one embodiment is shown;

[0013] Figure 6B Examples illustrate the changes in the equivalent resistance value of memory cells;

[0014] Figure 7A A detailed design diagram of a storage cell according to one embodiment is shown;

[0015] Figure 7B Examples illustrate the changes in the equivalent resistance value of memory cells;

[0016] Figures 8A-8C Examples illustrate a memory device and its operation method according to another embodiment;

[0017] Figure 9 A schematic diagram of a memory device according to another embodiment is illustrated;

[0018] Explanation of reference numerals in the attached figures:

[0019] 100, 200, 300, 400: Memory devices;

[0020] 430: Voltage modulation circuit;

[0021] C61, C62, C63, C64, C65, C66, C71, C72, C73, C74: Curves;

[0022] CAj, CAj', CAj”: Electrically adjustable elements;

[0023] cp: capacitor;

[0024] Dj: Data signal;

[0025] I1: Sensing signal;

[0026] I2: Measured value;

[0027] Ldj: Data cable;

[0028] Ls: Serial line;

[0029] LY_s, LY_s+1, LY_s+2, LY_s+3: stratum;

[0030] MS1, MS2: storage strings;

[0031] Nk: node;

[0032] Rj: A stored value;

[0033] RTj, RTj': Resistance;

[0034] S110, S120: Steps;

[0035] Sw: Switch signal;

[0036] TM: Endpoint;

[0037] ts1: First transistor;

[0038] ts2: Second transistor;

[0039] UCj, UCj', UCj”: storage units;

[0040] V1: Measured value;

[0041] V2: Sensing signal;

[0042] Xj: Enter a numerical value. Detailed Implementation

[0043] Please refer to Figure 1A and Figure 1B The example illustrates a memory device 100 and its operation method according to an embodiment. The memory device 100 includes at least one memory string MS1, multiple data lines Ldj, and a serial line Ls. The number of the at least one memory string MS1 is one or more. Figure 1A and 1BThe diagram shows only one storage string MS1. Storage string MS1 includes multiple storage units UCj. These multiple storage units UCj are connected in series.

[0044] Each memory cell UCj has a stored value Rj. The stored value Rj is, for example, a resistance value. Figure 1A As shown, data lines Ldj are connected to memory cells UCj to receive data signals Dj with input values ​​Xj. Each input value Xj can be a single value or the sum of a series of values ​​across multiple steps. When the data signal Dj is input to memory cell UCj, the nodes Nk between memory cells UCj are at the same voltage level. For example, the two ends of memory string MS1 can be grounded. Alternatively, in another embodiment, the two ends of memory string MS1 can be applied with the same voltage level. Because the nodes Nk connected to memory cells UCj are at the same voltage level, substrate effects will no longer occur.

[0045] The electrical characteristics of each memory cell UCj change with the stored value Rj and the input value Xj. For example, the equivalent resistance of memory cell UCj is positively correlated with the input value Xj and the stored value Rj. Therefore, the equivalent resistance of memory cell UCj can be expressed as the product of the input value Xj and the stored value Rj.

[0046] Next, as Figure 1B As shown, the serial line Ls connected to the memory string MS1 receives a sensing signal I1 to obtain a measured value V1. The sensing signal I1 is, for example, a constant current flowing through the memory cell UCj, and the measured value V1 is the voltage value that changes with all the equivalent resistance values ​​of the memory cell UCj. That is, the measured value V1 can be used to represent the sum of the product of the input value Xj and the stored value Rj.

[0047] Please refer to Figure 2A and Figure 2B The illustration depicts a memory device 200 and its operation method according to an embodiment. The memory device 200 includes at least one memory string MS2, a data line Ldj, and a serial line Ls. The number of the at least one memory string MS2 is one or more. Figure 2A and Figure 2B The diagram only shows one memory string MS2. Memory string MS2 consists of multiple memory cells UCj. One end of each memory cell UCj is connected to the serial line Ls.

[0048] Each memory cell UCj contains a stored value Rj. The stored value Rj is, for example, a resistance value. Figure 2AAs shown, data lines Ldj are connected to memory cells UCj to receive data signals Dj with input values ​​Xj. When the data signal Dj is input to memory cells UCj, the nodes Nk between memory cells UCj are at the same voltage level. For example, the two ends of memory string MS2 can be grounded. Alternatively, in another embodiment, the two ends of memory string MS2 can be applied with the same voltage level.

[0049] The electrical characteristics of each memory cell UCj change with the stored value Rj and the input value Xj. For example, the equivalent resistance of memory cell UCj is positively correlated with the input value Xj and the stored value Rj. Therefore, the equivalent resistance of memory cell UCj can be expressed as the product of the input value Xj and the stored value Rj.

[0050] Next, as Figure 2B As shown, the serial line Ls connected to the memory string MS2 receives a sensing signal V2 to obtain a measured value I2. The sensing signal V2 is, for example, a constant voltage, and the measured value I2 is the current value that changes with all the equivalent resistance values ​​of the memory cell UCj. That is, the measured value I2 can be used to represent the sum of the product of the input value Xj and the stored value Rj.

[0051] As mentioned above, Figure 1A and Figure 1B The operation method of the memory device 100 and Figure 2A and Figure 2B The operation of the memory device 200 can be performed according to the following flowchart. Please refer to... Figure 3 The diagram illustrates a flowchart of an operation method of a memory device 100, 200 according to an embodiment. In step S110, a data signal Dj having an input value Xj is input to a data line Ldj of at least one memory string MS1, MS2. In step S120, sensing signals I1, V2 are applied to a serial line Ls of the memory strings MS1, MS2 to obtain measurement values ​​V1, I2 representing the sum of the product of the input value Xj and the stored value Rj. Step S110 of inputting the data signal Dj to the data line Ldj and step S120 of applying the sensing signals I1, V2 to the serial line Ls are executed at different times, so that the two ends of the memory strings MS1, MS2 in step S110 can be grounded or have the same voltage level applied. The data signal Dj and the sensing signals I1, V2 are received at different times, for example, the data signal Dj is received by the data line Ldj in step S110 first, and then the sensing signals I1, V2 are received by the serial line Ls in step S120. When the data signal Dj is received by the data line Ldj in step S110, it is not necessary to receive the sensing signals I1 and V2 via the serial line Ls. Therefore, the two ends of the serial line Ls of the storage strings MS1 and MS2 can be grounded or have the same voltage level applied.

[0052] Please refer to Figure 4A and Figure 4B Its illustration is based on an embodiment Figure 1A , Figure 1B Detailed design of the memory device 100. Each memory cell UCj includes a resistor RTj and an electrically adjustable element CAj. The resistor RTj can be a high-impedance metallic material, resistive memory (such as ReRAM, PCRAM), or non-volatile memory (NVM). The resistance value of the resistor RTj represents the stored value Rj. The electrically adjustable element CAj is connected in parallel with the resistor RTj. The electrical characteristics of the electrically adjustable element CAj can be adjusted according to the data signal Dj. For example, the electrical characteristic of the electrically adjustable element CAj is, for example, a resistance value. When the electrical characteristics of the electrically adjustable element CAj change, the equivalent resistance value of the memory cell UCj also changes. When the data signal Dj is input to the memory cell UCj, the nodes Nk between the memory cells UCj are maintained at the same voltage level. Therefore, the data signal Dj input to the storage unit UCj will not be offset, and the product of the input value Xj and the stored value Rj can be correctly read from the storage string MS1.

[0053] Please refer to Figure 5A and Figure 5B Its illustration is based on an embodiment Figure 2A and Figure 2B Detailed design of the memory device 200. Each memory cell UCj includes a resistor RTj and an electrically adjustable element CAj. The resistance value of the resistor RTj represents the stored value Rj. The electrically adjustable element CAj is connected in parallel with the resistor RTj. The electrical characteristics of the electrically adjustable element CAj can be adjusted according to the data signal Dj. For example, the electrical characteristic of the electrically adjustable element CAj is, for example, a resistance value. When the electrical characteristics of the electrically adjustable element CAj change, the equivalent resistance value of the memory cell UCj also changes. When the data signal Dj is input to the memory cell UCj, the nodes Nk between the memory cells UCj are maintained at the same voltage level. Therefore, the data signal Dj input to the memory cell UCj will not be offset, and the sum of the product of the input value Xj and the stored value Rj can be correctly read from the memory string MS2.

[0054] Please refer to Figure 6AThe diagram illustrates a detailed design of a memory cell UCj' according to one embodiment. The memory cell UCj' includes a resistor RTj' and an electrically adjustable element CAj'. The electrically adjustable element CAj' is, for example, an electrochemical random-access memory (ECRAM), a resistive memory, or a ReRAM. The resistance of a channel in the ECRAM can be adjusted by ion exchange at the interface between the channel and the electrolyte when an electric field is applied. Therefore, the resistance value of the electrically adjustable element CAj' can be adjusted according to the data signal Dj. The memory cell UCj' can use... Figure 4A and Figure 4B memory device 100 or Figure 5A and Figure 5B Memory device 200.

[0055] Please refer to Figure 6B The example illustrates the change in the equivalent resistance value of the memory cell UCj'. Curves C61 to C66 represent the measured results of resistor RTj' at different resistance units of 0.5, 1, 2, 4, 8, and 16 units. As shown in curve C66, the equivalent resistance value of the memory cell UCj' is positively correlated with the resistance value of the electrically adjustable element CAj'. As shown in curves C61 to C66, the equivalent resistance value of the memory cell UCj' is also positively correlated with the resistance value of resistor RTj'. In other words, the equivalent resistance value of the memory cell UCj' is positively correlated with both the input value Xj and the stored value Rj. Therefore, the equivalent resistance value of the memory cell UCj' can be expressed as the product of the input value Xj and the stored value Rj.

[0056] Please refer to Figure 7A The diagram illustrates a detailed design of a memory cell UCj” according to an embodiment. The memory cell UCj” includes a resistor RTj” and an electrically adjustable element CAj”. The electrically adjustable element CAj” includes a first transistor ts1, a capacitor cp (which may be a series capacitor or a parasitic capacitance of the transistor), and a second transistor ts2. The first transistor ts1 is used to receive a data signal Dj. The capacitor cp is connected to the first transistor ts1. The second transistor ts2 is connected to the capacitor cp. When the first transistor ts1 is turned on by a switching signal Sw, the data signal Dj can be stored in the capacitor cp. Therefore, the resistance value of the electrically adjustable element CAj” can be adjusted according to the data signal Dj. The memory cell UCj” can be used... Figure 4A and Figure 4B memory device 100 or Figure 5A and Figure 5B Memory device 200.

[0057] Please refer to Figure 7BThe example illustrates the change in the equivalent resistance value of the memory cell UCj". Curves C71 to C74 show the measurement results of the resistance value of resistor RTj" at different units of 1, 2, 3, and 4. As shown in curve C74, the equivalent resistance value of the memory cell UCj" is positively correlated with the voltage input to the second transistor ts2. The voltage input to the second transistor ts2 is positively correlated with the input value Xj. As shown in curves C71 to C74, the equivalent resistance value of the memory cell UCj" is also positively correlated with the resistance value of resistor RTj". In other words, the equivalent resistance value of the memory cell UCj" is positively correlated with both the input value Xj and the stored value Rj. Therefore, the equivalent resistance value of the memory cell UCj" can be expressed as the product of the input value Xj and the stored value Rj.

[0058] Please refer to Figures 8A-8C Examples illustrate a memory device 300 and its operation method according to another embodiment. For example... Figure 8A As shown, the memory device 300 includes one or more memory strings MS1. The endpoint TM of memory string MS1 in level LY_s is connected to a memory cell UCj of memory string MS1 in level LY_s+1. The stored value Rj and the input value Xj are stored in memory string MS1 in level LY_s. A sensing signal I1 is applied to memory string MS1 in level LY_s to obtain a measurement value V1. The measurement value V1 is transmitted to memory string MS1 in level LY_s+1 and serves as a data signal Dj.

[0059] When performing step S120 of applying sensing signal I1 to storage string MS1 of layer LY_s, step S110 of inputting data signal Dj can be performed on storage string MS1 of layer LY_s+1 at the same time.

[0060] Next, as Figure 8B As shown, when step S120 of applying sensing signal I1 is performed on storage string MS1 of layer LY_s+1, step S110 of inputting data signal Dj can be performed on storage string MS1 of layer LY_s+2 at the same time.

[0061] Then, as Figure 8C As shown, when step S120 of applying the sensing signal I1 is performed on the storage string MS1 of layer LY_s+2, step S110 of inputting the data signal Dj can be performed on the storage string MS1 of layer LY_s+3 at the same time. That is, steps S110 and S120 can be performed alternately in each layer.

[0062] In addition, please refer to Figure 9The diagram illustrates a memory device 400 according to another embodiment. The memory device 400 also includes a voltage modulation circuit 430. After obtaining a measured value V1, the measured value V1 is input to the voltage modulation circuit 430. The voltage modulation circuit 430 adjusts the measured value V1 to meet the requirements of the memory cell UCj of level LY_s+1. The voltage modulation circuit 430 may employ mathematical calculation procedures required for neural network operations for modulation.

[0063] The measured value V1 is passed to the storage string MS1 of layer LY_s+1 and used as a data signal Dj. In other words, without using an analog-to-digital converter, the product and result of the neural network operation can be directly passed to the next layer. This significantly improves the computational efficiency and output capacity of the neural network.

[0064] According to the above embodiment, when the data signal Dj is input to the storage unit UCj, the nodes Nk between the storage units UCj can maintain the same voltage level. Therefore, the data signal Dj input to the storage unit UCj will not be offset, and the product sum of the input value Xj and the stored value Rj can be correctly read from the storage strings MS1 and MS2. In addition, the product sum result of the neural network operation can be directly passed to the next layer. In this way, the computational efficiency and output capability of the neural network can be greatly improved.

[0065] In summary, although this disclosure has been presented above with reference to embodiments, it is not intended to limit the scope of this disclosure. Those skilled in the art to which this disclosure pertains can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the appended claims.

Claims

1. A memory device, comprising: At least one storage string includes a plurality of storage cells connected in series, the plurality of storage cells having a plurality of stored values; Multiple data lines are connected to the multiple storage units respectively to receive multiple data signals. The multiple data signals have multiple input values. When the multiple data signals are input to the multiple storage units, the multiple nodes between the multiple storage units are at the same voltage level. as well as A serial line is connected to the at least one storage string to receive a sensing signal and obtain a measurement value that represents the sum of a product of the plurality of input values ​​and the plurality of stored values; The multiple data signals and the sensing signal are received at different times.

2. The memory device according to claim 1, wherein the plurality of memory cells are connected in series, and when the plurality of memory cells receive the plurality of data signals, both ends of the at least one memory string are grounded.

3. The memory device according to claim 1, wherein each memory cell comprises: A resistor, the resistance value of which represents a stored value; and An adjustable element with an electrical characteristic is connected in parallel with each resistor, and an electrical characteristic of each adjustable element is adjusted according to each data signal.

4. The memory device of claim 3, wherein each of the electrically adjustable elements comprises: A first transistor, each of the first transistors being used to receive each of the data signals; A capacitor, each of which is connected to each of the first transistors; as well as A second transistor, each of which is connected to each of the capacitors.

5. The memory device according to claim 1, wherein the number of the at least one memory string is multiple, and one end of one memory string is connected to one memory cell of one of the multiple memory strings of another memory string to input the product and result.

6. The memory device of claim 1, wherein one end of each memory cell is connected to the serial line and the other end of each memory cell is grounded.

7. A method of operating a memory device to perform a multiply-accumulate operation, comprising: Multiple data signals are input to at least one storage string, the multiple data signals having multiple input values, the at least one storage string comprising multiple storage cells connected in series, the multiple storage cells comprising multiple stored values, and multiple nodes between the multiple storage cells being at the same voltage level; A sensing signal is applied to the at least one storage string to obtain a measurement value that represents the sum of a product of the plurality of input values ​​and the plurality of stored values; The steps of inputting the multiple data signals and applying the sensing signal are performed at different times.

8. The method of operating the memory device according to claim 7, wherein the plurality of memory cells are connected in series, and wherein, in the step of inputting the plurality of data signals, the two ends of the at least one memory string are grounded.

9. The method of operating the memory device according to claim 7, wherein the number of the at least one memory string is multiple, and one end of one memory string is connected to one end of another memory string of the multiple memory strings to input the product and result.

10. The method of operating the memory device according to claim 7, wherein one end of each memory cell is connected to a serial line, and the other end of each memory cell is grounded.

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