A synchronization code type adaptation method and device, electronic equipment and storage medium

Abstract

The application discloses a synchronization code type adaptation method and device, electronic equipment and a storage medium. The method comprises the following steps: periodically acquiring front transmission interface data from a target register; determining the data type of the front transmission interface data according to a judgment field; when the front transmission interface data is first type data, based on the field type of a synchronization header, a preset conversion rule is combined to assign a value to an empty control field, and then the first type data is converted into second type data; and based on the control code and data code of the second type data, a data framing operation is performed to complete the synchronization code type adaptation. The application is aimed at the differences existing in different instantiation SERDES IPs. The front transmission interface data is converted into data with unified format at the data level by combining the preset conversion rule with the control field which is preset to be empty, so that the synchronization code type automatic adaptation scheme for the differentiated IP is realized, subsequent development and maintenance work is facilitated, the product development cycle is shortened, and the application can be widely used in the technical field of data processing.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a synchronization code adaptation method, apparatus, electronic device, and storage medium. Background Technology

[0002] As 5G indoor and outdoor coverage continues to improve, weak indoor 5G signal coverage in rural hotspots and low-value urban areas has become a key focus for operators. However, deploying traditional macro base stations in these areas requires rebuilding equipment rooms and transmission networks, which is costly and difficult. Therefore, it is urgent for operators to address the issue of improving 5G signal coverage in non-hotspot areas using low-cost outdoor base stations.

[0003] However, with operators' strong demand for cost reduction in 5G products, actual project iterations will select lower-specification chips from the same or different manufacturers (i.e., different manufacturers) while ensuring functionality and performance. Therefore, during FPGA development, the SERDES IP instantiated by the FPGA will differ, especially the external user-side interface. The synchronization code adaptation method of SERDES data needs to be modified and adjusted for different manufacturers' SERDES IPs, resulting in high development costs, long development cycles, and poor subsequent maintainability. Summary of the Invention

[0004] This invention aims to at least partially solve one of the technical problems in related technologies. To this end, this invention proposes a synchronization code adaptation method, apparatus, electronic device, and storage medium, capable of efficiently performing synchronization code adaptation.

[0005] On one hand, embodiments of the present invention provide a synchronization code pattern adaptation method, including: The system periodically retrieves fronthaul interface data from the target register; the target register includes different types of fronthaul interface IP selection registers; the fronthaul interface data packets contain discrimination fields. The data type of the fronthaul interface data is determined based on the discrimination field; the data types include a first type of data and a second type of data; the first type of data includes a synchronization header, synchronization data, and a control field; the second type of data includes a control code, a data code, and a control field; the control field of the first type of data is preset to empty; The current data transmitted through the interface is of type 1. Based on the field type of the synchronization header, and combined with the preset conversion rules, values ​​are assigned to empty control fields, thereby converting type 1 data into type 2 data. Synchronization code adaptation is achieved through data framing operations based on the control code and data code of the second type of data.

[0006] Optionally, the method further includes: Obtain the configuration file for the target FPGA; Based on the configuration file, different types of serial communication device IPs are instantiated on the target FPGA, and the clock frequency is configured through the internal phase-locked loop, thereby opening up the corresponding type of fronthaul interface IP selection register.

[0007] Optionally, the data types of the second type of data include frame start code, frame end code, and frame data stream; the field types include first field type and second field type; based on the field types of the synchronization header, and combined with preset conversion rules, empty control fields are assigned values, thereby converting the first type of data into the second type of data, including: When the field type of the synchronization header is the first field type, the empty control field in the first type data is assigned the first control field, and the synchronization header is converted into the control code corresponding to the frame data stream; When the field type of the synchronization header is the second field type, the empty control fields in the first type of data are assigned the second control fields; then, based on the field type of the synchronization data, the first type of data is converted into a frame start code or a frame end code.

[0008] Optionally, the field types include a first field type and a second field type; based on the field types of the synchronization data, the first type of data is converted into a frame start code or a frame end code, including: When the field type of the synchronization data is the first field type, the synchronization header of the second field type in the first type of data and the synchronization data of the first field type are sequentially converted into the control code and data code corresponding to the frame start code; When the field type of the synchronization data is the second field type, the synchronization header of the second field type in the first type of data and the synchronization data of the second field type are sequentially converted into the control code and data code corresponding to the frame end code.

[0009] Optionally, the discrimination field includes a first discrimination field corresponding to the first type of data and a second discrimination field corresponding to the second type of data; after the step of converting the first type of data to the second type of data, the method further includes: Convert the first discriminant field in the first type of data into the second discriminant field.

[0010] Optionally, based on the control code and data code of the second type of data, synchronization code adaptation is completed through data framing operations, including: The first frame of data in the second type of data is used as the target frame data. The data type of the target frame data is determined according to the control code of the target frame data. The data types of the target frame data include frame start code, frame end code, and frame data stream. Based on the data type of the target frame data, the data framing operation is performed by matching the data code with the control code, thereby completing the synchronization code type adaptation.

[0011] Optionally, the data code includes a first data code corresponding to the start of the frame code, a second data code corresponding to the end of the frame code, and a third data code corresponding to the frame data code; based on the data type of the target frame data, data framing is performed by matching the data code with the control code, including: When the data type is frame start code, determine whether the data code matching the control code is the first data code; if the data code is the first data code, complete the data framing operation; if the data code is not the first data code, determine whether the data code matching the control code is the second data code; if the data code is the second data code, complete the data framing operation; otherwise, use the next frame of the target frame data as the target frame data, and then return to the step of determining the data type of the target frame data based on the control code of the target frame data, until the data framing operation is completed. When the data type is frame end code, determine whether the data code matching the control code is the second data code; if the data code is the second data code, complete the data framing operation; otherwise, use the next frame data of the target frame data as the target frame data, and then return to the step of determining the data type of the target frame data based on the control code of the target frame data, until the data framing operation is completed.

[0012] On the other hand, embodiments of the present invention provide a synchronization code pattern adapter, comprising: The first module is used to periodically obtain fronthaul interface data from the target register; the target register includes different types of fronthaul interface IP selection registers; the fronthaul interface data packets contain discrimination fields; The second module is used to determine the data type of the fronthaul interface data based on the discrimination field; wherein, the data type includes a first type of data and a second type of data; the first type of data includes a synchronization header, synchronization data, and a control field; the second type of data includes a control code, a data code, and a control field; the control field of the first type of data is preset to empty; The third module is used when the current transmission interface data is of the first type. Based on the field type of the synchronization header and combined with the preset conversion rules, it assigns values ​​to the empty control fields, thereby converting the first type data into the second type data. The fourth module is used to complete the synchronization code adaptation through data framing operations based on the control code and data code of the second type of data.

[0013] Optionally, the device further includes: The fifth module is used to obtain the configuration file of the target FPGA; The sixth module is used to instantiate different types of serial communication device IPs on the target FPGA based on the configuration file, configure the clock frequency through the internal phase-locked loop, and then open the corresponding type of fronthaul interface IP selection register.

[0014] Optionally, the discrimination field includes a first discrimination field corresponding to the first type of data and a second discrimination field corresponding to the second type of data; after executing the operation of the third module, the device further includes: The seventh module is used to convert the first discriminant field in the first type of data into the second discriminant field.

[0015] On the other hand, embodiments of the present invention provide an electronic device, including: a processor and a memory; the memory is used to store a program; the processor executes the program to implement the above-described synchronization code adaptation method.

[0016] On the other hand, embodiments of the present invention provide a computer storage medium storing a processor-executable program, which, when executed by a processor, is used to implement the above-described synchronization code pattern adaptation method.

[0017] This invention embodiment acquires fronthaul interface data periodically from a target register. The target register includes different types of fronthaul interface IP selection registers. The fronthaul interface data packet contains a discrimination field. The data type of the fronthaul interface data is determined based on the discrimination field. The data types include a first type of data and a second type of data. The first type of data includes a synchronization header, synchronization data, and a control field. The second type of data includes a control code, a data code, and a control field. The control field of the first type of data is preset to empty. When the fronthaul interface data is of the first type, based on the field type of the synchronization header and combined with preset conversion rules, the empty control field is assigned a value, thereby converting the first type of data into the second type of data. Based on the control code and data code of the second type of data, synchronization code type adaptation is completed through data framing operations. This invention embodiment addresses the differences in fronthaul interface data when different SERDES IPs are instantiated. By combining the preset empty control field with preset conversion rules, the fronthaul interface data is converted into data with a unified data format at the data level, thereby achieving an automatic synchronization code type adaptation scheme for differentiated IPs. This facilitates subsequent development and maintenance work and shortens the product development cycle. Attached Figure Description

[0018] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.

[0019] Figure 1 A schematic diagram of an implementation environment for synchronization code pattern adaptation provided in an embodiment of the present invention; Figure 2 A flowchart illustrating a synchronization code pattern adaptation method provided in an embodiment of the present invention; Figure 3This is a schematic diagram showing that the SERDES IP user-side interface provided in this embodiment of the invention is output by the PCS layer; Figure 4 This is a schematic diagram showing that the SERDES IP user-side interface provided in this embodiment of the invention is output by the XGMII interface; Figure 5 A schematic diagram of the system structure of the customized outdoor station provided in an embodiment of the present invention; Figure 6 A schematic diagram of clock conversion based on FPGA provided in an embodiment of the present invention; Figure 7 This is a flowchart illustrating the process of determining the high-speed interface IP interface type provided in an embodiment of the present invention. Figure 8 A schematic diagram illustrating the principle of the frame start code conversion process provided in an embodiment of the present invention; Figure 9 A schematic diagram illustrating the principle of the frame end code conversion process provided in an embodiment of the present invention; Figure 10 A schematic diagram illustrating the principle of the user data conversion process provided in an embodiment of the present invention; Figure 11 A flowchart of the automatic adaptation design of synchronization code patterns for different high-speed interfaces provided in this embodiment of the invention; Figure 12 This is a flowchart illustrating the specific implementation of automatic synchronization code pattern adaptation for customized outdoor stations, as provided in this embodiment of the invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0021] It should be noted that although functional modules are divided in the system diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the system or the order in the flowchart. The terms "first / S100," "second / S200," etc., in the specification, claims, and the aforementioned figures are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] It is understood that the synchronization code adaptation method provided in this embodiment of the invention can be applied to any computer device with data processing and computing capabilities, and this computer device can be various types of terminals or servers. When the computer device in the embodiment is a server, the server is an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. Optionally, the terminal can be a smartphone, tablet computer, laptop computer, or desktop computer, but it is not limited to these.

[0024] like Figure 1 The diagram shown is a schematic representation of an implementation environment provided by an embodiment of the invention. (Refer to...) Figure 1 The implementation environment includes at least one terminal 102 and a server 101. The terminal 102 and the server 101 can be connected via a network, either wirelessly or via a wired connection, to complete data transmission and exchange.

[0025] Server 101 can be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms.

[0026] Additionally, server 101 can also be a node server in a blockchain network. Blockchain is a novel application model of computer technologies such as distributed data storage, peer-to-peer transmission, consensus mechanisms, and encryption algorithms.

[0027] Terminal 102 can be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, etc., but is not limited to these. Terminal 102 can also be a transmitter or receiver of a customized outdoor station (such as a 5G customized outdoor station). Terminal 102 and server 101 can be directly or indirectly connected through wired or wireless communication methods, and this embodiment of the invention does not impose any limitations.

[0028] Exemplary based on Figure 1 The implementation environment shown in this embodiment of the invention provides a synchronization code pattern adaptation method. The following description uses the application of this synchronization code pattern adaptation method in terminal 102 as an example. It can be understood that this synchronization code pattern adaptation method can also be applied in server 101 to call relevant data logic so that terminal 102 can implement the following synchronization code pattern adaptation method.

[0029] Reference Figure 2 , Figure 2 This is a flowchart illustrating a synchronization code pattern adaptation method applied to a server, provided in an embodiment of the present invention. The executing entity of this synchronization code pattern adaptation method can be any of the aforementioned computer devices (including servers or terminals). (Refer to...) Figure 2 The method includes the following steps: S100: Periodically acquire forward interface data from the target register; The target register includes different types of fronthaul interface IP selection registers; the fronthaul interface data packets contain discrimination fields. It should be noted that in some embodiments, the method may further include: obtaining the configuration file of the target FPGA; based on the configuration file, instantiating different types of serial communication device IPs through the target FPGA, configuring the clock frequency through the internal phase-locked loop, and then opening the corresponding type of fronthaul interface IP selection register.

[0030] S200. Determine the data type of the fronthaul interface data based on the discrimination field; The data types include a first type of data and a second type of data; the first type of data includes a synchronization header, synchronization data, and a control field; the second type of data includes a control code, a data code, and a control field; the control field of the first type of data is preset to empty. S300: The current data transmitted through the interface is of type 1. Based on the field type of the synchronization header, and combined with the preset conversion rules, the empty control field is assigned a value, thereby converting the type 1 data into type 2 data. It should be noted that the data types of the second type of data include frame start code, frame end code, and frame data stream; the field types include first field type and second field type; in some embodiments, based on the field type of the synchronization header, and combined with preset conversion rules, empty control fields are assigned values ​​to convert the first type of data into the second type of data, which may include: when the field type of the synchronization header is the first field type, the empty control fields in the first type of data are assigned the value of the first control field, and the synchronization header is converted into the control code corresponding to the frame data stream; when the field type of the synchronization header is the second field type, the empty control fields in the first type of data are assigned the value of the second control field; and then, based on the field type of the synchronization data, the first type of data is converted into a frame start code or a frame end code.

[0031] In some embodiments, the field types include a first field type and a second field type; based on the field type of the synchronization data, converting the first type of data into a frame start code or a frame end code may include: when the field type of the synchronization data is the first field type, sequentially converting the synchronization header of the second field type and the synchronization data of the first field type in the first type of data into the control code and data code corresponding to the frame start code; when the field type of the synchronization data is the second field type, sequentially converting the synchronization header of the second field type and the synchronization data of the second field type in the first type of data into the control code and data code corresponding to the frame end code.

[0032] In some embodiments, the discrimination field includes a first discrimination field corresponding to the first type of data and a second discrimination field corresponding to the second type of data; after the step of converting the first type of data into the second type of data, the method may further include: converting the first discrimination field in the first type of data into the second discrimination field.

[0033] S400, based on the control code and data code of the second type of data, completes the synchronization code adaptation through data framing operation.

[0034] It should be noted that in some embodiments, step S400 may include: taking the first frame data in the second type of data as the target frame data, determining the data type of the target frame data according to the control code of the target frame data; wherein, the data type of the target frame data includes frame start code, frame end code and frame data stream; based on the data type of the target frame data, performing data framing operation through the data code matched by the control code, thereby completing the synchronization code type adaptation.

[0035] In some embodiments, the data code includes a first data code corresponding to the frame start code, a second data code corresponding to the frame end code, and a third data code corresponding to the frame data code. Based on the data type of the target frame data, the data framing operation is performed by matching the data code with the control code. This can include: when the data type is the frame start code, determining whether the data code matching the control code is the first data code; if the data code is the first data code, completing the data framing operation; if the data code is not the first data code, determining whether the data code matching the control code is the second data code; if the data code is the second data code, completing the data framing operation; otherwise, using the next frame data of the target frame data as the target frame data, and then returning to the step of determining the data type of the target frame data based on the control code of the target frame data, until the data framing operation is completed; when the data type is the frame end code, determining whether the data code matching the control code is the second data code; if the data code is the second data code, completing the data framing operation; otherwise, using the next frame data of the target frame data as the target frame data, and then returning to the step of determining the data type of the target frame data based on the control code of the target frame data, until the data framing operation is completed.

[0036] To explain in detail the principle of the technical solution of the present invention, the overall process of the present invention will be described below in conjunction with some specific application scenarios. It is easy to understand that the following is an explanation of the technical principle of the present invention and should not be regarded as a limitation of the present invention.

[0037] To facilitate understanding of the technical solutions, the technical terms that may be involved in the embodiments of this invention will first be explained: SERDES (SERializer / DESerializer): A mainstream time-division multiplexing (TDM) and point-to-point (P2P) serial communication technology. At the transmitting end, multiple low-speed parallel signals are converted into high-speed serial signals, transmitted through a medium (optical fiber or copper wire), and finally converted back into low-speed parallel signals at the receiving end.

[0038] XGMII (10 Gigabit Media Independent Interface): is an Ethernet industry standard defined by IEEE-802.3, which includes a data interface and a management interface between the MAC and PHY.

[0039] First, it should be noted that the method of this invention can be applied to the transmitting or receiving end of a 5G customized outdoor station. A 5G customized outdoor station is a device that implements NR (New Radio, also known as 5G wireless network) wireless access functionality. It adopts an integrated design combining an indoor baseband unit (BBU) and a radio remote unit (RRU), supports inter-site cascading, and supports independent RRU remote deployment. It can access the 5G core network through a passive optical network (PON) or a smart transport network (STN) to provide NR services to users. The system adopts a flat network architecture, eliminating the need to rebuild equipment rooms and transmission networks, making it suitable for application areas with weak signal coverage, such as rural hotspots and low-value indoor scenarios in urban areas. Compared to deploying traditional macro base stations in rural hotspots and low-value indoor scenarios in urban areas, it has advantages such as rapid network construction and low maintenance costs.

[0040] A complete customized outdoor station consists of two parts: an integrated unit and a remote RRU. The integrated unit, as the main core baseband unit of the customized outdoor station, is primarily responsible for baseband signal processing functions (encoding, multiplexing, modulation, and spread spectrum, etc.) of the Uu interface. It also performs signaling processing, local and remote operation and maintenance functions, and monitors the station system's operating status and reports alarm information. The integrated unit itself has RF signal processing capabilities, capable of completing the entire digital-to-analog signal processing flow; the system architecture is equivalent to an integrated BBU and RRU.

[0041] The structure of a remote RRU is similar to that of an indoor distributed antenna system (DAS) RRU. It primarily completes the entire digital-to-analog signal processing flow, enabling radio frequency transceiver functionality. While the output power of an indoor DAS RRU is in the milliwatt range, the remote RRU increases its output power to the watt range, effectively improving its coverage area and meeting outdoor coverage requirements.

[0042] The integrated unit connects to the remote RRU via a fronthaul interface. Depending on the baseband function split point, the fronthaul interface is available in Option 7-2, Option 8, and Option 6. To reduce the cost of the remote RRU, a fronthaul interface based on Option 8 splitting is used. Framing can be done using a custom CPRI method or the standard CPRI method. At an online rate of 10137.6Mbps, the bandwidth supports up to NR 4T4R and LTE 2T2R, with further adjustments made to meet the product's low-specification, low-cost requirements.

[0043] CPRI data from outdoor customized base stations is processed by the intermediate frequency processing unit and then sent to SERDES. The PCS+PMA layer of SERDES is implemented based on FPGA-instantiated SERDES IP. Currently, different vendors' instantiated SERDES IPs have different methods for adapting synchronization codes for fronthaul data, such as... Figure 3 As shown, the Tx-side data plane of Manufacturer A's IP user-side interface uses PCS layer 64b / 66b encoding. PCS layer 64b / 66b encoding encodes 64 bits of "data or control information" into 66-bit blocks for transmission. Of these 66 bits, the first 2 bits are the sync header, with two values: "01" and "10". "01" indicates that the following 64 bits are all data; "10" indicates that the following 64 bits are a mixture of data and control information. The 8 bits immediately following the sync header are the block type field, and the remaining 56 bits are control information, data, or a mixture of both. The frame end code and start code in the sync control word correspond to Table 1 (frame data format of PCS layer 64b / 66b encoding). The Rx side is the opposite. Manufacturer B's IP user-side interface Tx-side data plane uses XGMII format, as shown... Figure 4 As shown, the xgmii interface data plane, as the input to the PCS layer 64b / 66b encoding, consists of two parts: xgmii_c[7:0] and xgmii_d[63:0]. xgmii_c is the control code, and xgmii_d is the data code. Each bit of xgmii_c corresponds sequentially to 8 bytes of xgmii_d from the least significant bit to the most significant bit. The frame end code and start code in the synchronization control word correspond to Table 2 (synchronization control word of the XGMII interface), and the opposite is true on the Rx side.

[0044] Table 1

[0045] Table 2

[0046] With operators' strong demand for cost reduction in 5G products, actual project iterations will select lower-specification chips from the same or different manufacturers (i.e., different manufacturers) while ensuring functionality and performance. Therefore, during FPGA development, the instantiated SerDes IPs will differ, especially in external user-side interfaces, such as... Figure 5 As shown, the synchronization code adaptation method for SerDes data needs to be modified and adjusted for different manufacturers' SerDes IPs, resulting in high development costs, long development cycles, and poor maintainability. Therefore, it is necessary to consider implementing automatic synchronization code adaptation when instantiating SerDes IPs to adapt to the differentiated IPs of different manufacturers and chip specifications.

[0047] In light of this, currently, to reduce costs and increase efficiency, operators use chips from different manufacturers and with different specifications for outdoor base station systems. These chips also have different fronthaul interface types, leading to inconsistencies in FPGA instantiation of SERDES IP. The synchronization code type used to synchronize fronthaul interface data needs to be modified for specific manufacturers' data interfaces, resulting in a lack of flexibility during product iteration and upgrades, long development cycles, high development costs, and poor maintainability. Therefore, the purpose of this invention is to address different data interface formats by proposing an interface discrimination and conversion mechanism that unifies the user-side interface of SERDES IP from PCS to the XGMII interface. When using synchronization codes for data frame header synchronization at the receiving end, the mechanism automatically changes the synchronization code format to complete the initial framing of the fronthaul interface data, thereby achieving an automatic synchronization code adaptation scheme for differentiated IPs. This facilitates subsequent development and maintenance work and shortens the product development cycle.

[0048] In some specific embodiments, the technical principles of the present invention are as follows: 1. Clock conversion design scheme based on FPGA: In practical engineering applications, the data from the PMA side reaches the PCS layer after processing, with a data rate of 10137.6 Mbit / s. Since the PCS layer uses 64b / 66b encoding to encode 64-bit "data or control information" into 66-bit blocks for transmission, the actual effective payload is 9830.4 Mbit / s. Because the actual effective data bit width differs before and after 64b / 66b encoding, the data processing clock used by the FPGA when instantiating the SERDES IP also differs for 64-bit and 66-bit data. When using 64-bit transmission, the FPGA processing clock is 153.6 MHz, and when using 66-bit transmission, the FPGA processing clock is 158.4 MHz.

[0049] In PCIe (Peripheral Component Interconnect Express), both PMA and PCS are components of the Physical Layer Sublayer.

[0050] PMA stands for Physical Medium Attachment, which manages the signal characteristics of the physical layers, including electrical, clock, and timing. PMA also handles timing control and signal reconstruction required for high-speed data transmission, ensuring signals are correctly transmitted to the remote receiver. PMA receives and transmits high-speed serial data on serial channels, performs serialization / deserialization, clock data recovery, and analog front-end functions such as continuous-time linear equalizer (CTLE), decision feedback equalizer (DFE), and transmission equalization.

[0051] PCS stands for Physical Coding Sublayer. It handles the encoding and decoding of data signals, as well as error detection and correction. PCS is responsible for converting logical data streams into physical layer digital signals and ensuring the reliability and correctness of data transmission through techniques such as 8b / 10b or 128b / 130b encoding. PCS acts as the interface between PMA and PCIe controllers, performing functions such as data encoding and decoding, scrambling and descrambling, and block synchronization.

[0052] PCS and PMA work together to enable PCIe to achieve high-speed and reliable data transmission.

[0053] Therefore, in some specific embodiments, for the differential clock processing before and after 64b / 66b encoding of SERDES IP, this embodiment of the invention also proposes a clock conversion design scheme based on FPGA implementation, as follows: To accommodate data with different bit widths, the phase-locked loop (PLL) needs to provide two clock frequencies: 153.6MHz and 158.4MHz. These two clocks must be from the same source. The CPU can configure the 153.6MHz clock frequency through the configuration interface of the external PLL. Then, the PLL inside the FPGA divides the frequency to 153.6MHz and 158.4MHz according to different clock requirements, providing the corresponding processing clock for SERDES logic processing.

[0054] like Figure 6 As shown, the SERDES IP corresponding to the FPGA requires an external 153.6MHz reference clock. This clock signal enters the FPGA's internal phase-locked loop (PLL) through the clock pin, and then two PLL IPs are instantiated. Each PLL outputs a clock frequency of 153.6MHz and 158.4MHz respectively. When SERDES uses 64b / 66b encoding, corresponding to 64-bit data, the SERDES data processing clock is 153.6MHz, resulting in a payload of 9830.4Mbit / s. Then, "10" is added to the start and stop codes, and "01" is added to the data code. A timeout is applied to the data, and it is encoded into a 66-bit block using a 158.4MHz clock domain for transmission, resulting in an actual output data rate of 10137.6Mbit / s.

[0055] 2. High-speed interface discrimination and conversion mechanism based on FPGA: Forward data transmission in a base station system requires transmission to the peer via SERDES. For chips from different manufacturers and with different specifications, the SERDES IP instantiated on the FPGA uses different formats of synchronization control words to synchronize the forward transmission interface data. This invention proposes a custom high-speed interface discrimination and conversion mechanism based on FPGA, opening up IP selection functionality and defining discrimination and control fields for the PCS and XGMII interfaces. The specific solution is as follows: For SERDES IPs from different manufacturers, the FPGA side enables a SERDES IP selection function from different manufacturers. Depending on the type of SERDES IP, function registers or macro definitions can be used. The function registers are controlled by the MCU microprocessor, which issues read / write commands via the SPI interface to control the FPGA-side registers, enabling the selection of SERDES IPs from different manufacturers. This allows for the selection of more than two SERDES IPs. If macro definitions are used, conditional instructions are used to distinguish between SERDES IPs from different manufacturers.

[0056] like Figure 7 As shown, in this embodiment of the invention, the external user-side fronthaul interface data is uniformly defined as 72-bit data, including an 8-bit control code (serdes_c) and a 64-bit data code (serdes_d). The FPGA detects the user-side fronthaul interface data in each clock cycle. If a high level is detected in the most significant bit of the fronthaul interface data, the system determines that the SERDESIP is an XGMII interface, and the actual valid control code is the 8-bit XGMII control code (xgmii_c). Otherwise, it is PCS layer data, and the actual valid control code is the 2-bit PCS control code (sync header), thereby completing the interface type identification.

[0057] For SERDES IP user-side interface data at the PCS layer, this embodiment defines a control field to uniformly convert the user-side data plane interface into the XGMII interface. Table 3 shows the correspondence between the XGMII interface, PCS layer control code, and user data before and after conversion. The FPGA detects the 2-bit PCS control code (sync header) of the user-side fronthaul interface data in each clock cycle. If the sync header is binary code "10", the control field level is pulled high. Then, the corresponding PCS layer data code (sync data) is determined. Based on the correspondence in Table 3, the FPGA converts the PCS layer data into the frame start code or frame end code of the XGMII interface. The conversion process is as follows: Figure 8 , Figure 9As shown. If the sync header is binary code "01", it is a user data field. The control field level is set low, and the control code of the XGMII interface is set to 8'h00. The user data of the PCS layer is consistent with the user data of the XGMII interface. The conversion process is as follows. Figure 10 As shown.

[0058] Table 3

[0059] 3. Automatic synchronization code pattern adaptation design scheme for different high-speed interfaces: In this embodiment of the invention, the integrated unit of the customized outdoor station serves as the main core baseband unit. It needs to connect to a remote RRU via a high-speed interface to achieve coverage in multiple areas. The fronthaul interface line rate between the integrated unit and the remote RRU is fixed at 10137.6 Mbps, with 66 / 64B encoding, and the effective payload data rate is 9830.4 Mbps. Therefore, this invention, in conjunction with differentiated SERDES IP from different manufacturers, proposes an automatic synchronization code pattern adaptation design scheme to accommodate differentiated high-speed interfaces.

[0060] Customized outdoor station system architecture, such as Figure 5 As shown, the remote RRU is connected to the integrated machine via fiber optic cable. Specific adaptation design schemes are as follows... Figure 11 As shown, the transmitting end encapsulates user-side data into frames according to the CPRI protocol. Based on the actual FPGA selection, different vendors' SERDES IPs are instantiated, and synchronization frame headers are added according to different SERDES formats. The data is then serially forwarded through a high-speed interface. The receiving end's MCU microprocessor controls the SERDES IP selection process. Then, the FPGA periodically checks the high 8 bits of the user-side data. If the external user-side data interface type of the SERDES IP is an XGMII interface, it remains unchanged, directly determining whether it is xgmii_c or xgmii_d, completing the sync bytes synchronization of the fronthaul data. If the external user-side data interface type of the SERDES IP is a PCS layer interface, a custom interface conversion mechanism is executed. According to the conversion mechanism in Table 3, the PCS layer data is unified into XGMII interface data, and then it is determined whether it is xgmii_c or xgmii_d, completing the sync bytes synchronization.

[0061] 4. Specific implementation examples of automatic synchronization code pattern adaptation applicable to customized outdoor stations: This invention can be applied to customized outdoor station systems, mainly defining a method for automatic synchronization code adaptation, specifically implemented on the high-speed interface between the integrated unit and the remote RRU of the customized outdoor station. For ease of description, the technical solution of this invention needs to distinguish between the transmitting end and the receiving end of the customized outdoor station system. If the integrated unit of the system is defined as the transmitting end, then the remote RRU is the receiving end, and vice versa. Figure 12 The flowchart for the specific implementation of this plan includes the following steps: Step 401: Start, power on the customized outdoor station system.

[0062] Step 402: Start and load the FPGA bit file (i.e., configuration file), instantiate SERDES IP cores from various manufacturers on the FPGA, complete the SERDES processing clock frequency configuration using the internal phase-locked loop, open the fronthaul interface IP selection register, define the discrimination field for the interface type, and the control field for interface conversion.

[0063] Step 403: Enable the FPGA fronthaul interface IP selection register on the receiving MCU microprocessor.

[0064] Step 404: The receiving end periodically checks the data of the fronthaul interface. If the most significant bit is "1", proceed to step 414; otherwise, proceed to step 405.

[0065] Step 405: The receiving end determines that the user-side data type of this IP is PCS layer data, and sets the determination field to "0".

[0066] Step 406: The FPGA periodically checks whether the sync header of the PCS layer is "10". If it is, proceed to step 409; otherwise, proceed to step 407.

[0067] Step 407: The interface conversion control field Tran_c outputs "0".

[0068] Step 408: The sync header is converted to 8'h00 of the XGMII interface. The user data is consistent with the user data of the XGMII interface. The program then proceeds to step 415 to execute the XGMII interface frame data synchronization process.

[0069] Step 409: The interface conversion control field Tran_c outputs "1".

[0070] Step 410: Determine if the sync data of the pcs layer is 64'h50505050_50505078. If it is, proceed to step 412; otherwise, proceed to step 411.

[0071] Step 411: Determine if the sync data of the ps layer is 64'h50505050_505050ff. If it is, proceed to step 413; otherwise, proceed to step 409.

[0072] Step 412: Convert the data of the PCS layer into the frame start code of the XGMII interface, and the program proceeds to step 415 to execute the XGMII interface frame data synchronization process.

[0073] Step 413: Convert the data of the PCS layer into the frame end code of the XGMII interface, and the program proceeds to step 415 to execute the XGMII interface frame data synchronization process.

[0074] Step 414: The receiving end discrimination field is set to "1", indicating that the data type of the IP user side is XGMII.

[0075] Step 415: Determine the 8-bit xgmii_c and 64-bit xgmii_d in the corresponding data of the XGMII interface.

[0076] Step 416: The receiving end determines whether xgmii_c is 8'h80. If it is, proceed to step 418; otherwise, proceed to step 417.

[0077] Step 417: The receiving end determines whether xgmii_c is 8'h01. If it is, proceed to step 419; otherwise, proceed to step 415.

[0078] Step 418: Check if xgmii_d is the start-of-frame code, i.e., 64'h50505050_50505050fb. If it is, proceed to step 420; otherwise, proceed to step 419.

[0079] Step 419: Check if xgmii_d is the end-of-frame code, i.e., 64'h fd505050_5050505050. If it is, proceed to step 420; otherwise, proceed to step 415.

[0080] Step 420: Complete the initial framing of the fronthaul interface data frames.

[0081] Step 421: End.

[0082] In summary, compared with the prior art, the present invention has at least the following beneficial effects: 1. This invention proposes a clock and data conversion method based on FPGA implementation, which provides corresponding clock frequencies for instantiating differentiated SERDES IPs from different manufacturers. The high bit-width data conversion method is beneficial for data logic processing. 2. This invention proposes a high-speed interface discrimination and conversion mechanism based on FPGA implementation. It defines a discrimination field for identifying the type of fronthaul interface of the base station system and a control field for interface conversion, and uniformly converts the user-side data plane interface of the fronthaul interface into the XGMII interface, which is beneficial for the unified processing of differentiated fronthaul interfaces in actual engineering.

[0083] 3. This invention proposes an automatic synchronization code pattern adaptation design scheme for different high-speed interfaces. Through a high-speed interface discrimination and conversion mechanism, it automatically identifies and processes the fronthaul interface data of the PCS layer and XGMII, completes the frame fixing operation of the fronthaul interface data, and thus realizes the automatic adaptation of the synchronization code pattern.

[0084] 4. This invention applies the automatic synchronization code adaptation design scheme to the customized outdoor station intermediate frequency processing unit, optimizes the processing flow of the fronthaul interface, and enhances the code portability of the fronthaul interface module when using chips from different manufacturers or with different specifications during product iteration, shortens the product development cycle, and is beneficial to subsequent development and maintenance work.

[0085] On the other hand, embodiments of the present invention provide a synchronization code pattern adaptation device, comprising: a first module, configured to periodically acquire fronthaul interface data from a target register; wherein the target register includes different types of fronthaul interface IP selection registers; the fronthaul interface data packet contains a discrimination field; a second module, configured to determine the data type of the fronthaul interface data according to the discrimination field; wherein the data type includes a first type of data and a second type of data; the first type of data includes a synchronization header, synchronization data, and a control field; the second type of data includes a control code, a data code, and the control field; the control field of the first type of data is preset to empty; a third module, configured to, when the fronthaul interface data is first type of data, assign a value to the empty control field based on the field type of the synchronization header and in combination with a preset conversion rule, thereby converting the first type of data into the second type of data; and a fourth module, configured to complete synchronization code pattern adaptation through data framing operations based on the control code and the data code of the second type of data.

[0086] In some embodiments, the apparatus may further include: a fifth module for obtaining a configuration file of the target FPGA; and a sixth module for instantiating different types of serial communication device IPs through the target FPGA based on the configuration file, configuring clock frequencies through an internal phase-locked loop, and thereby opening a corresponding type of fronthaul interface IP selection register.

[0087] In some embodiments, the discrimination field includes a first discrimination field corresponding to the first type of data and a second discrimination field corresponding to the second type of data; after the operation of the third module is performed, the device further includes: a seventh module, used to convert the first discrimination field in the first type of data into the second discrimination field.

[0088] The content of the method embodiments of the present invention is applicable to the device embodiments. The specific functions implemented by the device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above methods.

[0089] On the other hand, embodiments of the present invention also provide an electronic device, which includes at least one processor and at least one memory for storing at least one program and executing the program to implement the aforementioned synchronization code adaptation method; taking a processor and a memory as an example.

[0090] The processor and memory can be connected via a bus or other means.

[0091] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0092] The electronic device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0093] Another aspect of this invention provides a computer-readable storage medium storing a program that is executed by a processor to implement the aforementioned method.

[0094] The content of the method embodiments of the present invention is applicable to the computer-readable storage medium embodiments. The specific functions implemented by the computer-readable storage medium embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above methods.

[0095] This invention also discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions, causing the computer device to perform the aforementioned method.

[0096] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0097] It should be noted that although several modules for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0098] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of the present invention can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, portable hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the method according to the embodiments of the present invention.

[0099] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this invention are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and sub-operations described as part of a larger operation are executed independently.

[0100] Furthermore, although the invention has been described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the invention. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional skill of an engineer. Therefore, those skilled in the art can implement the invention as set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of the invention, which is determined by the full scope of the appended claims and their equivalents.

[0101] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0102] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution means, apparatus, or device (such as a computer-based device, a processor-including device, or other means that can fetch and execute instructions from, or in conjunction with, an instruction execution means, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution means, apparatus, or device.

[0103] More specific examples (a non-exhaustive list) of computer-readable media include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0104] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution device. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0105] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0106] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0107] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A synchronization code adaptation method, characterized in that, include: The system periodically retrieves fronthaul interface data from a target register; wherein the target register includes different types of fronthaul interface IP selection registers; and the fronthaul interface data packet contains a discrimination field. The data type of the fronthaul interface data is determined based on the discrimination field; wherein, the data type includes a first type of data and a second type of data; the first type of data includes a synchronization header, synchronization data, and a control field; the second type of data includes a control code, a data code, and the control field; the control field of the first type of data is preset to empty; When the data from the forwarding interface is of the first type, the empty control field is assigned a value based on the field type of the synchronization header and in accordance with the preset conversion rules, thereby converting the first type of data into the second type of data. Based on the control code and the data code of the second type of data, synchronization code adaptation is completed through data framing operation.

2. The synchronization code pattern adaptation method according to claim 1, characterized in that, The method further includes: Obtain the configuration file for the target FPGA; Based on the configuration file, different types of serial communication device IPs are instantiated through the target FPGA, and clock frequency points are configured through an internal phase-locked loop, thereby opening up the corresponding type of fronthaul interface IP selection register.

3. The synchronization code pattern adaptation method according to claim 1, characterized in that, The second type of data includes frame start code, frame end code, and frame data stream; the field types include a first field type and a second field type; the process of assigning values ​​to empty control fields based on the field types of the synchronization header and combining them with preset conversion rules to convert the first type of data into the second type of data includes: When the field type of the synchronization header is the first field type, the control field that is empty in the first type of data is assigned the first control field, and the synchronization header is converted into the control code corresponding to the frame data stream; When the field type of the synchronization header is the second field type, the control field that is empty in the first type of data is assigned the value of the second control field; then, based on the field type of the synchronization data, the first type of data is converted into the frame start code or the frame end code.

4. The synchronization code pattern adaptation method according to claim 3, characterized in that, The field types include a first field type and a second field type; the conversion of the first type of data into the frame start code or the frame end code based on the field types of the synchronization data includes: When the field type of the synchronization data is the first field type, the synchronization header of the second field type in the first type of data and the synchronization data of the first field type are sequentially converted into the control code and the data code corresponding to the frame start code; When the field type of the synchronization data is the second field type, the synchronization header of the second field type in the first type of data and the synchronization data of the second field type are sequentially converted into the control code and the data code corresponding to the frame end code.

5. The synchronization code pattern adaptation method according to claim 1, characterized in that, The discrimination field includes a first discrimination field corresponding to the first type of data and a second discrimination field corresponding to the second type of data; After the step of converting the first type of data into the second type of data, the method further includes: Convert the first discriminant field in the first type of data into the second discriminant field.

6. The synchronization code pattern adaptation method according to claim 1, characterized in that, The control code and the data code based on the second type of data complete the synchronization code type adaptation through data framing operation, including: Using the first frame data in the second type of data as the target frame data, the data type of the target frame data is determined according to the control code of the target frame data; wherein, the data type of the target frame data includes frame start code, frame end code, and frame data stream; Based on the data type of the target frame data, the data framing operation is performed by matching the data code with the control code, thereby completing the synchronization code type adaptation.

7. The synchronization code pattern adaptation method according to claim 6, characterized in that, The data code includes a first data code corresponding to the frame start code, a second data code corresponding to the frame end code, and a third data code corresponding to the frame data code; the data framing operation based on the data type of the target frame data, using the data code matched by the control code, includes: When the data type is the frame start code, determine whether the data code matching the control code is the first data code; if the data code is the first data code, complete the data framing operation; if the data code is not the first data code, determine whether the data code matching the control code is the second data code; if the data code is the second data code, complete the data framing operation; otherwise, use the next frame data of the target frame data as the target frame data, and then return to the step of determining the data type of the target frame data based on the control code of the target frame data, until the data framing operation is completed. When the data type is the frame end code, determine whether the data code matching the control code is the second data code; if the data code is the second data code, complete the data framing operation; otherwise, use the next frame data of the target frame data as the target frame data, and then return to the step of determining the data type of the target frame data based on the control code of the target frame data, until the data framing operation is completed.

8. A synchronization code pattern adapter, characterized in that, include: The first module is used to periodically acquire fronthaul interface data from a target register; wherein, the target register includes different types of fronthaul interface IP selection registers; and the fronthaul interface data packet contains a discrimination field. The second module is used to determine the data type of the fronthaul interface data based on the discrimination field; wherein, the data type includes a first type of data and a second type of data; the first type of data includes a synchronization header, synchronization data, and a control field; the second type of data includes a control code, a data code, and the control field; the control field of the first type of data is preset to empty; The third module is used to convert the first type of data into the second type of data when the data from the fronthaul interface is of the first type. Based on the field type of the synchronization header and in combination with the preset conversion rules, the module assigns a value to the empty control field. The fourth module is used to complete the synchronization code adaptation through data framing operation based on the control code and the data code of the second type of data.

9. An electronic device, characterized in that, Including the processor and memory; The memory is used to store programs; The processor executes the program to implement the method as described in any one of claims 1 to 7.

10. A computer storage medium storing a processor-executable program, characterized in that, The processor-executable program, when executed by the processor, is used to implement the method as described in any one of claims 1 to 7.

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