High precision programmable current biasing circuit

Abstract

The application provides a high-precision programmable current bias circuit, which comprises a reference input module, a first output module, a second output module and a negative feedback module, generates an internal bias voltage through the reference input module, generates a first bias voltage through the first output module, generates a second bias voltage through the second output module, accurately copies the reference current through the negative feedback effect of the negative feedback module to obtain a first copy current, then applies the first bias voltage and the second bias voltage to a load circuit respectively, copies the first copy current through the load circuit to obtain a second copy current, and then adjusts the proportional coefficient of the first copy current and the reference current based on the MOS transistor in the second output module, which is adjusted and controlled by the digital code output by a programmable controller, to obtain the second copy current with high precision and programmable adjustment size, so that the influence of the second-order effect and PVT fluctuation of the device on the reference current copying precision and copying flexibility can be effectively eliminated.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-precision programmable current bias circuit. Background Technology

[0002] In analog integrated circuits, each unit module requires a bias current (or bias voltage). The quality of the bias current (or bias voltage) directly determines the performance of the module. For example, in high-speed, high-precision digital-to-analog converters (DACs), the bias current directly determines the accuracy of the DAC. Existing technologies either use resistor voltage dividers or generate the bias voltage through diode connections of MOSFETs. These traditional methods are significantly affected by second-order effects of devices and PVT (process, voltage, temperature) fluctuations, and cannot be dynamically adjusted according to actual operating conditions. Therefore, they cannot meet the design requirements of high-performance analog integrated circuits for high-precision bias.

[0003] Therefore, there is an urgent need for a high-precision, flexible, and adjustable bias current copying technology. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high-precision and flexible adjustable bias current copying technology. This technology utilizes an input reference current and, through negative feedback, generates two bias voltages to flexibly copy the reference current by an adjustable multiple, obtaining a first copied current. The two generated bias voltages are then applied to a load circuit, which copies the first copied current to obtain a second copied current. This results in a high-precision, programmable, and adjustable copied current on the load circuit, eliminating the influence of second-order effects of devices and PVT fluctuations on the accuracy and flexibility of reference current copying.

[0005] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0006] A high-precision programmable current bias circuit includes:

[0007] The reference input module receives a reference current and generates an internal bias voltage based on the reference current.

[0008] The first output module is connected to the reference input module, receives the initial bias voltage and the internal bias voltage, and generates the first bias voltage under the action of the initial bias voltage and the internal bias voltage.

[0009] The second output module is connected to the reference input module and the first output module respectively, and generates a second bias voltage under the action of the internal bias voltage and the first bias voltage.

[0010] A negative feedback module, connected to the second output module, replicates the reference current through negative feedback, and obtains a first replicated current on the second output module. The first replicated current is proportional to the reference current.

[0011] The first bias voltage and the second bias voltage are respectively applied to the load circuit, and the first copy current is copied through the load circuit to obtain the second copy current. The second copy current is equal to the first copy current, and the ratio coefficient of the first copy current to the reference current is adjusted and controlled by the digital code output by the programmable controller.

[0012] Optionally, the reference input module includes a first NMOS transistor, the source of which is grounded, the gate of which is connected to the drain of which is connected to the drain of which is connected to the reference current, and the gate of which generates and outputs the internal bias voltage.

[0013] Optionally, the first output module includes a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first resistor, and a second resistor. The source of the second NMOS transistor is grounded, the gate of the second NMOS transistor is connected to the internal bias voltage, the drain of the second NMOS transistor is connected to the drain of the first PMOS transistor, the gate of the first PMOS transistor is connected to the initial bias voltage, the source of the first PMOS transistor is connected to the drain of the second PMOS transistor, the drain of the first PMOS transistor is also connected to the gate of the second PMOS transistor via the first resistor connected in series, and the source of the second PMOS transistor is connected to the power supply voltage via the second resistor connected in series. The gate of the second PMOS transistor generates and outputs the first bias voltage.

[0014] Optionally, the second output module includes a third NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a third resistor, and a first capacitor. The source of the third NMOS transistor is grounded, the gate of the third NMOS transistor is connected to the internal bias voltage, the drain of the third NMOS transistor is connected to the drain of the third PMOS transistor, the gate of the third PMOS transistor is connected to the first bias voltage, the source of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, the drain of the third PMOS transistor is also connected to the gate of the fourth PMOS transistor via the first capacitor and the third resistor connected in series, the source of the fourth PMOS transistor is connected to the power supply voltage, and the gate of the fourth PMOS transistor generates and outputs the second bias voltage.

[0015] Optionally, the negative feedback module includes an operational amplifier. The non-inverting input of the operational amplifier is connected to the drain of the third NMOS transistor, the inverting input is connected to the gate of the third NMOS transistor, and the output is connected to the gate of the fourth PMOS transistor. The drain of the third PMOS transistor outputs the first replicated current. The operational amplifier includes a fourth NMOS transistor, a fifth NMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor. The source of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor serves as the non-inverting input of the operational amplifier. The gate of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, and the drain of the fourth NMOS transistor is connected to the fifth PMOS transistor. The drain of the PMOS transistor, the gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor, the source of the fifth PMOS transistor is connected to the power supply voltage, the source of the fifth NMOS transistor is grounded, the gate of the fifth NMOS transistor serves as the inverting input terminal of the operational amplifier, the gate of the fifth NMOS transistor is connected to the gate of the third NMOS transistor, the drain of the fifth NMOS transistor is connected to the drain of the sixth PMOS transistor, the gate of the sixth PMOS transistor is connected to the gate of the fifth PMOS transistor, the source of the sixth PMOS transistor is connected to the power supply voltage, the drain of the sixth PMOS transistor serves as the output terminal of the operational amplifier, and the drain of the sixth PMOS transistor is connected to the gate of the fourth PMOS transistor.

[0016] Optionally, the load circuit includes a seventh PMOS transistor and an eighth PMOS transistor. The source of the seventh PMOS transistor is connected to the power supply voltage, the gate of the seventh PMOS transistor is connected to the second bias voltage, the drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor, the gate of the eighth PMOS transistor is connected to the first bias voltage, and the drain of the eighth PMOS transistor outputs the second replication current. The parameters of the seventh PMOS transistor are the same as those of the fourth PMOS transistor.

[0017] Optionally, the channel length of the first NMOS transistor is the same as the channel length of the third NMOS transistor, and the channel width of the third NMOS transistor is adjusted and controlled by the digital code output by the programmable controller.

[0018] Optionally, the reference input module includes a ninth PMOS transistor, the source of which is connected to the power supply voltage, the gate of which is connected to the drain of which is connected to the drain of which is connected to the reference current, and the gate of which generates and outputs the internal bias voltage.

[0019] Optionally, the first output module includes a sixth NMOS transistor, a seventh NMOS transistor, a tenth PMOS transistor, a fourth resistor, and a fifth resistor. The source of the tenth PMOS transistor is connected to the power supply voltage, the gate of the tenth PMOS transistor is connected to the internal bias voltage, the drain of the tenth PMOS transistor is connected to the drain of the sixth NMOS transistor, the gate of the sixth NMOS transistor is connected to the source of the seventh NMOS transistor via the fourth resistor connected in series, the source of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the seventh NMOS transistor is connected to the initial bias voltage, and the source of the seventh NMOS transistor is grounded via the fifth resistor connected in series. The gate of the sixth NMOS transistor generates and outputs the first bias voltage.

[0020] Optionally, the second output module includes an eighth NMOS transistor, a ninth NMOS transistor, and an eleventh PMOS transistor. The source of the eleventh PMOS transistor is connected to the power supply voltage, the gate of the eleventh PMOS transistor is connected to the internal bias voltage, the drain of the eleventh PMOS transistor is connected to the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor is connected to the gate of the sixth NMOS transistor, the source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor, the source of the ninth NMOS transistor is grounded, and the gate of the ninth NMOS transistor generates and outputs the second bias voltage.

[0021] Optionally, the negative feedback module includes an operational amplifier, the non-inverting input of which is connected to the gate of the eleventh PMOS transistor, the inverting input of which is connected to the drain of the eleventh PMOS transistor, the output of which is connected to the gate of the ninth NMOS transistor, and the drain of the eleventh PMOS transistor outputs the first replication current.

[0022] Optionally, the channel length of the ninth PMOS transistor is the same as that of the eleventh PMOS transistor, and the channel width of the eleventh PMOS transistor is adjusted and controlled by the digital code output by the programmable controller.

[0023] As described above, the high-precision programmable current bias circuit provided by the present invention has at least the following beneficial effects:

[0024] A high-precision programmable current bias circuit is designed by combining a reference input module, a first output module, a second output module, and a negative feedback module. The reference input module generates internal bias voltages for the first and second output modules. The first output module generates a first bias voltage, and the second output module generates a second bias voltage. The negative feedback module replicates the reference current to obtain a first replicated current. The first and second bias voltages are then applied to the load circuit to enable it. The load circuit then replicates the first replicated current to obtain a second replicated current. The second replicated current is proportional to the first replicated current. The ratio of the first replicated current to the reference current is adjusted by a digital code output from the programmable controller. This results in a highly accurate and programmable replicated current (i.e., the second replicated current) on the load circuit. This effectively eliminates the impact of second-order effects and PVT fluctuations on the accuracy and flexibility of reference current replication. When applied to analog integrated circuits, it can effectively improve the performance of analog integrated circuits. Attached Figure Description

[0025] Figure 1 The diagram shows a prior art circuit for generating bias voltage based on diode connections.

[0026] Figure 2 The diagram shown is a schematic block diagram of the high-precision programmable current bias circuit in this invention.

[0027] Figures 3-5 The diagram shown is a circuit diagram of a high-precision programmable current bias circuit in an optional embodiment of the present invention.

[0028] Figure 6 The diagram shown is a circuit diagram of a high-precision programmable current bias circuit in another optional embodiment of the present invention. Detailed Implementation

[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Please see Figures 1-6It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0031] As described in the background section, the inventors have discovered that in analog integrated circuits, the quality of the bias current (or bias voltage) directly affects the performance of the circuit module. For example, in high-speed, high-precision digital-to-analog converters (DACs), the bias current directly determines the accuracy of the DAC.

[0032] However, existing technologies either use resistor voltage division to generate bias voltage or use diode connections of MOSFETs to generate bias voltage. These traditional methods are greatly affected by the second-order effects of devices and PVT (process, voltage, temperature) fluctuations, and cannot be dynamically adjusted according to actual operating conditions. Therefore, they cannot meet the design requirements of high-performance analog integrated circuits for high-precision bias.

[0033] Specifically, existing techniques for generating bias voltage using the diode connection of a MOSFET can be found in [reference needed]. Figure 1 ,like Figure 1As shown, the drain of NMOS transistor N01 is connected to the reference current Iref0, the source of NMOS transistor N01 is grounded, and the gate of NMOS transistor N01 is connected to the drain of NMOS transistor N01. The source of NMOS transistor N02 is grounded, and the gate of NMOS transistor N02 is connected to the gate of NMOS transistor N01. The drain of NMOS transistor N02 is connected to the drain of PMOS transistor P01, and the gate of PMOS transistor P01 is connected to the drain of PMOS transistor P01. The source of PMOS transistor P01 is connected to the power supply voltage VDD through a series resistor R01. The source of NMOS transistor N03 is grounded, the gate of NMOS transistor N03 is connected to the gate of NMOS transistor N01, and the drain of NMOS transistor N03 is connected to the drain of PMOS transistor P03. The gate of NMOS transistor P03 is connected to the drain of PMOS transistor P03, and the source of PMOS transistor P03 is connected to the power supply voltage VDD. An internal bias voltage Vb0 is generated based on the diode connection of NMOS transistor N01. The internal bias voltage Vb0 turns on NMOS transistor N02. The turned-on NMOS transistor N02 then turns on PMOS transistor P01 based on the diode connection of PMOS transistor P01, and a first bias voltage Vout01 is obtained at the gate of PMOS transistor P01. The internal bias voltage Vb0 also turns on NMOS transistor N03. The turned-on NMOS transistor N03 then turns on PMOS transistor P02 based on the diode connection of PMOS transistor P02, and a second bias voltage Vout02 is obtained at the gate of PMOS transistor P02.

[0034] However, due to the significant influence of second-order effects (such as back-gate effect, channel length modulation effect, and subthreshold effect) and PVT (process, voltage, and temperature) fluctuations of devices (such as NMOS transistors N01-N03 and PMOS transistors P01-P02), the final actual circuit deviates from the theoretical circuit in terms of parameters. This results in errors between the obtained first bias voltage Vout01 (and second bias voltage Vout02) and their corresponding ideal values, thus preventing accurate current replication. Furthermore, as this circuit is fixed and non-adjustable, the obtained first bias voltage Vout01 (and second bias voltage Vout02) cannot be dynamically adjusted according to actual operating conditions. Consequently, the resulting bias voltage (i.e., the first bias voltage Vout01 and the second bias voltage Vout02) or the bias current generated by the bias voltage has large errors, low accuracy, and is not adjustable, limiting its applicability and failing to meet the design requirements of high-performance analog integrated circuits for high-precision bias.

[0035] Based on this, the present invention proposes a high-precision programmable bias current generation technology: a high-precision programmable current bias circuit is designed by combining a reference input module, a first output module, a second output module, and a negative feedback module. The reference input module generates internal bias voltages for the first and second output modules. The first output module generates a first bias voltage, and the second output module generates a second bias voltage. The negative feedback module replicates the reference current to obtain a first replicated current. The first and second bias voltages are then applied to the load circuit to enable the load circuit, and the load circuit replicates the first replicated current to obtain a second replicated current equal to the first replicated current. The ratio coefficient between the first replicated current and the reference current is adjusted by the digital code output by the programmable controller based on the aspect ratio of the second output module, and the controlled MOS transistor is adjusted. Thus, a high-precision, programmable adjustable second replicated current is obtained on the load circuit, eliminating the influence of the second-order effect of the device and PVT fluctuations on the accuracy and flexibility of the reference current replication.

[0036] like Figure 2 As shown, this invention proposes a high-precision programmable current bias circuit, which includes:

[0037] The reference input module receives the reference current Iref and generates an internal bias voltage Vb0 based on the reference current Iref.

[0038] The first output module is connected to the reference input module, receives the initial bias voltage Vb1 and the internal bias voltage Vb0, and generates the first bias voltage Vout1 under the action of the initial bias voltage Vb1 and the internal bias voltage Vb0.

[0039] The second output module is connected to the reference input module and the first output module respectively, and generates the second bias voltage Vout2 under the action of the internal bias voltage Vb0 and the first bias voltage Vout1.

[0040] The negative feedback module is connected to the second output module. It replicates the reference current Iref through negative feedback and obtains the first replicated current I01 on the second output module. The first replicated current I01 is proportional to the reference current Iref.

[0041] The first bias voltage Vout1 and the second bias voltage Vout2 are applied to the load circuit, and the first copy current I01 is copied through the load circuit to obtain the second copy current I02. The second copy current I02 is proportional to the first copy current I01. The proportional coefficient between the first copy current I01 and the reference current Iref is adjusted and controlled by the digital code output by the programmable controller.

[0042] Among them, such as Figure 2As shown, the second output module includes three MOSFETs Q1 to Q3 connected in series, and the load circuit includes two MOSFETs Q4 to Q5 connected in series. MOSFETs Q1, Q2, Q4, and Q5 are of type 1 (one of NMOS and PMOS), and MOSFET Q3 is of type 2 (the other of NMOS and PMOS). The parameters of MOSFET Q1 are the same as those of MOSFET Q4 (or of the same length and proportional width) to ensure accurate replication of the first replication current I01, so that the resulting second replication current I02 is equal to or proportional to the first replication current I01. Simultaneously, the width-to-length ratio of MOSFET Q3 is adjusted and controlled by the digital code output by the programmable controller, thereby adjusting the ratio coefficient between the first replication current I01 and the reference current Iref. The structure of the first output module is similar to that of the second output module, and the first output module also includes three MOSFETs connected in series. Figure 2 (Not shown in the image), which will not be elaborated upon here.

[0043] In detail, in an optional embodiment of the invention, such as Figure 3 As shown, the reference input module includes a first NMOS transistor N1. The source of the first NMOS transistor N1 is grounded, the gate of the first NMOS transistor N1 is connected to the drain of the first NMOS transistor N1, and the drain of the first NMOS transistor N1 is connected to the reference current Iref. Based on the diode connection of the first NMOS transistor N1, the first NMOS transistor N1 is turned on under the action of the reference current Iref provided by the current source, and the gate of the first NMOS transistor generates and outputs the internal bias voltage Vb0.

[0044] In detail, in an optional embodiment of the invention, such as Figure 3 As shown, the first output module includes a second NMOS transistor N2, a first PMOS transistor P1, a second PMOS transistor P2, a first resistor R1, and a second resistor R2. The source of the second NMOS transistor N2 is grounded, the gate of the second NMOS transistor N2 is connected to the internal bias voltage Vb0, the drain of the second NMOS transistor N2 is connected to the drain of the first PMOS transistor P1, the gate of the first PMOS transistor P1 is connected to the initial bias voltage Vb1, the source of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2, the drain of the first PMOS transistor P1 is also connected to the gate of the second PMOS transistor P2 via the first resistor R1 in series, and the source of the second PMOS transistor P2 is connected to the power supply voltage VDD via the second resistor R2 in series. The gate of the second PMOS transistor P2 generates and outputs the first bias voltage Vout1.

[0045] More in detail, such as Figure 3As shown, the initial bias voltage Vb1 is the ground potential VSS. Under the action of the internal bias voltage Vb0, the second NMOS transistor N2 is turned on, and the gate of the second PMOS transistor P2 (i.e. the first bias voltage Vout1) is pulled low, causing the second PMOS transistor P2 to turn on. Under the action of the initial bias voltage Vb1, the first PMOS transistor P1 is turned on, thereby making the first output module fully turn on, forming a current loop, generating a current I00 and producing the first bias voltage Vout1.

[0046] In detail, in an optional embodiment of the invention, such as Figure 3 As shown, the second output module includes a third NMOS transistor N3, a third PMOS transistor P3, a fourth PMOS transistor P4, a third resistor R3, and a first capacitor C1. The source of the third NMOS transistor N3 is grounded, the gate of the third NMOS transistor N3 is connected to the internal bias voltage Vb0, the drain of the third NMOS transistor N3 is connected to the drain of the third PMOS transistor P3, the gate of the third PMOS transistor P3 is connected to the first bias voltage Vout1, the source of the third PMOS transistor P3 is connected to the drain of the fourth PMOS transistor P4, and the drain of the third PMOS transistor P3 is connected to the gate of the fourth PMOS transistor P4 via the first capacitor C1 and the third resistor R3 connected in series. The source of the fourth PMOS transistor P4 is connected to the power supply voltage VDD, and the gate of the fourth PMOS transistor P4 generates and outputs the second bias voltage Vout2.

[0047] In detail, in an optional embodiment of the invention, such as Figure 3 As shown, the negative feedback module includes an operational amplifier OP1. The non-inverting input of the operational amplifier OP1 is connected to the drain of the third NMOS transistor N3, the inverting input of the operational amplifier OP1 is connected to the gate of the third NMOS transistor N3, and the output of the operational amplifier OP1 is connected to the gate of the fourth PMOS transistor P4.

[0048] More in detail, such as Figure 3 As shown, under the action of the internal bias voltage Vb0, the third NMOS transistor N3 is turned on, and under the action of the first bias voltage Vout1, the third PMOS transistor P3 is turned on. The drain of the third NMOS transistor N3 is pulled low, and the gate of the third NMOS transistor N3 is connected to the internal bias voltage Vb0, so that the output of the operational amplifier OP1 (i.e. the second bias voltage Vout2) is biased to a suitable voltage value, which in turn turns on the fourth PMOS transistor P4. This makes the second output module fully turn on, forming a current loop, replicating the reference current Iref, obtaining the first replicated current I01 and generating the second bias voltage Vout2. The drain of the third PMOS transistor P3 outputs the first replicated current I01.

[0049] More specifically, in an optional embodiment of the invention, such as Figure 4As shown, operational amplifier OP1 includes a fourth NMOS transistor N4, a fifth NMOS transistor N5, a fifth PMOS transistor P5, and a sixth PMOS transistor P6. The source of the fourth NMOS transistor N4 is grounded, and its gate serves as the non-inverting input of operational amplifier OP1. The gate of the fourth NMOS transistor N4 is connected to the drain of the third NMOS transistor N3, and its drain is connected to the drain of the fifth PMOS transistor P5. The gate of the fifth PMOS transistor P5 is connected to its drain, and its source is connected to the power supply voltage VDD. The source of the fifth NMOS transistor N5 is grounded, and the gate of the fifth NMOS transistor N5 serves as the inverting input of the operational amplifier OP1. The gate of the fifth NMOS transistor N5 is connected to the gate of the third NMOS transistor N3. The drain of the fifth NMOS transistor N5 is connected to the drain of the sixth PMOS transistor P6. The gate of the sixth PMOS transistor P6 is connected to the gate of the fifth PMOS transistor P5. The source of the sixth PMOS transistor P6 is connected to the power supply voltage VDD. The drain of the sixth PMOS transistor P6 serves as the output of the operational amplifier OP1. The drain of the sixth PMOS transistor P6 is connected to the gate of the fourth PMOS transistor P4.

[0050] Furthermore, such as Figure 4 As shown, the fourth NMOS transistor N4, the fifth NMOS transistor N5, the fifth PMOS transistor P5, and the sixth PMOS transistor P6 constitute operational amplifier OP1, generating currents I03 and I04. Operational amplifier OP1 is connected to the second output module, and the two together form a negative feedback loop, stabilizing the second bias voltage Vout2 of the output. Through the negative feedback, the reference current Iref is replicated, resulting in the first replicated current I01 on the second output module. The first replicated current I01 is proportional to the reference current Iref. At the same time, the third resistor R3 is connected in series with the first capacitor C1 to perform phase compensation for the negative feedback loop, stabilizing the negative feedback loop.

[0051] More specifically, in an optional embodiment of the invention, such as Figure 5 As shown, the load circuit includes a seventh PMOS transistor P7 and an eighth PMOS transistor P8. The source of the seventh PMOS transistor P7 is connected to the power supply voltage VDD, the gate of the seventh PMOS transistor P7 is connected to the second bias voltage Vout2, the drain of the seventh PMOS transistor P7 is connected to the source of the eighth PMOS transistor P8, the gate of the eighth PMOS transistor P8 is connected to the first bias voltage Vout1, and the drain of the eighth PMOS transistor P8 outputs the second replication current I02. The parameters of the seventh PMOS transistor P7 are the same as those of the fourth PMOS transistor P4 (same length, proportional width).

[0052] The channel lengths of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are the same. The first NMOS transistor N1 and the third NMOS transistor N3 are the same. The channel width of the third NMOS transistor N3 is adjusted and controlled by the digital code output by the programmable controller. The channel width of the second NMOS transistor N2 is also adjusted and controlled by the digital code output by the programmable controller.

[0053] In detail, in an optional embodiment of the invention, such as Figures 3-5 As shown, operational amplifier OP1 and the second output module are connected to form a negative feedback loop. Based on the virtual short principle of operational amplifier OP1, V GS_N3 =V DS_N3 The following formula applies to the first NMOS transistor N1 and the third NMOS transistor N3:

[0054] V DS_N1 =V GS_N1 =V GS_N3 =V DS_N3 (1)

[0055] Among them, V DS_N1 V is the drain-source voltage of the first NMOS transistor N1. GS_N1 V is the gate-source voltage of the first NMOS transistor N1. GS_N3 V is the gate-source voltage of the third NMOS transistor N3. DS_N3 This is the drain-source voltage of the third NMOS transistor N3.

[0056] Therefore, the first replication current I01 flowing through the fourth PMOS transistor P4, the third PMOS transistor P3, and the third NMOS transistor N3 is proportional to the reference current Iref flowing through the first NMOS transistor N1. When all parameters except the channel width are the same, the ratio of the first replication current I01 to the reference current Iref is equal to the ratio of the channel width-to-length ratio of the first NMOS transistor N1 to the channel width-to-length ratio of the third NMOS transistor N3. Since the channel lengths of the first NMOS transistor N1 and the third NMOS transistor N3 are the same, the ratio of the first replication current I01 to the reference current Iref is equal to the ratio of the channel width of the first NMOS transistor N1 to the channel width of the third NMOS transistor N3. The channel width of the first NMOS transistor N1 is fixed, while the channel width of the third NMOS transistor N3 is adjusted and controlled by the digital code output by the programmable controller, thus allowing for programmable adjustment of the ratio of the first replication current I01 to the reference current Iref.

[0057] The first bias voltage Vout1 is:

[0058] Vout1 = VDD - V DS_P4 -|V GS_P3 | (2);

[0059] The second bias voltage Vout2 is:

[0060] Vout2=VDD-|V GS_P4 | (3);

[0061] Among them, V DS_P4 V is the drain-source voltage of the fourth PMOS transistor P4. GS_P3 V is the gate-source voltage of the third PMOS transistor P3. GS_P4 This is the gate-source voltage of the fourth PMOS transistor, P4.

[0062] When the high-precision programmable current bias circuit proposed in this embodiment of the invention is connected to the load circuit, it forms as follows: Figure 5 The circuit diagram shown. From Figure 5 It can be seen that the gate-source voltage of the seventh PMOS transistor P7 (load transistor) is the same as that of the fourth PMOS transistor P4 (bias voltage generator transistor), and the parameters of the seventh PMOS transistor P7 are the same as those of the fourth PMOS transistor P4. The first replication current I01 flowing through the fourth PMOS transistor P4 is equal to (or proportional to) the second replication current I02 flowing through the seventh PMOS transistor P7. Therefore, the first replication current I01 can be accurately replicated through the load circuit to obtain the second replication current I02. The first replication current I01 is also an accurate replication of the reference current Iref, and the corresponding proportional coefficient is adjusted and controlled by the digital code output by the programmable controller. Thus, the output second replication current I02 is accurately and adjustablely replicated to the input reference current Iref. The obtained second replication current has high accuracy and programmable adjustment, which can effectively eliminate the influence of the second-order effect of the device and PVT fluctuation on the accuracy and flexibility of the reference current replication. When applied to analog integrated circuits, it can effectively improve the performance of analog integrated circuits.

[0063] The channel width of the third NMOS transistor N3 is adjusted and controlled by the digital code output by the programmable controller, with an adjustment factor of k. Therefore:

[0064] I02=I01=k×Iref (4)

[0065] It should be noted that the channel width of the third NMOS transistor N3 is controlled by digital code adjustment. The third NMOS transistor N3 includes M parallel MOS branches, each MOS branch including one unit NMOS transistor. The drains of the M unit NMOS transistors are connected together as the drain of the third NMOS transistor N3, the gates of the M unit NMOS transistors are connected together as the gate of the third NMOS transistor N3, and the sources of the M unit NMOS transistors are connected together as the source of the third NMOS transistor N3. Furthermore, the N MOS branches are switching MOS structures. In addition to the unit NMOS transistors, the switching MOS structure also includes unit switches. In each switching MOS structure... The input terminal of the unit switch is connected to the drain of the unit NMOS transistor, and the output terminal of the unit switch is connected to the source of the unit NMOS transistor. The control terminal of the unit switch is connected to a single digital code output by the programmable controller. N MOS branches are connected one-to-one with the N digital codes. The unit switches are controlled by the digital codes (0 or 1), thereby controlling whether the unit NMOS transistors in the corresponding MOS branches are connected in parallel. Assuming that the channel lengths of the M unit NMOS transistors are the same, the channel width of the third NMOS transistor N3 formed by parallel connection can be adjusted by regulating the number of unit NMOS transistors connected in parallel. Here, M is an integer greater than or equal to 2, and N is an integer from 1 to M. The structure of the second NMOS transistor N2, whose channel width is programmable and adjustable, is similar to that of the third NMOS transistor N3 and will not be described further here.

[0066] It needs to be emphasized that, in Figures 3-5 In the illustrated embodiment, the reference input module is a circuit structure based on an NMOS transistor (i.e., the first NMOS transistor N1). In other optional embodiments of the present invention, the reference input module may also be a circuit structure based on a PMOS transistor.

[0067] In detail, in another alternative embodiment of the invention, such as Figure 6 As shown, the reference input module includes a ninth PMOS transistor P9. The source of the ninth PMOS transistor P9 is connected to the power supply voltage VDD, the gate of the ninth PMOS transistor P9 is connected to the drain of the ninth PMOS transistor P9, the drain of the ninth PMOS transistor P9 is connected to the reference current Iref, and the gate of the ninth PMOS transistor P9 generates and outputs the internal bias voltage Vb0.

[0068] In detail, in another alternative embodiment of the invention, such as Figure 6As shown, the first output module includes a sixth NMOS transistor N6, a seventh NMOS transistor N7, a tenth PMOS transistor P10, a fourth resistor R4, and a fifth resistor R5. The source of the tenth PMOS transistor P10 is connected to the power supply voltage VDD, the gate of the tenth PMOS transistor P10 is connected to the internal bias voltage Vb0, and the drain of the tenth PMOS transistor P10 is connected to the drain of the sixth NMOS transistor N6. The gate of the sixth NMOS transistor N6 is connected to the source of the seventh NMOS transistor N7 via the fourth resistor R4 in series. The source of the sixth NMOS transistor N6 is connected to the drain of the seventh NMOS transistor N7. The gate of the seventh NMOS transistor N7 is connected to the initial bias voltage Vb1 (here, the initial bias voltage Vb1 is the positive power supply voltage, such as the power supply voltage VDD). The source of the seventh NMOS transistor N7 is grounded via the fifth resistor R5 in series. The gate of the sixth NMOS transistor N6 generates and outputs the first bias voltage Vout1.

[0069] In detail, in another alternative embodiment of the invention, such as Figure 6 As shown, the second output module includes an eighth NMOS transistor N8, a ninth NMOS transistor N9, and an eleventh PMOS transistor P11. The source of the eleventh PMOS transistor P11 is connected to the power supply voltage VDD, the gate of the eleventh PMOS transistor P11 is connected to the internal bias voltage Vb0, the drain of the eleventh PMOS transistor P11 is connected to the drain of the eighth NMOS transistor N8, the gate of the eighth NMOS transistor N8 is connected to the gate of the sixth NMOS transistor N6, the source of the eighth NMOS transistor N8 is connected to the drain of the ninth NMOS transistor N9, the source of the ninth NMOS transistor N9 is grounded, and the gate of the ninth NMOS transistor N9 generates and outputs the second bias voltage Vout2.

[0070] It should be noted that the corresponding load circuit includes two NMOS transistors connected in series, which can be compared to... Figure 5 The relevant descriptions of the medium-load circuit will be analyzed, and will not be repeated here.

[0071] In detail, in another alternative embodiment of the invention, such as Figure 6 As shown, the negative feedback module includes an operational amplifier OP2. The non-inverting input of the operational amplifier OP2 is connected to the gate of the eleventh PMOS transistor P11, the inverting input of the operational amplifier OP2 is connected to the drain of the eleventh PMOS transistor P11, the output of the operational amplifier OP2 is connected to the gate of the ninth NMOS transistor N9, and the drain of the eleventh PMOS transistor P11 outputs the first replication current I01.

[0072] Among them, the channel length of the ninth PMOS transistor P9 is the same as that of the eleventh PMOS transistor P11. The channel width of the eleventh PMOS transistor P11 is adjusted and controlled by the digital code output by the programmable controller. The structure of the eleventh PMOS transistor P11 is similar to that of the third NMOS transistor N3. For details, please refer to the description of the structure of the third NMOS transistor N3 in the above embodiment, which will not be repeated here.

[0073] It needs to be emphasized that, such as Figure 6 The specific working principle of the high-precision programmable current bias circuit shown can be compared to that of... Figures 3-5 The specific working principle of the high-precision programmable current bias circuit shown will be analyzed, and will not be repeated here.

[0074] In summary, the high-precision programmable current bias circuit provided by this invention combines a reference input module, a first output module, a second output module, and a negative feedback module. The reference input module generates internal bias voltages for the first and second output modules. The first output module generates a first bias voltage, and the second output module generates a second bias voltage. The negative feedback module replicates the reference current to obtain a first replicated current. The first and second bias voltages are then applied to the load circuit to enable it, and the load circuit replicates the first replicated current to obtain a second replicated current equal to or proportional to the first replicated current. Furthermore, the ratio of the first replicated current to the reference current is adjusted by a MOS transistor controlled by a digital code output from a programmable controller based on the width (or aspect ratio) of the second output module. This results in a highly accurate second replicated current with programmable adjustable size on the load circuit. This effectively eliminates the influence of second-order effects and PVT fluctuations on the accuracy and flexibility of reference current replication. When applied to analog integrated circuits, this circuit can effectively improve the performance of analog integrated circuits.

[0075] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high precision programmable current biasing circuit, characterized by, The application relates to a reference input module, a first output module, a second output module and a negative feedback module. The reference input module receives a reference current and generates an internal bias voltage according to the reference current. The first output module is connected with the reference input module and receives an initial bias voltage and the internal bias voltage, and generates a first bias voltage under the action of the initial bias voltage and the internal bias voltage. The second output module is connected with the reference input module and the first output module respectively, and generates a second bias voltage under the action of the internal bias voltage and the first bias voltage. The negative feedback module is connected with the second output module, and the reference current is copied through negative feedback, and a first copy current is obtained on the second output module, and the first copy current is proportional to the reference current. The first bias voltage and the second bias voltage are respectively applied to a load circuit, the first copy current is copied through the load circuit, a second copy current is obtained, the second copy current is proportional to the first copy current, and the proportional coefficient of the first copy current and the reference current is adjusted and controlled by a digital code output by a programmable controller. The reference input module comprises a first NMOS tube, the source of the first NMOS tube is grounded, the gate of the first NMOS tube is connected with the drain of the first NMOS tube, the drain of the first NMOS tube is connected with the reference current, and the gate of the first NMOS tube generates and outputs the internal bias voltage. The first output module comprises a second NMOS tube, a first PMOS tube, a second PMOS tube, a first resistor and a second resistor, the source of the second NMOS tube is grounded, the gate of the second NMOS tube is connected with the internal bias voltage, the drain of the second NMOS tube is connected with the drain of the first PMOS tube, the gate of the first PMOS tube is connected with the initial bias voltage, the source of the first PMOS tube is connected with the drain of the second PMOS tube, the drain of the first PMOS tube is connected with the gate of the second PMOS tube through the first resistor, the source of the second PMOS tube is connected with a power supply voltage through the second resistor, and the gate of the second PMOS tube generates and outputs the first bias voltage. The second output module comprises a third NMOS tube, a third PMOS tube, a fourth PMOS tube, a third resistor and a first capacitor, the source of the third NMOS tube is grounded, the gate of the third NMOS tube is connected with the internal bias voltage, the drain of the third NMOS tube is connected with the drain of the third PMOS tube, the gate of the third PMOS tube is connected with the first bias voltage, the source of the third PMOS tube is connected with the drain of the fourth PMOS tube, the drain of the third PMOS tube is connected with the gate of the fourth PMOS tube through the first capacitor and the third resistor, the source of the fourth PMOS tube is connected with a power supply voltage, and the gate of the fourth PMOS tube generates and outputs the second bias voltage. The negative feedback module comprises an operational amplifier, the non-inverting input terminal of the operational amplifier is connected to the drain of the third NMOS tube, the inverting input terminal of the operational amplifier is connected to the gate of the third NMOS tube, the output terminal of the operational amplifier is connected to the gate of the fourth PMOS tube, the drain of the third PMOS tube outputs the first copy current, the operational amplifier comprises a fourth NMOS tube, a fifth NMOS tube, a fifth PMOS tube and a sixth PMOS tube, the source of the fourth NMOS tube is connected to the ground, the gate of the fourth NMOS tube serves as the non-inverting input terminal of the operational amplifier, the gate of the fourth NMOS tube is connected to the drain of the third NMOS tube, the drain of the fourth NMOS tube is connected to the drain of the fifth PMOS tube, the gate of the fifth PMOS tube is connected to the drain of the fifth PMOS tube, the source of the fifth PMOS tube is connected to the power supply voltage, the source of the fifth NMOS tube is connected to the ground, the gate of the fifth NMOS tube serves as the inverting input terminal of the operational amplifier, the gate of the fifth NMOS tube is connected to the gate of the third NMOS tube, the drain of the fifth NMOS tube is connected to the drain of the sixth PMOS tube, the gate of the sixth PMOS tube is connected to the gate of the fifth PMOS tube, the source of the sixth PMOS tube is connected to the power supply voltage, the drain of the sixth PMOS tube serves as the output terminal of the operational amplifier, and the drain of the sixth PMOS tube is connected to the gate of the fourth PMOS tube.

2. The high precision programmable current biasing circuit of claim 1, wherein, The load circuit comprises a seventh PMOS tube and an eighth PMOS tube, the source of the seventh PMOS tube is connected to the power supply voltage, the gate of the seventh PMOS tube is connected to the second bias voltage, the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube, the gate of the eighth PMOS tube is connected to the first bias voltage, the drain of the eighth PMOS tube outputs the second copy current, and the parameter specification of the seventh PMOS tube is the same as that of the fourth PMOS tube.

3. The high precision programmable current biasing circuit of claim 2, wherein, The channel length of the first NMOS tube is the same as that of the third NMOS tube, and the channel width of the third NMOS tube is adjusted and controlled by the digital code output by the programmable controller.

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