A power clamp circuit, IO interface and integrated circuit chip
By introducing a power-on reset signal and an NMOS transistor design into the power clamping circuit, the problem of power glitches triggering the discharge transistor is solved, thus improving the reliability of the power clamping circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING TONGFANG MICROELECTRONICS
- Filing Date
- 2023-10-23
- Publication Date
- 2026-07-03
AI Technical Summary
Existing power clamping circuits cannot identify power glitches, leading to accidental discharge of transistors and damage to the chip.
A power-on reset signal is introduced, which forms the turn-on and turn-off path of the discharge transistor through the RC branch and the NMOS transistor to prevent the discharge transistor from being accidentally triggered during glitches.
It effectively prevents the discharge transistor from turning on accidentally during power supply glitches, avoids chip damage, and improves chip reliability.
Smart Images
Figure CN117353262B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing technology, specifically to a power clamping circuit, an I / O interface, and an integrated circuit chip. Background Technology
[0002] For integrated circuits, electrostatic discharge (ESD) often causes irreversible damage to the chip, rendering it unusable. Therefore, ESD protection design for integrated circuit chips is a crucial aspect of ensuring chip reliability.
[0003] The principle of ESD protection is to provide a low-resistance path for electrostatic charges when an electrostatic shock occurs, allowing the charges to dissipate through this pre-defined path and thus preventing damage to internal circuitry. As the functions of individual chips become increasingly complex, the number of I / O pins required also increases. To ensure the chip's ESD capability, power clamping modules distributed within the I / O rings are becoming more numerous. An ideal power clamping module must ensure that the discharge transistors are activated promptly to dissipate the ESD current when the chip is subjected to an ESD current surge, thereby protecting the internal circuitry, while also ensuring that the discharge transistors are deactivated when the chip is operating normally.
[0004] When a glitch occurs in the power supply, a power clamping circuit in the prior art cannot identify it as a glitch and mistakenly identifies it as ESD, leading to accidental discharge. Summary of the Invention
[0005] In view of this, this application provides a power clamping circuit, an I / O interface, and an integrated circuit chip, which can prevent the discharge transistor from being accidentally triggered when power glitches occur.
[0006] This application provides a power clamping circuit, including: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, an RC branch, and a power-on reset module;
[0007] The RC branch includes a resistor and a capacitor connected in series, and the RC branch is connected between the power supply and ground.
[0008] The source of the first PMOS transistor is connected to the power supply, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, and the drain of the second PMOS transistor is grounded through the second NMOS transistor.
[0009] The gate of the first NMOS transistor is connected to the drain of the second PMOS transistor, the drain of the first NMOS transistor is connected to the power supply, and the source of the first NMOS transistor is grounded.
[0010] The gates of the second PMOS transistor and the second NMOS transistor are both connected to the common terminal of the resistor and capacitor;
[0011] The gate of the first PMOS transistor is connected to the power-on reset module;
[0012] The power-on reset module is used to output a reset signal according to the voltage of the power supply, and the reset signal is synchronized with the voltage of the power supply.
[0013] Preferably, the power-on reset module includes: a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor;
[0014] The drain of the third NMOS transistor is connected to the power supply through the second resistor, the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is grounded through the third resistor; the gates of the third NMOS transistor and the fourth NMOS transistor are both grounded.
[0015] The drain of the fifth NMOS transistor is connected to the power supply through the fourth resistor, and the source of the fifth NMOS transistor is grounded.
[0016] The drain of the fifth NMOS transistor serves as the output terminal of the power-on reset module.
[0017] Preferably, the power-on reset module further includes: an inverter;
[0018] The input terminal of the inverter is connected to the drain of the fifth NMOS transistor, and the output terminal of the inverter is connected to the gate of the first PMOS transistor as the output terminal of the power-on reset module.
[0019] Preferably, the power-on reset module further includes: a second capacitor;
[0020] The first and second terminals of the second capacitor are respectively connected to the drain and source of the fifth NMOS transistor.
[0021] Preferably, the inverter output remains at a low level before the power supply is fully powered on, and the inverter outputs a high level after the power supply is fully powered on.
[0022] Preferably, when a glitch occurs in the power supply, the first NMOS transistor is turned off.
[0023] This application also provides an I / O interface, including the power clamping circuit described above.
[0024] This application also provides an integrated circuit chip, including the power clamping circuit described above.
[0025] Preferably, the chip is a SIM card chip in an electronic device terminal.
[0026] Preferably, the chip is a chip found in a financial card.
[0027] Therefore, this application has the following beneficial effects:
[0028] The temperature acquisition circuit provided in this application, to prevent false triggering, introduces a power-on reset signal into the discharge transistor's turn-on path compared to the power clamping circuit of the prior art. This reset signal is connected to the gate of the first PMOS transistor. The first and second PMOS transistors constitute the discharge transistor's turn-on path, used to turn on the discharge transistor based on the identification signal given by the ESD pulse detection unit when an ESD pulse arrives, and to remain off when power glitches occur. The second NMOS transistor constitutes the discharge transistor's turn-off path, used to turn off the discharge transistor after providing sufficient time delay for the discharge transistor to turn on after the turn-on path has opened it. Because the output of the power-on reset module can remain high when a small glitch occurs on VCC, meaning the gate of the first PMOS transistor always remains high, the gate of the first NMOS transistor will not be pulled high, and the first NMOS transistor will not turn on to generate leakage current from VCC to GND. Therefore, false discharge will not occur when power glitches occur. Attached Figure Description
[0029] Figure 1 This is a schematic diagram of a traditional power clamping circuit;
[0030] Figure 2 A schematic diagram of a power clamping circuit provided in an embodiment of this application;
[0031] Figure 3 A graph showing the relationship between the voltage of the reset signal provided in this application and the voltage of the power supply over time;
[0032] Figure 4 A schematic diagram of a power-on reset module provided in an embodiment of this application;
[0033] Figure 5 This is a schematic diagram of an ESD discharge current provided in an embodiment of this application. Detailed Implementation
[0034] To enable those skilled in the art to better understand the technical solutions provided in the embodiments of this application, a conventional power clamping circuit will be introduced below.
[0035] See Figure 1 The figure shows a schematic diagram of a traditional power clamping circuit.
[0036] The circuit includes an RC branch formed by resistor R1 and capacitor C1, as well as a PMOS transistor PM1 and two NMOS transistors, namely NM1 and NM2. PM1 and NM2 are connected in series between power supply VCC and ground VSS, and the RC branch is also connected in series between VCC and VSS.
[0037] In this circuit, PM1 serves as the discharge enable path, NM2 serves as the discharge disable path, and NM1 serves as the discharge transistor.
[0038] The power clamping circuit uses an RC branch to determine whether to turn on the discharge transistor and the turn-on time of the discharge transistor. To ensure that the discharge transistor has sufficient turn-on time to discharge the electrostatic charge when an ESD impact occurs, the delay of this RC branch is designed to be slightly longer than the duration of the ESD current. Since there is no other way to limit the turn-on of the discharge transistor, when a power supply glitches occur, the ESD pulse detection unit will send an identification signal to the turn-on path of the discharge transistor, causing the discharge transistor to turn on erroneously.
[0039] To address the issue of accidental discharge when power supply glitches occur, this application provides a power clamping circuit, which will be described in detail below with reference to the accompanying drawings.
[0040] See Figure 2 The figure is a schematic diagram of a power clamping circuit provided in an embodiment of this application.
[0041] The power clamping circuit provided in this application embodiment includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, a second NMOS transistor NM2, an RC branch, and a power-on reset module 100.
[0042] The RC branch includes a resistor R1 and a capacitor C1 connected in series, and the RC branch is connected between the power supply VCC and the ground VSS.
[0043] The source of the first PMOS transistor PM1 is connected to the power supply, the drain of the first PMOS transistor PM1 is connected to the source of the second PMOS transistor PM2, and the drain of the second PMOS transistor PM2 is grounded through the second NMOS transistor NM2.
[0044] The gate of the first NMOS transistor NM1 is connected to the drain of the second PMOS transistor PM2, the drain of the first NMOS transistor NM1 is connected to the power supply, and the source of the first NMOS transistor NM1 is grounded.
[0045] The gate of the second PMOS transistor PM2 and the gate of the second NMOS transistor NM2 are both connected to the common terminal of the resistor and the capacitor.
[0046] The gate of the first PMOS transistor PM1 is connected to the power-on reset module 100.
[0047] The power-on reset module 100 is used to output a reset signal according to the voltage of the power supply VCC, and the reset signal is synchronized with the voltage of the power supply.
[0048] R1 and C1 constitute an ESD pulse detection unit, used to determine whether the signal between the power supply and ground is an ESD pulse. If it is an ESD pulse signal, an identification signal is sent to the first NMOS transistor NM1 to turn on. After ensuring that the electrostatic charge is discharged, an identification signal is sent to the first NMOS transistor NM1 to turn off. NM1 constitutes a discharge transistor, whose function is to provide a low-resistance discharge path to discharge ESD charge when an ESD pulse is applied between the power supply and ground.
[0049] PM1 and PM2 form the discharge transistor turn-on path, which is used to turn on the discharge transistor according to the identification signal given by the ESD pulse detection unit when an ESD pulse arrives, and to keep it in the off state when a power supply glitches occur; NM2 forms the discharge transistor turn-off path, which is used to turn off the discharge transistor after the discharge transistor is turned on by the discharge transistor turn-on path, after providing sufficient time delay for the discharge transistor to be in the turn-on state.
[0050] In order to prevent false triggering, the temperature acquisition circuit provided in this application introduces a power-on reset signal in the opening path of the discharge transistor, compared with the power clamping circuit of the prior art, and connects the reset signal to the gate of PM1.
[0051] For example, the relationship between the voltage of the reset signal output by the power-on reset module 100 and the voltage of the power supply over time is as follows: Figure 3 As shown, Figure 3 The horizontal axis represents time, and the vertical axis represents voltage.
[0052] After a power-on delay Td, for example, Td = 10µs, the reset signal changes from low to high, turning off PM1. If a power supply glitch occurs, the reset signal and the power supply voltage remain the same, PM1 remains off, and NM1 will not be accidentally turned on. (Comparison) Figure 1 In the prior art power clamping circuit shown, glitch voltages can couple to the gate of the discharge transistor NM1 through PM1, causing the discharge transistor to turn on erroneously.
[0053] It should be understood that the power-on reset module can be a voltage follower. The following describes an implementation method of the power-on reset module with reference to the attached diagram.
[0054] See Figure 4 The figure is a schematic diagram of a power-on reset module provided in an embodiment of this application.
[0055] The power-on reset module provided in this application includes: a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM5.
[0056] The drain of the third NMOS transistor NM3 is connected to the power supply through the second resistor R2. The source of the third NMOS transistor NM3 is connected to the drain of the fourth NMOS transistor NM4. The source of the fourth NMOS transistor NM4 is grounded to VSS through the third resistor R3. The gates of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are both grounded to VSS.
[0057] The drain of the fifth NMOS transistor NM5 is connected to the power supply VCC through the fourth resistor R4, and the source of the fifth NMOS transistor NM5 is grounded to VSS.
[0058] The drain of the fifth NMOS transistor NM5 serves as the output terminal of the power-on reset module.
[0059] Among them, NM3, NM4, NM5, R2, R3, and R4 constitute the power supply voltage detection module. Before VCC is powered on, the signal output by the power-on reset module POR remains at a low level. When VCC is powered on, POR outputs a high level.
[0060] The embodiments of this application do not specifically limit the specific resistance values of R2, R3, and R4. The above three resistors are used to adjust the power-on time and the power-off time, and can be selected according to actual needs.
[0061] In addition, in order to perform waveform shaping on the signal, the power-on reset module provided in this application embodiment also includes: an inverter U1;
[0062] The input terminal of inverter U1 is connected to the drain of the fifth NMOS transistor NM5, and the output terminal of inverter U1 serves as the output terminal of the power-on reset module. Figure 2 The gate of the first PMOS transistor PM1.
[0063] In addition, in order to adjust the pulse width of the glitch in the power supply VCC, the power-on reset module provided in this application embodiment further includes: a second capacitor C2;
[0064] The first and second terminals of the second capacitor C2 are connected to the drain and source of the fifth NMOS transistor NM5, respectively.
[0065] Before the power supply is fully powered on, the inverter U1 output remains at a low level. Once the power supply is fully powered on, the inverter U1 outputs a high level.
[0066] Because the output terminal POR of the power-on reset module can remain high when a minor glitch occurs at VCC during power-on, therefore, Figure 2If the gate of PM1 in the power clamping circuit is always kept at a high level, the gate of the discharge transistor NM1 will not be pulled high, and the discharge transistor NM1 will not turn on to generate leakage current from VCC to GND.
[0067] See Figure 5 The figure is a schematic diagram of an ESD discharge current provided in an embodiment of this application.
[0068] Figure 5 The corresponding parameters are 1kV CDM, 2kV HBM, and 200V MM.
[0069] Figure 5 The rise time of the CDM pulse is 400 ps; the rise time of the HBM pulse is 10 ns; and the rise time of the MM pulse is 20 ns.
[0070] When there is Figure 5 The ESD pulse shown is applied between the power supply and ground. Figure 2 In the process, since the rise time of the gate voltage of PM2 is much longer than the rise time of the power supply voltage, and there is a 10us delay from the rise of the power supply voltage to the high level of the reset signal output to turn off PM1, which is much longer than the rise time of the ESD pulse, the discharge transistor formed by PM1 and PM2 is turned on, and the discharge transistor NM1 is turned on to discharge the ESD current.
[0071] Based on the power clamping circuit provided in the above embodiments, this application also provides an IO interface, which will be described in detail below.
[0072] The embodiments of this application do not specifically limit the specific application scenario of the power clamping circuit. It can be applied to any scenario of chip pin power supply, such as integrated circuits or I / O chips.
[0073] The IO interface provided in this application includes the power clamping circuit described in the above embodiments.
[0074] This application does not specifically limit the type of chip. For example, the chip can be a SIM card chip in an electronic device terminal, such as a SIM card in a mobile phone. Alternatively, the chip can also be a chip in a financial card, such as a chip in a bank card.
[0075] Since the IO interface or chip provided in this application embodiment includes the power clamping circuit described in the above embodiment, it can prevent false triggering caused by glitches when the power is turned on.
[0076] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems or apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.
[0077] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A power clamping circuit, characterized in that, include: First PMOS transistor, second PMOS transistor, first NMOS transistor, second NMOS transistor, RC branch and power-on reset module; The RC branch includes a resistor and a capacitor connected in series, and the RC branch is connected between the power supply and ground. The source of the first PMOS transistor is connected to the power supply, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, and the drain of the second PMOS transistor is grounded through the second NMOS transistor. The gate of the first NMOS transistor is connected to the drain of the second PMOS transistor, the drain of the first NMOS transistor is connected to the power supply, and the source of the first NMOS transistor is grounded. The gates of the second PMOS transistor and the second NMOS transistor are both connected to the common terminal of the resistor and capacitor; The gate of the first PMOS transistor is connected to the power-on reset module; The power-on reset module is used to output a reset signal according to the voltage of the power supply, and the reset signal is synchronized with the voltage of the power supply.
2. The circuit according to claim 1, characterized in that, The power-on reset module includes: a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; The drain of the third NMOS transistor is connected to the power supply through the second resistor, the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is grounded through the third resistor; the gates of the third NMOS transistor and the fourth NMOS transistor are both grounded. The drain of the fifth NMOS transistor is connected to the power supply through the fourth resistor, and the source of the fifth NMOS transistor is grounded. The drain of the fifth NMOS transistor serves as the output terminal of the power-on reset module.
3. The circuit according to claim 2, characterized in that, The power-on reset module further includes: an inverter; The input terminal of the inverter is connected to the drain of the fifth NMOS transistor, and the output terminal of the inverter is connected to the gate of the first PMOS transistor as the output terminal of the power-on reset module.
4. The circuit according to claim 3, characterized in that, The power-on reset module further includes: a second capacitor; The first and second terminals of the second capacitor are respectively connected to the drain and source of the fifth NMOS transistor.
5. The circuit according to claim 3 or 4, characterized in that, Before the power supply is fully powered on, the inverter output remains at a low level; once the power supply is fully powered on, the inverter outputs a high level.
6. The circuit according to claim 5, characterized in that, When a glitch occurs in the power supply, the first NMOS transistor is turned off.
7. An I / O interface, characterized in that, Includes the power clamping circuit as described in any one of claims 1-6.
8. An integrated circuit chip, characterized in that, Includes the power clamping circuit as described in any one of claims 1-6.
9. The chip according to claim 8, characterized in that, The chip in question is a SIM card chip used in electronic device terminals.
10. The chip according to claim 8, characterized in that, The chip mentioned is the chip in a financial card.