One-time-programmable memory cell and memory thereof

Abstract

The present invention relates to an anti-fuse type one-time-programmable memory cell and its memory. The memory cell comprises a select transistor and a gate capacitor, which are connected in series, in a substrate containing active regions and isolation regions; wherein the gate capacitor comprises a gate, a gate oxide layer between the gate and the substrate, and an ion-doped region below the gate oxide layer, the ion-doped region being located in the active regions in the substrate and overlapping a part of the lower surface of the gate oxide layer; the part of the lower surface of the gate oxide layer not overlapping the ion-doped region entirely overlaps the isolation regions in the substrate, and the ion-doped region and the isolation regions are seamlessly adjacent in the substrate below the gate oxide layer. The memory cell and its memory of the present invention can be prepared compatible with advanced standard processes, and have high programming efficiency, fast programming and reading speed, low power consumption, and stable and reliable performance.

Description

Technical Field

[0001] This invention relates to a non-volatile memory cell and its memory, and more particularly to a one-time programmable non-volatile memory cell and its memory, specifically to an antifuse type one-time programmable non-volatile memory cell and its memory. Background Technology

[0002] Non-volatile memory has the advantage that data stored in it will not disappear even when power is off, and it can retain data for a long time. Therefore, it is currently widely used in electronic devices.

[0003] Non-volatile memory is divided into erasable programmable memory (EPM) and one-time programmable memory (OTP). EEPM generally has large storage cells, which cannot meet the needs of large-capacity storage, and it is also expensive. Therefore, one-time programmable (OTP) memory is popular in some applications and markets.

[0004] Based on their characteristics, once-programmable memories (OTPs) can be categorized into floating-gate, electro-fuse, and anti-fuse types. Floating-gate OTP cells achieve high- and low-resistance switching by changing the threshold voltage of the device after electron or hole injection into the floating gate. Electro-fuse OTP cells are in a low-resistance state before programming and in a high-resistance state after programming, typically achieved through electromigration of the polysilicon gate. Anti-fuse cells are in a high-resistance state before programming and in a low-resistance state after programming.

[0005] Floating-gate OTP memories compatible with standard processes require I / O devices with a gate oxide thickness greater than 65 Å to ensure good data retention. Processes of 90nm and above can meet this requirement. However, on 55nm / 40nm or lower process platforms, the gate oxide thickness of I / O devices at 2.5V and below is less than 60 Å. On these process platforms, floating-gate OTP memories cannot guarantee good data retention, thus failing to achieve full compatibility with standard processes and making them difficult to apply to more advanced processes. Furthermore, with the continuous miniaturization of semiconductor manufacturing processes, electrons or holes trapped by floating-gate OTPs on advanced processes are easily leaked, leading to data loss.

[0006] Electric fuse type OTP is limited by polysilicon gates. If advanced processes replace polysilicon gates with metal gates, its use will be further limited.

[0007] Antifuse-type OTPs are programmed based on the physical breakdown mechanism of the gate oxide layer, eliminating the risk of electron or hole leakage. Furthermore, their breakdown is irreversible, resulting in superior reliability. They are also not limited by polysilicon gates and exhibit high compatibility with advanced processes. Consequently, they have attracted considerable attention and made significant progress in recent years.

[0008] Currently, there is a continuous demand in the industry for antifuse OTP memories with optimized structure and performance, especially those with high programming efficiency, fast programming and reading speeds, and low power consumption. Summary of the Invention

[0009] A first aspect of the present invention relates to a first type of one-time programmable memory cell, comprising: a selection transistor and a gate capacitor connected in series in a substrate, the substrate including an active region and an isolation region; wherein the gate capacitor includes a gate, a gate oxide layer located between the gate and the substrate, and an ion-doped region below the gate oxide layer, the ion-doped region being located within the active region in the substrate and overlapping a portion of the lower surface of the gate oxide layer; the portion of the lower surface of the gate oxide layer not overlapping with the ion-doped region completely overlapping the isolation region in the substrate, the ion-doped region and the isolation region being seamlessly adjacent in the substrate below the gate oxide layer.

[0010] In a preferred embodiment, the select transistor has a drain and a source, and the gate capacitor has an ion-doped region, the source of the select transistor coinciding with the ion-doped region of the gate capacitor.

[0011] In another preferred embodiment, the select transistor has a drain and a source, and the gate capacitor has two ion-doped regions, with the source of the select transistor coinciding with one ion-doped region of the gate capacitor; both ion-doped regions of the gate capacitor overlap a portion of the lower surface of the gate oxide layer and are separated by the isolation region, and are seamlessly adjacent to the isolation region. More preferably, the two ion-doped regions of the gate capacitor are connected by a metal line.

[0012] In another preferred embodiment, the gate capacitor has a thin gate oxide layer, which is thinner than that of the selection transistor.

[0013] In another preferred embodiment, the selection transistor is an NMOS transistor, and the ion-doped region of the gate capacitor is an N-type doped region.

[0014] A second aspect of the present invention relates to a one-time programmable memory comprising at least one memory cell as described above, arranged in a multi-row × multi-column array, wherein the substrates of all memory cells are integrated; wherein any two adjacent memory cells in each row are arranged in a left-right mirror symmetry, two adjacent select transistors share a drain, and two adjacent gate capacitors do not contact each other; the select transistors of all memory cells in each column are aligned vertically, and their gates are connected as one unit.

[0015] In a preferred embodiment, the memory further includes: a bit line in each row connected to the drain of the select transistor of each memory cell in that row; a programming line in each row connected to the gate of the gate capacitor of each memory cell in that row; and a word line in each column connected to the gate of the select transistor of each memory cell in that column.

[0016] A third aspect of the present invention relates to a second type of one-time programmable memory cell, which is based on the first type of memory cell described above, and further includes: a first selection transistor and a detection transistor connected in series and located in the substrate; the selection transistor in the first type of memory cell is called a second selection transistor and is connected in series with a gate capacitor; the detection transistor and the gate capacitor share a gate.

[0017] In a preferred embodiment, the detection transistor and gate capacitor have thin gate oxide, and their gate oxide layer thickness is thinner than that of the two selection transistors.

[0018] In another preferred embodiment, the two selection transistors and the detection transistor are of the same type. More preferably, the two selection transistors and the detection transistor are NMOS transistors, and the ion-doped region below the gate oxide layer of the gate capacitor is an N-type doped region.

[0019] In another preferred embodiment, the first selection transistor and the second selection transistor share a common gate.

[0020] The fourth aspect of the present invention relates to a one-time programmable memory cell group comprising four of the above-described second type of memory cells arranged in a centrally symmetrical array of 2 rows × 2 columns, wherein the substrates of all memory cells are integrated into one unit; wherein two memory cells in each row are left-right mirror symmetrical, wherein the two detection transistors in the two cells share a source, and their drains coincide with the sources of the first selection transistors in their respective cells; two gate capacitors are adjacent to each other in the middle of the row, without contacting each other, and an ion-doped region of each gate capacitor is bonded to the source of the second selection transistor in its respective cell; two selection transistors in one cell are arranged on one side of the group, and two selection transistors in another cell are arranged on the other side of the group; two memory cells in each column are vertically mirror symmetrical, all selection transistors in the column are vertically aligned, and the gates of two adjacent second selection transistors or two first selection transistors in two cells are connected.

[0021] In a preferred embodiment, the four storage units in the group have the same structure, composition, and components.

[0022] In another preferred embodiment, the memory cell group further includes: a common line in each row connected to the common source of two detection transistors in that row; a bit line in each row connected to the drain of the first selection transistor of each memory cell in that row; a programming line in each row connected to the drain of the second selection transistor of each memory cell in that row; a programming line in each row connected to the gate capacitance of each memory cell in that row and the common gate of the detection transistor; and two / or one word line in each column connected to the two gates of the first and second selection transistors / or the common gate of the first and second selection transistors in each memory cell in that column.

[0023] The fifth aspect of the present invention relates to a one-time programmable memory, comprising: at least one group of memory cells as described above, forming an array, wherein each group in the array has the same arrangement and the substrates of the memory cells in each group are merged into one to form the substrate of the array; wherein: in each row, two adjacent first selection transistors in two adjacent groups share a drain, and two adjacent second selection transistors in two adjacent groups also share a drain; in each column, the gates of two adjacent second selection transistors or two adjacent first selection transistors in two adjacent groups are connected; the common line, bit line, programming line, and programming line of each group in each row are respectively connected to form the common line, bit line, programming line, and programming line of that row; and the two / or one word line of each group in each column are respectively connected / or connected to form the two / or one word line of that column.

[0024] In a preferred embodiment, the structures, compositions, and components of each group in the array are identical.

[0025] The antifuse-type one-time programmable memory cell and its memory of the present invention, through optimized structure and arrangement, can quickly and efficiently implement breakdown programming, with low breakdown voltage and stable and reliable performance; moreover, it has low power consumption, fast programming and reading speed, high read sensitivity, and can be manufactured compatible with advanced standard processes.

[0026] The one-time programmable memory unit and its memory of the present invention can be manufactured using standard processes of 130nm, 110nm, 90nm, or from 55nm down to 7nm. Attached Figure Description

[0027] Figure 1 A top view of one embodiment of the first storage unit of the present invention is shown.

[0028] Figures 1a-1c They are shown respectively Figure 1 The cross-sectional view of the storage cell shown is obtained along the section lines a1-a1, b1-b1, and c1-c1.

[0029] Figure 2 A top view of another embodiment of the first storage unit of the present invention is shown.

[0030] Figures 2a-2c They are shown respectively Figure 2 The cross-sectional view of the storage cell shown is obtained along the section lines a2-a2, b2-b2, and c2-c2.

[0031] Figure 3 It shows Figure 1 The image shows a top view of a 2x2 array of the first type of storage unit.

[0032] Figure 4 It shows Figure 3 The circuit diagram of the array shown.

[0033] Figure 5 It shows Figure 3-4 The array shown is connected to bias signals during different operations.

[0034] Figure 6 It shows Figure 1 The image shows a top view of a multi-row x multi-column array of storage cells.

[0035] Figure 7 A top view of one embodiment of the second type of storage unit of the present invention is shown.

[0036] Figures 7a-7e They are shown respectively Figure 7 The cross-sectional view of the storage cell shown is obtained along the section lines a3-a3, b3-b3, c3-c3, d3-d3, and e3-e3.

[0037] Figure 8 A top view of another embodiment of the second type of storage unit of the present invention is shown.

[0038] Figure 9 A top view of yet another embodiment of the second type of storage unit of the present invention is shown.

[0039] Figures 9b-9d They are shown respectively Figure 9 The cross-sectional view of the storage cell shown is obtained along the section lines b5-b5, c5-c5, and d5-d5.

[0040] Figure 10 It shows Figure 7 The diagram shows a top view of a 2x2 array of the second type of storage unit.

[0041] Figure 11 It shows Figure 10 The circuit diagram of the array shown.

[0042] Figure 12 It shows Figure 10-11 The array shown is connected to bias signals during different operations.

[0043] Figure 13 It shows Figure 7 The image shows a top view of a multi-row x multi-column array of storage cells.

[0044] Figure 14 It shows Figure 9 The diagram shows a top view of a 2x2 array of the second type of storage unit.

[0045] Detailed description of the invention

[0046] The same numbers in the attached figures indicate similar elements.

[0047] The embodiments of the present invention are illustrated by way of example and are not limited to the examples shown in the accompanying drawings. It should be understood that the drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related embodiments and their accompanying drawings can be obtained from these drawings without creative effort.

[0048] The storage unit and its memory of the present invention can be manufactured compatible with advanced standard processes, can be quickly and efficiently implemented through breakdown programming, has a low breakdown voltage, and stable and reliable performance; moreover, it has low power consumption, fast programming and reading speed, and high read sensitivity.

[0049] The present invention includes two types of antifuse type one-time programmable (OTP) memory cells and their arrays or memories.

[0050] The first type of antifuse type one-time programmable (OTP) memory cell, its array, and memory.

[0051] The first antifuse type one-time programmable (OTP) memory cell of the present invention includes: a select transistor and a gate capacitor connected in series and located in a substrate.

[0052] The ion-doped region of the gate capacitor coincides with the source of the select transistor. During programming, the select transistor is turned on, thereby allowing the ion-doped region beneath the gate oxide layer of the gate capacitor to obtain a low potential through the select transistor connected in series. Simultaneously, a high potential is applied to the gate of the gate capacitor, causing the gate oxide layer to break down under the voltage difference across it.

[0053] During a read operation, the select transistor is turned on, and a potential higher than that of the drain of the select transistor is applied to the gate of the gate capacitor. For a memory cell that has undergone breakdown programming, a read current is generated from the source to the drain of its select transistor.

[0054] The substrate contains active regions (AA) and isolation regions (FOX). The ion-doped regions of the transistor's source / drain and gate capacitor are located within the active regions. The active and isolation regions are adjacent. When there are multiple active regions in the substrate, adjacent active regions are separated by isolation regions. The isolation region, also known as a shallow trench isolation region, is filled with a thick field oxide. The isolation region surrounds the transistor and gate capacitor.

[0055] Preferably, the substrate contains a well, which can be a P-well (PW) or an N-well (NW), with a P-well being preferred. In the case where the substrate contains a well, the aforementioned active region and isolation region are located within the well.

[0056] A gate capacitor can have one or two ion-doped regions.

[0057] When the gate capacitor has an ion-doped region, the source of the selection transistor coincides with this ion-doped region. This ion-doped region extends horizontally within the active region of the substrate or P-well towards the side of the gate capacitor that does not contain the N-doped region, until it overlaps with a portion of the lower surface of the gate oxide layer. The isolation region FOX, located in the substrate or a P-well on the substrate, extends horizontally from the side of the gate capacitor that does not contain the N-doped region, into the lower surface of the gate oxide layer, and overlaps with a portion of the lower surface of the gate oxide layer until it seamlessly joins with the opposing extending N-doped region. The portion of the lower surface of the gate oxide layer that does not overlap with the N-doped region completely overlaps with the isolation region FOX.

[0058] At the boundary between the ion-doped region, the isolation region, and the lower surface of the gate oxide layer, the silicon substrate of the isolation region has a large curvature and a large change in surface orientation at the boundary (which is also the corner of its upper surface). This makes the structure of the subsequent gate oxide layer grown at this point relatively weak, forming structural defects. This makes the gate oxide layer at this point prone to breakdown under low voltage, thus hindering programming.

[0059] When the gate capacitor has two ion-doped regions, the source of the selection transistor coincides with one of the ion-doped regions of the gate capacitor. The two N-type ion-doped regions extend horizontally towards each other within the active region of the substrate or P-well until they overlap a portion of the lower surface of the gate oxide layer, and extend until they are seamlessly bonded to an isolation region FOX located in the substrate or P-well below the gate oxide layer. The two N-type ion-doped regions are separated by this isolation region FOX.

[0060] In this scenario, there are two boundary lines between the ion-doped region, the isolation region, and the lower surface of the gate oxide layer. This results in more defects in the gate oxide layer, making it more susceptible to breakdown and programming at low voltages.

[0061] In the case where the gate capacitor has two ion-doped regions, it is preferable that the two ion-doped regions are connected by a metal line. In this way, the two regions can operate simultaneously.

[0062] The ion-doped region and the isolation region of the gate capacitor are seamlessly bonded in the substrate, which can effectively prevent leakage current between the gate and the substrate during breakdown programming and readout.

[0063] The gate capacitor preferably has a thin gate oxide layer, which is thinner than that of the selected transistor. This allows for a reduction in operating voltage, lower power consumption, and increased programming speed.

[0064] The gate oxide thickness of the transistor is selected to be a conventional value in the industry. The ratio of the gate oxide thickness of the transistor to that of the gate capacitor is selected to be 1.1:1-20:1, preferably 1.2:1-15:1, more preferably 1.3:1-10:1, even more preferably 1.4:1-5:1, and most preferably 1.5:1-3.5:1.

[0065] The selector transistor can be a PMOS transistor or an NMOS transistor, and the type of ion-doped region of the gate capacitor is the same as that of the selector transistor. The selector transistor is preferably an NMOS transistor, and the ion-doped region of the gate capacitor is N-type. In this case, a P-well is preferably present in the substrate, and the selector transistor and the gate capacitor are located within this P-well.

[0066] At least one of the aforementioned first-type memory cells can be arranged into a multi-row × multi-column array to form a memory. This can also be referred to as the first type of memory. The substrates of all memory cells are merged to form the substrate of the array or memory; each pair of adjacent memory cells in each row is arranged in a left-right mirror symmetrical configuration, where two adjacent selection transistors share a drain, while two adjacent gate capacitors do not contact each other; the selection transistors of all memory cells in each column are vertically aligned, and their gates are connected as a single unit.

[0067] The array or memory preferably further includes: a bit line in each row connected to the drain of the select transistor of each memory cell in that row; a programming line in each row connected to the gate of the gate capacitor of each memory cell in that row; and a word line in each column connected to the gate of the select transistor of each memory cell in that column.

[0068] In the array or memory, each storage cell can be programmed independently.

[0069] The second type of antifuse type one-time programmable (OTP) memory cell and its group and memory

[0070] The second type of antifuse type one-time programmable (OTP) memory cell of the present invention is based on the first type of memory cell described above, and further includes: a first selection transistor and a detection transistor connected in series and located in the substrate; the selection transistor in the first type of memory cell is called the second selection transistor, which is connected in series with the gate capacitor; and the detection transistor and the gate capacitor share a gate.

[0071] The ion-doped region of the gate capacitor coincides with the source of the second selection transistor. During programming, the second selection transistor is turned on, thereby allowing the ion-doped region beneath the gate oxide layer of the gate capacitor to obtain a low potential through the second selection transistor connected in series with it. Simultaneously, a high potential is applied to the gate of the gate capacitor, causing the gate oxide layer of the gate capacitor to break down under the voltage difference across it.

[0072] The drain of the detection transistor coincides with the source of the first selection transistor. During programming, the first selection transistor is turned on, thereby providing a high potential to the drain of the detection transistor through the first selection transistor connected in series with it. Simultaneously, a high potential is also applied to the source of the detection transistor. This protects the detection transistor from breakdown during programming and prevents it from being damaged. Furthermore, during readout operations after breakdown programming, the readout current is amplified, improving readout speed and sensitivity. The readout current flows out from the drain of the first selection transistor.

[0073] The second type of memory cell contains three transistors, each comprising: a gate, a gate oxide layer below the gate, and a drain and source layer below the gate oxide layer. The gate capacitance includes the gate, the gate oxide layer below the gate, and an ion-doped region below the gate oxide layer.

[0074] Similar to the first type of memory cell described above, the substrate of the second type of memory cell includes an active region (AA) and an isolation region (FOX), with the active and isolation regions adjacent to each other. The source and drain terminals of the first selection transistor and the detection transistor are located within one active region, while the source and drain terminals of the second selection transistor and the ion-doped region of the gate capacitor are located within another active region. An isolation region separates the two active regions. The isolation region surrounds the three transistors and the gate capacitor.

[0075] The substrate preferably contains a well, which can be a P-well (PW) or an N-well (NW), with a P-well being preferred. In the case of a well in the substrate, both the active region and the isolation region are located in the well.

[0076] The gate oxide thickness of the two select transistors is a conventional value, preferably equal in thickness.

[0077] The gate capacitor preferably has a thin gate oxide layer, which is thinner than the two select transistors. This allows for a lower operating voltage, reduced power consumption, and increased programming speed. Simultaneously, in the structure of this invention, the detection transistor also preferably has a thin gate oxide layer, thereby further reducing power consumption and increasing readout speed. More preferably, the gate oxide layer thickness of the gate capacitor is equal to the gate oxide layer thickness of the detection transistor.

[0078] The ratio of the gate oxide layer thickness of the selected transistor to the gate capacitor is 1.1:1-20:1, preferably 1.2:1-15:1, more preferably 1.3:1-10:1, even more preferably 1.4:1-5:1, and most preferably 1.5:1-3.5:1. Similarly, the ratio of the gate oxide layer thickness of the selected transistor to the detection transistor is 1.1:1-20:1, preferably 1.2:1-15:1, more preferably 1.3:1-10:1, even more preferably 1.4:1-5:1, and most preferably 1.5:1-3.5:1.

[0079] Similar to the first type of memory cell, the gate capacitor has one or two ion-doped regions beneath its gate oxide layer. These regions extend horizontally within the active region to a portion of the lower surface of the overlapping gate capacitor's gate oxide layer. The portion of the lower surface of the gate oxide layer that does not overlap with the ion-doped regions completely overlaps with an isolation region (FOX) located in the substrate or P-well and beneath the gate oxide layer. The ion-doped regions are seamlessly bonded to this isolation region. This effectively prevents leakage current between the gate and the substrate during programming and readout processes.

[0080] In the memory cell of this invention, the first selection transistor is of the same type as the detection transistor, and the second selection transistor is of the same type as the ion-doped region of the gate capacitor. Preferably, all three transistors are of the same type, and the ion-doped region of the gate capacitor is of the same type as the source and drain of the three transistors.

[0081] More preferably, the two select transistors and the detector transistor are NMOS transistors, and the ion-doped region below the gate oxide layer of the gate capacitor is an N-type doped region. In this case, it is preferable that there is a P-well in the substrate, and the three NMOS transistors and the gate capacitor are located in the P-well.

[0082] When the two selection transistors are of the same type, it is preferable that the gates of the first selection transistor and the second selection transistor are connected and share a gate. This can further simplify the memory cell structure and make the operation more convenient, as both selection transistors can be turned on or off at the same time.

[0083] The two selection transistors can also be independent of each other's gates. This allows the first selection transistor to be turned on before programming begins, providing a high potential to the drain of the detection transistor and applying a high potential to its source. Then, the second selection transistor is turned on to perform programming. This method better protects the detection transistor from damage during programming.

[0084] The one-time programmable memory cell group of the present invention includes four of the above-mentioned second type of memory cells, arranged in a centrally symmetrical array of 2 rows × 2 columns, and the substrates of all memory cells are merged into one.

[0085] In each row of the group, the two memory cells are mirror-symmetrical from left to right. The two detection transistors of the two cells share a common source, and the two gate capacitors are adjacent to each other in the middle of the row, without touching each other. The two selection transistors of one cell are arranged on one side of the group, and the two selection transistors of the other cell are arranged on the other side of the group. The two memory cells in each column are mirror-symmetrical from top to bottom. The four selection transistors in each column are aligned vertically. The gates of the two adjacent second selection transistors or the two first selection transistors of the two cells are connected vertically to form a single unit.

[0086] In the case where the first and second selection transistors in each cell share a gate, the gates of the four selection transistors in each column are connected to form a common gate.

[0087] Preferably, the four storage cells in the storage cell group have the same structure, composition, and components.

[0088] The memory cell group of the present invention preferably further includes: a common line, a bit line, a programming line, and a programming line in each row, respectively connected to the common source of two detection transistors in the row, the drain of the first selection transistor of each memory cell in the row, the drain of the second selection transistor of each memory cell in the row, and the gate capacitance of each memory cell in the row and the common gate of the detection transistor; and two / or one word line in each column, respectively connected to the two gates of the first and second selection transistors in each memory cell in the column and / or the common gate of the first and second selection transistors.

[0089] The second type of one-time programmable memory of the present invention includes at least one of the above-mentioned memory cell groups, forming an array, wherein each group in the array is arranged in the same way, and the substrates of the memory cells of each group are merged into one to form the substrate of the array.

[0090] In the array, the two adjacent first selection transistors in each row share a drain, and the two adjacent second selection transistors in each row also share a drain; the gates of the two adjacent second selection transistors or the two first selection transistors in each column are connected; the common lines, bit lines, programming line bottoms, and programming lines of each group in each row are connected to form the common lines, bit lines, programming line bottoms, and programming lines of that row; the two / or one word lines of each group in each column are connected / or connected to form the two / or one word lines of that column.

[0091] In the case where the first and second selection transistors of each cell in each group share a gate, the gates of all selection transistors in each column are connected to form a common gate.

[0092] Preferably, in the array, the structure, composition, and components of each group are completely identical.

[0093] In the storage cell group and its array and memory of the present invention, each second type of storage cell can be programmed independently.

[0094] The two one-time programmable memory units and their memories of the present invention can be fabricated using conventional processes that are mature in the industry, such as 130nm, 110nm, and 90nm standard processes, or they can be fabricated using advanced processes, such as standard processes from below 55nm to 7nm.

[0095] In the above fabrication process, the location and pattern size of the isolation regions in the substrate or in the substrate well are formed using industry-standard methods. For example, the shape and size of the isolation regions, including the shape and size of the isolation regions extending below the gate oxide layer of the gate capacitor, are defined in the layout design and generated at the desired locations by photolithography and dry etching using their corresponding photomasks.

[0096] One or two ion-doped regions of the gate capacitor overlap with a portion of the lower surface of the gate oxide layer and are seamlessly adjacent to an isolation region in the substrate / or a well within the substrate, formed through an industry-standard doping region extension step. Specifically, in the standard process described above, after forming ion-doped regions on one or both sides of the gate of the gate capacitor, the ion-doped regions are further extended to the location of the isolation region, seamlessly joining it.

[0097] In the gate capacitor, the metal line (ML) connecting the two ion-doped regions is also formed using an industry-standard method. Specifically, in the above process, after forming the two ion-doped regions of the gate capacitor, two contact points are formed on the surfaces of the two ion-doped regions respectively, and a metal line is formed on the contact points, with the two ends of the metal line connecting to the two contact points respectively.

[0098] When the gate oxide layer thicknesses of the select transistor and the gate capacitor differ, the different gate oxide layer thicknesses are formed using industry-standard growth methods in the fabrication process. For example, using a thermal oxidation method, a gate oxide layer of thickness 1 is first grown in the region where the gate oxide layer of the select transistor and the gate oxide layer of the gate capacitor are to be formed. Then, the existing gate oxide layer 1 in the region where the gate oxide layer of the gate capacitor is to be formed is completely removed by wet etching. Then, a new gate oxide layer is formed simultaneously in the gate oxide regions of the select transistor and the gate capacitor using another thermal oxidation method, achieving the desired gate capacitor thickness. Here, thickness 1 is the difference between the thickness of the gate oxide layer of the select transistor and the gate oxide layer of the gate capacitor. The gate oxide layer of a detection transistor with a thin gate oxide layer is grown in the same way as that of the gate capacitor described above.

[0099] The following description, in conjunction with the accompanying drawings, describes two types of storage cells and their group structures and array structures according to the present invention. It is obvious that the specific embodiments described in the drawings are only a part of the embodiments of the present invention, and not all of them. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0100] Figure 1 A top view of one embodiment of the first storage unit of the present invention is shown. Figures 1a-1c The cross-sectional views of the storage cell along the section lines a1-a1, b1-b1, and c1-c1 are shown respectively.

[0101] The memory cell contains a selection transistor ST and a gate capacitor GC connected in series with ST.

[0102] The selector transistor ST is an NMOS transistor, comprising a gate, a gate oxide layer below the gate, and an N-type drain and an N-type source below the gate oxide layer. The gate capacitance GC comprises the gate, the gate oxide layer below the gate, and an N-type ion-doped region below the gate oxide layer. The transistor and the gate capacitance are located in a medium-voltage P-well (MVPW) and a low-voltage P-well (LVPW) in a P-type substrate, respectively.

[0103] The gate capacitor GC and the select transistor ST are fabricated on the same 110nm standard process platform. The gate capacitor GC is a 1.5V device, and the select transistor ST is a 5V device. The gate capacitor GC is a low-voltage device with thin gate oxide, located in a low-voltage P-well (LVPW), while the select transistor ST is a medium-voltage device with thick gate oxide, located in a medium-voltage P-well (MVPW).

[0104] The P-well contains an active region (AA) and an isolation region (FOX). Figure 1 and Figures 1a-1c In this diagram, AA is the active region, where the source / drain of the select transistor and the ion-doped regions of the gate capacitor are located. FOX is the shallow trench isolation region, filled with a thick field oxide. Both the select transistor ST and the gate capacitor GC are surrounded by the shallow trench isolation region.

[0105] The source of the selected transistor coincides with the N-type ion-doped region of the gate capacitor. The drain of the selected transistor is connected to the bit line (BL), the gate is connected to the word line (WL), and the gate of the gate capacitor is connected to the programming line (PL).

[0106] The gate oxide layer of the gate capacitor is thinner than that of the select transistor, while the gate oxide layer thickness of the select transistor is a standard value. The ratio of the gate oxide layer thickness of the select transistor to that of the gate capacitor is 3.5:1.

[0107] The N-ion doped region of the gate capacitor extends horizontally within the active region of the P-well towards the side of the gate capacitor that does not contain an N-ion doped region, until it overlaps with a portion of the lower surface of the gate oxide layer. The isolation region FOX, located in the substrate or on the P-well, extends horizontally from the side of the gate capacitor that does not contain an N-ion doped region, into the lower surface of the gate oxide layer, and overlaps with a portion of the lower surface of the gate oxide layer until it seamlessly joins with the horizontally extending N-ion doped region. The portion of the lower surface of the gate oxide layer that does not overlap with the N-ion doped region completely overlaps with the isolation region FOX.

[0108] Figure 2 A top view of another embodiment of the first storage unit of the present invention is shown. Figures 2a-2c The cross-sectional views of the storage cell along the section lines a2-a2, b2-b2, and c2-c2 are shown respectively.

[0109] The structure of this storage unit is similar to Figure 1 Similar to, but different in that the gate capacitor GC has two N-type ion-doped regions below the gate oxide layer, which extend horizontally towards each other within the active region of the P-well until they overlap a portion of the lower surface of the gate oxide layer, and extend to seamlessly join with an isolation region FOX located in the P-well and below the gate oxide layer. The two N-type ion-doped regions are separated by this isolation region FOX, but are connected by a metal line (ML).

[0110] Figure 3 Four were shown Figure 1 A top view of the 2×2 array of storage cells shown. Figure 4 This is the circuit diagram of the array.

[0111] The four memory cells in this array are located on the same P-type substrate and arranged in a 2x2 row, 2 column mirror-symmetric array. The four memory cells in the array are identical, including their structure, composition, and components; only their arrangement and orientation differ.

[0112] The two memory cells 101 and 102 in the first row are mirror images of each other. The two gate capacitors GC are adjacent to each other in the middle of the row, but do not touch. The two select transistors are located on opposite sides of the row.

[0113] The two storage cells 103 and 104 in the second row are arranged in the same way as those in the first row, but are mirror images of the first row.

[0114] The two memory cells 101 and 103 in the first column are mirror images of each other. The gates of the two adjacent selection transistors ST in the two cells are connected to form a common gate.

[0115] The two storage cells 102 and 104 in the second column are arranged in the same way as those in the first column, but are mirror images of the first column.

[0116] In each row, two adjacent low-pressure P-wells (LVPWs) of two cells are merged into one.

[0117] In each column, the two medium-pressure P-wells (MVPWs) of two cells are merged into one, and the two low-pressure P-wells (LVPWs) are also merged into one.

[0118] In the array, each row has a bit line BL and a programming line PL, which are connected to the drain of the select transistor ST and the gate of the gate capacitor GC of each memory cell in that row, respectively. Each column has a word line WL, which is connected to the common gate of the select transistors of the memory cells in that column.

[0119] Figure 5 It shows Figure 3-4 The array shown is connected to bias signals during different operations.

[0120] Each memory cell in the array described above can be programmed independently. During programming, a high voltage difference is applied between the gate of the programming cell's gate capacitor and the N-doped region beneath the gate oxide layer, causing the gate oxide layer to break down and forming a conductive path from the N-doped region to the gate.

[0121] For example, memory cell 101 in the designated group is a programming cell. Memory cell 101 is programmed as follows: the word line WL and programming line PL are driven to potentials of 5.0V and 4.0V respectively, the bit line BL is at potential 0V, and the P-wells (LVPW and MVPW) are at potential 0V. The high potential of the word line WL causes the select transistor ST to turn on quickly, thereby giving the N-ion doped region of the gate capacitor GC a potential of 0V equal to that of the bit line BL connected to the drain of the select transistor. The gate of the gate capacitor receives a high potential of 4.0V through the programming line PL, while the potential of the N-ion doped region below it is 0V. This creates a high voltage difference across the gate oxide layer, causing gate oxide layer breakdown and programming to occur.

[0122] The potential of word line WL in memory cell 102 is 0V, and the other drive potentials are the same as in cell 101. The select transistor cannot be turned on, thus the N-ion doped region of the gate capacitor GC is in a floating state. Although the potential of the gate of the gate capacitor (programming line PL) is 4.0V, there is a lack of voltage difference across the gate oxide layer that would cause breakdown, so it cannot be broken down for programming.

[0123] The programming line PL of memory cell 103 has a potential of 0V, and the other drive potentials are the same as those of cell 101. The gate potential of the gate capacitor is 0V, which is equal to the potential of the N-ion doped region below it, so the gate oxide layer cannot be broken down.

[0124] The word line WL, bit line BL, and programming line PL of memory cell 104 are all at 0V. The select transistor cannot be turned on, and the gate potential of the gate capacitor is 0V, so the gate oxide layer cannot be broken down.

[0125] During the readout operation, the selector ST needs to be turned on, and there is a voltage difference between the source (which is also the N-type ion-doped region of the gate capacitor) and the drain of the selector. Then, a readout current is generated between the source and the drain (BL) of the selector.

[0126] Memory cell 101 is designated as the read cell. The potential of the driving word line WL and bit line BL is 1.5V, and the potential of the programming line PL and P-wells (LVPW and MVPW) is 0V. The 1.5V potential of the word line WL turns on the select transistor ST. Due to the breakdown of the gate oxide layer of the gate capacitor, a conductive path is formed, and the N-type doped region below it has the same potential as the gate. As a result, the source of the select transistor (which is also the N-type ion doped region of the gate capacitor) obtains the same potential of 0V as the programming line PL. Since there is a voltage difference between the source potential 0V and the drain potential 1.5V of the select transistor ST, a read current is generated from the source to the drain.

[0127] The word line WL of memory cell 102 is 0V, and the other drive potentials are the same as those of cell 101. The select transistor cannot be turned on, and the gate oxide layer of the gate capacitor has not been broken down and programmed. Therefore, a conductive path cannot be formed between the source and drain of the select transistor, and there is no voltage difference, so no read current can be generated.

[0128] The bit line BL of memory cell 103 has a potential of 0V, and the other drive potentials are the same as those of cell 101. The word line WL has a potential of 1.5V, and the select transistor ST is turned on. Because the gate oxide layer of the gate capacitor is not broken down for programming, the N-ion doped region below it cannot obtain potential from the programming line PL. There is no voltage difference between the source and drain of the select transistor, and no read current can be generated.

[0129] The relevant drive potentials of memory cell 104 are all 0V. The select transistor cannot be turned on, and no read current can be generated from its source to its drain.

[0130] Figure 2 The storage units shown can also be arranged as follows: Figure 3 The 2×2 array shown has the same array arrangement, array structure, and operation method as described above. Figure 1 The memory cell shown is the same; its bias signal during operation is the same as... Figure 5 The similarity shown is only that, during programming, the potential value of the programming line PL of the specified programming unit is different from that of the programming unit. Figure 5 In Figure 1 The PL potential of the shown memory cell is approximately 0.2V lower. Because the metal line ML connects the two N-ion doped regions of the gate capacitor, both doped regions have the same potential during programming and participate in the programming process together.

[0131] Figure 6 Show more Figure 1 The image shows a top view of the array formed by the storage cells. The arrangement, structure, and connections of the storage cells in the array are consistent with... Figure 3 The same applies as shown. Furthermore, in each row, the two adjacent select transistors ST of two adjacent cells share a drain, and the two adjacent low-voltage P-wells (LVPWs) of two adjacent cells in each row are merged into one; the gates of the select transistors ST of all cells in each column are connected to form a common gate, and the medium-voltage P-wells (MVPWs) and low-voltage P-wells (LVPWs) of all cells in each column are merged into one.

[0132] Figure 7 A top view of one embodiment of the second type of storage unit of the present invention is shown. Figures 7a-7e The cross-sectional views of the memory cell along the profile lines a3-a3, b3-b3, c3-c3, d3-d3, and e3-e3 are shown respectively.

[0133] The memory cell includes a first selection transistor S1, a detection transistor T1 connected in series with S1, a second selection transistor S2, and a gate capacitor C1 connected in series with S2. The detection transistor T1 and the gate capacitor C1 share a common gate, and the two selection transistors S1 and S2 also share a common gate.

[0134] The second selection transistor S2 and the gate capacitance C1 are respectively connected to Figure 1 The selected transistor ST and gate capacitor GC in the shown memory cell are the same, and their composition, arrangement, structure and interconnection are the same; the only difference is that the drain of the second selected transistor is connected to the programming line (PS) instead of the bit line BL.

[0135] S1, S2, and T1 are of the same type, all being NMOS transistors. Each includes a gate, a gate oxide layer below the gate, and an N-type drain and an N-type source below the gate oxide layer. The gate capacitance C1 includes the gate, the gate oxide layer below the gate, and an N-type ion-doped region below the gate oxide layer.

[0136] Two selection transistors are located in a medium-voltage P-well (MVPW) in a P-type substrate, while the detection transistor and gate capacitor are located in a low-voltage P-well (LVPW) in a P-type substrate.

[0137] The gate oxide thicknesses in the two select transistors S1 and S2 are equal, and the gate oxide thicknesses in T1 and C1 are equal. The gate oxide thicknesses of the two select transistors are standard values, while the gate oxide thicknesses of T1 and C1 are thinner than those of the select transistors. The ratio of the gate oxide thickness of the select transistor to that of the detection transistor T1 (or gate capacitor C1) is 3.5:1.

[0138] The detection transistor T1, gate capacitor C1, and select transistors S1 and S2 are fabricated on the same 110nm standard process platform. Detection transistor T1 and gate capacitor C1 are 1.5V devices, while select transistors S1 and S2 are 5V devices. Detection transistor T1 and gate capacitor C1 are low-voltage devices with thin gate oxide, located in a low-voltage P-well (LVPW), while select transistors S1 and S2 are medium-voltage devices with thick gate oxide, located in a medium-voltage P-well (MVPW).

[0139] The P-well contains an active region (AA) and an isolation region (FOX). Figure 7 and Figures 7a-7e In this diagram, AA is the active region, where the source / drain electrodes of the transistor and the ion-doped regions of the gate capacitor are located. FOX is the shallow trench isolation region, filled with a thick field oxide. All three transistors ST and the gate capacitor GC are surrounded by the shallow trench isolation region.

[0140] The drain of the first selection transistor S1 is connected to the bit line (BL), and its source coincides with the drain of the detection transistor T1. The source of the detection transistor T1 is connected to the common line (COM).

[0141] The drain of the second selection transistor S2 is connected to the programming baseline (PS), and its source is bonded to the N-type doped region of the gate capacitor C1. The N-type doped region of the gate capacitor C1 extends horizontally to overlap a portion of its lower gate oxide layer. The portion of the lower gate oxide layer not overlapping with the N-type doped region overlaps entirely with the isolation region FOX, which extends horizontally into the P-well from the side of the self-gate capacitor that does not contain the N-doped region. The N-type doped region and the FOX isolation region are seamlessly bonded within the P-well. Figure 7b As shown.

[0142] The common gate of the two select transistors is connected to the word line (WL), and the common gate of the sense transistor and the gate capacitor is connected to the programming line (PL). There is only one word line WL in this memory cell.

[0143] The gates of the two selection transistors S1 and S2 can also be separate, such as... Figure 8As shown. In this case, the gate of the first selection transistor is connected to word line 1 (WL1), and the gate of the second selection transistor is connected to word line 2 (WL2).

[0144] Figure 9 A top view of another embodiment of the second type of storage unit of the present invention is shown. Figures 9b-9d The cross-sectional views of the storage cell along the section lines b5-b5, c5-c5, and d5-d5 are shown respectively.

[0145] The structure of this storage unit is similar to Figure 7 Similar to, but different in that the gate capacitor GC has two N-type ion-doped regions below the gate oxide layer, which extend horizontally towards each other within the active region of the P-well until they overlap a portion of the lower surface of the gate oxide layer, and extend to seamlessly join with an isolation region FOX located in the P-well and below the gate oxide layer. The two N-type ion-doped regions are separated by this isolation region FOX, but are connected by a metal line (ML).

[0146] Figure 10 Four were shown Figure 7 The top view of the array of storage cells shown. Figure 11 This is the circuit diagram of the array.

[0147] The four memory cells in this array are located on the same P-type substrate and arranged in a centrally symmetrical array of 2 rows × 2 columns. The four memory cells in the group are identical, including identical structure, composition, and components, only differing in their arrangement and orientation.

[0148] The two memory cells 101 and 102 in the first row are mirror images of each other. The two detection transistors T1 in the two cells are adjacent to each other, share a common source, and are connected to a common line COM0. The two gate capacitors C1 are adjacent to each other in the middle of the row, but do not touch each other. The two selection transistors in cell 101 are arranged on the right side of the group, and the two selection transistors in cell 102 are arranged on the left side of the group.

[0149] The two storage cells 103 and 104 in the second row are arranged in the same way as those in the first row, but are mirror images of the first row.

[0150] The two memory cells 101 and 103 in the first column are mirror images of each other, and the gates of the two adjacent second selection transistors S2 in the two cells are connected vertically. Because the first and second selection transistors in each cell share a gate, all four selection transistors in the first column share a gate and are connected to a word line WL0.

[0151] The two storage cells 102 and 104 in the second column are arranged in the same way as those in the first column, but are mirror images of the first column.

[0152] In each row, two adjacent low-pressure P-wells (LVPWs) of two cells are merged into one.

[0153] In each column, the two medium-pressure P-wells (MVPWs) of two cells are merged into one, and the two low-pressure P-wells (LVPWs) are also merged into one.

[0154] In the array, there is a common line COM in each row, which is connected to the common source of two adjacent detection transistors in that row;

[0155] Each row has a bit line BL and a programming line PS, which are connected to the drain of the first selection transistor S1 and the drain of the second selection transistor S2 of each memory cell in that row, respectively; there is a programming line PL, which is connected to the common gate of the gate capacitance and the detection transistor of each memory cell in that row. Each column has a word line WL, which is connected to the common gate of the selection transistor of the memory cell in that column.

[0156] Figure 12 It shows Figure 10 The bias signals connected to the memory cell array shown are displayed during different operations.

[0157] Each memory cell in the group can be programmed independently. During programming, a high voltage difference is applied between the gate of the programming cell's gate capacitor and the N-doped region beneath the gate oxide layer, causing the gate oxide layer to break down and forming a conductive path from the N-doped region to the gate.

[0158] For example, memory cell 101 in the designated group is a programming cell. Memory cell 101 is programmed as follows: the potentials of word line WL and programming line PL are driven to 5.0V and 4.0V respectively; the potentials of bit line BL and common line COM are driven to 1.5V; and the potentials of PS and P-well are 0V. The high potential of word line WL causes selection transistors S1 and S2 to conduct rapidly, thereby obtaining a potential of 0V equal to the programming line PS in the N-ion doped region of gate capacitor C1; simultaneously, the drain of detection transistor T1 obtains a potential equal to the drain of selection transistor S1, i.e., the potential of bit line BL, 1.5V. The gate of the gate capacitor receives a high potential of 4.0V through programming line PL, while the potential of the N-ion doped region below it is 0V, thus creating a high voltage difference across the gate oxide layer, leading to gate oxide layer breakdown and programming. Although the gate of the detection transistor T1 also receives a high potential of 4.0V through the programming line PL, the potential of its drain and source (COM) is 1.5V, and the voltage difference across the gate oxide layer is insufficient to cause breakdown.

[0159] The potential of word line WL in memory cell 102 is 0V, and the other drive potentials are the same as in cell 101. The two select transistors cannot conduct, thus the N-ion doped region of gate capacitor C1 is in a floating state. Although the potential of the gate capacitor (programming line PL) is 4.0V, there is a lack of voltage difference across the gate oxide layer that would cause breakdown, preventing programming.

[0160] The programming line PL of memory cell 103 has a potential of 0V, and the other drive potentials are the same as those of cell 101. The gate potential of the gate capacitor is 0V, which is equal to the potential of the N-ion doped region below it, so the gate oxide layer cannot be broken down.

[0161] The potentials of the word line WL, programming line PL, and programming line PS of memory cell 104 are all 0V. The select transistor cannot be turned on, and the gate potential of the gate capacitor is 0V, so the gate oxide layer cannot be broken down.

[0162] During the readout operation, both the series-connected detection transistor T1 and the selection transistor S1 need to be turned on, and there is a voltage difference between the source (COM) and drain of the detection transistor T1. Then, a readout current is generated between the source (COM) of the detection transistor T1 and the drain (BL) of the selection transistor S1.

[0163] Memory cell 101 is designated as the read cell. The potential of the driving word line WL and bit line BL is 1.5V, the programming line PS is 1V, the common line COM and P-well are 0V, and the programming line PL is in a floating state. The 1.5V potential of the word line WL turns on the select transistors S1 and S2, thereby giving the N-type doped region of the gate capacitor C1 a potential of 1V, which is close to or equal to the programming line PS. The drain of the detection transistor T1 also receives a potential close to or equal to the drain of the select transistor S1. Due to the breakdown of the gate oxide layer of the gate capacitor, a conductive path is formed, and its gate potential is equal to that of the underlying N-type doped region. This gate potential is greater than the threshold of the thin gate oxide detection transistor T1, causing the detection transistor T1 to turn on. Because there is a voltage difference between the source (COM) potential of the detection transistor T1 (0V) and the drain potential (1.5V), a read current is generated from its source (COM) to its drain, and to the drain (BL) of the select transistor T1.

[0164] The word line WL of memory cell 102 is 0V, and the other driving potentials are the same as those of cell 101. The select transistor cannot be turned on, and the gate oxide layer of the gate capacitor C1 has not been broken down for programming. The programming line PL is in a floating state. Therefore, the gate of the gate capacitor cannot obtain a potential. As a result, the detection transistor T1 cannot be turned on, and there is no voltage difference between its source and drain, so no read current can be generated.

[0165] The bit line BL and programming line PS of memory cell 103 have a potential of 0V, while the other drive potentials are the same as those of cell 101. Since the word line WL is 1.5V, select transistors S1 and S2 are turned on, and the N-type doped region below the gate capacitor C1 obtains a potential of 0V. Because the gate oxide layer of the gate capacitor has not been broken down for programming, and the programming line PL is floating, the gate cannot obtain a potential, thus the detection transistor T1 cannot be turned on, and no read current can be generated.

[0166] The relevant drive potentials of memory cell 104 are all 0V, and the programming line PL is floating. Neither of the two select transistors nor the detection transistor T1 can conduct, and no read current can be generated from the source (COM) to the drain (BL) of the detection transistor T1.

[0167] and Figure 7 The storage units shown are the same. Figure 8 or Figure 9 The storage units shown can also be arranged as follows: Figure 10 The 2×2 array shown has the same array arrangement, array structure, and operation method as described above. Figure 7 The memory cells shown are identical; their bias signals during operation are the same as those shown. Figure 12 The similarities shown are different in that: Figure 8 In the memory cell array shown, each column has two bit lines, which are respectively connected to the first and second selection transistors of each memory cell in that column. The potential values ​​of the two bit lines are the same in each operation process, and are also the same as... Figure 12 The potential of the bit line BL is the same in each operation process; Figure 9 When programming the memory cell array shown, the potential value of the programming line PL of the specified programming cell is compared to... Figure 12 In Figure 7 The PL potential of the shown memory cell is approximately 0.2V lower. Figure 9 In the memory cell array shown, since the metal line ML in the memory cell connects the two N-ion doped regions of the gate capacitor, the two ion doped regions have the same potential value during programming and participate in programming together. Figure 14 There are 4 Figure 9 Top view of a 2×2 array of storage cells shown.

[0168] Figure 13 Multiple Figure 10 The image shows a top view of the array formed by the groups of memory cells. Each group in the array has the same arrangement, and the substrates of the memory cells in each group are merged into one to form the substrate of the array.

[0169] In this array, adjacent first selection transistors in two adjacent groups in each row share a drain, and adjacent second selection transistors in two adjacent groups also share a drain. In each column, the gates of adjacent first selection transistors S1 aligned vertically in two adjacent groups are connected vertically. Because the four selection transistors in each group in each column share a gate, all selection transistors in each column have their gates connected, forming a common gate. The common lines, bit lines, programming line base lines, and programming lines of each group in each row are connected to form the common lines, bit lines, programming line base lines, and programming lines of that row; the word lines of each group in each column are connected to form the word lines of that column.

[0170] In each row, the two adjacent medium-pressure P-wells (MVPWs) of two adjacent groups are merged into one. In each column, the low-pressure P-wells (LVPWs) of all groups are merged into one, and the medium-pressure P-wells (MVPWs) are also merged into one.

[0171] The antifuse-type one-time programmable (OTP) memory cell and its memory array of the present invention can be fabricated compatible with advanced standard processes, and have high programming efficiency, fast programming and reading speed, low power consumption, and stable and reliable performance.

Claims

1. A one-time programmable memory cell, comprising: a first selection transistor and a detection transistor connected in series; a second selection transistor and a gate capacitor connected in series; the three transistors and the gate capacitor are all located in a substrate; the substrate includes an active region and an isolation region; wherein the gate capacitor includes a gate, a gate oxide layer located between the gate and the substrate, and an ion-doped region below the gate oxide layer, the ion-doped region being located within the active region in the substrate and overlapping a portion of the lower surface of the gate oxide layer; the portion of the lower surface of the gate oxide layer not overlapping with the ion-doped region completely overlapping the isolation region in the substrate, the ion-doped region and the isolation region being seamlessly adjacent in the substrate below the gate oxide layer; the detection transistor and the gate capacitor share a gate.

2. The memory cell of claim 1, wherein the selection transistor has a drain and a source, the gate capacitor has an ion-doped region, and the source of the selection transistor coincides with the ion-doped region of the gate capacitor.

3. The memory cell of claim 1, wherein the selection transistor has a drain and a source, the gate capacitor has two ion-doped regions, the source of the selection transistor coincides with one ion-doped region of the gate capacitor; both ion-doped regions of the gate capacitor overlap with a portion of the lower surface of the gate oxide layer and are separated by the isolation region, and both are seamlessly adjacent to the isolation region.

4. The memory cell of claim 3, wherein the two ion-doped regions of the gate capacitor are connected by a metal line.

5. The memory cell of claim 1, wherein the detection transistor and the gate capacitor have thin gate oxide, the thickness of which is thinner than that of the two selection transistors.

6. The memory cell of claim 1, wherein the two selection transistors are of the same type as the detection transistor.

7. The memory cell of claim 6, wherein the two select transistors and the detect transistor are NMOS transistors, and the ion-doped region below the gate oxide layer of the gate capacitor is an N-type doped region.

8. The memory cell according to any one of claims 1-7, wherein the first selection transistor and the second selection transistor share a gate.

9. A one-time programmable memory cell array comprising four memory cells as described in any one of claims 1-8, arranged in a centrally symmetrical array of 2 rows × 2 columns, wherein the substrates of all memory cells are integrated into one unit; The two memory cells in each row are mirror images of each other. The two detection transistors in the two cells share a source, and their drains coincide with the source of the first selection transistor in the cell. The two gate capacitors are adjacent to each other in the middle of the row and do not touch each other. One ion-doped region of each gate capacitor is connected to the source of the second selection transistor in the cell. The two selection transistors in one cell are arranged on one side of the group, and the two selection transistors in the other cell are arranged on the other side of the group. The two memory cells in each column are mirror images of each other, and all the select transistors in the column are aligned vertically. The gates of the two adjacent second select transistors or the two first select transistors in the two cells are connected.

10. The storage cell group as described in claim 9, wherein the four storage cells in the group have the same structure, composition, and components.

11. The storage cell group as described in any one of claims 9-10, further comprising: There is a common line in each row, which is connected to the common source of the two detection transistors in that row; Each row has a bit line that connects to the drain of the first selection transistor of each memory cell in that row; Each row has a programming baseline that connects to the drain of the second selection transistor in each memory cell within that row; There is one programming line in each row, which is connected to the gate capacitance of each memory cell in that row and the common gate of the detection transistor; Each column has two / or one word line, which are respectively connected to the two gates of the first and second selection transistors in each memory cell of that column, or the common gate of the first and second selection transistors.

12. A one-time programmable memory, comprising: At least one group of memory cells according to any one of claims 9-11 constitutes an array, wherein each group in the array has the same arrangement, and the substrates of the memory cells in each group are merged into one to form the substrate of the array; wherein: In each row, the two adjacent first selection transistors in two adjacent groups share a drain, and the two adjacent second selection transistors in two adjacent groups also share a drain. In each column, the gates of two adjacent second selection transistors or two first selection transistors in two adjacent groups are connected. The common lines, bit lines, programming bottom lines, and programming lines of each group in each row are connected to form the common lines, bit lines, programming bottom lines, and programming lines of that row; The two / or one word lines in each group of each column are connected / or linked together to form the two / or one word lines of that column.

13. The memory structure of claim 12, wherein the structures, compositions, and components of each group in the array are completely identical.

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