System on chip, voltage control method of system on chip, and terminal

Abstract

This application discloses a system-on-a-chip (SoC), a voltage control method for the SoC, and a terminal, belonging to the field of storage technology. The SoC includes a main device and multiple storage-related devices; the main device is a device with data processing capabilities; the main device and at least one of the multiple storage-related devices are connected; the multiple storage-related devices include at least two groups of storage-related devices operating in at least two voltage domains; wherein the at least two voltage domains are independent voltage domains, and each of the at least two voltage domains corresponds one-to-one with the at least two groups of storage-related devices. By dividing the SoC into at least two independent voltage domains, each independent voltage domain can independently achieve its operating voltage without affecting others, achieving finer-grained and more flexible voltage control of the SoC, supporting independent control of devices within the voltage domain to a low-power voltage state, and effectively reducing the power consumption of the SoC.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a system-on-a-chip, a voltage control method for the system-on-a-chip, and a terminal. Background Technology

[0002] System-on-a-chip (SoC) is incorporated into mobile devices such as smartphones and tablets. This SoC integrates various electrical components, including a central processing unit (CPU), a graphics processing unit (GPU), memory, and a power management chip.

[0003] When a system-on-a-chip (SoC) is operating, the power management chip provides power to the other electrical components of the SoC. However, with technological advancements, the number of electrical components integrated into SoCs is increasing, and the power consumption per unit time is growing, causing the battery life of mobile terminals to fail to meet design requirements. Summary of the Invention

[0004] This application provides a system-on-a-chip (SoC), a voltage control method for the SoC, and a terminal. The technical solution is as follows:

[0005] According to one aspect of this application, a system-on-a-chip is provided, the system-on-a-chip comprising: a host device and a plurality of storage-related devices;

[0006] The main device is a device with data processing capabilities; the main device is connected to at least one of the plurality of storage-related devices;

[0007] The plurality of memory-related devices include: at least two sets of memory-related devices operating in at least two voltage domains;

[0008] The at least two voltage domains are independent of each other, and each of the at least two voltage domains corresponds one-to-one with the at least two sets of storage-related devices.

[0009] According to one aspect of this application, a voltage control method for an on-chip system is provided, the method being applied to the on-chip system described above, the method comprising:

[0010] The master device controls the storage-related devices operating in the target voltage domain to be at a low power voltage, and the target voltage domain is at least one of the at least two voltage domains.

[0011] The low-power voltage is a working voltage that is lower than the normal operating voltage.

[0012] According to one aspect of this application, a terminal is provided, the terminal having a memory and a system-on-a-chip as described above. The memory may be a double data rate (DDR) memory.

[0013] The technical solutions provided in this application have at least the following beneficial effects:

[0014] By dividing the on-chip system into at least two independent voltage domains, the operating voltage of each voltage domain can be controlled independently without being affected by adjacent voltage domains. This enables finer-grained and more flexible voltage control of different storage-related devices, allowing some storage-related devices on the on-chip system to be controlled in a low-power voltage state. This effectively reduces the power consumption of the on-chip system while meeting the voltage requirements under different operating conditions. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the memory read architecture in related technologies;

[0017] Figure 2 This is a schematic diagram of the structure of an on-chip system illustrated in an exemplary embodiment of this application;

[0018] Figure 3 This is a schematic diagram of the voltage domain of an on-chip system illustrated in an exemplary embodiment of this application;

[0019] Figure 4 This is a schematic diagram illustrating the structure of the physical layer interface in an exemplary embodiment of this application;

[0020] Figure 5 This is a schematic diagram of the voltage domain of an on-chip system illustrated in an exemplary embodiment of this application;

[0021] Figure 6 This is a schematic diagram of the structure of an on-chip system illustrated in an exemplary embodiment of this application;

[0022] Figure 7 This is a schematic diagram of the structure of an on-chip system illustrated in an exemplary embodiment of this application;

[0023] Figure 8 This is a schematic diagram of the structure of an on-chip system illustrated in an exemplary embodiment of this application;

[0024] Figure 9This is a schematic diagram of the structure of an on-chip system illustrated in an exemplary embodiment of this application;

[0025] Figure 10 This is a schematic diagram of the structure of an on-chip system illustrated in an exemplary embodiment of this application;

[0026] Figure 11 This is a schematic diagram of the structure of an on-chip system illustrated in an exemplary embodiment of this application;

[0027] Figure 12 This is a flowchart illustrating a voltage control method for an on-chip system according to an exemplary embodiment of this application;

[0028] Figure 13 This is a schematic diagram illustrating a voltage control method for an on-chip system according to an exemplary embodiment of this application;

[0029] Figure 14 This is a schematic diagram of the terminal structure shown in an exemplary embodiment of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0031] In this article, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0032] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0033] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0034] System-on-a-Chip (SoC) in related technologies, such as Figure 1As shown, the terminal has N master devices (101 to 10N), including but not limited to processors such as Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and Digital Signal Processor (DSP), as well as non-processor devices such as Image Sensor, Image Signal Processing Unit (ISP), and Video Processing Unit (VPU). All of these master devices require memory data read and / or write operations during operation.

[0035] Figure 1 Each master device 101 to 10N establishes four bus links with the master bus 11 to send data read / write commands to the master bus 11. The master bus 11 also establishes four links with the slave bus 12 of the storage control device, while the slave bus 12 establishes four memory channels with the four controllers 13. During data read / write operations, the slave bus 12 sends data read / write commands to the controller 13 corresponding to a specific memory channel, and the controller 13 performs data read / write operations on the memory 15 through the physical layer interface 14. In related technologies, the master devices, master bus 11, slave bus 12, controllers 13, and physical layer interface 14 are all in the same voltage domain. When any part of these components needs to be in a high-voltage state, the other parts also need to be in a high-voltage state, resulting in high power consumption of the on-chip system and affecting the terminal's battery life.

[0036] Among them, bus 12, controller 13, and physical layer interface 14 can be considered as storage-related devices. These storage-related devices are used to provide a data path between the master device and the memory.

[0037] To address the aforementioned issues, this application improves the system-on-a-chip (SoC) by enabling the main device or different storage-related devices on the SoC to operate in independent voltage domains, effectively reducing the SoC's power consumption while meeting operational requirements. The structure and operating principle of the SoC are explained below through illustrative embodiments.

[0038] The system-on-a-chip in this application can be used in mobile terminals such as smartphones, smartwatches, e-book readers, tablets, laptops, desktop computers, televisions, game consoles, augmented reality (AR) terminals, virtual reality (VR) terminals, mixed reality (MR) terminals, wearable devices, in-vehicle devices, electronic tags, etc.

[0039] Figure 2 This illustration shows a schematic diagram of a system-on-a-chip (SoC) 200 provided in an exemplary embodiment of this application. The SoC 200 in this embodiment includes: a master device 201, a primary bus 203, a secondary bus 205, a memory controller 207, and a physical layer (PHY) interface 209. The primary bus 203, secondary bus 205, memory controller 207, and physical layer interface 209 are all memory-related devices.

[0040] The main device 201 is a device with data processing capabilities, i.e., a device with data access requirements. This device may include a processor or a non-processor. The processor may include a CPU, GPU, NPU, DSP, etc., while the non-processor may include an image sensor, ISP, VPU, etc. The main device 201 may have both data read and write requirements, such as a processor, or it may only have read or write requirements, such as an image sensor. Whether the main device 201 has both read and write requirements does not constitute a limitation of this application. In this embodiment, the processor includes CPUs, GPUs, and NPUs, and the non-processor includes image sensors and VPUs for illustrative purposes, but this does not constitute a limitation.

[0041] The processor connects various parts of the terminal device through various interfaces and lines. It performs various functions of the terminal device and processes data by running or executing instructions, programs, code sets or instruction sets stored in memory, and calling data stored in memory.

[0042] In some embodiments, the processor may be implemented in at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA).

[0043] A processor can integrate one or more of the following: CPU, GPU, NPU, and baseband chip. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content displayed on the screen; the NPU implements AI functions; and the baseband chip handles wireless communication.

[0044] The master device 201 is connected to at least one of a plurality of storage-related devices. For example, the master device 201 is connected to other storage-related devices via the master bus 203.

[0045] In some embodiments, the master device 201 is connected to the master bus 203 via m links. The master bus 203 establishes m links with the slave bus 205 by interleaving the links corresponding to different master devices, where m is an integer not less than 1. This embodiment uses m as an example of 4.

[0046] In some embodiments, the links between the master device 201 and the master bus 203, and between the master bus 203 and the slave bus 205, employ the same bus protocol. For example, these links all use the Advanced Dextensible Interface (AXI) bus protocol. This application does not limit the specific bus protocol used for the links.

[0047] In some embodiments, the main bus 203 is implemented as a system cache (SC) bus, or the main bus is implemented as an SC bus and SC slices (or stripes). Optionally, the number of SC slices is m. The main bus 203 has data caching capabilities.

[0048] Bus 205 is connected to memory controller 207. Memory controller 207 includes k controllers (corresponding to k memory channels), where k is a positive integer. Exemplarily, the link between bus 205 and memory controller 207 uses the AXI protocol. This application embodiment does not limit the specific bus protocol used for the link.

[0049] In some embodiments, the slave bus is implemented as a Double Data Rate (DDR) bus. Exemplarily, the slave bus 205 includes DDR bus 2051, DDR bus 2052, DDR bus 2053, and DDR bus 2054.

[0050] In some embodiments, k memory channels are established between the slave bus 205 and the memory controller 207. The number of memory channels is related to the branching structure in the master bus 203 or slave bus 205, and k can be an integer multiple or a non-integer multiple of m; this embodiment does not limit this. For example, four links are established between the master bus and the slave bus. After branching through the slave bus, the slave bus is connected to eight controllers, establishing eight memory channels. For example, the memory controller (DDR controller, DMC) includes DMC 2071, DMC 2072, DMC 2073, DMC 2074, DMC 2075, DMC 2076, DMC 2077, and DMC 2078.

[0051] A memory controller 207 establishes k memory channels with the physical layer interface 209, and the memory controller 207 reads and writes data to the memory through the physical layer interface 209. For example, the physical layer interface 209 includes DDR PHY 2091, DDR PHY 2092, DDR PHY 2093, DDR PHY 2094, DDR PHY 2095, DDR PHY 2096, DDR PHY 2097, and DDR PHY 2098.

[0052] In some embodiments, the physical layer interface 209 includes N groups of physical layer interfaces, where N is a positive integer not less than 1. For example, the 8 physical layer interfaces 209 can be divided into two groups of 4 physical layer interfaces 209 each; or, the 8 physical layer interfaces 209 can be divided into two groups of 2 physical layer interfaces 209 each, and 6 physical layer interfaces 209 each; or, the 8 physical layer interfaces 209 can be divided into two groups of 1 physical layer interface 209 each, and 7 physical layer interfaces 209 each.

[0053] In this embodiment, the main device and multiple storage-related devices can operate in the same or different voltage domains. The multiple storage-related devices include at least two groups of storage-related devices operating in at least two voltage domains. These at least two voltage domains are independent of each other, and each of the at least two voltage domains corresponds one-to-one with the at least two groups of storage-related devices. Different voltage domains do not affect each other.

[0054] In some embodiments, for at least two voltage domains corresponding to storage-related devices, the master device operates in one of the at least two voltage domains; or, the master device operates in another voltage domain independent of the at least two voltage domains, such as the top voltage domain.

[0055] In this embodiment of the application, each of the at least two sets of storage-related devices includes at least one of the following: master bus 203, slave bus 205, storage controller 207, and physical layer interface 209.

[0056] In the embodiments of this application, the distribution of at least two voltage domains of multiple storage-related devices can be classified into at least the following four categories:

[0057] Type 1: Divided into two voltage domains;

[0058] Type 2: Divided into three voltage domains;

[0059] Type 3: Divided into four voltage domains;

[0060] Type 4: Divided into 3+N voltage domains.

[0061] The voltage domain distribution of multiple storage-related devices under four different types will be described next:

[0062] Type 1: Divided into two voltage domains

[0063] In this type, at least two sets of storage-related devices include: a first storage-related device operating in a first voltage domain, and a second storage-related device operating in a second voltage domain.

[0064] In some embodiments, the first storage-related device includes a master bus 203, and the second storage-related device includes a slave bus 205, a storage controller 207, and a physical layer interface 209.

[0065] In some embodiments, the first storage-related device includes a master bus 203 and a slave bus 205, and the second storage-related device includes a storage controller 207 and a physical layer interface 209.

[0066] In some embodiments, the first storage-related device includes a master bus 203, a slave bus 205 and a storage controller 207, and the second storage-related device includes a physical layer interface 209.

[0067] In some embodiments, the physical layer interface 209 includes N groups of physical layer interfaces, each of which operates in a first voltage domain and a second voltage domain; or, each of the N groups of physical layer interfaces operates in the second voltage domain.

[0068] Type 2: Divided into three voltage domains

[0069] In this type, at least two sets of storage-related devices include: a first storage-related device operating in a first voltage domain, a second storage-related device operating in a second voltage domain, and a third storage-related device operating in a third voltage domain.

[0070] In some embodiments, the first storage-related device includes a master bus 203, the second storage-related device includes a slave bus 205 and a storage controller 207, and the third storage-related device includes a physical layer interface 209.

[0071] In some embodiments, the first storage-related device includes a master bus 203, the second storage-related device includes a slave bus 205, and the third storage-related device includes a storage controller 207 and a physical layer interface 209.

[0072] In some embodiments, the first storage-related device includes a master bus 203 and a slave bus 205, the second storage-related device includes a storage controller 207, and the third storage-related device includes a physical layer interface 209.

[0073] In some embodiments, the physical layer interface 209 includes N groups of physical layer interfaces, each of which operates in at least two voltage domains of a first voltage domain, a second voltage domain, and a third voltage domain; or, each of the N groups of physical layer interfaces operates in the third voltage domain.

[0074] Type 3: Divided into four voltage domains

[0075] like Figure 3 As shown, at least two sets of memory-related devices include: a first memory-related device operating in a first voltage domain (SC voltage domain), a second memory-related device operating in a second voltage domain (belonging to the DMC voltage domain), a third memory-related device operating in a third voltage domain (belonging to the DMC voltage domain), and a fourth memory-related device operating in a fourth voltage domain (PHYD voltage domain).

[0076] The first storage-related device includes a master bus 203, the second storage-related device includes a slave bus 205, the third storage-related device includes a storage controller 207, and the fourth storage-related device includes a physical layer interface 209.

[0077] In some embodiments, the physical layer interface 209 includes N groups of physical layer interfaces, each of which operates in at least two voltage domains among a first voltage domain, a second voltage domain, a third voltage domain, and a fourth voltage domain; or, each of the N groups of physical layer interfaces operates in the fourth voltage domain.

[0078] Type 4: Divided into 3+N voltage domains

[0079] In this type, the physical layer interface 209 includes N groups of physical layer interfaces, that is, k physical layer interfaces are divided into N groups, and each group of physical layer interfaces operates in the same or different voltage domains.

[0080] In this embodiment of the application, k=8 is used as an example for illustrative purposes.

[0081] In some embodiments, N is 1, and the 8 physical layer interfaces form a group of physical layer interfaces, operating in the fourth voltage domain as described in Type 3.

[0082] In some embodiments, N is a positive integer greater than 1. For example, N = 2 is used for illustrative purposes. The eight physical layer interfaces are divided into two groups. The first group consists of a subset of the eight physical layer interfaces, and the second group consists of the remaining physical layer interfaces excluding the first group. For example... Figure 4 As shown, the first group of physical layer interfaces consists of four physical layer interfaces: physical layer interface 2091, physical layer interface 2092, physical layer interface 2093, and physical layer interface 2094. The second group of physical layer interfaces consists of four physical layer interfaces: physical layer interface 2095, physical layer interface 2096, physical layer interface 2097, and physical layer interface 2098.

[0083] It should be noted that the number of physical layer interfaces in each group of physical layer interfaces can be any positive integer less than k. This application does not impose any limitation on this, and this embodiment is intended to illustrate the concept. For example, the first group of physical layer interfaces includes 1 physical layer interface, and the second group of physical layer interfaces includes 7 physical layer interfaces; or, the first group of physical layer interfaces includes 2 physical layer interfaces, and the second group of physical layer interfaces includes 6 physical layer interfaces, depending on the specific embodiment. This application does not impose any limitation on this.

[0084] In some embodiments, such as Figure 5 As shown, at least two sets of memory-related devices include: a first memory-related device operating in a first voltage domain, a second memory-related device operating in a second voltage domain, a third memory-related device operating in a third voltage domain, a fourth memory-related device operating in a fourth voltage domain, and a fifth memory-related device operating in a fifth voltage domain.

[0085] The first storage-related device includes a master bus 203, the second storage-related device includes a slave bus 205, the third storage-related device includes a storage controller 207, the fourth storage-related device includes a first set of physical layer interfaces in physical layer interface 209, and the fifth storage-related device includes a second set of physical layer interfaces in physical layer interface 209.

[0086] For example, taking N=3 as an illustration, the 8 physical layer interfaces are divided into 3 groups. The first group of physical layer interfaces is a subset of the 8 physical layer interfaces, the second group is another subset of the 8 physical layer interfaces, and the third group is a subset of the 8 physical layer interfaces excluding the first and second groups. For example, the first group includes 1 physical layer interface, the second group includes 5 physical layer interfaces, and the third group includes 2 physical layer interfaces.

[0087] In some embodiments, at least two sets of memory-related devices include: a first memory-related device operating in a first voltage domain, a second memory-related device operating in a second voltage domain, a third memory-related device operating in a third voltage domain, a fourth memory-related device operating in a fourth voltage domain, a fifth memory-related device operating in a fifth voltage domain, and a sixth memory-related device operating in a sixth voltage domain.

[0088] The first storage-related device includes a master bus 203, the second storage-related device includes a slave bus 205, the third storage-related device includes a storage controller 207, the fourth storage-related device includes a first set of physical layer interfaces in physical layer interface 209, the fifth storage-related device includes a second set of physical layer interfaces in physical layer interface 209, and the sixth storage-related device includes a third set of physical layer interfaces in physical layer interface 209.

[0089] In some embodiments, the number of N can be increased or decreased as needed for the operating mode, and is dynamically configured by the master device.

[0090] In some embodiments, the number of physical layer interfaces in each group of physical layer interfaces can be increased or decreased as needed for the operating mode, and is dynamically configured by the master device.

[0091] In summary, the embodiments of this application divide the on-chip system into at least two independent voltage domains, thereby enabling finer-grained and more flexible voltage control of the main device or storage-related devices. This supports controlling some devices on the on-chip system to be in a low-power voltage state, effectively reducing the power consumption of the on-chip system while meeting the voltage requirements under different operating conditions.

[0092] The aforementioned at least two voltage domains can be implemented by different power management integrated circuits (PMICs), or by a combination of a PMIC and a low dropout regulator (LDO).

[0093] An example implementation using a separate PMIC for each voltage domain:

[0094] This application provides a schematic embodiment of a system-on-a-chip (SoC) 200 structure, which is illustrated by the example of an SoC 200 including at least two PMICs. Each voltage domain described in the above embodiment has a one-to-one corresponding PMIC.

[0095] In some embodiments, the system-on-chip 200 includes two PMICs, and the system-on-chip 200 includes two voltage domains corresponding one-to-one with each PMIC. For example, Figure 6 As shown, the master bus 203, operating in the first voltage domain, is connected to PMIC 601, while the slave bus 205, memory controller 207, and physical layer interface 209, operating in the second voltage domain, are connected to PMIC 602. Optionally, the master device operates in the first voltage domain and is connected to PMIC 601; or, the master device operates in the second voltage domain and is connected to PMIC 602.

[0096] In some embodiments, the system-on-chip 200 includes three PMICs, and the system-on-chip 200 includes three voltage domains corresponding one-to-one with each PMIC. For example, Figure 7 As shown, the master bus 203, operating in the first voltage domain, is connected to PMIC 701; the slave bus 205 and memory controller 207, operating in the second voltage domain, are connected to PMIC 702; and the physical layer interface 209, operating in the third voltage domain, is connected to PMIC 703. Optionally, the master device operates in the first voltage domain and is connected to PMIC 701; or, the master device operates in the second voltage domain and is connected to PMIC 702; or, the master device operates in the third voltage domain and is connected to PMIC 703. Alternatively, multiple memory-related devices operate in two voltage domains, each corresponding to one of the two PMICs, while the master device operates in another independent voltage domain, corresponding to a third PMIC.

[0097] In some embodiments, the system-on-chip 200 includes four PMICs, and the system-on-chip 200 includes four voltage domains corresponding one-to-one with each PMIC. For example, Figure 8As shown, the master bus 203, operating in the first voltage domain, is connected to PMIC 801; the slave bus 205, operating in the second voltage domain, is connected to PMIC 802; the memory controller 207, operating in the third voltage domain, is connected to PMIC 803; and the physical layer interface 209, operating in the fourth voltage domain, is connected to PMIC 804. Optionally, the master device operates in the first voltage domain and is connected to PMIC 801; or, the master device operates in the second voltage domain and is connected to PMIC 802; or, the master device operates in the third voltage domain and is connected to PMIC 803; or, the master device operates in the fourth voltage domain and is connected to PMIC 804. Alternatively, multiple memory-related devices operate in three voltage domains, each corresponding to one of the three PMICs, while the master device operates in another independent voltage domain, corresponding to the fourth PMIC.

[0098] In some embodiments, the system-on-chip 200 includes 3+N PMICs, and the system-on-chip 200 includes 3+N voltage domains corresponding one-to-one with each PMIC. For example, N is 2, and the k physical layer interfaces in the physical layer interface 209 operate in two voltage domains, each of which has a corresponding PMIC.

[0099] The main device operates independently in one of the aforementioned voltage domains and has its own corresponding PMIC; or, the main device and a portion of the storage-related devices from at least two groups of storage-related devices operate together in one of the aforementioned voltage domains and share a corresponding PMIC.

[0100] The possible scenarios for memory-related devices operating in each voltage domain corresponding to a PMIC are as described in the previous embodiment, and will not be repeated in this embodiment. This embodiment aims to illustrate that each independent voltage domain has a corresponding PMIC.

[0101] In summary, the system-on-a-chip provided in this application divides the system-on-a-chip into at least two independent voltage domains. Each independent voltage domain is equipped with a corresponding power management chip, which enables finer-grained and more flexible voltage control of the system-on-a-chip. It supports controlling the devices in the corresponding voltage domain to be in a low-power voltage state through an independent power management chip, effectively reducing the power consumption of the system-on-a-chip.

[0102] An example implementation using PMIC+LDO for an independent voltage domain:

[0103] This application provides an illustrative embodiment of a system-on-a-chip (SoC) 200 structure, which is illustrated by the example of the SoC 200 including at least one pin-microcontroller (PMIC). In this embodiment, the number of PMICs is less than the number of voltage domains in the SoC 200.

[0104] In this embodiment, there are M voltage domains sharing the same PMIC. These M voltage domains are connected to the same PMIC through M LDOs. The M voltage domains and M LDOs correspond one-to-one, and M is a positive integer not greater than the number of voltage domains in the system-on-chip 200.

[0105] In some embodiments, the system-on-chip 200 has two voltage domains sharing the same PMIC, and these two voltage domains are connected to the PMIC via two LDOs. For example... Figure 9 As shown, the master bus 203 operating in the first voltage domain is connected to the PMIC 902 via LDO 901, and the slave bus 205, memory controller 207, and physical layer interface 209 operating in the second voltage domain are connected to the PMIC 902 via LDO 903.

[0106] In some embodiments, the system-on-chip 200 has three voltage domains sharing the same PMIC, and these three voltage domains are connected to the PMIC via three LDOs. For example... Figure 10 As shown, the master bus 203, which operates in the first voltage domain, is connected to the PMIC 1002 via LDO 1001; the slave bus 205 and the memory controller 207, which operate in the second voltage domain, are connected to the PMIC 1002 via LDO 1003; and the physical layer interface 209, which operates in the third voltage domain, is connected to the PMIC 1002 via LDO 1004.

[0107] In some embodiments, the system-on-chip 200 has four voltage domains sharing the same PMIC, and these four voltage domains are connected to the PMIC through four LDOs. For example... Figure 11 As shown, the master bus 203, which operates in the first voltage domain, is connected to the PMIC 1102 via LDO 1101; the slave bus 205, which operates in the second voltage domain, is connected to the PMIC 1102 via LDO 1103; the memory controller 207, which operates in the third voltage domain, is connected to the PMIC 1102 via LDO 1104; and the physical layer interface 209, which operates in the fourth voltage domain, is connected to the PMIC 1102 via LDO 1105.

[0108] In some embodiments, the system-on-chip 200 has 3+N voltage domains sharing the same PMIC, and these 3+N voltage domains are connected to the PMIC through 3+N LDOs. For example, N is 2, and the k physical layer interfaces in the physical layer interface 209 operate in two voltage domains, each connected to the same PMIC through a corresponding LDO.

[0109] The master device operates independently in one of the aforementioned voltage domains and is connected to a PMIC via a single LDO; or, the master device and a portion of the storage-related devices from at least two sets of storage-related devices operate together in one of the aforementioned voltage domains and are connected to a PMIC via the same LDO.

[0110] The possible configurations of memory-related devices operating in each voltage domain connected to the LDO are as described in the previous embodiments, and will not be repeated in this embodiment. This embodiment is intended to illustrate that each independent voltage domain is connected to a PMIC through a separate LDO.

[0111] In summary, the system-on-a-chip provided in this application divides the system-on-a-chip into at least two independent voltage domains. Each independent voltage domain is connected to a PMIC through an independent LDO, which enables finer-grained and more flexible voltage control of the system-on-a-chip. It supports controlling the devices in its corresponding voltage domain to be in a low-power voltage state through an independent power management chip, effectively reducing the power consumption of the system-on-a-chip and reducing the setup cost of the system-on-a-chip.

[0112] Figure 12 The diagram illustrates a flowchart of a voltage control method for a system-on-chip according to an exemplary embodiment of this application. The method is applied to the system-on-chip 200 as described above and includes at least some of the following steps:

[0113] Step 121: The master device controls the storage-related devices operating in the target voltage domain to operate at a low power voltage.

[0114] The target voltage domain is at least one of at least two voltage domains, and the low-power voltage is the operating voltage that is less than or equal to the normal operating voltage.

[0115] In some embodiments, the master device controls the storage-related devices operating in the target voltage domain to operate at a low-power voltage based on the operating state of at least one of the multiple storage-related devices.

[0116] In some embodiments, the master device controls the memory-related devices operating in the target voltage domain to operate at a low-power voltage based on the operating scenario. Different operating scenarios are determined by the operating state of at least one of the multiple memory-related devices.

[0117] In some embodiments, at least one storage-related device includes a main bus 203. When the cached data in the main bus 203 reaches a heavy load, the master device controls the storage-related device operating in a target voltage domain to operate at a low-power voltage. Optionally, the target voltage domain is the voltage domain of the main bus 205 and / or the storage controller 207 and / or the physical layer interface 209. Here, heavy load refers to a situation where data read / write operations exceed a threshold. Optionally, this threshold is predefined, preconfigured, or dynamically configured by the master device. For example, when the cached data in the main bus 203 exceeds a preconfigured threshold, the main bus 203 reaches a heavy load.

[0118] For example, when the main bus 203 reaches the heavy load condition, the master device 201 controls the voltage of the voltage domain where the storage controller 207 and the physical layer interface 209 are located to be reduced to a low power voltage. Without affecting the operation of the main bus 203, the total power consumption of the on-chip system is reduced, achieving finer-grained low power control and improving the terminal's battery life.

[0119] In some embodiments, at least one storage-related device includes a main bus 203. When the main bus 203 is in bypass mode, the master device 201 controls the storage-related devices operating in a target voltage domain to operate at a low-power voltage. Optionally, the target voltage domain is the voltage domain in which the main bus 203 is located. Here, the main bus 203 being in bypass mode means that the main bus 203 is only used for signaling and / or data transmission and does not process data. Optionally, the master device dynamically configures whether the main bus 203 is in bypass mode.

[0120] For example, when the main bus 203 is not required to provide data access services, the master device 201 controls the main bus 203 to be in bypass mode and controls the voltage of the voltage domain where the main bus 203 is located to be reduced to a low-power voltage. A current path is formed in the on-chip system including the master device 201 and storage-related devices other than the voltage domain where the main bus 203 is located. Without affecting the operation of other storage-related devices, the total power consumption of the on-chip system is reduced, more granular low-power control is achieved, and the battery life of the terminal is improved.

[0121] In some embodiments, at least one storage-related device includes N sets of physical layer interfaces. When the first set of physical layer interfaces in the N sets of physical layer interfaces is in a target operating mode and the other sets of physical layer interfaces are in a non-target operating mode, the master device controls the storage-related device operating in the target voltage domain to operate at a low-power voltage. Optionally, the target voltage domain is the voltage domain of the other sets of physical layer interfaces besides the first set of physical layer interfaces.

[0122] For example, the target operating mode is a working mode, a high-performance working mode, or a common working mode. Here, a working mode refers to the state in which the device is providing data access services (or read / write services); a high-performance working mode refers to the state in which the device is providing data access services for high-performance applications; and a common working mode refers to the operating state that is typically in, which can be a default setting, a mode defined by the device, or a mode determined based on usage frequency.

[0123] For example, when the first group of physical layer interfaces in physical layer interface 209 is in high-performance working mode, the voltage of the voltage domain of the physical layer interfaces other than the first group of physical layer interfaces in physical layer interface 209 is reduced to a low-power voltage. Without affecting the operation of the first group of physical layer interfaces, the total power consumption of the on-chip system is reduced, achieving finer-grained low-power control and improving the terminal's battery life.

[0124] In some embodiments, at least one storage-related device includes all storage-related devices, and the master device controls the storage-related device operating in the target voltage domain to operate at a low-power voltage when all storage-related devices meet a non-target operating mode. Optionally, the target voltage domain is the voltage domain in which at least one of the storage-related devices is located.

[0125] For example, non-target operating modes are idle mode or low-performance operating mode. Idle mode refers to a state in which no data access services are provided to the main device; low-performance mode refers to a state in which data access services are provided only for low-performance applications or the default kernel control.

[0126] For example, when the master bus 203, slave bus 205, memory controller 207 and physical layer interface 209 are all in idle mode or in low-performance operating mode, the voltage of the voltage domain where the master bus 203, slave bus 205, memory controller 207 and physical layer interface 209 are located is reduced to a low-power voltage. Without affecting the operation of the on-chip system, the total power consumption of the on-chip system is reduced, achieving finer-grained low-power control and improving the terminal's battery life.

[0127] When some of the main bus 203, slave bus 205, memory controller 207 and physical layer interface 209 are in idle mode and some are in low-performance operating mode, the voltage of the voltage domain of the memory-related devices in idle mode is reduced to a low-power voltage. Without affecting the operation of the on-chip system, the total power consumption of the on-chip system is reduced, achieving finer-grained low-power control and improving the terminal's battery life.

[0128] In some embodiments, the target voltage domain has an independent PMIC, or the target voltage domain has an independent LDO. Therefore, step 121 includes at least the following two implementations:

[0129] Method 1: The master device sends control commands to the PMIC;

[0130] Control commands are used to control memory-related devices operating in the target voltage domain to operate at low power voltages.

[0131] Method 2: The master device sends control commands to the LDO.

[0132] Control commands are used to control memory-related devices operating in the target voltage domain to operate at low power voltages.

[0133] In summary, the method provided in this embodiment controls the main device and storage-related devices in the on-chip system to be in at least two voltage domains through independent PMIC or LDO under different operating states, so that some devices are under low power voltage, thereby effectively reducing the power consumption of the on-chip system while ensuring normal operation.

[0134] Figure 13 This illustration shows a schematic diagram of a voltage control method for a system-on-a-chip 200 provided in an exemplary embodiment of this application. This embodiment is illustrated by taking the main bus 203 including an SC bus and four SC chips, the slave bus 205 including four DDR buses, the memory controller 207 including eight controllers, and the physical layer interface 209 including eight physical layer interfaces as examples. It does not mean that the specific structure of the system-on-a-chip 200 in this application is limited.

[0135] Phase 1: During the initialization phase, the master device 201, master bus 203, slave bus 205, storage controller 207, and physical layer interface 209 are all in the same voltage domain.

[0136] Phase Two: When the system-on-chip 200 is in its default operating state, the master device 201 is in the first voltage domain, while the master bus 203, slave bus 205, memory controller 207, and physical layer interface 209 are all in the second voltage domain. The voltage in the second voltage domain is less than or equal to the voltage in the first voltage domain.

[0137] Phase 3: When the cached data in the main bus 203 reaches the overload condition, the master device 201 sends control commands to the PMIC or LDO connected to other storage-related components other than the main bus 203, controlling these components to operate at low-power voltages. For example, the master device 201 is in a first voltage domain, the main bus 203 is in a second voltage domain, and the slave bus 205, storage controller 207, and physical layer interface 209 are in a third voltage domain. The voltage in the third voltage domain is less than or equal to the voltage in the first voltage domain, and the voltage in the first voltage domain is less than or equal to the voltage in the second voltage domain.

[0138] Phase Four: When the physical layer interface 209 is in idle mode, the master device 201 sends control commands to the PMIC or LDO connected to the physical layer interface 209 to control other storage-related components, except for the main bus 203, to operate at low-power voltages. For example, the master device 201 is in a first voltage domain, the main bus 203 is in a second voltage domain, the slave bus 205 and the storage controller 207 are in a third voltage domain, and the physical layer interface 209 is in a fourth voltage domain. The voltage in the fourth voltage domain is less than or equal to the voltage in the third voltage domain, the voltage in the third voltage domain is less than or equal to the voltage in the first voltage domain, and the voltage in the first voltage domain is less than or equal to the voltage in the second voltage domain.

[0139] Phase 5: When the first group of physical layer interfaces in physical layer interface 209 switches to the working mode, the second group of physical layer interfaces in physical layer interface 209 remains in the idle mode. The master device 201 sends a control command to the PMIC or LDO connected to the first group of physical layer interfaces to control the first group of physical layer interfaces to switch to the same voltage domain as the master device 201, the master bus 203, the slave bus 205, or the storage controller 207, or another independent voltage domain. For example, the master device 201 is in the first voltage domain, the master bus 203 and the slave bus 205 are in the second voltage domain, the storage controller 207 is in the third voltage domain, the second group of physical layer interfaces in physical layer interface 209 is in the fourth voltage domain, and the first group of physical layer interfaces in physical layer interface 209 is in the fifth voltage domain. Wherein, the voltage in the fourth voltage domain is less than or equal to the voltage in the third and fifth voltage domains, the voltage in the third and fifth voltage domains is less than or equal to the voltage in the first voltage domain, and the voltage in the first voltage domain is less than or equal to the voltage in the second voltage domain.

[0140] In summary, the on-chip voltage control method provided in this application supports independent control of device voltage adjustment in the target voltage domain based on changes in operating state. By controlling the main device and storage-related devices in the on-chip system to operate at low power voltage with finer granularity and greater flexibility, the power consumption of the on-chip system is effectively reduced.

[0141] Figure 14 A structural block diagram of a terminal provided in an exemplary embodiment of this application is shown. The example described uses a terminal 1400 in this embodiment, including a system-on-chip 200 and a memory 1402, as an example:

[0142] The terminal 1400 is equipped with the system-on-a-chip 200 described in the above embodiments, and the system-on-a-chip 200 and the memory 1402 are electrically connected. The memory 1402 may be located inside the system-on-a-chip 200 or outside the system-on-a-chip 200.

[0143] In some embodiments, the memory 1402 is a memory that supports k memory channels, and each of the k storage elements in the memory 1402 has a working bus, that is, the working bus of each storage element is connected to the system on-chip 200 in a concurrent manner.

[0144] In some embodiments, the k storage elements in the memory 1402 are respectively connected to the k physical layer interfaces in the system-on-chip 200. For example, k is 8, and the 8 physical layer interfaces correspond one-to-one with the 8 storage elements, forming 8 memory channels between the physical layer interface 209 and the memory 1402. For example, the link between the physical layer interface 209 and the memory 1402 adopts the AXI protocol. This application does not limit the specific bus protocol used for the link.

[0145] In some embodiments, the internal particles of the storage element may be arranged in a 2D or 3D manner.

[0146] In some embodiments, the component parameters (e.g., capacity) of each storage element are the same; for example, each storage element has a 16Gb×16 data width specification. In other embodiments, some storage elements have the same component parameters, some storage elements have different component parameters, or different storage elements have different component parameters. This application does not limit the specific component parameters of each storage element.

[0147] k memory elements are packaged into a single memory chip, such as a dynamic random access memory device using stacked packaging (package stacking technology). In some possible designs, the k memory elements are packaged in 2D or 3D packaging; the embodiments of this application do not limit the specific packaging method.

[0148] It should be noted that, in addition to the system-on-chip 200, the terminal 1400 may also include other necessary components, such as read-only memory (ROM), display components, input units, audio circuits, speakers, microphones, power supplies, etc., which will not be described in detail in this embodiment.

[0149] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A system-on-a-chip, characterized in that, The system-on-a-chip includes: a main device, multiple storage-related devices, a power management chip, and at least two low-dropout regulators (LDOs); The main device is a device with data processing capabilities; the main device is connected to at least one of the plurality of storage-related devices; The plurality of storage-related devices include: at least two sets of storage-related devices operating in at least two independent voltage domains, the number of voltage domains being dynamically configured by the master device; The main device and the plurality of storage-related devices all correspond to the power management chip. The at least two voltage domains are connected to the power management chip through the LDOs that correspond one-to-one. The at least two voltage domains correspond one-to-one with the at least two sets of storage-related devices. The plurality of storage-related devices include a master bus and a slave bus. The master bus has data caching capability, and the slave bus is a double data rate (DDR) bus. The master device has the capability to control the storage-related devices operating in the target voltage domain to operate at a low power voltage based on whether the cached data in the master bus reaches a heavy load. Alternatively, the master device has the capability to control the storage-related devices operating in the target voltage domain to operate at a low power voltage based on whether the master bus is in bypass mode. The low power voltage is an operating voltage lower than the normal operating voltage.

2. The system-on-a-chip according to claim 1, characterized in that, The plurality of storage-related devices also include at least one of the following: a storage controller and a physical layer interface.

3. The system-on-a-chip according to claim 2, characterized in that, The at least two sets of storage-related devices include: a first storage-related device operating in a first voltage domain, and a second storage-related device operating in a second voltage domain; The first storage-related device includes the master bus, and the second storage-related device includes the slave bus, the storage controller, and the physical layer interface; or, The first storage-related device includes the master bus and the slave bus, and the second storage-related device includes the storage controller and the physical layer interface; or, The first storage-related device includes the master bus, the slave bus, and the storage controller; the second storage-related device includes the physical layer interface.

4. The system-on-a-chip according to claim 2, characterized in that, The at least two sets of storage-related devices include: a first storage-related device operating in a first voltage domain, a second storage-related device operating in a second voltage domain, and a third storage-related device operating in a third voltage domain; The first storage-related device includes the master bus, the second storage-related device includes the slave bus and the storage controller, and the third storage-related device includes the physical layer interface; or, The first storage-related device includes the master bus, the second storage-related device includes the slave bus, and the third storage-related device includes the storage controller and the physical layer interface; or, The first storage-related device includes the master bus and the slave bus, the second storage-related device includes the storage controller, and the third storage-related device includes the physical layer interface.

5. The system-on-a-chip according to claim 2, characterized in that, The at least two sets of storage-related devices include: a first storage-related device operating in a first voltage domain, a second storage-related device operating in a second voltage domain, a third storage-related device operating in a third voltage domain, and a fourth storage-related device operating in a fourth voltage domain. The first storage-related device includes the master bus, the second storage-related device includes the slave bus, the third storage-related device includes the storage controller, and the fourth storage-related device includes the physical layer interface.

6. The system-on-a-chip according to any one of claims 2 to 5, characterized in that, The physical layer interface includes N groups of physical layer interfaces, each of which operates in a different voltage domain, where N is a positive integer greater than 1.

7. The system-on-a-chip according to any one of claims 1 to 5, characterized in that, The main equipment operates in one of the at least two voltage domains; or, The master device operates in a voltage domain that is independent of the at least two voltage domains.

8. A voltage control method for a system-on-a-chip, characterized in that, The method is applied to the on-chip system as described in any one of claims 1 to 7, and the method includes: The master device controls the storage-related devices operating in the target voltage domain to be at the low power voltage, where the target voltage domain is at least one of the at least two voltage domains.

9. The voltage control method according to claim 8, characterized in that, The master device controls the storage-related devices operating in the target voltage domain to be at the low-power voltage, including: The master device controls the storage-related devices operating in the target voltage domain to be at the low-power voltage based on the operating state of at least one of the plurality of storage-related devices.

10. The voltage control method according to claim 9, characterized in that, The at least one storage-related device includes a main bus; The master device controls the storage-related devices operating in the target voltage domain to be at the low-power voltage based on the operating state of at least one of the plurality of storage-related devices, including: When the cached data in the main bus reaches the overload condition, the master device controls the storage-related devices operating in the target voltage domain to be at the low power voltage. The target voltage domain is the voltage domain of the bus and / or memory controller and / or physical layer interface.

11. The voltage control method according to claim 9, characterized in that, The at least one storage-related device includes N sets of physical layer interfaces; The master device controls the storage-related devices operating in the target voltage domain to be at the low-power voltage based on the operating state of at least one of the plurality of storage-related devices, including: When the first physical layer interface in the N physical layer interfaces is in the target operating mode and the other physical layer interfaces are in the non-target operating mode, the master device controls the storage-related devices operating in the target voltage domain to be at the low power voltage. The target voltage domain is the voltage domain of the other physical layer interfaces besides the first group of physical layer interfaces.

12. The voltage control method according to claim 9, characterized in that, The at least one storage-related device includes a main bus; The master device controls the storage-related devices operating in the target voltage domain to be at the low-power voltage based on the operating state of at least one of the plurality of storage-related devices, including: When the main bus is in bypass mode, the master device controls the storage-related devices operating in the target voltage domain to be at the low power voltage. The target voltage domain is the voltage domain in which the main bus is located.

13. The voltage control method according to claim 9, characterized in that, The at least one storage-related device includes all storage-related devices; The master device controls the storage-related devices operating in the target voltage domain to be at the low-power voltage based on the operating state of at least one of the plurality of storage-related devices, including: When all storage-related devices meet the non-target operating mode, the main device controls the storage-related devices operating in the target voltage domain to be at the low power voltage. The target voltage domain is the voltage domain in which at least one of the memory-related devices is located.

14. The voltage control method according to any one of claims 8 to 13, characterized in that, The master device sends a control command to the power management chip, the control command being used to control the storage-related devices operating in the target voltage domain to be at the low power voltage.

15. The voltage control method according to any one of claims 8 to 13, characterized in that, The target voltage domain has an independent low-dropout regulator (LDO); The master device sends a control command to the LDO, the control command being used to control the memory-related devices operating in the target voltage domain to be at the low power voltage.

16. A terminal, characterized in that, The terminal is provided with a memory and a system-on-a-chip as described in any one of claims 1 to 7.

17. The terminal according to claim 16, characterized in that, The memory is a double data rate (DDR) memory.

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